Voltage-to-time conversion circuit, analog digital converter, and electronic device

Abstract

This voltage-to-time conversion circuit has a first capacitor, a second capacitor, a ramp voltage generation unit, and a time signal generation unit. The first capacitor has: a first terminal to which a first input voltage is applied during a first period; and a second terminal to which a reference voltage is applied during the first period. The second capacitor has: a first terminal to which a second input voltage is applied during the first period; and a second terminal to which the reference voltage is applied during the first period. The ramp voltage generation unit applies, to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period which is after the first period, a voltage that changes at a prescribed rate. The time signal generation unit generates: a first time signal representing a period of time until the voltage at the second terminal of the first capacitor changes to a prescribed threshold voltage during the second period; and a second time signal representing a period of time until the voltage at the second terminal of the second capacitor changes to a prescribed threshold voltage during the second period.

Description

Voltage-time conversion circuit, analog-to-digital converter, and electronic device

[0001] The present disclosure relates to a voltage-time conversion circuit, an analog-to-digital converter, and an electronic device.

[0002] A voltage-to-time converter converts an input voltage signal into a time signal. By combining this voltage-to-time converter with a time-to-digital converter, an analog-to-digital conversion circuit can be configured. For example, an analog-to-digital conversion circuit configured by combining a voltage-to-time conversion circuit and a time-to-digital conversion circuit has been proposed (see, for example, Patent Document 1).

[0003] This prior art analog-to-digital conversion circuit further includes a successive approximation type analog-to-digital conversion circuit that generates a digital signal of higher order bits and also generates a residual voltage between an analog input voltage and an analog signal voltage corresponding to the digital signal of higher order bits. The voltage-to-time converter and the time-to-digital converter generate a digital signal of lower order bits based on the residual voltage.

[0004] The voltage-to-time conversion circuit described above includes a capacitor, a constant current source, and a comparison circuit. The input voltage is sampled by the capacitor. Next, the capacitor is discharged by a current from the constant current source. As a result, the voltage of the capacitor changes at a constant slope. The comparison circuit detects when the voltage of the capacitor has changed to a predetermined potential (e.g., 0 V). The signal representing the detection result of the comparison circuit is a signal representing time according to the input voltage.

[0005] JP 2015-028780 A

[0006] However, the above-mentioned conventional techniques have the problem that they are easily affected by fluctuations in the power supply voltage and reference voltage, and the conversion accuracy is low.

[0007] Therefore, the present disclosure proposes a voltage-to-time conversion circuit that improves conversion accuracy.

[0008] A voltage-time conversion circuit according to the present disclosure includes a first capacitor, a second capacitor, a ramp voltage generator, and a time signal generator. The first capacitor has a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period. The second capacitor has a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period. The ramp voltage generator applies voltages that change at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period following the first period. The time signal generator generates a first time signal representing a time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal representing a time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period.

[0009] FIG. 1 is a diagram illustrating a configuration example of a voltage-time conversion circuit according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of operation of a voltage-time conversion circuit according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a configuration example of a conventional voltage-time conversion circuit. FIG. 4 is a diagram illustrating an example of operation of a conventional voltage-time conversion circuit. FIG. 5 is a diagram illustrating another configuration example of a voltage-time conversion circuit according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a configuration of an analog-to-digital converter according to a second embodiment of the present disclosure. FIG. 7 is a diagram illustrating another configuration example of an analog-to-digital converter according to the second embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a configuration of an analog-to-digital converter according to the second embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of a configuration of an imaging device according to an embodiment of the present disclosure.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. 1. First embodiment 2. Second embodiment 3. Example of application to an imaging device

[0011] 1. First Embodiment [Configuration of Voltage-Time Converter] FIG. 1 is a diagram illustrating a configuration example of a voltage-time conversion circuit according to a first embodiment of the present disclosure. The same diagram is a circuit diagram illustrating a configuration example of a voltage-time conversion circuit 10. The voltage-time conversion circuit 10 in the same diagram converts voltages on input signal lines VinP and VinN into time signals, respectively. The converted time signals are output to output signal lines Tp and Tn. Here, the input voltages from the input signal lines VinP and VinN are referred to as a first input voltage and a second input voltage, respectively. A first time signal, which is the result of converting the first input voltage, is output to the output signal line Tp. Furthermore, a second time signal, which is the result of converting the second input voltage, is output to the output signal line Tn. The input signals on the input signal lines VinP and VinN can be DC or AC signals.

[0012] The voltage-time conversion circuit 10 includes a first capacitor 101, a second capacitor 102, a ramp voltage generator 12, and a time signal generator 11. The voltage-time conversion circuit 10 also includes an input voltage application unit 13 and a reference voltage application unit 14. The voltage-time conversion circuit 10 includes a power supply line Vdd, which is a wiring node that supplies power, and a reference potential line Vss that transmits a reference potential such as GND. Hereinafter, the power supply voltage supplied by the power supply line Vdd will be referred to as Vdd, and the reference potential of the reference potential line Vss will be referred to as Vss.

[0013] The first capacitor 101 and the second capacitor 102 correspond to so-called sampling capacitors. The first capacitor 101 corresponds to a first input voltage from the input signal line VinP, and the second capacitor 102 corresponds to a second input voltage from the input signal line VinN. The two terminals of the first capacitor 101 and the second capacitor 102 are referred to as a first terminal and a second terminal, respectively.

[0014] The first capacitor 101 has a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period. The second capacitor 102 has a first terminal to which a second input voltage is applied during the first period and a second terminal to which a reference voltage is applied during the first period. Here, the first period is a period during which the first capacitor 101 and the second capacitor 102 are charged to a voltage based on the input voltage, and corresponds to a sampling period.

[0015] The ramp voltage generator 12 applies a voltage (ramp voltage) that changes at a predetermined ratio to the first terminal of the first capacitor 101 and the first terminal of the second capacitor 102 during a second period following the first period. The ramp voltage generator 12 shown in FIG. 1 outputs a ramp voltage to a wiring node Vc. The wiring node Vc is connected to the first terminal of the first capacitor 101 via a switch 114 and to the first terminal of the second capacitor 102 via a switch 115. A control signal H1 is commonly input to the control terminals of the switches 114 and 115. Note that the switches 114 and 115 may be, for example, n-channel MOS transistors.

[0016] The ramp voltage generating unit 12 includes a capacitor 103, a switch 116, and a constant current circuit 121. One end of the capacitor 103 is connected to a reference potential line Vss, and the other end is connected to a wiring node Vc. The sink-side terminal of the constant current circuit 121 is connected to a power supply line Vdd, and the source-side terminal is connected to the wiring node Vc. The switch 116 is connected between the wiring node Vc and the reference potential line Vss. A control signal H2 is input to the control terminal of the switch 116. During the first period, the switch 116 is turned on. This causes the potential of the wiring node Vc to become Vss. During the second period, the switch 116 is turned off. The capacitor 103 is charged by the constant current circuit 121, generating a ramp voltage that increases at a predetermined rate. By turning on the switches 114 and 115 during the second period, the ramp voltage can be applied to the first terminal of the first capacitor 101 and the first terminal of the second capacitor 102. The switch 116 can be an n-channel MOS transistor.

[0017] The time signal generating unit 11 generates a first time signal representing the time until the voltage at the second terminal of the first capacitor 101 changes to a predetermined threshold voltage during the second period. The time signal generating unit 11 further generates a second time signal representing the time until the voltage at the second terminal of the second capacitor 102 changes to a predetermined threshold voltage during the second period.

[0018] The time signal generating unit 11 in FIG. 1 includes a comparator 122 and a comparator 123. The inverting input terminal of the comparator 122 is connected to a wiring node Vth that supplies a threshold voltage (Vth), and the non-inverting input terminal is connected to the second terminal of the first capacitor. The output terminal of the comparator 122 is connected to an output signal line Tp. The inverting input terminal of the comparator 123 is connected to the wiring node Vth, and the non-inverting input terminal is connected to the second terminal of the second capacitor. The output terminal of the comparator 123 is connected to an output signal line Tn.

[0019] The input voltage application unit 13 applies a first input voltage and a second input voltage to the first capacitor 101 and the second capacitor 102, respectively. The input voltage application unit 13 includes a switch 110 and a switch 111. The switch 110 is connected between the input signal line VinP and the first terminal of the first capacitor 101. The switch 111 is connected between the input signal line VinN and the first terminal of the second capacitor 102. A control signal S1 is commonly input to control terminals of the switches 110 and 111. When the switches 110 and 111 are in an on state, the first input voltage and the second input voltage are transmitted to the first terminal of the first capacitor 101 and the first terminal of the second capacitor 102, respectively. For example, n-channel MOS transistors can be used for the switches 110 and 111. The switch 110 is an example of a "third switch" in the present disclosure. The switch 111 is an example of a "fourth switch" in the present disclosure.

[0020] The reference voltage application unit 14 applies a reference voltage to the first capacitor 101 and the second capacitor 102. Here, the reference voltage is a voltage that serves as a reference when sampling the first input voltage and the second input voltage to the first capacitor 101 and the second capacitor 102. The reference voltage application unit 14 of FIG. 1 includes a switch 112 and a switch 113. The reference voltage application unit 14 of FIG. 1 applies a power supply voltage (Vdd) as a reference voltage to the first capacitor 101 and the second capacitor 102. The switch 112 is connected between the power supply line Vdd and the second terminal of the first capacitor 101. The switch 113 is connected between the power supply line Vdd and the second terminal of the second capacitor 102. A control signal S2 is commonly input to the control terminals of the switches 112 and 113. When the switches 112 and 113 are in the on state, Vdd is applied to the second terminal of the first capacitor 101 and the second terminal of the second capacitor 102. For example, p-channel MOS transistors can be used for the switches 112 and 113. The switch 112 is an example of a "first switch" in the present disclosure. The switch 113 is an example of a "second switch" in the present disclosure.

[0021] The control signals S1, S2, H1, H2, and threshold voltage (Vth) are supplied from a control circuit (not shown).

[0022] [Operation of the Voltage-Time Converter] FIG. 2 is a diagram illustrating an example of the operation of the voltage-time conversion circuit according to the first embodiment of the present disclosure. This diagram is a timing diagram illustrating an example of the operation of the voltage-time conversion circuit 10. In this diagram, "VinP" represents the waveform of the first input voltage. "VinN" represents the waveform of the second input voltage. "S1" represents the voltage waveform of the control signal S1. "S2" represents the voltage waveform of the control signal S2. "H1" represents the voltage waveform of the control signal H1. "H2" represents the voltage waveform of the control signal H2. "Vc" represents the voltage waveform of the wiring node Vc. "Vp" represents the voltage waveform of the first terminal of the first capacitor 101. "Vn" represents the voltage waveform of the first terminal of the second capacitor 102. "Sp" represents the voltage waveform of the second terminal of the first capacitor 101. "Sn" represents the voltage waveform of the second terminal of the second capacitor 102. "Tp" represents the voltage waveform of the first time signal. "Tn" represents the voltage waveform of the second time signal.

[0023] The control signal S1 represents an ON voltage in which the H level portion of the binarized waveform turns ON the switch 110. The same applies to the control signals S2, H1, and H2.

[0024] 2, the dashed lines in the waveforms of "Vc," "Vp," "Vn," "Sp," and "Sn" represent the potential of Vss. The dashed lines in the waveforms of "Sp" and "Sn" represent the potential of Vth.

[0025] In the initial state, the control signals S1, S2, and H1 are at L level. The control signal H2 is at H level. The first terminal of the first capacitor 101 and the first terminal of the second capacitor 102 are in a floating state. The wiring node Vc is at Vss. The first time signal and the second time signal are at H level.

[0026] At T1, the control signals S1 and S2 go to H level. As a result, the switches 110, 111, 112, and 113 are turned on. The first input voltage and Vdd are applied to the first terminal and the second terminal of the first capacitor 101, respectively. The second input voltage and Vdd are applied to the first terminal and the second terminal of the second capacitor 102, respectively.

[0027] At T2, the control signal S2 goes low. This turns off the switches 112 and 113. The first capacitor 101 and the second capacitor 102 hold a voltage based on the first input voltage and a voltage based on the second input voltage, respectively. The period from T1 to T2 corresponds to the first period.

[0028] At T3, the control signal S1 goes low, causing the switches 110 and 111 to turn off.

[0029] At T4, the control signal H1 goes high and the control signal H2 goes low. This causes the ramp voltage generator 12 to generate a ramp voltage and output it to the wiring node Vc. Furthermore, the switches 114 and 115 are turned on, and the ramp voltage is applied to the first terminal of the first capacitor 101 and the first terminal of the second capacitor 102. Furthermore, the potentials of the second terminal of the first capacitor 101 and the second terminal of the second capacitor 102 become lower than Vth, and the first time signal and the second time signal go low.

[0030] Thereafter, as the ramp voltage increases, the first time signal transitions to an H level at the timing when the potential at the second terminal of the first capacitor 101 exceeds Vth. Similarly, the second time signal transitions to an H level at the timing when the potential at the second terminal of the second capacitor 102 exceeds Vth.

[0031] At T5, the control signal H1 goes low and the control signal H2 goes high. This causes the ramp voltage generator 12 to stop generating the ramp voltage. The switches 114 and 115 are turned off. The period from T4 to T5 corresponds to the second period.

[0032] During the period from T4 to T5 described above, a first time signal and a second time signal having pulse widths corresponding to the first input voltage and the second input voltage are generated, respectively. In this manner, the voltage-to-time conversion circuit 10 of FIG. 1 performs voltage-to-time conversion on the first input voltage to generate the first time signal, and performs voltage-to-time conversion on the second input voltage to generate the second time signal. During this conversion, a ramp voltage is commonly applied to the first capacitor 101 and the second capacitor 102, which are sampling capacitors. As described above, the ramp voltage is generated by the ramp voltage generator 12. Since this ramp voltage contains errors due to the influence of Vdd and the constant current circuit 121, the first time signal and the second time signal also contain errors. However, when used to extract the difference between the first time signal and the second time signal, as in the analog-to-digital converter 1 described in FIG. 6, the errors commonly contained in the first time signal and the second time signal are canceled out. Therefore, the voltage-to-time conversion circuit 10 of FIG. 1 can reduce errors.

[0033] Furthermore, during the first period, the first capacitor 101 has a first terminal to which a first input voltage is applied via the switch 110 and a second terminal to which a reference voltage is applied via the switch 112. Similarly, during the first period, the second capacitor 102 has a first terminal to which a second input voltage is applied via the switch 111 and a second terminal to which a reference voltage is applied via the switch 113. In this manner, the first capacitor 101 holds the first input voltage based on the reference voltage, and the second capacitor 102 holds the second input voltage based on the reference voltage. Thereafter, when transitioning to the second period, the switches 112 and 113 are turned off, and then the switches 110 and 111 are turned off. This makes it possible to prevent errors from occurring due to the on / off switching of the switches 110 and 111. This will be explained next.

[0034] [Configuration of a Conventional Voltage-to-Time Converter] FIG. 3A is a diagram showing an example of the configuration of a conventional voltage-to-time conversion circuit. This figure is a circuit diagram showing an example of the configuration of a voltage-to-time conversion circuit 90. This voltage-to-time conversion circuit 90 is shown as a comparative example. This voltage-to-time conversion circuit 90 is a voltage-to-time conversion circuit in which an input voltage is applied to one end of a sampling capacitor via a switch element during sampling, and a ramp voltage is applied to the other end of the sampling capacitor during conversion. In the voltage-to-time conversion circuit 90, elements with the same reference numerals are arranged in parts common to the voltage-to-time conversion circuit 10.

[0035] The voltage-time conversion circuit 90 includes a switch 110 , a switch 111 , a switch 116 , a switch 117 , a first capacitor 101 , a second capacitor 102 , a capacitor 103 , a constant current circuit 121 , and a comparator 122 and a comparator 123 .

[0036] The switch 110 is connected between the input signal line VinP and the first terminal of the first capacitor 101. The switch 111 is connected between the input signal line VinN and the first terminal of the second capacitor 102. The second terminal of the first capacitor 101 and the second terminal of the second capacitor 102 are commonly connected to a wiring node Vc. The sink side terminal of the constant current circuit 121 is connected to the power supply line Vdd, and the source side terminal is connected to one end of the switch 117. The other end of the switch 117 is connected to the wiring node Vc. The switch 116 is connected between the wiring node Vc and the reference potential line Vss. The capacitor 103 is connected between the wiring node Vc and the reference potential line Vss. The non-inverting input terminal of the comparator 122 is connected to the first terminal of the first capacitor 101. The non-inverting input terminal of the comparator 123 is connected to the first terminal of the second capacitor 102. A control signal S1 is input to the control terminal of the switch 116. A control signal S3 is input to the control terminal of the switch 117. Other than these, the connections are common to the voltage-time conversion circuit 10 of FIG.

[0037] 3B is a diagram showing an example of the operation of a conventional voltage-to-time conversion circuit. While the control signal S1 is at H level, the switches 110 and 111 are turned on, and the first capacitor 101 and the second capacitor 102 are charged to the first input voltage and the second input voltage, respectively. Next, when the control signal S1 goes to L level, the switches 110 and 111 are turned off. At the same time, a ramp voltage is generated and applied to the second terminal of the first capacitor 101 and the second terminal of the second capacitor 102. The generation of the time signal by the comparator 122 and the like is the same as that of the voltage-to-time conversion circuit 10 in FIG. 1, and therefore is not described here.

[0038] Like the voltage-time conversion circuit 10, the voltage-time conversion circuit 90 performs conversion by applying a ramp voltage to the first capacitor 101 and the second capacitor 102 in common, thereby reducing the occurrence of errors. On the other hand, in the voltage-time conversion circuit 90, when the switches 110 and 111 are transitioned from the on state to the off state, the charging voltages of the first capacitor 101 and the second capacitor 102 change, causing errors.

[0039] 4A is a diagram showing an example of the configuration of a conventional voltage-to-time conversion circuit. This figure is a circuit diagram of a portion of a voltage-to-time conversion circuit 90 near a first capacitor 101. The circuit in this figure represents an equivalent circuit during sampling. In this figure, an n-channel MOS transistor is depicted as the switch 110.

[0040] 4B is a diagram showing an example of the operation of a conventional voltage-to-time conversion circuit. This figure is a timing diagram showing an example of the operation of the circuit of FIG. 4A. In this figure, the waveform of the control signal S1 and the waveform of the first input voltage (VinP) are superimposed. When the control signal S1 is at an H level, the switch 110 is turned on. That is, an on-voltage is applied to the gate of the MOS transistor that constitutes the switch 110, causing the MOS transistor to become conductive. At this time, the capacitance between the channel and gate of the MOS transistor is charged to a voltage corresponding to the gate voltage.

[0041] Thereafter, when the control signal S1 changes to an L level, the switch 110 is turned off. At this time, the charge on the capacitance between the channel and gate of the MOS transistor is transferred to the first capacitor 101, causing a change in the charging voltage of the first capacitor 101. ε1 in FIG. 4B represents this change in charging voltage. The charge on the capacitance between the channel and gate of this MOS transistor changes depending on the first input voltage. As shown in FIG. 4B, when the switch 110 is turned on for the second time, the first input voltage is lower than the first time, so the change in the charging voltage of the first capacitor 101 (ε2) is a different value from the first time. In this way, the voltage-time conversion circuit 90 generates an error that changes depending on the input voltage (first input voltage and second input voltage).

[0042] In contrast, in the voltage-to-time conversion circuit 10 of FIG. 1 , during a first period, a first input voltage is applied to the first terminal of the first capacitor 101 via the switch 110, and a reference voltage is applied to the second terminal via the switch 112. Similarly, during a first period, a second input voltage is applied to the first terminal of the second capacitor 102 via the switch 111, and a reference voltage is applied to the second terminal via the switch 113. Then, the switches 112 and 113 are turned off first. At this time, the charge in the capacitance between the channel and gate of the MOS transistor is transferred to the first capacitor 101, etc. However, because the reference voltage is constant, the change in the charging voltage of the first capacitor 101 and the second capacitor 102 also remains constant. Next, even if the switches 110 and 111 are turned off, the first capacitor 101 and the second capacitor 102 are in a floating state, so no charge is transferred. This prevents the occurrence of errors dependent on the input voltage.

[0043] [Another Configuration of the Voltage-Time Converter] Figure 5 is a diagram showing another example configuration of the voltage-time conversion circuit according to the first embodiment of the present disclosure. This figure is a circuit diagram showing another example configuration of the voltage-time conversion circuit 10. The voltage-time conversion circuit 10 shown in this figure uses Vss as the reference voltage, and shows an example in which the ramp voltage generator 12 generates a ramp voltage whose voltage decreases at a predetermined rate. P-channel MOS transistors can be used for the switches 110, 111, 114, 115, and 116. N-channel MOS transistors can be used for the switches 112 and 113.

[0044] As described above, the voltage-to-time conversion circuit 10 according to the first embodiment of the present disclosure performs voltage-to-time conversion on a first input voltage to generate a first time signal, and performs voltage-to-time conversion on a second input voltage to generate a second time signal. During this voltage-to-time conversion, a ramp voltage is commonly applied to the first capacitor 101 and the second capacitor 102, which are sampling capacitors. By applying this voltage-to-time conversion circuit 10 to an application for extracting the difference between the first time signal and the second time signal, errors can be reduced. Therefore, the voltage-to-time conversion circuit 10 can improve conversion accuracy.

[0045] (2. Second Embodiment) An example in which the voltage-time conversion circuit 10 of the first embodiment described above is applied to an analog-to-digital converter will be described.

[0046] [Configuration of Analog-Digital Converter] Fig. 6 is a diagram showing a configuration example of an analog-digital converter according to a second embodiment of the present disclosure. The figure is a block diagram showing a configuration example of an analog-digital converter 1. The analog-digital converter 1 in the figure converts a voltage corresponding to the difference between input signals 1 and 2 into a digital signal. The analog-digital converter 1 includes a voltage-time conversion circuit 10 and a time-digital conversion circuit 20.

[0047] A voltage-time conversion circuit 10 in the figure performs voltage-time conversion on input signals 1 and 2 and outputs the converted first and second time signals to a time-digital conversion circuit 20 .

[0048] The time-to-digital conversion circuit 20 converts the difference between the input first time signal and second time signal into a digital signal.

[0049] 7 is a diagram showing a configuration example of an analog-digital converter according to a second embodiment of the present disclosure. The figure is a block diagram showing a configuration example of an analog-digital converter 1. The analog-digital converter 1 in the figure is a detailed description of the configuration of the time-digital conversion circuit 20 of the analog-digital converter 1 in FIG. 6. Note that in the figure, a "voltage-time conversion circuit" is abbreviated as "VTC."

[0050] 7 includes a comparison unit 140, a changing edge detection circuit 150, non-inverting gates 160 to 166, D flip-flops 170 to 176, and an encoding circuit 180. The time-to-digital conversion circuit 20 is connected to the output signal lines Tp and Tn of the voltage-to-time conversion circuit 10.

[0051] The comparator 140 compares the transition edges of the first and second time signals from the voltage-to-time conversion circuit 10 to detect the signal of the transition edge that occurs earlier in time. Specifically, the comparator 140 outputs a value of "1" if the transition edge of the first time signal occurs earlier in time than the transition edge of the second time signal. On the other hand, the comparator 140 outputs a value of "0" if the transition edge of the second time signal occurs earlier in time than the transition edge of the first time signal. The output of the comparator 140 is transmitted to the encoder circuit 180 as a sign bit. The comparator 140 can be configured, for example, by an RS flip-flop circuit.

[0052] The changing edge detection circuit 150 detects one of two input signals, one whose changing edge occurs earlier in time and one whose changing edge occurs later in time. This changing edge detection circuit 150 outputs the signal whose changing edge occurs earlier in time, one of the first time signal and the second time signal, to a signal line "early." Also, this changing edge detection circuit 150 outputs the signal whose changing edge occurs later in time, one of the first time signal and the second time signal, to a signal line "late." The changing edge detection circuit 150 can be configured with an AND gate and an OR gate.

[0053] The non-inverting gates 160 to 166 are connected in series to form a non-inverting gate string. This non-inverting gate string sequentially delays the signal on the signal line early. The D flip-flops 170 to 176 form a flip-flop string. The signal line late is connected to the D input terminals of the D flip-flops 170 to 176. The output signals of the non-inverting gates 160 to 166 are input to the clock input terminals of the D flip-flops 170 to 176. By detecting the position where the outputs of the D flip-flops 170 to 176 change from low to high, the time from the changing edge of the signal on the signal line early to the changing edge of the signal on the signal line late can be detected. The Q outputs of the D flip-flops 170 to 176 are transmitted to the encoding circuit 180.

[0054] The encoding circuit 180 generates a digital signal based on the sign bit from the comparison section 140 and the output signals of the D flip-flops 170 to 176 .

[0055] 8 is a diagram showing another example configuration of an analog-digital converter according to the second embodiment of the present disclosure. The figure is a block diagram showing another example configuration of the analog-digital converter 1. This analog-digital converter 1 includes switches 117 and 118, an analog-digital converter 30, a voltage-time conversion circuit 10, a time-digital conversion circuit 20, and an encoding circuit 180. Note that in the figure, the "time-digital conversion circuit" is abbreviated as "TDC."

[0056] The analog-to-digital converter 30 performs successive approximation type analog-to-digital conversion and includes a digital-to-analog converter 31, a comparison circuit 32, and a logic circuit 33. In the figure, the "digital-to-analog converter" is abbreviated as "DAC."

[0057] The digital-to-analog converter 31 generates an analog signal under the control of the logic circuit 33 and superimposes it on the input signal 1 and the input signal 2. The input signal 1 and the input signal 2 are input to the digital-to-analog converter 31 via the switches 117 and 118. The comparator circuit 32 compares the difference between the input signal 1 and the input signal 2 with a predetermined value (e.g., 0 V) ​​and outputs the comparison result to the logic circuit 33. The logic circuit 33 controls the entire analog-to-digital converter 30. The logic circuit 33 also generates a clock signal for the comparator circuit 32.

[0058] The values ​​of input signal 1 and input signal 2 are changed by digital-to-analog converter 31. Logic circuit 33 performs conversion by changing the output of digital-to-analog converter 31 until the difference between the values ​​of input signal 1 and input signal 2 reaches a predetermined value. The conversion result of analog-to-digital converter 30 corresponds to a digital signal of the most significant bits, and is transmitted to encoding circuit 180. Furthermore, analog-to-digital converter 30 outputs the residual voltage after conversion to voltage-to-time conversion circuit 10.

[0059] The voltage-time conversion circuit 10 converts the residual voltage from the analog-to-digital converter 30 into a time signal and outputs it to the time-to-digital conversion circuit 20 .

[0060] The time-to-digital conversion circuit 20 converts into a digital signal the difference between the first time signal and the second time signal from the voltage-to-time conversion circuit 10. The conversion result of the voltage-to-time conversion circuit 10 corresponds to a digital signal of the lower bits and is transmitted to the encoding circuit 180.

[0061] The encoding circuit 180 in FIG. 8 generates a digital signal based on the conversion result of the analog-to-digital converter 30 and the conversion result of the time-to-digital conversion circuit 20 .

[0062] 9 is a diagram showing another configuration example of an analog-digital converter according to the second embodiment of the present disclosure. The figure is a block diagram showing another configuration example of the analog-digital converter 1. The analog-digital converter 1 in the figure is a detailed description of the configuration of the time-to-digital conversion circuit 20 of the analog-to-digital converter 1 in FIG.

[0063] 9 includes comparison units 140 to 143, changing edge detection circuits 150 to 152, and delay units 167 to 169. In the time-to-digital conversion circuit 20 shown in the figure, the comparison unit 140 and changing edge detection circuit 150, the comparison unit 141 and changing edge detection circuit 151, and the comparison unit 142 and changing edge detection circuit 152 are cascaded in multiple stages.

[0064] The delay units 167 to 169 delay the signal on the signal line early. The delay unit 167 is configured by four non-inverting gates connected in series. The delay unit 168 is configured by two non-inverting gates connected in series. The delay unit 169 is configured by one non-inverting gate. In this way, the delay units 167 to 169 are assigned binary-weighted (power of 2) delay times.

[0065] As described above, the comparator 140 compares the transition edges of the first and second time signals from the voltage-time conversion circuit 10 to detect the signal of the transition edge that occurs earlier in time. The transition edge detection circuit 150 outputs the signal of the first and second time signals whose transition edge occurs earlier in time to the signal line "early," and outputs the signal of the first and second time signals whose transition edge occurs later in time to the signal line "late." This signal line "late" is connected to the transition edge detection circuit 151 of the next stage. Meanwhile, the signal line "early" is connected to the transition edge detection circuit 151 of the next stage via the delay unit 167. Therefore, the signal on the signal line "early" is subjected to time subtraction by the delay unit 167.

[0066] Similarly, in the next stage, a signal whose transition edge occurs earlier in time is detected by the comparison unit 141. Furthermore, a signal whose transition edge occurs earlier in time is selected by the transition edge detection circuit 151, and is delayed by the delay unit 168, and a time is subtracted.

[0067] Similarly, in the next stage, the comparator 142 detects a signal whose changing edge occurs earlier in time. Furthermore, the changing edge detection circuit 152 selects a signal whose changing edge occurs earlier in time, and the signal is delayed by the delay unit 169 and subjected to time subtraction. In this way, the time-to-digital conversion circuit 20 compares the time difference between the changing edges of the input signals, and performs time subtraction so that the time difference between the changing edges gradually approaches zero.

[0068] The comparison unit 143 compares the changing edges of the signal on the signal line late and the signal line early of the changing edge detection circuit 152, and detects the signal with the changing edge that occurs earlier in time.

[0069] The comparison results of the comparison units 140 to 143 are transmitted to the encoding circuit 180 as digital signals of the lower bits.

[0070] In this way, the time-to-digital conversion circuit 20 of the present disclosure can be applied to the analog-to-digital converter 1. By applying the time-to-digital conversion circuit 20 of the present disclosure to the analog-to-digital converter 1, the accuracy of the analog-to-digital conversion can be improved.

[0071] (3. Application Example to Imaging Device) The voltage-time conversion circuit 10 of the above-described embodiment can be applied to an imaging device.

[0072] 10 is a diagram illustrating an example configuration of an imaging device according to an embodiment of the present disclosure. The figure is a block diagram illustrating an example configuration of an imaging device 5. The imaging device 5 includes an image sensor 2, a digital-to-analog converter 3, an analog-to-digital converter 1, and a processor 4.

[0073] The image sensor 2 captures an image of a subject and generates image data, which is a digital signal.

[0074] The digital-to-analog converter 3 converts the image data into an analog signal and generates a PAM4 signal, which is a differential analog signal.

[0075] The analog-to-digital converter 1 receives the PAM4 signal from the digital-to-analog converter 3 and generates a digital signal.

[0076] The processor 4 processes the digital signal from the analog-to-digital converter 1. The processor 4 is an example of a "processing circuit" in the present disclosure. The imaging device 5 is an example of an "electronic device" in the present disclosure.

[0077] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0078] The present technology may also be configured as follows: (1) A voltage-to-time conversion circuit including: a first capacitor having a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period; a second capacitor having a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period; a ramp voltage generation unit that applies a voltage that changes at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period after the first period; and a time signal generation unit that generates a first time signal that represents a time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal that represents a time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period. (2) The voltage-time conversion circuit according to (1), further comprising: a reference voltage application unit that applies the reference voltage to the first capacitor and the second capacitor; and an input voltage application unit that applies the first input voltage and the second input voltage to the first capacitor and the second capacitor, respectively. (3) The reference voltage application unit comprises a first switch connected between a wiring node that supplies the reference voltage and the second terminal of the first capacitor, and a second switch connected between the wiring node and the second terminal of the second capacitor, and the input voltage application unit comprises a third switch connected between the wiring node that supplies the first input voltage and the first terminal of the first capacitor, and a fourth switch connected between a wiring node that supplies the second input voltage and the first terminal of the second capacitor. (4) The voltage-to-time conversion circuit according to (3), wherein the input voltage application unit transitions the third switch and the fourth switch of the reference voltage application unit to an OFF state after the first switch and the second switch of the reference voltage application unit transition to an OFF state at the end of the first period.(5) The voltage-to-time conversion circuit according to any one of (1) to (4), wherein the ramp voltage generation unit includes a third capacitor and a constant current circuit that supplies a predetermined current to the third capacitor. (6) The voltage-to-time conversion circuit according to any one of (1) to (5), wherein the time signal generation unit includes a comparator circuit that generates the first time signal by comparing the voltage of the second terminal of the first capacitor with the predetermined threshold voltage, and a comparator circuit that generates the second time signal by comparing the voltage of the second terminal of the second capacitor with the predetermined threshold voltage. (7) An analog-to-digital converter comprising: a voltage-to-time conversion circuit including: a first capacitor having a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period; a second capacitor having a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period; a ramp voltage generation unit that applies a voltage that changes at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period after the first period; and a time signal generation unit that generates a first time signal that represents a time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal that represents a time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period; and a time-to-digital conversion circuit that converts the first time signal and the second time signal into digital values. (8) The analog-to-digital converter according to (7), further comprising an analog-to-digital conversion unit that converts a first input signal and a second input signal into digital signals and generates a residual voltage that is a voltage of a difference between analog signals corresponding to the first input signal and the second input signal, respectively, and the voltage-to-time conversion circuit generates the first time signal and the second time signal using the residual voltage as the first input voltage and the second input voltage.(9) An electronic device comprising: a voltage-to-time converter including: a first capacitor having a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period; a second capacitor having a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period; a ramp voltage generating unit that applies a voltage that changes at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period after the first period; and a time signal generating unit that generates a first time signal that represents a time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal that represents a time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period; and a processing circuit that processes the first time signal and the second time signal.

[0079] REFERENCE SIGNS LIST 1, 30 Analog-to-digital converter 5 Imaging device 10 Voltage-to-time conversion circuit 11 Time signal generation unit 12 Ramp voltage generation unit 13 Input voltage application unit 14 Reference voltage application unit 20 Time-to-digital conversion circuit 90 Voltage-to-time conversion circuit 101 First capacitor 102 Second capacitor 103 Capacitor 110 to 118 Switch 121 Constant current circuit 122, 123 Comparator

Claims

1. A voltage-to-time conversion circuit comprising: a first capacitor having a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period; a second capacitor having a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period; a ramp voltage generation unit that applies a voltage that changes at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period after the first period; and a time signal generation unit that generates a first time signal that represents the time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal that represents the time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period.

2. The voltage-time conversion circuit according to claim 1, further comprising: a reference voltage application section that applies the reference voltage to the first capacitor and the second capacitor; and an input voltage application section that applies the first input voltage and the second input voltage to the first capacitor and the second capacitor, respectively.

3. The voltage-time conversion circuit of claim 2, wherein the reference voltage application unit comprises a first switch connected between a wiring node supplying the reference voltage and the second terminal of the first capacitor, and a second switch connected between the wiring node and the second terminal of the second capacitor, and the input voltage application unit comprises a third switch connected between a wiring node supplying the first input voltage and the first terminal of the first capacitor, and a fourth switch connected between a wiring node supplying the second input voltage and the first terminal of the second capacitor.

4. A voltage-to-time conversion circuit as described in claim 3, wherein the input voltage application unit transitions the third switch and the fourth switch to the OFF state after the first switch and the second switch of the reference voltage application unit transition to the OFF state at the end of the first period.

5. The voltage-time conversion circuit according to claim 1, wherein the ramp voltage generating section comprises a third capacitor and a constant current circuit that supplies a predetermined current to the third capacitor.

6. The voltage-to-time conversion circuit according to claim 1, wherein the time signal generating unit comprises a comparison circuit that generates the first time signal by comparing the voltage at the second terminal of the first capacitor with the predetermined threshold voltage, and a comparison circuit that generates the second time signal by comparing the voltage at the second terminal of the second capacitor with the predetermined threshold voltage.

7. An analog-to-digital converter comprising: a voltage-to-time conversion circuit including: a first capacitor having a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period; a second capacitor having a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period; a ramp voltage generation unit that applies a voltage that changes at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period after the first period; and a time signal generation unit that generates a first time signal that represents the time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal that represents the time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period; and a time-to-digital conversion circuit that converts the first time signal and the second time signal into digital values.

8. The analog-to-digital converter according to claim 7, further comprising an analog-to-digital conversion unit that converts the first input signal and the second input signal into digital signals and generates a residual voltage that is a voltage difference between analog signals corresponding to the first input signal and the second input signal, respectively, and the voltage-to-time conversion circuit generates the first time signal and the second time signal using the residual voltage as the first input voltage and the second input voltage.

9. An electronic device comprising: a voltage-to-time converter including: a first capacitor having a first terminal to which a first input voltage is applied during a first period and a second terminal to which a reference voltage is applied during the first period; a second capacitor having a first terminal to which a second input voltage is applied during the first period and a second terminal to which the reference voltage is applied during the first period; a ramp voltage generating unit that applies a voltage that changes at a predetermined rate to the first terminal of the first capacitor and the first terminal of the second capacitor during a second period after the first period; and a time signal generating unit that generates a first time signal that represents the time until the voltage at the second terminal of the first capacitor changes to a predetermined threshold voltage during the second period and a second time signal that represents the time until the voltage at the second terminal of the second capacitor changes to the predetermined threshold voltage during the second period; and a processing circuit that processes the first time signal and the second time signal.

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