Light detection device and electronic apparatus

Abstract

Provided is a light detection device in which narrowing of a dynamic range is minimized. This light detection device comprises a photoelectric conversion element, a charge accumulation region, a reset transistor, an amplification transistor, and a selection transistor connected in series to the amplification transistor. At least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector device and an electronic device, and more particularly to a photodetector device and an electronic device in which a signal line is shared by multiple pixels.

[0002] Conventionally, each pixel has a transfer gate that transfers charge from the pixel (PD) to a floating potential node, an amplification transistor that transfers that signal to the downstream circuit, and a selection transistor that switches the target pixel. The inclusion of this selection transistor allows multiple pixels to share the signal line (VSL) that transfers the signal to the downstream circuit, thereby reducing the scale of the downstream circuit. However, as mentioned above, when the VSL is shared by multiple pixels, the dynamic range (D-Range) of the pixel output is often narrowed due to the selection transistors of the non-selected pixels.

[0003] The image sensor disclosed in Patent Document 1 uses a charge pump to prevent the dynamic range from being narrowed.

[0004] Furthermore, Patent Document 2 discloses a transistor in which a part of the gate electrode is buried in the substrate.

[0005] JP 2021-82901 A JP 2013-125862 A

[0006] The present technology aims to provide a photodetector and electronic device in which the narrowing of the dynamic range is suppressed.

[0007] A photodetector according to one aspect of the present technology includes a photoelectric conversion element, a charge accumulation region, a reset transistor, an amplification transistor, and a selection transistor connected in series to the amplification transistor, and at least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

[0008] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device.

[0009] FIG. 1 is a chip layout diagram showing a configuration example of a photodetector according to a first embodiment of the present technology. FIG. 2 is a block diagram showing a configuration example of a photodetector according to the first embodiment of the present technology. FIG. 3 is an equivalent circuit diagram of a pixel of the photodetector according to the first embodiment of the present technology. FIG. 4 is an equivalent circuit diagram showing a selected pixel and a non-selected pixel of the photodetector according to the first embodiment of the present technology. FIG. 5 is an explanatory diagram showing a relationship between a voltage range that an amplifying transistor can output, a voltage range that can pass a selection transistor of a selected pixel, and a voltage range that can be cut off by a selection transistor of a non-selected pixel in the first embodiment of the present technology. FIG. 6 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the first embodiment of the present technology. FIG. 7 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the first modification of the first embodiment of the present technology. FIG. 8 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the second modification of the first embodiment of the present technology. FIG. 9 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the third modification of the first embodiment of the present technology. FIG. 10 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the fourth modification of the first embodiment of the present technology. FIG. 11 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in the photodetector according to the fifth modification of the first embodiment of the present technology. FIG. 1 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a sixth modification of the first embodiment of the present technology. FIG. 2 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a seventh modification of the first embodiment of the present technology. FIG. 3 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a seventh modification of the first embodiment of the present technology. FIG. 4 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a ninth modification of the first embodiment of the present technology. FIG. 5 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a tenth modification of the first embodiment of the present technology. FIG. 6 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to an eleventh modification of the first embodiment of the present technology. FIG. 7 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a twelfth modification of the first embodiment of the present technology. FIG. 8 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a thirteenth modification of the first embodiment of the present technology.FIG. 1 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a sixteenth modification of the first embodiment of the present technology. FIG. 2 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a seventeenth modification of the first embodiment of the present technology. FIG. 3 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to an eighteenth modification of the first embodiment of the present technology. FIG. 4 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a nineteenth modification of the first embodiment of the present technology. FIG. 5 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a twentieth modification of the first embodiment of the present technology. FIG. 6 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a twenty-first modification of the first embodiment of the present technology. FIG. 7 is an equivalent circuit diagram of a pixel included in a photodetector according to a second embodiment of the present technology. FIG. 8 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first modification of the second embodiment of the present technology. FIG. 9 is an equivalent circuit diagram of a pixel included in a photodetector according to a fourth embodiment of the present technology. FIG. 10 is a longitudinal sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fourth embodiment of the present technology. FIG. 11 is a block diagram showing an example of a schematic configuration of an electronic device.

[0010] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0011] In the following drawings, identical or similar parts are denoted by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that parts with different dimensional relationships and ratios are included between the drawings. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings. Note that well regions may be omitted from the drawings related to the present technology. Even when well regions are omitted, NMOS transistors are provided in p-type well regions, and PMOS transistors are provided in n-type well regions.

[0012] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] The description will be given in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment Application examples to electronic devices

[0015] First Embodiment In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0016] <Overall Configuration of Photodetection Device> First, the overall configuration of the photodetection device 1 will be described. As shown in Fig. 1 , the photodetection device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the photodetection device 1 is mounted on the semiconductor chip 2. As shown in Fig. 33 , the photodetection device 1 captures image light (incident light 106) from a subject via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0017] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes, in a two-dimensional plane including an X direction and a Y direction that intersect with each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A.

[0018] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 33 . In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction, which intersect with each other, on the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. The direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction, depth direction). The direction perpendicular to the Z direction is the horizontal direction (lateral direction).

[0019] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0020] 2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0021] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0022] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0023] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0024] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0025] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0026] 3 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR (or transfer gate) that transfers the signal charges photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0027] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0028] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD, and the gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0029] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0030] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are made of, for example, a silicon oxide film (SiO ２ These transistors are configured as MOSFETs having a gate insulating film made of a silicon nitride film (Si film, SiO film), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. ３ N ４ Alternatively, the readout circuit 15 may be a MISFET (Metal Insulator Semiconductor FET) made of a stacked film of a silicon nitride film, a silicon oxide film, or the like. The readout circuit 15 may be provided for each photoelectric conversion element PD, or one readout circuit 15 may be shared by multiple photoelectric conversion elements PD. Similarly, the charge accumulation region FD may be provided for each photoelectric conversion element PD, or one charge accumulation region FD may be shared by multiple photoelectric conversion elements PD.

[0031] The amplifier transistor AMP has a source region electrically connected to the first terminal a of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0032] The select transistor SEL has a second terminal b electrically connected to the vertical signal line 11 (VSL), a first terminal a electrically connected to the source region of the amplifier transistor AMP, and a gate electrode electrically connected to a select transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0033] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd (or the power supply line VBO) and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0034] The amplification transistor AMP and the selection transistor SEL will be described in more detail below with reference to FIG. 4 . Note that FIG. 4 omits illustration of transistors other than the amplification transistor AMP and the selection transistor SEL. The amplification transistor AMP is connected in series with the selection transistor SEL and electrically connected to the vertical signal line 11 (VSL) via the selection transistor SEL. Because the selection transistor SEL switches the pixel 3 to be read, one vertical signal line 11 can be shared by multiple pixels 3. Note that the number of pixels 3 sharing one vertical signal line 11 is not limited to that shown in FIG. 4 . The selection transistor SEL is configured as a CMOS transistor (CMOS circuit). The CMOS transistor (CMOS circuit) includes a first transistor SEL1 and a second transistor SEL2 connected in parallel. The first transistor SEL1 is an NMOS transistor (an n-channel conductivity type MOSFET, hereinafter sometimes referred to as NMOS), and the second transistor SEL2 is a PMOS transistor (a p-channel conductivity type MOSFET, hereinafter sometimes referred to as PMOS). The drain region of the first transistor SEL1 and the source region of the second transistor SEL2 are connected to a first terminal a. The source region of the first transistor SEL1 and the drain region of the second transistor SEL2 are connected to a second terminal b. Hereinafter, the pixel 3 to be read out will be referred to as a selected pixel 3a, and the pixel 3 not to be read out will be referred to as a non-selected pixel 3b, to distinguish them from each other. When there is no need to distinguish between the selected pixel 3a and the non-selected pixel 3b, they will simply be referred to as pixels 3. The selection transistor SEL of the selected pixel 3a is in an on state, and the amplification transistor AMP is electrically connected to the vertical signal line 11 via the selection transistor SEL. The selection transistor SEL of the non-selected pixel 3b is in an off state.

[0035] 5 shows the relationship between the voltage range L that the amplifier transistor AMP can output, the voltage range M that can pass the select transistor SEL of the selected pixel 3a, and the voltage range N that can shut off the select transistor SEL of the non-selected pixel 3b. The voltage range L that the amplifier transistor AMP can output is designed to range from voltage V1 to voltage V2. The voltage range M that can pass the select transistor SEL of the selected pixel 3a is designed to range from voltages higher than voltage V1 to voltages lower than voltage V2. In the selected pixel 3a, the output voltage of the amplifier transistor AMP is supplied to the vertical signal line 11 via at least one of the first transistor SEL1 and the second transistor SEL2. The voltage range N that can shut off the select transistor SEL of the non-selected pixel 3b is designed to range from voltages higher than voltage V1 to voltages lower than voltage V2. Since the select transistor SEL is configured using the above-mentioned CMOS transistor, it is possible to design the cut-off voltage CutLo of the first transistor SEL1 to be lower than voltage V2, which is the lower limit of the voltage that the amplifier transistor AMP can output. This prevents the voltage V2 from being restricted by the cut-off voltage CutLo, allowing the selection transistor SEL in the non-selected pixel 3b to block a voltage range including the voltage range L that the amplification transistor AMP can output.

[0036] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1 according to the first embodiment of the present technology will be described with reference to Fig. 6. Note that in Fig. 6 and subsequent drawings, the wiring of the equivalent circuit shown in Fig. 3 may be indicated by solid lines or dotted lines.

[0037] <<Layer Structure of Photodetector>> The photodetector 1 has a layer structure in which, for example, a first semiconductor layer 20 and a first wiring layer 30 are layered in that order. The photodetector 1 further has a second semiconductor layer 40. In the following description, a case will be described in which the first conductivity type is n-type and the second conductivity type is p-type. Note that simply referring to n-type indicates the first conductivity type, and simply referring to p-type indicates the second conductivity type. Note that the present technology is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0038] <First Semiconductor Layer> One surface of the first semiconductor layer 20 is a first surface S1, and the other surface is a second surface S2. The first surface S1 may be referred to as an element formation surface or a main surface, and the second surface S2 may be referred to as a back surface. In this embodiment, a case where the second surface S2 is a light incident surface will be described, but the present technology is not limited to this. The first surface S1 may also be a light incident surface.

[0039] The first semiconductor layer 20 is made of a semiconductor substrate. The first semiconductor layer 20 is made of, for example, a single-crystal silicon substrate, although not limited thereto. The first semiconductor layer 20 is provided with semiconductor regions such as an n-type photoelectric conversion region 21, an n+-type charge accumulation region 22, and a p-type well region (not shown). Furthermore, a transfer transistor TR, a reset transistor RST, and an amplification transistor AMP are provided on the first surface S1 side of the first semiconductor layer 20. All of the transfer transistor TR, reset transistor RST, and amplification transistor AMP are NMOS transistors capable of forming an n-channel.

[0040] 1, a plurality of island-shaped cell regions 20a partitioned by isolation regions are provided in a matrix in a portion of the first semiconductor layer 20 corresponding to the pixel region 2A. For example, the cell region 20a is provided for each pixel 3. A plurality of photoelectric conversion regions 21 (FIG. 6) are provided in a matrix in a portion of the first semiconductor layer 20 corresponding to the pixel region 2A. For example, the photoelectric conversion region 21 is provided for each cell region 20a. The photoelectric conversion element PD includes the photoelectric conversion region 21.

[0041] <Second Wiring Layer and Second Semiconductor Layer> As shown in Figure 6, the first wiring layer 30 is a multi-layer wiring layer stacked on the first surface S1. The first wiring layer 30 includes, but is not limited to, an insulating film 31 made of a known insulating material, and wiring such as horizontal wiring and vertical wiring (vias) made of a conductive material provided within the insulating film 31. The insulating film 31 may have a layered structure in which multiple insulating films are stacked. The horizontal wiring is wiring that extends mainly in the horizontal direction. The vertical wiring is wiring that extends mainly in the depth direction. Furthermore, the first wiring layer 30 is provided with gate electrodes of transistors.

[0042] A second semiconductor layer 40 is provided on the first wiring layer 30. The second semiconductor layer 40 is a semiconductor layer provided at a position different from the first semiconductor layer 20 along the depth direction of the photodetector 1. The second semiconductor layer 40 is not in direct contact with the first semiconductor layer 20, and an insulating film, for example, is provided between the two. The first transistor SEL1 and the second transistor SEL2 of the select transistor SEL are provided on the second semiconductor layer 40. The second semiconductor layer 40 is a thin-film semiconductor layer and is different from the first semiconductor layer 20, which is a bulk semiconductor layer. The first transistor SEL1 and the second transistor SEL2 are thin-film transistors (TFTs) provided on the thin-film semiconductor layer. Hereinafter, all transistors provided on the thin-film semiconductor layer are considered to be thin-film transistors. The first transistor SEL1 is an NMOS capable of forming a channel of the same conductivity type (e.g., n-type) as the conductivity type of the photoelectric conversion region 21. The second transistor SEL2 is a PMOS capable of forming a channel of a conductivity type (for example, p-type) different from the conductivity type of the photoelectric conversion region 21.

[0043] The first transistor SEL1 has a first semiconductor region 40a of the second semiconductor layer 40, electrodes 32a and 32b, a gate electrode 33a, and a gate insulating film 34a. The second transistor SEL2 has a second semiconductor region 40b of the second semiconductor layer 40, electrodes 32b and 32c, a gate electrode 33b, and a gate insulating film 34b. When the first semiconductor region 40a and the second semiconductor region 40b are not distinguished from one another, they are simply referred to as the second semiconductor layer 40. When the electrodes 32a, 32b, and 32c are not distinguished from one another, they are simply referred to as the electrode 32. When the gate electrodes 33a and 33b are not distinguished from one another, they are simply referred to as the gate electrode 33. When the gate insulating film 34a and the gate insulating film 34b are not distinguished from one another, they are simply referred to as the gate insulating film 34. The second transistor SEL2, which is a PMOS, is desirably provided in a semiconductor layer other than the first semiconductor layer 20.

[0044] The insulating film 31 (interlayer insulating film) of the first wiring layer 30 is made of, for example, TEOS, silicon nitride, silicon oxide, etc. Also, for example, the insulating film of the first wiring layer 30 is made of, for example, SiCN, SiCON, HfO ２ , Al ２ O ３ , ZrO ２ The insulating film of the first wiring layer 30 may be formed using other insulating materials. The insulating film of the first wiring layer 30 also serves as a passivation film (protective film) for the thin film transistors, and is formed so as to cover the periphery of each thin film transistor.

[0045] The first semiconductor region 40a and the second semiconductor region 40b of the second semiconductor layer 40 are regions where a channel is formed (channel regions). The second semiconductor layer 40 is made of, for example, a two-dimensional material (MoS ２ , W.S. ２ , MoSe ２ , WSe ２ , HfS ２ etc.), oxide semiconductors (InGaZnO, InZnO, ZnO, SnO, TiO ２ The second semiconductor layer 40 may be formed using an organic semiconductor (fullerene, pentacene, rubrene, etc.), carbon nanotubes, hydrogenated amorphous silicon, low-temperature polysilicon, etc. as a channel material.

[0046] One of the electrodes 32a and 32b is the source electrode of the first transistor SEL1, and the other of the electrodes 32a and 32b is the drain electrode of the first transistor SEL1. One of the electrodes 32b and 32c is the source electrode of the second transistor SEL2, and the other of the electrodes 32b and 32c is the drain electrode of the second transistor SEL2. The electrode 32 is formed using a metal material such as copper (Cu), tungsten (W), ruthenium (Ru), or cobalt (Co). The electrode 32 may also be formed using other conductive materials. The electrode 32 may also be formed using a low-resistance conductive material. The electrode 32 may also be formed using a portion of the wiring provided in the first wiring layer 30.

[0047] The gate electrode 33 is formed using a metal material such as Au, Pt, Cu, Ti, W, Pd, TiN, TaN, TiAl, Bi, In, Al, Sc, Co, or Mo. The gate electrode 33 may be formed using other conductive materials. The gate electrode 33 may be formed using a part of the wiring provided in the first wiring layer 30.

[0048] The gate insulating film 34 is made of, for example, silicon oxide, silicon nitride, etc. Also, for example, the gate insulating film 34 is made of Al ２ O ３ , HfO ２ , ZrO ２ , LaO ２ , HfSiO, Y ２ O ３ The gate insulating film 34 is formed using an insulating material such as SiON, etc. The gate insulating film 34 may be made of other insulating materials.

[0049] <<Main Effects of the First Embodiment>> Below, the main effects of the first embodiment will be described, but first, an overview will be provided. Conventionally, the selection transistor SEL has been configured with a single transistor. For example, the selection transistor SEL has been configured with a single NMOS. As a result, in a non-selected pixel 3 b, a leakage current may be supplied to the vertical signal line 11 via the selection transistor SEL in the off state. More specifically, the cut-off voltage of the selection transistor SEL cannot be made sufficiently small, and a leakage current may be supplied to the vertical signal line 11 via the selection transistor SEL in the off state. As a result, the voltage range L that can be output by the amplification transistor AMP of the selected pixel 3 a may be narrowed. More specifically, the voltage range L that can be output by the amplification transistor AMP of the selected pixel 3 a may be limited to between the voltage V1 and the cut-off voltage of the selection transistor SEL.

[0050] Generally, all pixel transistors are NMOS transistors capable of forming the same n-type channel as the photoelectric conversion region 21, and do not include PMOS transistors. A p-type well region is provided between the n-type photoelectric conversion region 21 and the NMOS transistor in the first semiconductor layer 20. The reason why it is difficult to configure pixel transistors with PMOS transistors will be explained below. To provide a PMOS transistor in the cell region 20a, an n-type well region must be provided. However, to ensure an area for providing an n-type well region in the minute cell region 20a, the area occupied by the n-type photoelectric conversion region 21 must be reduced. This affects the saturation charge amount of the photoelectric conversion region 21.

[0051] In contrast, according to the photodetector 1 according to the first embodiment of the present technology, the selection transistor SEL is configured using a CMOS transistor including a parallel connection of an NMOS and a PMOS. Therefore, it is possible to design the cut-off voltage CutLo of the first transistor SEL1 to be lower than the voltage V2, which is the lower limit of the voltage range L that can be output by the amplification transistor AMP. For the NMOS and PMOS of the selection transistor SEL, a cut-off voltage CutLo that does not cause leakage current in the non-selected pixels 3 b can be set. Therefore, even when the vertical signal line 11 is shared by multiple pixels 3, it is possible to prevent the dynamic range of the amplification transistor AMP from being narrowed due to the non-selected pixels 3 b.

[0052] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the selection transistor SEL is configured using a CMOS transistor, and therefore, in the selected pixel 3 a, the output voltage of the amplification transistor AMP can be supplied to the vertical signal line 11 via at least one of an NMOS and a PMOS. As a result, the voltage range L that can be output by the amplification transistor AMP is included in the voltage range M that can pass through the selection transistor SEL in the selected pixel 3 a. The threshold voltage of the amplification transistor AMP can be lowered without any restrictions on the cut-high voltage CutHi of the selection transistor SEL, which makes it possible to suppress an increase in random noise (RN) and to suppress a decrease in the saturation charge amount (Qs) by increasing the operating value of the amplification transistor AMP.

[0053] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the narrowing of the dynamic range is suppressed by using CMOS transistors, which eliminates the need to use a charge pump for lowering the cut-low voltage CutLo, and eliminates the need to secure an area for providing the charge pump on the semiconductor chip 2.

[0054] Furthermore, since the photodetector 1 according to the first embodiment of the present technology uses a CMOS transistor for switching, the on / off potential difference of the transistor can be reduced compared to when using only an NMOS or a PMOS for switching, thereby reducing power consumption.

[0055] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the photodetector 1 includes a first semiconductor layer 20 and a second semiconductor layer 40 provided at a position different from the first semiconductor layer 20 along the depth direction. The PMOS, of the NMOS and PMOS transistors included in the CMOS transistor, is provided in the second semiconductor layer 40. By providing the PMOS in the second semiconductor layer 40, only the NMOS transistor is provided in the cell region 20a of the first semiconductor layer 20. Therefore, the well region provided in the cell region 20a of the first semiconductor layer 20 needs to be only a p-type well region out of p-type and n-type well regions. This eliminates the need to provide an n-type well region in the cell region 20a of the first semiconductor layer 20, which may compress the region where the photoelectric conversion region 21 is provided. This prevents a decrease in the saturated charge amount. Furthermore, by providing the PMOS in the second semiconductor layer 40, it is possible to prevent the area occupied by the select transistor SEL in the cell region 20a of the first semiconductor layer 20 from becoming too large. This prevents the area occupied by the amplification transistor AMP from becoming smaller, and prevents random noise from becoming larger.

[0056] Modifications of the First Embodiment Modifications of the first embodiment will be described below. In each of the following modifications, the positions of the first transistor SEL1 and the second transistor SEL2 may be interchanged. In such cases, the routing of wiring related to the first transistor SEL1 and the second transistor SEL2 may be appropriately changed according to the equivalent circuit diagram shown in FIG.

[0057] 7 , the photodetector 1 according to the first modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The second semiconductor layer 40 is a bulk semiconductor layer rather than a thin film. The first transistor SEL1 and the second transistor SEL2 included in the select transistor SEL are provided in the second semiconductor layer 40.

[0058] One surface of the second semiconductor layer 40 is the third surface S3, and the other surface is the fourth surface S4. The third surface S3 may be referred to as the element formation surface or the main surface, and the fourth surface S4 may be referred to as the back surface. In this modification, the fourth surface S4 faces the first surface S1 of the first semiconductor layer 20. The second semiconductor layer 40 is made of a semiconductor substrate. The second semiconductor layer 40 is made of, for example, a single-crystal silicon substrate, although this is not limited thereto. The first transistor SEL1 and the second transistor SEL2 provided in the second semiconductor layer 40 are not thin-film transistors, but are ordinary planar transistors provided in a bulk semiconductor layer.

[0059] A second wiring layer 50 is stacked on the third surface S3 of the second semiconductor layer 40. The second wiring layer 50 is a multi-layer wiring layer. The second wiring layer 50 includes, but is not limited to, an insulating film 51 made of a known insulating material and wiring such as horizontal wiring and vertical wiring (vias) formed within the insulating film 51 and made of a conductive material. The insulating film 51 may have a layered structure in which multiple insulating films are stacked. Examples of insulating materials that constitute the insulating film 51 include silicon oxide, silicon nitride, and silicon oxynitride (SiON). Examples of conductive materials include metal materials such as copper (Cu), aluminum (Al), and tungsten (W), and semiconductor materials such as silicon made conductive by impurities. The material that constitutes the second wiring layer 50 may be the same as the material that constitutes the first wiring layer 30.

[0060] The photodetector 1 has a through conductor TSV that constitutes part of the wiring of the equivalent circuit of the pixel 3. The through conductor TSV penetrates the second semiconductor layer 40.

[0061] The photodetector 1 according to the first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0062] 8 , the photodetector 1 according to Modification 2 of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, and a second semiconductor layer 40 are stacked in that order. The second semiconductor layer 40 is a bulk semiconductor layer rather than a thin film. The first transistor SEL1 and the second transistor SEL2 of the select transistor SEL are provided in the second semiconductor layer 40. More specifically, the first transistor SEL1, which is an NMOS transistor, is provided in a p-type well region 41, and the second transistor SEL2, which is a PMOS transistor, is provided in an n-type well region 42. In this modification, the third surface S3 faces the first surface S1 of the first semiconductor layer 20.

[0063] The photodetector 1 has connection pads C1 and C2 that electrically connect wirings to each other. The connection pad C1 is provided on the first wiring layer 30, and the connection pad C2 is provided on the second wiring layer 50. The connection pads C1 and C2 form a pair of connection pads and are joined to each other. For example, the connection pads C1 and C2 electrically connect the wirings provided on the first wiring layer 30 and the second wiring layer 50.

[0064] The photodetector 1 according to the second modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0065] 9 , the photodetector 1 according to Modification 3 of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A of a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The second semiconductor layer 40 includes the first layer 40A and a second layer 40B that is provided at a different position in the depth direction from the first layer 40A. The first layer 40A is not in direct contact with the second layer 40B, and an insulating film, for example, is provided between the two.

[0066] The first layer 40A is a bulk semiconductor layer, not a thin film. The first layer 40A has a configuration similar to that of the second semiconductor layer 40 described in Modification 1 of the first embodiment. The fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The second transistor SEL2 is provided in the first layer 40A. The second layer 40B is a thin film semiconductor layer and is provided in the second wiring layer 50. The second layer 40B has a configuration similar to that of the second semiconductor layer 40 described in the first embodiment. The first transistor SEL1 is provided in the second layer 40B. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A. In this way, the first transistor SEL1 and the second transistor SEL2 may be provided separately in a thin film semiconductor layer and a bulk semiconductor layer.

[0067] The photodetector 1 according to the third modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0068] 10 , the photodetector 1 according to the fourth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A, and a second wiring layer 50 are stacked in that order. A fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided on the first layer 40A. The second layer 40B is a thin-film semiconductor layer and is provided on the first wiring layer 30. The first transistor SEL1 is provided on the second layer 40B. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A.

[0069] The photodetector 1 according to the fourth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0070] 11 , the photodetector 1 according to the fifth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, and a first layer 40A are stacked in that order. The third surface S3 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided on the first layer 40A. The second layer 40B is a thin-film semiconductor layer and is provided on the first wiring layer 30. The first transistor SEL1 is provided on the second layer 40B. The photodetector 1 has connection pads C1 and C2.

[0071] The photodetector 1 according to the fifth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0072] 12 , the photodetector 1 according to the sixth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, and a first layer 40A are stacked in that order. The third surface S3 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided on the first layer 40A. The second layer 40B is a thin-film semiconductor layer and is provided on the second wiring layer 50. The first transistor SEL1 is provided on the second layer 40B. The photodetector 1 has connection pads C1 and C2.

[0073] The photodetector 1 according to the sixth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0074] 13 , the photodetector 1 according to the seventh modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A, a second wiring layer 50, a third wiring layer 60, and a second layer 40B are stacked in this order. The fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided in the first layer 40A. The second layer 40B is a bulk semiconductor layer, not a thin film. The second layer 40B has a configuration similar to that of the first layer 40A. The first transistor SEL1 is provided in the second layer 40B.

[0075] A third wiring layer 60 is stacked on the fifth surface S5 of the second layer 40B. The third wiring layer 60 is a multi-layer wiring layer. The third wiring layer 60 includes, but is not limited to, an insulating film 61 made of a known insulating material and wiring such as horizontal wiring and vertical wiring (vias) made of a conductive material disposed within the insulating film 61. The insulating film 61 may have a layered structure in which multiple insulating films are stacked. Examples of insulating materials that constitute the insulating film 61 include silicon oxide, silicon nitride, and silicon oxynitride (SiON). Examples of conductive materials include metal materials such as copper (Cu), aluminum (Al), and tungsten (W), and semiconductor materials such as silicon that has been made conductive by impurities. The material that constitutes the third wiring layer 60 may be the same as the material that constitutes the first wiring layer 30.

[0076] The photodetector 1 has connection pads C1 and C2 that electrically connect wirings to each other. The connection pad C1 is provided on the second wiring layer 50, and the connection pad C2 is provided on the third wiring layer 60. For example, the connection pads C1 and C2 electrically connect wirings provided on the second wiring layer 50 and wirings provided on the third wiring layer 60. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A.

[0077] The photodetector 1 according to the seventh modification of the first embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment described above.

[0078] 14 , the photodetector 1 according to the eighth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 50, a first layer 40A, a third wiring layer 60, and a second layer 40B are stacked in this order. The third surface S3 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is a bulk semiconductor layer. The second transistor SEL2 is provided in the first layer 40A. The second layer 40B is a bulk semiconductor layer, not a thin film. The second layer 40B has a configuration similar to that of the first layer 40A. The first transistor SEL1 is provided in the second layer 40B.

[0079] The photodetector 1 has connection pads C1 and C2 that electrically connect wirings to each other. The connection pad C1 is provided on the first wiring layer 30, and the connection pad C2 is provided on the second wiring layer 50. For example, the connection pads C1 and C2 electrically connect wirings provided on the first wiring layer 30 and wirings provided on the second wiring layer 50. The photodetector 1 has a through conductor TSV that penetrates the first layer 40A.

[0080] The photodetector 1 according to the eighth modified example of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0081] 15 , the photodetector 1 according to the ninth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20 and a first wiring layer 30 are stacked in that order. A second semiconductor layer 40 is provided on the first wiring layer 30. The second semiconductor layer 40 is a thin-film semiconductor layer and is different from the bulk first semiconductor layer 20. The second semiconductor layer 40 is a semiconductor layer provided at a position different from the first semiconductor layer 20 in the depth direction of the photodetector 1. The first transistor SEL1 is provided in the first semiconductor layer 20, and the second transistor SEL2 is provided in the second semiconductor layer 40. The first transistor SEL1 is an NMOS, and therefore can be provided in the first semiconductor layer 20.

[0082] The photodetector 1 according to the ninth modification of the first embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment described above.

[0083] 16 shows a photodetector 1 according to a tenth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the first modification of the first embodiment shown in FIG. 7 in that the first transistor SEL1 is provided in the first semiconductor layer 20. The first transistor SEL1 is an NMOS, and therefore can be provided in the first semiconductor layer 20.

[0084] The photodetector 1 according to the tenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0085] <Modification 11> As shown in FIG. 17, a photodetector 1 according to Modification 11 of the first embodiment differs from the photodetector 1 according to Modification 10 in the routing of wiring.

[0086] The photodetector 1 according to the eleventh modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0087] 18 shows a photodetector 1 according to a twelfth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the second modification of the first embodiment shown in FIG. 8 in that the first transistor SEL1 is provided in the first semiconductor layer 20. The first transistor SEL1 is an NMOS, and therefore can be provided in the first semiconductor layer 20.

[0088] The photodetector 1 according to the twelfth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0089] 19 shows a photodetector 1 according to a thirteenth modification of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the first modification of the first embodiment shown in FIG. 7 in that the amplification transistor AMP is provided in the second semiconductor layer 40.

[0090] The photodetector 1 according to the thirteenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0091] 20 , the photodetector 1 according to the fourth modification of the first embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a first layer 40A of a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The first layer 40A is a bulk semiconductor layer, not a thin film. The fourth surface S4 of the first layer 40A faces the first surface S1 of the first semiconductor layer 20. The first layer 40A is provided with an amplifying transistor AMP. The second layer 40B is a thin film semiconductor layer and is provided in the second wiring layer 50. The first transistor SEL1 and the second transistor SEL2 are provided in the second layer 40B. The photodetector 1 has a through conductor TSV penetrating the first layer 40A.

[0092] The photodetector 1 according to the fourteenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0093] 21 shows a photodetector 1 according to a modification 15 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the modification 14 of the first embodiment shown in FIG. 20 in that the second transistor SEL2 is provided on the first layer 40A.

[0094] The photodetector 1 according to the fifteenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0095] 22 shows a photodetector 1 according to a modification 16 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the modification 7 of the first embodiment shown in FIG. 13 in that the second transistor SEL2 is provided on the second layer 40B and the amplification transistor AMP is provided on the first layer 40A.

[0096] The photodetector 1 according to the sixteenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0097] <Modification 17> Figure 23 shows a photodetector 1 according to Modification 17 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 16 of the first embodiment shown in Figure 22 in that the second semiconductor layer 40 has a third layer 40C. The third layer 40C is a thin-film semiconductor layer and is provided in the second wiring layer 50. The third layer 40C has a configuration similar to that of the second semiconductor layer 40 described in the first embodiment. The second transistor SEL2 is provided in the third layer 40C.

[0098] The photodetector 1 according to the seventeenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0099] 24 shows a photodetector 1 according to a modification 18 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the modification 17 of the first embodiment shown in FIG. 23 in that a third layer 40C is provided in the third wiring layer 60. The second transistor SEL2 is provided in the third layer 40C.

[0100] The photodetector 1 according to the eighteenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0101] 25 shows a photodetector 1 according to a modification 19 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the modification 2 of the first embodiment shown in FIG. 8 in that the amplification transistor AMP is provided in the second semiconductor layer 40.

[0102] The photodetector 1 according to the nineteenth modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0103] 26 shows a photodetector 1 according to Modification 20 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to Modification 6 of the first embodiment shown in FIG. 12 in that the amplification transistor AMP is provided in the first layer 40A and the second transistor SEL2 is provided in the second layer 40B.

[0104] The photodetector 1 according to the modification 20 of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0105] 27 shows a photodetector 1 according to a modification 21 of the first embodiment. The photodetector 1 according to this modification differs from the photodetector 1 according to the modification 20 of the first embodiment shown in FIG. 26 in that the second transistor SEL2 is provided on the first layer 40A.

[0106] The photodetector 1 according to the twenty-first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0107] 28 and 29 , a second embodiment of the present technology will be described below. In this embodiment, instead of the select transistor SEL, the reset transistor RST is configured as a CMOS transistor (CMOS circuit). The CMOS transistor (CMOS circuit) includes a first transistor RST1 and a second transistor RST2 connected in parallel. The first transistor RST1 is an NMOS (n-channel conductivity type MOSFET), and the second transistor RST2 is a PMOS (p-channel conductivity type MOSFET).

[0108] 28, the reset transistor RST has a fourth terminal d electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a third terminal c electrically connected to the power supply line Vdd (or power supply line VBO) and the drain region of the amplifier transistor AMP. The drain region of the first transistor RST1 and the source region of the second transistor RST2 are connected to the third terminal c. The source region of the first transistor RST1 and the drain region of the second transistor RST2 are connected to the fourth terminal d.

[0109] 29 , the photodetector 1 has a layered structure in which, for example, a first semiconductor layer 20 and a first wiring layer 30 are layered in that order. The photodetector 1 has a second semiconductor layer 40 provided on the first wiring layer 30. The second semiconductor layer 40 is a thin-film semiconductor layer and is different from the bulk first semiconductor layer 20. The first transistor RST1 and the second transistor RST2 are thin-film transistors provided on the second semiconductor layer 40. The second transistor RST2, which is a PMOS, is desirably provided in a semiconductor layer other than the first semiconductor layer 20.

[0110] <<Major Effects of the Second Embodiment>> The major effects of the second embodiment will be described below, but first, a brief overview will be provided. Conventionally, the reset transistor RST is configured with a single transistor. For example, the reset transistor RST is configured with a single NMOS. The reset transistor RST has the function of initializing the charge storage region FD. When the reset transistor RST is turned on, electrons accumulated in the charge storage region FD are discharged, and the voltage of the charge storage region FD rises to the power supply voltage Vdd. The reset transistor RST then turns off. After the initialization of the charge storage region FD is complete, the transfer transistor TR turns on. When the transfer transistor TR is turned on, signal charges (electrons) generated by the photoelectric conversion element PD are transferred to the charge storage region FD, and the voltage of the charge storage region FD drops. However, the minimum value of the voltage of the charge storage region FD is restricted by the cut-off voltage of the reset transistor RST. Therefore, it is difficult for the minimum value of the voltage of the charge storage region FD to be smaller than the cut-off voltage of the reset transistor RST. Therefore, the voltage range that can be output from the charge storage region FD is restricted by the cut-off voltage of the reset transistor RST, making it difficult to sufficiently lower the lower limit of the voltage input to the gate electrode of the amplification transistor AMP.

[0111] Furthermore, the conventional reset transistor RST suffers from a reset field-through phenomenon, in which the potential of the charge storage region FD drops from the Vdd potential when the reset transistor RST switches from on to off, restricting the voltage range that can be output from the charge storage region FD.

[0112] In the photodetector 1 according to the second embodiment, the reset transistor RST is configured as a CMOS transistor, and therefore the same effects as those of the photodetector 1 according to the first embodiment can be obtained. More specifically, the output range of the charge accumulation region FD is less likely to be restricted by the cut-off voltage of the reset transistor RST, and therefore it is possible to prevent the dynamic range of the voltage range that the charge accumulation region FD can output from being narrowed.

[0113] Furthermore, in the photodetector 1 according to the second embodiment, the reset transistor RST is configured as a CMOS transistor, so the reset field-through effects of the NMOS and PMOS cancel each other out. More specifically, the voltage of the charge storage region FD, which drops due to the reset field-through effect of the NMOS, rises due to the reset field-through effect of the PMOS. As a result, the output range of the charge storage region FD is less susceptible to the reset field-through effect, and the dynamic range of the amplification transistor AMP can be prevented from being narrowed.

[0114] Modifications of the Second Embodiment Modifications of the second embodiment will be described below. In each of the following modifications, the positions of the first transistor RST1 and the second transistor RST2 may be interchanged. In this case, the routing of the wiring related to the first transistor RST1 and the second transistor RST2 may be appropriately changed according to the equivalent circuit diagram shown in FIG.

[0115] <Modification 1> As shown in FIG. 30 , the photodetector 1 according to Modification 1 of the second embodiment has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second semiconductor layer 40, and a second wiring layer 50 are stacked in that order. The second semiconductor layer 40 is a bulk semiconductor layer rather than a thin film. The first transistor RST1 and the second transistor RST2 included in the reset transistor RST are provided in the second semiconductor layer 40. The first transistor RST1 and the second transistor RST2 are not thin film transistors but ordinary planar transistors provided in a bulk semiconductor layer. In this modification, the fourth surface S4 faces the first surface S1 of the first semiconductor layer 20. The photodetector 1 has a through conductor TSV penetrating the second semiconductor layer 40.

[0116] The photodetector 1 according to the first modified example of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0117] <Modification 2> In the photodetector 1 according to Modification 2 of the second embodiment, the positions of the first transistor RST1 and the second transistor RST2 are not limited to the positions described in the already-described second embodiment ( FIG. 29 ) and Modification 1 of the second embodiment ( FIG. 30 ). The positions of the first transistor RST1 and the second transistor RST2 may be determined with reference to the positions of the transistors shown in Modifications 2 ( FIG. 8 ) to 12 ( FIG. 18 ) of the first embodiment.

[0118] The photodetector 1 according to the second modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0119] Third Embodiment A third embodiment of the present technology will be described below. In this embodiment, the selection transistor SEL according to the first embodiment or any of its modifications and the reset transistor RST according to the second embodiment or any of its modifications are combined.

[0120] The photodetector 1 according to the third embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment and the photodetector 1 according to the second embodiment.

[0121] Fourth Embodiment A fourth embodiment of the present technology shown in FIGS. 31 and 32 will be described below. In this embodiment, the photodetector 1 includes an inverter circuit INV that inverts the positive and negative polarities of an input voltage and outputs the inverted voltage. The inverter circuit INV is provided for each of the multiple selection transistors SEL (CMOS transistors). The inverter circuit INV is connected to only one of the gate electrode of the first transistor SEL1 and the gate electrode of the second transistor SEL2. By providing the inverter circuit INV, the voltages simultaneously supplied to the gate electrode of the first transistor SEL1 and the gate electrode of the second transistor SEL2 are voltages of opposite polarities.

[0122] As shown in FIG. 31 , the inverter circuit INV includes a third transistor INV3 and a fourth transistor INV4 connected in series. The third transistor INV3 is an NMOS, and the fourth transistor INV4 is a PMOS. The inverter circuit INV inverts the voltage sel input to terminal e and supplies the inverted voltage to the gate electrode of the second transistor SEL2. The voltage sel input to terminal e is input to the gate electrode of the first transistor SEL1 without passing through the inverter circuit INV. Therefore, the first transistor SEL1 and the second transistor SEL2 can be turned on simultaneously, and the first transistor SEL1 and the second transistor SEL2 can be turned off simultaneously.

[0123] 32 , the photodetector 1 has a second semiconductor layer 40 provided on the first wiring layer 30. The second semiconductor layer 40 is a thin-film semiconductor layer. The third transistor INV3 and the fourth transistor INV4 of the inverter circuit INV are thin-film transistors provided on the second semiconductor layer 40. The fourth transistor INV4, which is a PMOS, is desirably provided in a semiconductor layer other than the first semiconductor layer 20.

[0124] The photodetector 1 according to the fourth embodiment also provides the same effects as the photodetector 1 according to the first embodiment. The inverter circuit INV can be provided in the select transistor SEL according to the first embodiment and its modifications.

[0125] Modifications of the Fourth Embodiment Modifications of the fourth embodiment will be described below. In each of the following modifications, the positions of the third transistor INV3 and the fourth transistor INV4 may be interchanged. In this case, the routing of the wiring related to the third transistor INV3 and the fourth transistor INV4 may be appropriately changed according to the equivalent circuit diagram shown in FIG.

[0126] <Modification 1> In a photodetector 1 according to Modification 1 of the fourth embodiment, an inverter circuit INV is provided for each of the multiple reset transistors RST. The inverter circuit INV is connected to only one of the gate electrode of the first transistor RST1 and the gate electrode of the second transistor RST2. By providing the inverter circuit INV, the voltages simultaneously supplied to the gate electrode of the first transistor RST1 and the gate electrode of the second transistor RST2 have opposite polarities.

[0127] The photodetector 1 according to the first modification of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment. The inverter circuit INV can be provided for the reset transistor RST according to the second embodiment and its modifications.

[0128] <Modification 2> In a photodetector 1 according to Modification 2 of the fourth embodiment, an inverter circuit INV is provided for each of the selection transistor SEL and the reset transistor RST according to the third embodiment.

[0129] The photodetector 1 according to the second modification of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above.

[0130] <Modification 3> In the photodetector 1 according to Modification 3 of the fourth embodiment, the third transistor INV3 and the fourth transistor INV4 may be provided in a bulk semiconductor layer, or may be provided separately in a thin-film semiconductor layer and a bulk semiconductor layer. The positions of the third transistor INV3 and the fourth transistor INV4 may be determined with reference to the positions of the transistors shown in the already-described embodiments and their modifications. The third transistor INV3 may be provided in the first semiconductor layer 20 or the second semiconductor layer 40. Furthermore, in the photodetector 1 according to Modification 3 of the fourth embodiment, the stacked structure and wiring layout of the photodetector 1 may be similar to the stacked structures shown in the already-described embodiments and their modifications.

[0131] The photodetector 1 according to the third modification of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above.

[0132] [Fifth Embodiment] In the already-described embodiments and their modifications, the transistors provided in the bulk semiconductor layer are planar transistors with a two-dimensional structure, but the present technology is not limited to this. In the photodetector 1 according to Modification 3 of the fourth embodiment, any transistor provided in the bulk semiconductor layer may be a transistor with a three-dimensional structure. A three-dimensional transistor is, for example, a transistor having a structure similar to that of the amplifier transistor 34 described in Patent Document 2.

[0133] The photodetector 1 according to the fifth embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment.

[0134] Sixth Embodiment 1. Application Example to Electronic Devices Next, an electronic device 100 according to a sixth embodiment of the present technology will be described, as shown in Fig. 33 . The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector device 1 as the solid-state imaging device 101.

[0135] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed in accordance with the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0136] With this configuration, the electronic device 100 can prevent the dynamic range of the solid-state imaging device 101 from being narrowed, thereby improving the image quality of the video signal.

[0137] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0138] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector 1 according to any of the first to fifth embodiments and modified versions of those embodiments, or a photodetector 1 according to a combination of at least two of the first to fifth embodiments and modified versions of those embodiments.

[0139] [Other Embodiments] As described above, the present technology has been described by the first to sixth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0140] For example, it is also possible to combine the technical ideas described in the first to sixth embodiments with each other.

[0141] Furthermore, the present technology can be applied to photodetection devices in general, including not only the solid-state imaging device as the image sensor described above but also distance measurement sensors, also known as ToF (Time of Flight) sensors, that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected by the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The above-described CMOS transistor structure can be adopted as the structure of this distance measurement sensor.

[0142] Furthermore, for example, the materials cited as constituting the above-mentioned components may contain additives, impurities, and the like.

[0143] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0144] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0145] The present technology may be configured as follows: (1) A photodetector including a photoelectric conversion element, a charge accumulation region, a reset transistor, an amplification transistor, and a selection transistor connected in series to the amplification transistor, wherein at least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor. (2) The photodetector according to (1), including a first semiconductor layer including the photoelectric conversion element, and a second semiconductor layer provided at a position different from the first semiconductor layer in the depth direction, wherein the first semiconductor layer includes a transistor of a first conductivity type, and when the NMOS transistor and the PMOS transistor included in the CMOS transistor are defined as a first transistor and a second transistor, respectively, the second transistor is provided in the second semiconductor layer. (3) The photodetector according to (2), wherein the first transistor is provided in the first semiconductor layer or the second semiconductor layer. (4) The photodetector according to (2) or (3), wherein at least one of the first transistor and the second transistor is a thin-film transistor. (5) The photodetector according to any one of (2) to (5), wherein the second semiconductor layer includes a first layer and a second layer provided at a different position from the first layer in the depth direction, and the second transistor is provided in the first layer or the second layer. (6) The photodetector according to any one of (2) to (6), wherein the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers. (7) The photodetector according to (6), wherein the photodetector includes a pair of connection pads that electrically connect wirings to each other. (8) The photodetector according to any one of (2) to (7), wherein the photodetector includes an inverter circuit provided for each CMOS transistor, inverting an input voltage and outputting it, and the inverter circuit is connected to only one of the gate electrode of the first transistor and the gate electrode of the second transistor.(9) The photodetector according to (8), wherein the inverter circuit includes an NMOS transistor and a PMOS transistor, and when a first conductivity type transistor of the NMOS transistor and the PMOS transistor included in the inverter circuit is defined as a third transistor and a second conductivity type transistor is defined as a fourth transistor, the fourth transistor is provided in the second semiconductor layer. (10) The photodetector according to (9), wherein the third transistor is provided in the first semiconductor layer or the second semiconductor layer. (11) The photodetector according to (9) or (10), wherein at least one of the third transistor and the fourth transistor is a thin film transistor. (12) The photodetector according to any of (9) to (11), wherein the second semiconductor layer includes a first layer and a second layer provided at a position different from the first layer in the depth direction, and the fourth transistor is provided in the first layer or the second layer. (13) The photodetector according to any one of (9) to (12), wherein the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers. (14) The photodetector according to (13), further comprising a pair of connection pads that electrically connect wirings to each other. (15) An electronic device comprising: a photodetector and an optical system that forms an image light from a subject on the photodetector, the photodetector comprising: a photoelectric conversion element; a charge accumulation region capable of accumulating signal charge generated by the photoelectric conversion element; a reset transistor that can initialize the charge accumulation region; an amplification transistor that outputs a voltage according to the amount of signal charge accumulated in the charge accumulation region; and a selection transistor connected in series to the amplification transistor, wherein at least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

[0146] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0147] 1 Photodetector device 20 First semiconductor layer 21 Photoelectric conversion region 22, FD Charge storage region 34 Amplifying transistor 40 Second semiconductor layer 40A First layer 40B Second layer 100 Electronic device 102 Optical system AMP Amplifying transistor C1, C2 Connection pad INV Inverter circuit INV3 Third transistor INV4 Fourth transistor PD Photoelectric conversion element RST Reset transistor RST1 First transistor RST2 Second transistor sel Voltage SEL Select transistor SEL1 First transistor SEL2 Second transistor

Claims

1. A photodetector comprising: a photoelectric conversion element; a charge accumulation region; a reset transistor; an amplification transistor; and a selection transistor connected in series to the amplification transistor, wherein at least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

2. A photodetector according to claim 1, comprising: a first semiconductor layer including the photoelectric conversion element; and a second semiconductor layer provided at a position different from that of the first semiconductor layer in the depth direction, wherein the first semiconductor layer includes a transistor of a first conductivity type, and when the NMOS transistor and the PMOS transistor included in the CMOS transistor are defined as a first transistor and a second transistor, respectively, the second transistor is provided in the second semiconductor layer.

3. The photodetector device according to claim 2, wherein the first transistor is provided in the first semiconductor layer or the second semiconductor layer.

4. The photodetector device according to claim 2, wherein at least one of the first transistor and the second transistor is a thin film transistor.

5. The photodetector device according to claim 2, wherein the second semiconductor layer includes a first layer and a second layer provided at a different position in the depth direction from the first layer, and the second transistor is provided in the first layer or the second layer.

6. The photodetector device according to claim 2, wherein the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers.

7. The photodetector according to claim 6, further comprising a pair of connection pads for electrically connecting the wirings together.

8. The photodetector according to claim 2, further comprising an inverter circuit provided for each of the CMOS transistors, which inverts an input voltage and outputs the inverted voltage, and the inverter circuit is connected to only one of the gate electrode of the first transistor and the gate electrode of the second transistor.

9. The photodetector according to claim 8, wherein the inverter circuit includes an NMOS transistor and a PMOS transistor, and when the NMOS transistor and the PMOS transistor included in the inverter circuit have a first conductivity type transistor as a third transistor and a second conductivity type transistor as a fourth transistor, the fourth transistor is provided in the second semiconductor layer.

10. The photodetector device according to claim 9, wherein the third transistor is provided in the first semiconductor layer or the second semiconductor layer.

11. The photodetector device according to claim 9, wherein at least one of the third transistor and the fourth transistor is a thin film transistor.

12. The photodetector device according to claim 9, wherein the second semiconductor layer includes a first layer and a second layer provided at a different position in the depth direction from the first layer, and the fourth transistor is provided in the first layer or the second layer.

13. The photodetector device according to claim 9, wherein the first semiconductor layer and the second semiconductor layer are bulk semiconductor layers.

14. The photodetector device according to claim 13, further comprising a pair of connection pads for electrically connecting the wirings together.

15. An electronic device comprising: a photodetector; and an optical system that focuses image light from a subject on the photodetector; wherein the photodetector comprises: a photoelectric conversion element; a charge accumulation region capable of accumulating signal charge generated by the photoelectric conversion element; a reset transistor capable of initializing the charge accumulation region; an amplification transistor that outputs a voltage according to the amount of signal charge accumulated in the charge accumulation region; and a selection transistor connected in series to the amplification transistor; and at least one of the reset transistor and the selection transistor is configured using a CMOS transistor including a parallel connection of an NMOS transistor and a PMOS transistor.

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