Integrated circuit wafer, integrated circuit board, and integrated circuit electron acceleration apparatus

Abstract

The present invention relates to an integrated circuit, an integrated circuit board, and an integrated circuit electron acceleration apparatus and, more specifically, to an integrated circuit wafer, an integrated circuit board and an integrated circuit electron acceleration apparatus, capable of improving the performance of a semiconductor by sufficiently accelerating the flow of a signal even in a narrow channel by using semiconductor microfabrication processes such as Planar, Fin F, and MBCFET.

Description

Integrated circuit wafers, integrated circuit substrates, and integrated circuit electron accelerators

[0001] The present invention relates to an integrated circuit, an integrated circuit substrate, and an integrated circuit electron accelerator, and more particularly, to an integrated circuit wafer, an integrated circuit substrate, and an integrated circuit electron accelerator capable of sufficiently accelerating the flow of signals even in a narrow channel through a semiconductor microprocess such as a planar, FinFET, or MBCFET to improve the performance of a semiconductor.

[0002] The semiconductor market has been advancing various technologies, such as integration and miniaturization, for about 40 years.

[0003] Typically, as semiconductors become smaller, their speed increases and power consumption decreases, so the domestic and international semiconductor industries are struggling to gain leadership in ultra-fine processes.

[0004] Recently, semiconductor miniaturization technology development has become a core technology in the semiconductor industry, including the development of technologies to produce more miniaturized chips using a single wafer.

[0005] These semiconductors are composed of a source, drain, and gate formed on a substrate, and allow current to flow by moving carriers such as electrons or holes through a channel existing between the source and drain.

[0006] Additionally, the source supplies electrons, the drain receives electrons, and the gate controls whether the current in the active layer flows or not.

[0007] However, as semiconductors become smaller, the length of the channel, which is the distance through which carriers move, becomes shorter, and the device characteristics deteriorate due to current leakage and voltage reduction, which results in a high number of defective products and a low production yield.

[0008] Meanwhile, the phenomenon that occurs as the channel length of a semiconductor decreases is called the short channel effect, and representative examples of the short channel effect include the drain-induced barrier lowering (DIBL) phenomenon and the punch-through phenomenon.

[0009] First, the drain-induced barrier lowering (DIBL) phenomenon occurs when a semiconductor is manufactured under the same conditions, and the threshold voltage (V) of a device with a long channel length is lowered. T ) The threshold voltage (V) of a channel with a shorter channel length T ) comes from this small thing.

[0010] Threshold voltage (V T ) refers to the gate voltage at the point where the switch is turned on, allowing current to flow within the semiconductor.

[0011] That is, the threshold voltage (V T ) is the minimum gate voltage value (V) required to form a channel between the source and drain. gs ) can be said.

[0012] As the channel length decreases due to miniaturization of semiconductor devices, the voltage at the drain (V) becomes larger as the distance between the source and drain becomes closer, causing the potential barrier that carriers must overcome when moving from the source to the drain due to electrostatic coupling. ds ) is affected by the threshold voltage (V) within the channel. T ) will gradually decrease.

[0013] This drain-induced barrier lowering (DIBL) phenomenon is called threshold voltage (V T ) can cause leakage current that flows even when the switch is not turned on in the subthreshhold region where a lower voltage is applied.

[0014] Additionally, as the drain voltage increases, the depletion region around the drain expands and meets the depletion region of the source at the bottom of the substrate. At this time, charge flow between the source and drain becomes easier, and a punch-through phenomenon may occur in which current flows even without applying voltage.

[0015] That is, if the single-channel effect persists, there is a problem that power supply may not be smooth due to leakage current caused by voltage reduction.

[0016] In addition, the voltage control function is lost due to the internal electric field, and the device characteristics deteriorate due to increased power consumption.

[0017] Accordingly, research is being conducted to control the channel area by using structures in which the gate surrounds multiple sides of the channel, such as planar, FinFET, and MBCFET structures in the MOSFET structure, or to develop new materials with low dielectric constants, which are sensitive to external electrical interference.

[0018] The principle behind new materials with low permittivity is that a low permittivity reduces electrical interference, which allows for smaller spacing between metal wires within semiconductor devices, making it possible to make semiconductors smaller.

[0019] However, although research on the development of semiconductor structures or materials as a direct solution to improve the single-channel effect is actively being conducted, there are not many technologies that can indirectly supply electrical signals paralyzed by the single-channel effect from the outside.

[0020] Therefore, there is a need to develop a technology that enables excellent signal transmission even in narrow channels by accelerating electrons using a magnetic field in the wires connected to semiconductor circuit elements.

[0021] The present invention has been devised to solve the above-described problems, and the purpose of the present invention is to provide an integrated circuit wafer, an integrated circuit substrate, and an integrated circuit electron accelerator that can overcome the phenomenon of current leakage due to the single-channel effect and electric signal paralysis due to voltage reduction by accelerating electrons by applying a magnetic field pulse to a wire connected to the integrated circuit.

[0022] In order to achieve the above object, the present invention provides an integrated circuit wafer comprising: a wafer capable of integrating a semiconductor circuit; a coil layer formed on the wafer and coupled to a metal layer with an insulating layer therebetween; a solenoid array in which a plurality of solenoids are spaced apart from each other along a power line and a clock signal line of an integrated circuit and which form a magnetic field when pulse power is applied; a controller for supplying the pulse power to the solenoid array; and an integrated circuit connected to the power line and the clock signal line and receiving power and a clock signal accelerated through a magnetic field induced from the solenoid array; wherein the solenoid array, the controller, and the integrated circuit are formed on the one wafer and are mounted insulated above or below the power line and the clock signal line connected to the integrated circuit, and are characterized in that the power and clock signal supplied to the integrated circuit are accelerated.

[0023] In addition, the present invention provides an integrated circuit substrate comprising a PCB substrate having an integrated circuit mounted thereon, a coil layer coupled to a metal layer with an insulating layer interposed therebetween on the PCB substrate, a solenoid array in which a plurality of solenoids are arranged spaced apart from each other along a power line and a clock signal line of the integrated circuit to form a magnetic field when pulse power is applied, and a controller for supplying the pulse power to the solenoid array, wherein the solenoid array and the controller are formed on the PCB substrate and are mounted in an insulated manner above or below the power line and the clock signal line connected to the integrated circuit on the PCB substrate, and are characterized in that they accelerate the power and clock signal supplied to the integrated circuit.

[0024] In addition, the present invention provides an integrated circuit electron accelerator device comprising a solenoid array in which a plurality of solenoids are spaced apart from each other and formed of a coil layer coupled to a metal layer with an insulating layer in between and which form a magnetic field when pulse power is applied, a controller for supplying the pulse power to the solenoids, and a chip for a solenoid array on which the solenoid array and the controller can be mounted, and characterized in that the solenoid array and the controller can be separately mounted on a wire of a semiconductor integrated circuit to be mounted as chips formed on one chip for the solenoid array.

[0025] The present invention has the following excellent effects.

[0026] In addition, the present invention has the advantage of increasing the yield of producing good semiconductor products in any type of process by overcoming the phenomenon of reduced electrical signal transmission resulting from the single-channel effect through electron acceleration.

[0027] In addition, the integrated circuit wafer according to an embodiment of the present invention has an advantage in that it can reduce the electrical resistance between the wires by accelerating the electron movement speed of the wires connected between the integrated circuits through the solenoid array and the solenoid controller.

[0028] In addition, the present invention can reduce noise generated in an electronic circuit by reducing overshoot resulting from digital signal conversion of a semiconductor.

[0029] In addition, the present invention has the advantage of increasing the energy efficiency of semiconductors and reducing heat generation.

[0030] In addition, the present invention has the advantage of being able to accelerate electrons flowing in power lines and clock signal lines by directly placing a solenoid array on a PCB on which an already manufactured wafer is mounted or by manufacturing it in chip form and implanting it.

[0031] FIG. 1 is a drawing illustrating an integrated circuit wafer according to an embodiment of the present invention;

[0032] Figure 2 is a side view of a solenoid according to an embodiment of the present invention;

[0033] FIG. 3 is a drawing illustrating an integrated circuit substrate according to another embodiment of the present invention;

[0034] FIG. 4 is a drawing illustrating an integrated circuit electron accelerator device according to another embodiment of the present invention.

[0035] <Explanation of symbols>

[0036] 10: PCB board

[0037] 20: Existing integrated circuits

[0038] 21: Chips for existing integrated circuits

[0039] 100: Integrated circuit wafer

[0040] 110: Solenoid array

[0041] 111: Solenoid

[0042] 111a: Metal layer

[0043] 111b: Coil layer

[0044] 111c insulation layer

[0045] 120: Integrated circuit

[0046] 121: Power line

[0047] 122: Clock signal line

[0048] 130: Wafer

[0049] 140: Chip for solenoid array

[0050] 150: Controller

[0051] 200: Integrated circuit board

[0052] 300: Integrated Circuit Electron Accelerator

[0053] The terms used in the present invention are selected from the most widely used general terms as much as possible, but in certain cases, there are terms arbitrarily selected by the applicant. In such cases, the meaning of the terms should be understood by considering the meaning described or used in the detailed description of the invention, rather than the simple name of the term.

[0054] Hereinafter, the technical configuration of the present invention will be described in detail with reference to preferred embodiments illustrated in the attached drawings.

[0055] However, the present invention is not limited to the embodiments described herein and may be embodied in other forms.

[0056] Identical reference numbers throughout the specification represent identical components.

[0057] First, FIG. 1 is a drawing illustrating an integrated circuit wafer (100) according to an embodiment of the present invention, wherein the integrated circuit wafer (100) is composed of a solenoid array (110), a controller (150), an integrated circuit (120), and a wafer (130).

[0058] The above solenoid array (110) is composed of a plurality of solenoids (111) that form a magnetic field when pulse power is applied.

[0059] A solenoid is usually a cylindrical coil of wire that generates a magnetic field when current flows through it.

[0060] When a current whose magnitude changes over time, such as an alternating current, is passed through a solenoid, a magnetic field is formed according to Faraday's law of electromagnetic induction.

[0061] The integrated circuit wafer (100) of the present invention is conceived based on the law of electromagnetic induction and utilizes a magnetic field formed by a solenoid (111) to which pulse power is applied.

[0062] That is, by accelerating electrons using a magnetic field through the solenoid (111) in the type of conductor such as the power line (121) and the clock signal line (122), it is possible to solve the problem of semiconductor quality deterioration caused by single-channel effects such as the DIBL (Drain Induced Barrier Lowering) phenomenon and the punch-through phenomenon.

[0063] In addition, the electronic acceleration technology according to the present invention can reduce power consumption and heat generation by reducing electrical resistance on wires connecting integrated circuits.

[0064] Additionally, the above-mentioned electronic acceleration technology can reduce noise phenomena within semiconductors by reducing the electrical resistance on the wires connecting the integrated circuits.

[0065] The above noise phenomenon mainly occurs in signal lines with long lengths within semiconductor circuits, and is caused by an overshoot phenomenon in which the output waveform appears higher than the set value due to a transient phenomenon in response to the input value.

[0066] A transient phenomenon refers to a certain amount of time required to obtain a desired value through an initial signal generated in a circuit. When a signal is applied to a circuit, the shorter the time it takes to rise from 0 to 1, the higher the overshoot. This causes an undershoot corresponding to the overshoot, thereby generating noise.

[0067] Meanwhile, the solenoid (111) is composed of a metal layer (111a), a coil layer (111b), and an insulating layer (111c) as shown in FIG. 2, and the coil layer (111b) is manufactured with a structure in which an insulating layer (111c) is placed between the coil layer (111b) and the metal layer (111a) when combined with the metal layer (111a).

[0068] At this time, the coil layer (111b) uses a conductive material and the wire is wound in the shape of a flat coil.

[0069] In addition, referring to FIG. 1, the coil layer (111b) used in the present invention is illustrated as having a circular shape, but the shape of the coil can also be used in a polygonal structure such as an ellipse or a square shape, and is not limited to a specific shape or number of turns.

[0070] In addition, the solenoid (111) is positioned spaced apart from each other along the power line and clock signal line connected to the integrated circuit (120), and can be mounted by positioning it above or below the power line and clock signal line.

[0071] Preferably, the insulating layer (111c) of the solenoid (111) is made to come into contact with the power line (121) and the clock signal line (122), thereby insulating the solenoid (111), the power line (121), and the clock signal line (122) from each other.

[0072] This is to accelerate the power and clock signal supplied to the integrated circuit by using the magnetic field formed in the solenoid (111).

[0073] The above controller (150) supplies pulse power to generate a magnetic field to the solenoids (111).

[0074] In addition, the controller (150) is installed in a structure that is positioned close to the solenoid (111) and connected to the solenoid coil layer (111b).

[0075] Therefore, the solenoid array (110) and the controller (150) are mounted on a semiconductor substrate as a single unit.

[0076] The above wafer (130) is one of the semiconductor substrates on which the solenoid array (110) and the controller (150) can be mounted. It is manufactured by processing a silicon plate, and a designed circuit can be engraved on the surface through an etching process.

[0077] In the semiconductor industry, a wafer, also known as a slice, is a very thin piece of crystalline silicon.

[0078] Additionally, the size of the wafers varies from 50 mm to 300 mm, and the thickness is manufactured to be 0.5 mm to 1 mm, which is easy to handle during the semiconductor manufacturing process.

[0079] However, considering the increasingly miniaturized nature of semiconductor devices, there is no need to limit the size and thickness of the wafer.

[0080] Meanwhile, there are various methods for applying the solenoid (111) and the controller (150) to the power line and clock signal line connected to the integrated circuit.

[0081] In addition, the integrated circuit wafer (100) of the present invention is manufactured by manufacturing a wafer made of silicon in the order of washing, diffusion, oxidation, photoprocess, etching, wiring, etc. during the wafer process, and by integrating the solenoid array (110) and the controller (150) into the power line (121) and clock signal line (122) connected to the integrated circuit during the wiring process.

[0082] As discussed above, the present invention has been illustrated and described with reference to examples, but is not limited to the above-described examples, and various changes and modifications may be made by a person having ordinary skill in the art to which the invention pertains within a scope that does not depart from the spirit of the present invention.

[0083] The terms used in the present invention are selected from the most widely used general terms as much as possible, but in certain cases, there are terms arbitrarily selected by the applicant. In such cases, the meaning of the terms should be understood by considering the meaning described or used in the detailed description of the invention, rather than the simple name of the term.

[0084] Hereinafter, the form for carrying out the invention relates to other embodiments of the present invention, and the technical configuration of the present invention is described in more detail with reference to the preferred embodiments illustrated in the attached drawings.

[0085] However, other embodiments of the present invention may be embodied in other forms without being limited to the embodiments described herein.

[0086] Identical reference numbers throughout the specification represent identical components.

[0087] FIG. 3 illustrates an integrated circuit substrate (200) according to another embodiment of the present invention. The integrated circuit substrate (200) is a PCB substrate (10) on which an integrated circuit (20) is pre-installed, as compared to an integrated circuit wafer (100) according to an embodiment of the present invention, in which the solenoid array (110) and the controller (150) are mounted.

[0088] However, the solenoid array (110) and the controller (150) are formed on a single substrate together with integrated circuits, and are mounted insulated above or below the power lines and clock signal lines connected to the integrated circuits, and are technically identical in terms of the technical aspect of accelerating the power and clock signals supplied to the integrated circuits.

[0089] In addition, FIG. 4 illustrates an integrated circuit electron accelerator (300) as another embodiment of the present invention. Compared to the integrated circuit wafer (100) according to an embodiment of the present invention and the integrated circuit substrate (200) according to another embodiment of the present invention, the integrated circuit electron accelerator (300) can be used by separately mounting the integrated circuit electron accelerator (300) on another circuit substrate by integrating the solenoid array (110) and the controller (150) into one solenoid array chip (140).

[0090] In addition, the chip (140) for the solenoid array uses a magnetic chip, waver, or semiconductor-only substrate as a material.

[0091] In addition, in the present invention, the power line and clock signal line of the integrated circuit (10) existing in the integrated circuit wafer (100) and the integrated circuit substrate (200) are used as examples of the power line and clock signal line, which are the most basic conductors connected to the integrated circuit, but the solenoid array can be used by placing it on other conductors connected between integrated circuits in addition to the power line or clock signal line.

[0092] Accordingly, the present invention overcomes the phenomenon of reduced electrical signal transmission due to the single-channel effect of the semiconductor process resulting from miniaturization of semiconductors, and can obtain a good semiconductor product in any process.

[0093] As described above, the present invention has been illustrated and described with reference to other embodiments, but is not limited to the other embodiments described above, and various changes and modifications may be made by a person having ordinary skill in the art to which the invention pertains within a scope that does not depart from the spirit of the present invention.

Claims

1. A wafer on which semiconductor circuits can be integrated; A solenoid array comprising a coil layer coupled to a metal layer with an insulating layer interposed therebetween on the wafer, and a plurality of solenoids arranged spaced apart from each other along the power line and clock signal line of the integrated circuit to form a magnetic field when pulse power is applied; A controller for supplying the pulse power to the solenoid array; An integrated circuit wafer comprising an integrated circuit connected to the power line and the clock signal line and supplied with accelerated power and clock signals through a magnetic field induced from the solenoid array; wherein the solenoid array, the controller, and the integrated circuit are formed on the single wafer and are mounted insulated above or below the power line and clock signal line connected to the integrated circuit, and the integrated circuit wafer accelerates the power and clock signals supplied to the integrated circuit.

2. PCB board with integrated circuit mounted on it; A solenoid array comprising a coil layer combined with a metal layer with an insulating layer between the coil layers on the PCB substrate, and a plurality of solenoids that form a magnetic field when pulse power is applied, spaced apart from each other along the power line and clock signal line of the integrated circuit; An integrated circuit board comprising a controller for supplying the pulse power to the solenoid array; wherein the solenoid array and the controller are formed on the PCB substrate and are mounted insulated above or below the power line and clock signal line connected to the integrated circuit on the PCB substrate, and are characterized in that they accelerate the power and clock signal supplied to the integrated circuit.

3. A solenoid array comprising a coil layer coupled to a metal layer and a plurality of solenoids spaced apart from each other to form a magnetic field when pulse power is applied; A controller that supplies the pulse power to the solenoid; A chip for a solenoid array capable of mounting the solenoid array and the controller; An integrated circuit electronic accelerator device characterized in that the solenoid array and the controller are formed as a chip on a single chip for the solenoid array and can be separately mounted on the conductors of a semiconductor integrated circuit to be mounted.

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