High bandwidth nonvolatile memory devices

Abstract

An apparatus is provided that includes a memory system that includes a plurality of memory die, each comprising a memory array including a plurality of non-volatile memory cells. The memory system has a bandwidth of about 3 TB / s, and each memory array has a power efficiency of about 1 pJ / bit.

Description

HIGH BANDWIDTH NONVOLATILE MEMORY DEVICES CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of and priority to U.S. non-provisional patent application Ser. No. 18 / 660,476 filed May 10, 2024, and U.S. provisional patent application Ser. No. 63 / 552,772 filed February 13, 2024.BACKGROUND

[0002] Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory' may be non-volatile memory or volatile memory. A nonvolatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery).

[0003] Non-volatile memory' devices include one or more memory chips having multiple arrays of memory' cells. The memory arrays may have associated decoders and circuits for performing read, write, and erase operations. Memory cells within the arrays may be arranged in horizontal rows and vertical columns. Each row may be addressed by a word line, and each column may be addressed by a bit line. Data may be loaded into columns of the array using a series of data busses. Each column may hold a predefined unit of data, for instance, a word encompassing two bytes of information.

[0004] In some applications, semiconductor memory is used to store very large amounts of data that are repeatedly accessed (e.g., read) very rapidly. For example, in some machine learning applications, large language models that include a terabyte (or more) of data must be stored in memory' and retrieved at a very high data rate. Accordingly, such applications require very high bandwidth and low power.

[0005] Currently, high bandwidth volatile memory devices (e.g., DRAM memory devices called ‘’high bandwidth memory” or “HBM”) are used for such applications. Non-volatile memory' (e.g., NAND) is significantly less expensive than DRAM, but the bandwidth of conventional NAND memory devices is too low, and the power consumption of conventional NAND memory devices is too high to provide a viable alternative to HBM devices.Therefore, there is a need to provide high bandwidth, low power non-volatile memory.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like-numbered elements refer to common components in the different figures.

[0007] FIG. 1 is a block diagram depicting one embodiment of a storage system.

[0008] FIG. 2A is a block diagram of one embodiment of a memory die.

[0009] FIG. 2B is a block diagram of one embodiment of an integrated memory' assembly.

[0010] FIGS. 3A and 3B depict different embodiments of integrated memory assemblies.

[0011] FIG. 4A is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0012] FIG. 4B is a block diagram of one embodiment of a memory’ structure having four planes.

[0013] FIG. 4C depicts a top view of a portion of one embodiment of a block of memory' cells.

[0014] FIG. 4D depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

[0015] FIG. 4E depicts a cross sectional view of a portion of one embodiment of a block of memory' cells.

[0016] FIG. 4F is a cross sectional view of one embodiment of a vertical column of memory cells.

[0017] FIG. 4G is a schematic of a plurality of NAND strings in multiple regions of a same block.

[0018] FIG. 5 A is a block diagram of one embodiment of a memory' structure having four planes.

[0019] FIG. 5B is a block diagram of one embodiment of a memory structure having thirty-two planes.

[0020] FIG. 5C is a block diagram of another embodiment of a memory structure having thirty-two planes.

[0021] FIG. 5D is a block diagram of still another embodiment of a memory structure having thirty -two planes.

[0022] FIGS. 6A-6C depict an example NAND string during inhibit, program and sensing, respectively.

[0023] FIG. 7 A depicts an example threshold voltage distribution of a NAND memory cell.

[0024] FIG. 7B depicts another example threshold voltage distribution of a NAND memory7cell.

[0025] FIG. 8 A depicts example threshold voltage distributions of two blocks of NAND memory cells.

[0026] FIG. 8B depicts example threshold voltage distributions of a single block ofNAND memory7cells

[0027] FIG. 9A depicts a block of memory cells divided into a first sub-block SBO and a second sub-block SB 1.

[0028] FIG. 9B also depicts a block of memory cells divided into a first sub-block SBO and a second sub-block SB1.DETAILED DESCRIPTION

[0029] Technology is described for increasing the bandwidth and improving the power efficiency of NAND memory to provide a viable alternative to HBM devices.

[0030] FIG. 1 is a block diagram of one embodiment of a storage system 100 that implements the proposed technology described herein. In one embodiment, storage system 100 is a solid state drive (‘"SSD”). Storage system 100 also can be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system.

[0031] Storage system 100 is connected to a host 102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from, but connected to, storage system 100. In other embodiments, storage system 100 is embedded within host 102.

[0032] The components of storage system 100 depicted in FIG. 1 are electrical circuits. Storage system 100 includes a memory controller 104 connected to non-volatile memory 106 and local high speed volatile memory 108 (e.g., DRAM). Local high speed volatile memory 108 is used by memory7controller 104 to perform certain functions. For example, local high speed volatile memory7108 stores logical to physical address translation tables ( ‘L2P tables”).

[0033] Memory controller 104 includes a host interface 110 that is connected to and in communication with host 102. In one embodiment, host interface 110 implements aNVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 110 also is connected to a network-on-chip (NOC) 112.

[0034] A NOC is a communication subsystem on an integrated circuit. NOC’s can span synchronous and asynchronous clock domains or use un-clocked asynchronous logic. NOC technology7applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs.

[0035] The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC 112 can be replaced by a bus.

[0036] Connected to and in communication with NOC 112 is a processor 1 14, an ECC engine 116, a memory interface 118, and a DRAM controller 120. DRAM controller 120 is used to operate and communicate with local high speed volatile memory 108 (e.g., DRAM). In other embodiments, local high speed volatile memory 108 can be SRAM or another type of volatile memory’.

[0037] Processor 114 performs the various controller memory’ operations, such as programming, erasing, reading, and memory' management processes. In one embodiment, processor 114 is programmed by firmware. In other embodiments, processor 114 is a custom and dedicated hardware circuit without any software. Processor 114 also implements a translation module, as a software / firmware process or as a dedicated hardware circuit.

[0038] In many systems, the non-volatile memory’ is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory’ die. To implement this system, memory controller 104 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory die.

[0039] One example implementation is to maintain tables (i.e., the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word ‘‘tables’’ they need not literally be tables.

[0040] Instead, the logical address to physical address tables (or L2P tables) can be any ty pe of data structure. In some examples, the memory' space of a storage system is so large that the local memory 108 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in non-volatile memory 106 and a subset of the L2P tables are cached(L2P cache) in the local high speed volatile memory 108.

[0041] ECC engine 116 performs error correction services. For example, ECC engine 116 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 116 is an electrical circuit programmed by software. For example, ECC engine 116 can be a processor that can be programmed. In other embodiments, ECC engine 116 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 116 is implemented by processor 114.

[0042] Memory7interface 118 communicates with non-volatile memory' 106. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces also can be used. In some example implementations, memory interface 118 (or another portion of controller 104) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory' die.

[0043] In one embodiment, non-volatile memory' 106 includes one or more memory die. FIG. 2A is a functional block diagrams of one embodiment of a memory die 200 that includes non-volatile memory 106. Each of the one or more memory die of non-volatile memory 106 can be implemented as memory die 200 of FIG. 2A. The components depicted in FIG. 2A are electrical circuits.

[0044] Memory die 200 includes a memory array 202 that can include non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented.

[0045] Memory die 200 includes row control circuitry’ 204, whose outputs 206 are connected to respective word lines of the memory array 202. Row control circuitry 204 receives a group of M row address signals and one or more various control signals from system control logic circuit 208, and ty pically may include such circuits as row decoders 210, array terminal drivers 212, and block select circuitry’ 214 for both reading and writing (programming) operations.

[0046] Row control circuitry' 204 also may include read / write circuitry. Memory' die 200 also includes column control circuitry’ 216 including sense amplifier(s) 218 whose input / outputs 220 are connected to respective bit lines of memory array 202. Although only a single block is shown for memory array 202, a memory die can include multiple arrays that can be individually accessed.

[0047] Column control circuitry 216 receives a group of N column address signals and one or more various control signals from system control logic 208, and typically may include such circuits as column decoders 222, array terminal receivers or driver circuits 224, block select circuitry 226, as well as read / write circuitry, and I / O multiplexers.

[0048] System control logic 208 receives data and commands from memory controller 104 (FIG. 1) and provides output data and status to host 102. In some embodiments, system control logic 208 (which includes one or more electrical circuits) includes a state machine 228 that provides die-level control of memory operations.

[0049] In one embodiment, state machine 228 is programmable by software. In other embodiments, state machine 228 does not use software and is completely implemented in hardware (e.g.. electrical circuits). In another embodiment, state machine 228 is replaced by a micro-controller or microprocessor, either on or off the memory chip.

[0050] System control logic 208 also can include a power control module 230 that controls the power and voltages supplied to the rows and columns of memory' structure 202 during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic 208 includes storage 232 (e.g.. RAM, registers, latches, etc.), which may7be used to store parameters for operating memory array 202.

[0051] Commands and data are transferred between memory7controller 104 and memory7die 200 via memory controller interface 234 (also referred to as a “communication interface’"). Memory controller interface 234 is an electrical interface for communicating with memory7controller 104. Examples of memory controller interface 234 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces can also be used.

[0052] In an embodiment, system control logic 208 also includes column replacement control circuits 236, described in more detail below.

[0053] In some embodiments, all elements of memory die 200, including the system control logic 208, can be formed as part of a single die. In other embodiments, some or all of the system control logic 208 can be formed on a different die.

[0054] In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. Memory structure 202 may include any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers.

[0055] In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other ty pes of memory' cells (e.g., NOR-type flash memory) can also be used.

[0056] The exact ty pe of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory' technology' is required for purposes of the new claimed embodiments proposed herein.

[0057] Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of memory’ structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

[0058] One example of a ReRAM cross-point memory' includes reversible resistanceswitching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell.

[0059] A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory' element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

[0060] Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from tw o ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization canbe changed to match that of an external field to store memory. A memory' device is built from a grid of such memory cells.

[0061] In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below' the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.

[0062] Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe - SbiTea super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light.

[0063] In other PCM embodiments, the memory' cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or another wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.

[0064] A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory' structures within the spirit and scope of the technology as described herein and as understood by one of ordinary' skill in the art.

[0065] The elements of FIG. 2A can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes all of the other components depicted in FIG. 2A. An important characteristic of a memory' circuit is its capacity', which can be increased by increasing the area of the memory' die of storage system 100 that is given over to memory' structure 202. However, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry.

[0066] For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to system control logic 208, reduced availability of area can limit the available functions that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system 100 is the amount of area to devote to memory structure 202 and the amountof area to devote to the peripheral circuitry.

[0067] Another area in which memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based.

[0068] For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 208 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.

[0069] To improve upon these limitations, embodiments described below can separate the elements of FIG. 2A onto separately formed die that are then bonded together. More specifically , memory structure 202 can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die).

[0070] For example, a memory die can be formed of just the memory elements, such as the array of memory7cells of flash NAND memory7, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology7.

[0071] For example, a NAND memory7die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array.

[0072] The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery7elements on the other die. Although the following will focus on a bonded memory7circuit of one memory7die and one control die, other embodiments can use more die, such as tw o memory7die and one control die, for example.

[0073] FIG. 2B shows an alternative arrangement to that of FIG. 2A which may beimplemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 240. One or more integrated memory assemblies 240 may be used to implement the non-volatile memory 106 of storage system 100.

[0074] Integrated memory assembly 240 includes two types of semiconductor die (or more succinctly, “die”). Memory die 242 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 244 includes control circuitry 208, 216, and 204 (as described above). In some embodiments, control die 244 is configured to connect to memory structure 202 in memory die 242. In some embodiments, memory die 242 and control die 244 are bonded together.

[0075] FIG. 2B shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die 244 coupled to memory structure 202 formed in memory die 242. Common components are labelled similarly to FIG. 2A. System control logic 208, row control circuitry' 204, and column control circuitry 216 are located in control die 244. In some embodiments, all or a portion of column control circuitry 216 and all or a portion of row control circuitry 204 are located on memory die 242. In some embodiments, some of the circuitry in system control logic 208 is located on memory die 242.

[0076] System control logic 208, row control circuitry 204, and column control circuitry 216 may be formed by a common process (e g., CMOS process), so that adding elements and functions, such as ECC, more typically found on a memory controller 104 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 104 may also be used to fabricate system control logic 208, row control circuitry 204, and column control circuitry' 216).

[0077] Thus, while moving such circuits from a die such as memory 242 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 244 may not require many additional process steps. Control die 244 also could be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 204, 208, 216.

[0078] FIG. 2B shows column control circuitry 216 including sense amphfier(s) 218 on control die 244 coupled to memory structure 202 on memory die 242 through electrical paths 220. For example, electrical paths 220 may provide electrical connection between column decoder 222. driver circuitry 224, and block select 226 and bit lines of memory' structure 202. In an embodiment, column control circuitry 216 also includes column replacement control circuits 236, described in more detail below.

[0079] Electrical paths may extend from column control circuitry 216 in control die 244 through pads on control die 244 that are bonded to corresponding pads of the memory die 242, which are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical paths 220, including a pair of bond pads, which connects to column control circuitry 216.

[0080] Similarly, row control circuitry 204, including row decoder 210, array drivers 212, and block select 214 are coupled to memory structure 202 through electrical paths 206. Each of electrical path 206 may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die 244 and memory die 242.

[0081] For purposes of this document, the phrases "a control circuit” or "one or more control circuits” can include any one of or any combination of memory controller 104, state machine 228, all or a portion of system control logic 208, all or a portion of row control circuitry7204, all or a portion of column control circuitry7216, a microcontroller, a microprocessor, and / or other similar functioned circuits.

[0082] The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

[0083] In some embodiments, there is more than one control die 244 and more than one memory die 242 in an integrated memory assembly 240. In some embodiments, the integrated memory7assembly 240 includes a stack of multiple control die 244 and multiple memory7die 242.

[0084] FIG. 3A depicts a side view of an embodiment of an integrated memoryassembly 300 stacked on a substrate 302 (e.g., a stack including control die 304 and memory die 306). The integrated memory assembly 300 has three control die 304 and three memory die 306. In some embodiments, there are more than three memory7die 306 and more than three control die 304.

[0085] Each control die 304 is affixed (e.g.. bonded) to at least one memory die 306. Some of the bond pads 308 / 310 are depicted, although there may be many more bond pads. A space between two die 306, 304 that are bonded together is filled with a solid layer 312, which may be formed from epoxy or other resin or polymer. This solid layer 312 protects the electrical connections between the die 306, 304. and further secures the die together. Various materials may be used as solid layer 312, but in embodiments, it may be Hysol epoxy resinfrom Henkel Corp., having offices in California, USA.

[0086] Integrated memory assembly 300 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 314 connected to the bond pads connect control die 304 to substrate 302. A number of such wire bonds may be formed across the width of each control die 304 (i.e., into the page of FIG. 3A).

[0087] A memory die through silicon via (TSV) 316 may be used to route signals through each memory die 306. A control die TSV 318 may be used to route signals through each control die 304. The TSVs 316, 318 may be formed before, during or after formation of the integrated circuits in semiconductor die 306, 304. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

[0088] Solder balls 320 optionally may be affixed to contact pads 322 on a lower surface of substrate 302. Solder balls 320 may be used to couple integrated memory assembly 300 electrically and mechanically to a host device such as a printed circuit board. Solder balls 320 may be omitted where the integrated memory' assembly 300 is to be used as an LGA package. Solder balls 320 may form a part of an interface between integrated memory assembly 300 and memory controller 104 (FIG. 1).

[0089] FIG. 3B depicts a side view of another embodiment of an integrated memory assembly 300 stacked on a substrate 302. The integrated memory' assembly 300 of FIG. 3B has three control die 304 and three memory die 306. In some embodiments, there are many more than three memory die 306 and many more than three control die 304. In this example, each control die 304 is bonded to at least one memory die 306. Optionally, a control die 304 may be bonded to two or more memory die 306.

[0090] Some of the bond pads 308, 310 are depicted. There may be many more bond pads. A space between two die 306. 304 that are bonded together is filled with a solid layer 312, which may be formed from epoxy or other resin or polymer. In contrast to the example in FIG. 3 A, integrated memory^ assembly 300 of FIG. 3B does not have a stepped offset. A memoiy die TSV 316 may be used to route signals through each memory' die 306. A control die TSV 318 may be used to route signals through each control die 304.

[0091] As has been briefly discussed above, control die 304 and memory die 306 may be bonded together. Bond pads on each control die 304 and each memory die 306 may be usedto bond the two die together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process.

[0092] In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension.

[0093] Such bonds may be formed at room temperature, though heat also may be applied. In embodiments using cu-to-cu bonding, the bond pads may be about 5 pm square and spaced from each other with a pitch of 5 m to 5pm. Although this process is referred to herein as cu-to-cu bonding, this term also may apply even where the bond pads are formed of materials other than copper.

[0094] When the area of bond pads is small, it may be difficult to bond the semiconductor die together. The size of and pitch between bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor die including the bond pads. The film layer is provided around the bond pads. When the die are brought together, the bond pads may bond to each other, and the film layers on the respective die may bond to each other.

[0095] Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5pm square and spaced from each other with a pitch of 1pm to 5pm. Bonding techniques may be used providing bond pads with even smaller (or greater) sizes and pitches.

[0096] Some embodiments may include a film on surface of control die 304 and memory die 306. Where no such film is initially provided, a space between the die may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between control die 304 and memory die 306, and further secures the die together. Various materials may be used as under-fill material, such as Hysol epoxy resin from Henkel Corp., having offices in California, USA.

[0097] FIG. 4A is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array / structure included in memory structure 202, which includes a plurality non-volatile memory7cells arranged as vertical NAND strings. For example, FIG. 4A shows a portion 400 of one block of memory.

[0098] The structure depicted includes a set of bit lines BL positioned above a stack 402 of alternating dielectric layers and conductive layers. For example purposes, one of thedielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements.

[0099] As will be explained below, in one embodiment the alternating dielectric layers and conductive layers are divided into four or five (or a different number of) regions by isolation regions IR. FIG. 4A shows one isolation region IR separating two regions. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers.

[0100] For example, one of the memory7holes is marked as MH. Note that in FIG. 4A, the dielectric layers are depicted as see-through so that the reader can see the memory7holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory7cells.

[0101] Each memory7cell can store one or more bits of data. Thus, the non-volatile memory cells are arranged in memory holes. More details of the three dimensional monolithic memory array that comprises memory structure 202 is provided below.

[0102] FIG. 4B is a block diagram explaining one example organization of memory structure 202, which is divided into four planes 404, 406, 408 and 410. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used.

[0103] In one embodiment, a block of memory cells is a unit of erase. That is, all memoty cells of a block are erased together. In other embodiments, blocks can be divided into sub-blocks and the sub-blocks can be the unit of erase. Memory cells also can be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits.

[0104] In some embodiments, a block represents a groups of connected memory cells as the memory7cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. Although FIG. 4B shows four planes, more or less than four planes can be implemented. In some embodiments, memory7structure 202 includes eight planes.

[0105] Each block ty pically is divided into one or more pages. In an embodiment, a page is a unit of programming / writing and a unit of reading. Other units of programming also can be used. In an embodiment, one or more pages of data are typically stored in one row of memory cells. For example, one or more pages of data may be stored in memory cellsconnected to a common word line. In an embodiment, a page includes data stored in all memory cells connected to a common word line.

[0106] FIGS. 4C-4G depict an example three dimensional ('‘3D”) NAND structure that corresponds to the structure of FIG. 4A and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4C is a block diagram depicting a top view of a portion 412 of Block 2 of plane 404. As can be seen from FIG. 4C, the block depicted in FIG. 4C extends in the direction of 414. In one embodiment, the memory array has many layers. However. FIG. 4C only shows the top layer.

[0107] FIG. 4C depicts a plurality of circles that represent the memory holes, which are also referred to as vertical columns. Each of the memory holes / vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each memory hole / vertical column implements a NAND string. For example, FIG. 4C labels a subset of the memory holes / vertical columns / NAND strings 416, 418, 420. 422, 424, 426. 428, 430 and 432.

[0108] FIG. 4C also depicts a set of bit lines 434, including bit lines 436, 438, 440. 442, ... 444. FIG. 4C shows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty’ four bit lines connected to memory holes / vertical columns of the block. Each of the circles representing memory’ holes / vertical columns has an “x” to indicate its connection to one bit line. For example, bit line 436 is connected to memory holes / vertical columns 418. 420, 422, 426 and 432.

[0109] The block depicted in FIG. 4C includes a set of isolation regions 446, 448, 450 and 452, which are formed of SiCty However, other dielectric materials also can be used. Isolation regions 446, 448. 450 and 452 serve to divide the top layers of the block into five regions For example, the top layer depicted in FIG. 4C is divided into regions 454, 456, 458, 460 and 462.

[0110] In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different regions can be independently selected. In one example implementation, a bit line connects to one memory’ hole / vertical column / NAND string in each of regions 454, 456, 458, 460 and 462. In that implementation, each block has twenty four rows of active columns and each bit line connects to five rows in each block.

[0111] In one embodiment, all of the five memory’ holes / vertical columns / NAND strings connected to a common bit line are connected to the same set of word lines; therefore, the system uses the drain side selection lines to choose one (or another subset) of the five to besubjected to a memory operation (program, verify, read, and / or erase).

[0112] FIG. 4C also shows Line Interconnects LI. which are metal connections to the source line SL from above the memory array. Line Interconnects LI are positioned adjacent regions 454 and 462.

[0113] Although FIG. 4C shows each region 454, 456, 458, 460 and 462 having four rows of memory holes / vertical columns, five regions and twenty four rows of memory holes / vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of memory' holes / vertical columns per region and more or less rows of vertical columns per block.

[0114] FIG. 4C also shows the memory holes / vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the memory holes / vertical columns are not staggered.

[0115] FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line AA of FIG. 4C. This cross sectional view cuts through memory holes / vertical columns (NAND strings) 428 and 430 of region 462 (see FIG. 4C).

[0116] The structure of FIG. 4D includes two drain side select layers SGD0 and SGD, the source side select layers SGSO and SGS1, two drain side GIDL generation transistor layers SGDT0 and SGDT1. two source side GIDL generation transistor layers SGSBO and SGSB1. two drain side dummy word line layers DD0 and DD1, two source side dummy word line layers DS0 and DS1, dummy word line layers DU and DL, one hundred and sixty' two word line layers WL0-WL161 for connecting to data memory cells, and dielectric layers DL.

[0117] Other embodiments can implement more or less than the numbers described above for FIG. 4D. In one embodiment, SGD0 and SGD1 are connected together; and SGSO and SGS1 are connected together. In other embodiments, more or less number of SGDs (greater or lesser than two) are connected together, and more or less number of SGS devices (greater or lesser than two) connected together.

[0118] In one embodiment, erasing the memory cells is performed using gate induced drain leakage (GIDL), which includes generating charge carriers at the GIDL generation transistors such that the carriers get injected into the charge trapping layers of the NAND strings to change threshold voltage of the memory cells. FIG. 4D shows two GIDL generation transistors at each end of the NAND string; however, in other embodiments there are more or less than three.

[0119] Embodiments that use GIDL at both sides of the NAND string may have GIDL generation transistors at both sides. Embodiments that use GIDL at only the drain side of the NAND string may have GIDL generation transistors only at the drain side. Embodiments that use GIDL at only the source side of the NAND string may have GIDL generation transistors only at the source side.

[0120] FIG. 4D shows two GIDL generation transistors at each end of the NAND string. It is likely that charge carriers are only generated by GIDL at one of the two GIDL generation transistors at each end of the NAND string. Based on process variances during manufacturing, it is likely that one of the two GIDL generation transistors at an end of the NAND string is best suited for GIDL.

[0121] For example, the GIDL generation transistors have an abrupt PN junction to generate the charge carriers for GIDL and, during fabrication, a phosphorous diffusion is performed at the poly silicon channel of the GIDL generation transistors. In some cases, the GIDL generation transistor with the shallowest phosphorous diffusion is the GIDL generation transistor that generates the charge carriers during erase. However, in some embodiments charge carriers can be generated by GIDL at multiple GIDL generation transistors at a particular side of the NAND string.

[0122] Memon holcs / V ertical columns 428 and 430 are depicted protruding through the drain side select layers, source side select layers, dummy word line layers, GIDL generation transistor layers and word line layers. In one embodiment, each memory hole / vertical column comprises a vertical NAND string. Below the memory holes / vertical columns and the layers listed below is substrate 464, an insulating film 466 on the substrate, and source line SL. The NAND string of memory hole / vertical column 428 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with FIG. 4C, FIG. 4D show vertical memory hole / column 428 connected to bit line 442 via connector 468.

[0123] For ease of reference, drain side select layers, source side select layers, dummy word line layers, GIDL generation transistor layers and data word line layers collectively are referred to as conductive layers.

[0124] In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten, metal silicide, such as nickel silicide, tungsten silicide, aluminum silicide or the combination thereof.

[0125] In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL. In one embodiment, thedielectric layers are made from SiCh. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0126] The non-volatile memory cells are formed along memory holes / vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0- W161 connect to memory cells (also called data memory cells). Dummy word line layers connect to dummy memory cells.

[0127] A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layers SGD0 and SGD1 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGSO and SGS1 are used to electrically connect and disconnect NAND strings from the source line SL.

[0128] FIG. 4D shows that the memory array is implemented as a two tier architecture, with the tiers separated by a Joint area. In one embodiment it is expensive and / or challenging to etch so many word line layers intermixed with dielectric layers. To ease this burden, one embodiment includes laying dow n a first stack of word line layers (e.g., WL0-WL80) alternating with dielectric layers, laying down the Joint area, and laying down a second stack of word line layers (e.g.. WL81-WL161) alternating with dielectric layers. The Joint area are positioned between the first stack and the second stack. In one embodiment, the Joint areas are made from the same materials as the word line layers. In other embodiments, there can no Joint area or there can be multiple Joint areas.

[0129] FIG. 4E depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line BB of FIG. 4C. This cross sectional view cuts through memon holes / vertical columns (NAND strings) 416 and 470 of region 454 (see FIG. 4C). FIG. 4E shows the same alternating conductive and dielectric layers as FIG. 4D.

[0130] FIG. 4E also shows isolation region 446. Isolation regions 446. 448, 450 and 452) occupy space that would have been used for a portion of the memory holes / vertical columns / NAND stings. For example, isolation region 446 occupies space that would have been used for a portion of memory hole / vertical column 470. More specifically, a portion (e.g., half the diameter) of vertical column 470 has been removed in layers SGDT0, SGDT1. SGD0, and SGD1 to accommodate isolation region 446.

[0131] Thus, while most of the vertical column 470 is cylindrical (with a circular cross section), the portion of vertical column 470 in layers SGDT0. SGDT1, SGD0, and SGD1 has a semi-circular cross section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region and that space is then filled in with SiCh. This structure allows for separate control of SGDT0. SGDT1, SGD0, and SGD1 for regions 454, 456, 458, 460, and 462.

[0132] FIG. 4F depicts a cross sectional view of region 472 of FIG. 4D that includes a portion of memory hole / vertical column 428. In one embodiment, the memory holes / vertical columns are round. However, in other embodiments other shapes can be used. In one embodiment, memory hole / vertical column 428 includes an inner core layer 474 that is made of a dielectric, such as S1O2. Other materials can also be used.

[0133] Surrounding inner core 474 is polysilicon channel 476. Materials other than polysilicon can also be used. Note that it is the channel 476 that connects to the bit line and the source line. Surrounding channel 476 is a tunneling dielectric 478. In one embodiment, tunneling dielectric 478 has an ONO structure. Surrounding tunneling dielectric 478 is charge trapping layer 480, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

[0134] FIG. 4F depicts dielectric layers DL as well as word line layers WL160, WL159, WL158, WL157. and WL156. Each of the word line layers includes a word line region 482 surrounded by an aluminum oxide layer 484, which is surrounded by a blocking oxide layer 486. In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer 480. The physical interaction of the word line layers with the vertical column forms the memory cells.

[0135] Thus, in one embodiment a memory cell includes channel 476, tunneling dielectric 478, charge trapping layer 480, blocking oxide layer 486, aluminum oxide layer 484 and word line region 482. For example, word line layer WL160 and a portion of memory7hole / vertical column 428 comprise a memory7cell MCI. Word line layer WL159 and a portion of memory hole / vertical column 428 comprise a memory cell MC2. Word line layer WL158 and a portion of memory7hole / vertical column 428 comprise a memory cell MC3. Word line layer WL157 and a portion of memory hole / vertical column 428 comprise a memory7cell MC4. Word line layer WL156 and a portion of memory7hole / vertical column 428 comprise a memory cell MC5. In other architectures, a memory cell may have adifferent structure; however, the memory cell would still be the storage unit.

[0136] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 480 which is associated with (e.g. in) the memory cell. These electrons are drawn into the charge trapping layer 480 from the channel 476, through the tunneling dielectric 478, in response to an appropriate voltage on word line region 482. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge.

[0137] In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0138] FIG. 4G is a schematic diagram of a portion of the three dimensional memon' array 202 depicted in in FIGS. 4B-4F. FIG. 4G shows physical data word lines WL0-WL161 running across the entire block. The structure of FIG. 4G corresponds to a portion 412 in Block 2 of FIG. 4B, including bit line 436. Within the block, in one embodiment, each bit line is connected to five NAND strings, one in each region of regions 454, 456, 458, 460, 462.

[0139] Thus, FIG. 4G shows bit line 436 connected to NAND string NS0 (which corresponds to memory hole / vertical column 418 of region 454), NAND string NS1 (which corresponds to memory hole / vertical column 420 of region 456), NAND string NS2 (which corresponds to vertical column 422 of region 458), NAND string NS3 (which corresponds to memory hole / vertical column 426 of region 460), and NAND string NS4 (which corresponds to memory hole / vertical column 432 of region 462).

[0140] Drain side select line / layer SGD0 is separated by isolation regions isolation regions 446, 448, 450 and 452 to form SGDO-sO, SGDO-sl, SGD0-s2, SGD0-s3 and SGD0- s4 in order to separately connect to and independently control regions 454, 456, 458, 460, 462.

[0141] Similarly, drain side select line / layer SGD1 is separated by isolation regions 446, 448, 450 and 452 to form SGDl-sO, SGDl-sl, SGDl-s2, SGDl-s3 and SGD1- s4 in order to separately connect to and independently control regions 454, 456, 458, 460, 462.

[0142] Drain side GIDL generation transistor control line / layer SGDT0 is separated by isolation regions 446, 448, 450 and 452 to form SGDTO-sO, SGDTO-sl, SGDT0-s2, SGDT0-s3 and SGDT0-s4 in order to separately connect to and independently control regions 454, 456, 458, 460, 462.

[0143] Drain side GIDL generation transistor control line / layer SGDT1 is separated by isolation regions 446, 448, 450 and 452 to form SGDTl-sO, SGDTl-sl, SGDTl-s2, SGDT1- s3 and SGDTl-s4 in order to separately connect to and independently control regions 454, 456, 458, 460, 462.

[0144] FIG. 4G only shows NAND strings connected to bit line 436. However, a full schematic of the block would show every bit line and five vertical NAND strings (that are in separate regions) connected to each bit line.

[0145] Although the example memories of FIGS. 4B-4G are three dimensional memory structures that include vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein.

[0146] As described above, in some machine learning applications, large language models that include a terabyte (or more) of data must be stored in memory and retrieved at a very high data rate. Such applications, which require very high bandwidth and low power, typically store data in HBM DRAM. For example, in an existing machine learning system application, a processor (e.g., a CPU, GPU or other processor) is coupled to six HBM DRAM devices and has a system bandwidth of 3 TB / s. However, DRAM is very' expensive, each DRAM has limited capacity, and the number of HBM chips needed to store an entire large language model is very’ costly.

[0147] Non-volatile memory (e g., NAND) is significantly less expensive than DRAM, but the bandwidth of conventional NAND memory’ devices is much lower than that of HBM. For example, an HBM die has a bandwidth of about 75 GB / sec. In contrast, a conventional NAND memory die has a bandwidth of about 4.4GB / sec.

[0148] Achieving a bandwidth of 3 TB / s using conventional NAND memory devices would require a prohibitively large number of memory package. For example, with 16 memory7die per memory package, each memory package has a bandwidth of 16 x 4.4 GB / s = 70.4 GB / s. To provide a bandwidth of 3 TB / sec, 44 memory packages would be required, which is not practical.

[0149] In addition, the power consumption of conventional NAND memory devices is too high to provide a viable alternative to HBM devices. For example, in current NAND technology, the memory array itself has a pow er efficiency of about 4.5 pj / bit. To be a viable alternative to HBM, NAND devices need to have a power efficiency of about 1 pJ / bit.

[0150] Technology is described for increasing the bandwidth, and reducing the powerconsumption of non-volatile memory, such as flash memory. In particular, technology is described for high bandwidth flash memory devices that may be used as a replacement for HBM for machine learning inferencing operations. Such devices are referred to herein as “high bandwidth flash,” or “HBF” memory.

[0151] During inferencing, the large language model data stored in memory' are repeatedly read, but are fairly static. That is, once the model data have been stored in memory, the model data are not updated or changed very often. Thus, for a machine learning inferencing application, the memory- can be considered write once, read many memory.

[0152] NAND memory devices include memory' cells that typically can be operated to store 1 bit per memory cell (sometimes referred to as “single level cell” or “SLC” memory) or multiple bits per memory cell (sometimes referred to as “multi- level cell” or “MLC” memory). SLC memory is the fastest solution for reducing read latency (and increasing bandwidth). So the remaining discussion describes HBF memory' devices that operate using SLC memory' cells.

[0153] In embodiments, the bandwidth of HBF memory’ is increased by: (1) increasing the number of memory planes per memory die, (2) increasing the number of input / output (I / O) per memory die to accommodate the increased bandwidth of the memory die, and (3) reducing the physical page size to decrease read latency. These are discussed beloyv.

[0154] As described above, a memory structure (such as memory structure 202 of FIG. 2A) may include multiple planes, and each plane may operate in parallel. For example, FIG. 5A is a diagram depicting a memory structure that includes four planes: POO, P01 , P02 and P03.

[0155] In an embodiment, each of planes POO. P01, P02 and P03 is divided into two subplanes. For example, plane POO includes a first sub-plane POOo and a second sub-plane POOi, second sub-plane P01 includes a first sub-plane POlo and a second sub-plane POli, third subplane P02 includes a first sub-plane PO2o and a second sub-plane P02i, and fourth subplane P03 includes a first sub-plane PO3o and a second sub-plane P03i.

[0156] In an embodiment, each of planes POO, P01, P02 and P03 includes a logical page and a physical page size. In the embodiment of FIG. 5A, the physical page size is 8kB / page, and each logical page includes two physical pages (i.e., 16 kB per logical page).

[0157] In an embodiment, a memory’ die that includes planes POO, POL P02 and P03 has a capacity of 32GB. In an embodiment, 16 memory' die are included in a memory package, and the memory' package has a capacity' of 1 x 32GB = 512GB. Other capacities per memory'die. and other numbers of memory die per memory7package may be used.

[0158] In an embodiment, a memory7die that includes planes POO, P01. P02 and P03 has a read latency (“tR”) of approximately 15 psec. The per-die bandwidth can be determined from read latency and the logical page size as follows: planes = 4.4 GB / sF 7

[0159] In an embodiment, a memory7die that includes planes POO, P01, P02 and P03 has an 8 bit I / O, and has an I / O speed of 4.8 G-transfers / s. Because the I / O speed (4.8 G- transfers / s) is faster that the memory die data rate (4.4 GB / sec). the I / O speed is not a factor limiting the data rate of the memory die.

[0160] In an embodiment, the number of planes per memory die is increased to increase the memory7die bandwidth. For example, FIG. 5B is a diagram depicting a memory7structure that includes 32 planes: four planes in the x-direction (e.g., planes POO, P01, P02 and P03) and eight planes in the y-direction (e.g., planes P03. P13, P23, P33. P43, P53, P63 and P73).

[0161] In an embodiment, each of planes POO, P01, P02, . . ., P72 and P73 is divided into two sub-planes. For example, plane POO includes a first sub-plane POOQ and a second subplane POOi, a second sub-plane P01 includes a first sub-plane POlo and a second sub-planePOh. . . ., and a thirty-secondth sub-plane P73 includes a first sub-plane P73o and a second sub-plane P73i.

[0162] In an embodiment, each of planes POO. P01, P02, . . ., P72 and P73 includes a logical page and a physical page size. In the embodiment of FIG. 5B, the physical page size is 8kB / page, and each logical page includes two physical pages (i.e., 16 kB per logical page).

[0163] The structure of FIG. 5B can be derived from the structure of FIG. 5 A by keeping the same number of planes in the x-direction (4 planes in x-direction), splitting the planes in half in the y-direction, and repeating four copies (for a total of 8 planes in y-direction). for a total of 4 x 8 = 32 planes per memory die. This is 8 times the number of planes of FIG. 5A embodiment. Thus, the total capacity of each die is 0.5 x 8 x 32GB = 128GB and the bandwidth of each die is 8 x 4.4 GB / s = 35.2 GB / s.

[0164] In an embodiment, 16 memory die are included in a memory package, and thus the memory package has a capacity of 16 x 128GB = 2TB. Each memory package has a bandwidth of 16 x 35.2 GB / s = 563.2 GB / s. To provide a bandwidth of approximately 3 TB / sec, 5 memory packages would be required, which is practical.

[0165] To provide this bandwidth, the number of I / O per die must be increased. Asdescribed above, an 8 bit I / O has a speed of 4.8 G-transfers / s. If the number of I / O are increased by a factor of 8 to 64 I / O, the I / O speed increases to 8 x 4.8 G-transfers / s = 38.4 G- transfers / s, which is faster that the memory die data rate (35.2 GB / sec).

[0166] In additional embodiments, memory die bandwidth can be increased by’ reducing the physical page size to reduce read latency tR. For example, FIG. 5C is a diagram depicting a memory structure that includes 32 planes: eight planes in the x-direction (e.g., planes POO, P01. . . .. and P07) and four planes in the y-direction (e.g., planes P07, P17, P27 and P37).

[0167] In an embodiment, each of planes POO, P01, P02, . . ., P36 and P37 is divided into two sub-planes. For example, plane POO includes a first sub-plane POOo and a second subplane POOi, a second sub-plane P01 includes a first sub-plane POlo and a second sub-plane POli, . . ., and a thirty-secondth sub-plane P37 includes a first sub-plane P37o and a second sub-plane P37i.

[0168] In an embodiment each of planes POO, P01, P02, . . P36 and P37 includes a logical page and a physical page size. In the embodiment of FIG. 5C, the physical page size is 4kB / page, and each logical page includes two physical pages (i.e., 8 kB per logical page).

[0169] The structure of FIG. 5C can be derived from the structure of FIG. 5B by dividing each 8 kB plane into two 4 kB planes in the x-direction (8 planes in x-direction). and reducing the number of planes by half in the y-direction (4 planes in y-direction), for a total of 32 planes. This is the same number of planes as the FIG. 5B embodiment. The total capacity of each die is 64GB.

[0170] By cutting each word line in half (from 8 kB to 4 kB). the read latency tR decreases. In an embodiment, the read latency tR of the embodiment of FIG. 5C is 4 psec(compared with a read latency tR of 15 psec for the FIG. 5B embodiment). The per-die bandwidth can be determined from read latency and the logical page size as follows: planes = 66 GB / sF'

[0171] In an embodiment, 16 memory die are included in a memory’ package, and thus the memory package has a capacity of 16 x 64GB = 1TB. Each memory package has a bandwidth of 16 x 66 GB / s = 1.1 TB / s. To provide a bandwidth of approximately 3 TB / sec, 3memory packages would be required, which is practical.

[0172] To provide this bandwidth, the number of I / O per die must be increased. As described above, an 8 bit I / O has a speed of 4.8 G-transfers / s. If the number of I / O areincreased by a factor of 16 to 128 I / O, the I / O speed increases to 16 x 4.8 G-transfers / s = 77 G-transfers / s, which is faster than the memory die data rate (66 GB / sec).

[0173] The memory die bandwidth can be further increased by further reducing the physical page size to reduce read latency tR. For example, FIG. 5D is a diagram depicting a memory structure that includes 32 planes: eight planes in the x-direction (e.g., planes POO, P01, . . ., and P07) and four planes in the y-direction (e.g., planes P07, P17, P27 and P37).

[0174] In an embodiment, each of planes POO. P01, P02, . . ., P36 and P37 is divided into two sub-planes. For example, plane POO includes a first sub-plane POOo and a second subplane POOi, a second sub-plane P01 includes a first sub-plane POlo and a second sub-planePOli, . . ., and a thirty-secondth sub-plane P37 includes a first sub-plane P37o and a second sub-plane P37i.

[0175] In an embodiment, each of planes POO. P01, P02, . . ., P36 and P37 includes a logical page and a physical page size. In the embodiment of FIG. 5D, the physical page size is 2kB / page, and each logical page includes two physical pages (i.e., 4 kB per logical page).

[0176] The structure of FIG. 5D can be derived from the structure of FIG. 5C by dividing each 4 kB plane into two 2 kB planes in the x-direction (8 planes in x-direction), and keeping the same number of planes by half in the y-direction (4 planes in y-direction), for a total of 32 planes. This is the same number of planes as the FIG. 5C embodiment. The total capacity of each die is 32GB.

[0177] By cutting each word line in half (from 4 kB to 2 kB), the read latency tR decreases. In an embodiment, the read latency tR of the embodiment of FIG. 5D is 1.7 psec (compared with a read latency tR of 15 psec for the FIG. 5B embodiment and a read latency of 4 psec for the FIG. 5C embodiment). The per-die bandwidth can be determined from read latency and the logical page size as follows:(4kBBW=v -1.7 x

[0178] In an embodiment, 8 memory die are included in a memory package, and thus the memory package has a capacity of 8 x 32GB = 256GB. Each memory package has a bandwidth of 8 x 77 GB / s = 61 GB / s. To provide a bandwidth of approximately 3 TB / sec, 5 memory packages would be required, which is practical.

[0179] To provide this bandwidth, the number of I / O per die must be increased. As described above, an 8 bit I / O has a speed of 4.8 G-transfers / s. If the number of I / O are increased by a factor of 16 to 128 I / O, the I / O speed increases to 16 x 4.8 G-transfers / s = 77G-transfers / s, which is about the same as the memory die data rate (77 GB / sec).

[0180] Without wanting to be bound by any particular theory, it is believed that the techniques described above for (1) increasing the number of memory planes per memory die, (2) increasing the number of input / output (I / O) per memory die to accommodate the increased bandwidth of the memory die, and (3) reducing the physical page size to decrease read latency may provide HBF memory with a bandwidth of about 3 TB / s.

[0181] As described above, in cunent NAND technology the memory array has a power efficiency of about 4.5 pj / bit, but to be a viable alternative to HBM NAND devices need to have a power efficiency of about 1 pJ / bit. Technology7is described for improving the power efficiency of HBM NAND devices.

[0182] A first technique to improve the power efficiency of HBM NAND devices is to reduce the supply voltage. The power consumed by a NAND array is approximately equal to VCC x ICC, where VCC is the supply voltage and ICC is the supply current. For current NAND memory7, a supply voltage of VCC = 2.5V is ty pically used. One technique for reducing power consumption (and thereby improve the power efficiency) is to reduce supply voltage VCC, such as VCC = 1.2V.

[0183] To reduce VCC to 1.2V, the memory7device must still perform various functions, such as program, inhibit, and sensing. That would not be possible for multi-level NAND memory. But for SLC memory, there is a lot of margin. So reducing the VCC to 1.IN may be feasible. FIGS. 6A-6C depict an example NAND string during three different memory operations. In particular FIGS. 6A-6C depict an example NAND string during inhibit, program and sensing, respectively.

[0184] For inhibit, depicted in FIG. 6A, we need to provide the 1 ,2V VCC to the inhibit bit line. This voltage needs to be high enough to cut off the unselected SGD transistors to provide the channel boosting to provide the inhibit operation. That is, (VSGD - VDD) < Vt.

[0185] For programming, depicted in FIG. 6B, a bit line voltage VBL = 0V needs to deliver to channel. This requires that the bias VSGD on the SGD cells is greater than the threshold voltage of the SGD cells, VSGD > Vt. In an embodiment, the threshold voltage of the SGD cells is approximately 1.5V.

[0186] Thus, for inhibit we require that (VSGD - VDD) < Vt, and for programming we require that VSGD > Vt. From these two requirements the following can be derived:VSGD > Vt upper tailVSGD < VDDSA + Vt lower tail

[0187] In embodiments, the Vt lower tail is about 1 ,5V and the Vt upper tail isabout 1.9V, and VDDSA is about 1.1V. Thus, from the two conditions above:1.9V < VSGD < 2.6V

[0188] For sensing, depicted in FIG. 6C, the bit line voltage VBL needs to provide enough drain-to-source voltage for the NAND string. In a conventional NAND device we use a source line voltage VCELSRC = IV. In such a scenario, the bit line voltage needs to provide VBLC (-0.2V) + VCELSRC + a few transistor threshold voltages + some temperature compensation (TCO) voltage, which leads to approximately 1.5V. which needs to be derived from VCC. If VCC = 1.2V, we cannot supply sufficient voltage.

[0189] However, if the source line voltage VCELSRC is instead set to 0V, referred to herein as a “positive sensing” scheme, the bit line voltage need to provide VBLC (-0.2V) + 0V + a few transistor threshold voltages + some temperature compensation (TCO) voltage, which leads to approximately 0.5V, which can be provided with VCC = 1.2V.

[0190] Thus, from a device physics standpoint, a VCC 1.2V external power supply can offer the proper voltage for the NAND array operation.

[0191] A second technique to improve the power efficiency of HBM NAND devices is to reduce all internal voltages inside the NAND device. In particular:cell. In particular, the example threshold voltage distribution includes an erased state (e.g., “1”) distribution and a programmed state (e.g., “0”) distribution for a conventional NAND memory cell.

[0193] In the illustrated example, both threshold distributions are broad (e.g.. such as may be achieved using a one program, zero verify (“1P0V”) program method) and there is a wide separation between the two threshold distributions. In the depicted example, read verify level SLRC of 0V is used and unselected word lines are biased at a voltage of Vread = 4.7V.

[0194] FIG. 7B depicts an example threshold voltage distribution of an HBF NAND memory cell. In particular, the example threshold voltage distribution includes an erased state (e.g., “1”) distribution and a programmed state (e.g.. “0”). As described above, for a machine learning inferencing application, the memory can be considered write once, readmany memory. As a result, because programming operations are performed infrequently, during programming the threshold voltage distributions can be made very’ narrow, much narrower than the threshold voltage distribution of a conventional NAND memory device depicted in FIG. 7A.

[0195] In addition, the gap between the two distributions can be made very close together. By reducing he gap and the threshold voltage distribution width, the unselected word line voltage of Vread can be reduced from 4.7V. Instead. Vread can be reduced by 50% to 2.4V to achieve power reduction.

[0196] In addition, the read verify level SLRC can be reduced from 0V (e.g., in the middle of the two distributions in FIG. 7A). In an embodiment, read verify level SLCR is set at the upper tail of the erase distribution. For example, read verify level SLCR = -IV or some other level. By setting read verify level SLCR at the upper tail of the erase distribution, the amount of overdrive between the erase state distribution and the read verify’ level SLCR is reduced, which in turn reduces the ICC power supply current during sensing. This also reduces power consumption.

[0197] As described above, to improve the power efficiency of HBF devices, one technique for reducing power consumption (and thereby improve the power efficiency) is to reduce supply voltage VCC, such as VCC = 1.2V. Another technique is to reduce all internal voltages inside the NAND device.

[0198] Without wanting to be bound by any particular theory, it is believed that these two techniques may be used to provide an HBF memory array with a power efficiency of about IpJ / bit.

[0199] As described above, machine learning inferencing applications are read-intensive. As a result, the HBF memory devices will experience a lot of read disturb. Conventionally, after we experience severe read disturb in one block, we relocate the date to a new block (called “relocation”), and then the host can continue reading from the new block.

[0200] For example, FIG. 8 A depicts example threshold voltage distributions of tw o blocks of NAND memory cells. In particular, the top diagram depicts threshold voltage distributions immediately after programming the block (e.g., block A). After some large number of reads of the same block (e.g., 100 thousand reads), the erase distribution will widen and the erase upper tail will encroach on the program state lower tail, such as depicted in the middle diagram of FIG. 8A. As a result, the margin between the erased state and the programmed state shrinks.

[0201] In a conventional technique, whenever the block reads are detected as almostfailing, the data in the block are relocate to a new lock (e.g., block B). In particular, a replacement block B is located, the data in block B is erased, and the data in block A is read and then programmed to block B, resulting in the example threshold voltage distribution depicted in the bottom diagram of FIG. 8 A.

[0202] Although this results in well-defined threshold voltage distributions in the relocated block, this requires consuming a program-erase cycle to program the data to new block B, which hurts endurance. In addition, the block management function becomes more complicated because a logical-to-physical block table must keep track of the relocated data.

[0203] To avoid these technical problems, an alternative “in-place read refresh” technique for addressing read disturb is described that eliminates the need to erase memory cells. Instead, the data in the same block that experiences read disturb are refreshed.

[0204] In embodiments, the described in-place read refresh technique may be implemented by any one of or any combination of memory controller 104, state machine 228, all or a portion of system control logic 208, all or a portion of row control circuitry 204, all or a portion of column control circuitry 216, a microcontroller, a microprocessor, and / or other similar functioned circuits.

[0205] For example, FIG. 8B depicts example threshold voltage distributions of a single block of NAND memory’ cells. In particular, the top diagram depicts threshold voltage distributions immediately after programming the block (e g., block A). This is similar to the distributions in the top diagram of FIG. 8A, but here the threshold voltage distributions are very narrow and closer together, such as described above in FIG. 7B.

[0206] After some large number of reads of the same block (e.g., 100 thousand reads), the erase distribution will widen and the erase upper tail will encroach on the program state lower tail, such as depicted in the middle diagram of FIG. 8B. As a result, the margin between the erased state and the programmed state shrinks.

[0207] In an embodiment, just before read failure is detected, instead of finding another block (B) to erase and program, an in-place read refresh is performed. In an embodiment, additional program pulses are applied to the programmed state memory cells, to shift the programmed state threshold distribution higher to increase separation from the erase state distribution.

[0208] For example, as depicted in the bottom diagram of FIG. 8B, the threshold voltage distribution of the programmed state memory cells are shifted higher, increasing the separation from the threshold voltage distribution of the erased state memory cells. In embodiments, this process can be repeated - increasing the program state distribution as theerase state distribution widens.

[0209] In the embodiment of FIG. 7B. the erase state and program state distributions are very close together and very narrow. As a result, the in-place read-refresh technique has a lot of room to keep pushing the program state distribution higher and higher as necessary for read refresh.

[0210] Without wanting to be bound by any particular theory, it is believed that the described in-place read refresh technique for addressing read disturb avoids the need to find another block (e.g., B) and avoids the need to perform another program-erase cycle on the new block.

[0211] As described above, one technical problem of a conventional read refresh technique is the need to identify an alternative block for receiving the re-written data following read disturb. Finding a new block for the re-written data can be complicated, because the new block can be random. And this randomness must be managed very well, and is unpredictable - it depends on the moment at which the original block must be refreshed, and depends on what blocks are available (i.e., have invalid data) and that can be erased and programmed with data from the original block. This changes constantly with time, so this adds a lot of complexity to the controller to manage this process.

[0212] To avoid these technical problems, an alternative “sub-block read refresh'’ technique for addressing read disturb is described that eliminates the need and unpredictability of locating an alternative block for the relocated data.

[0213] In embodiments, the described sub-block read refresh technique may be implemented by any one of or any combination of memory controller 104, state machine 228, all or a portion of system control logic 208, all or a portion of row control circuitry 204, all or a portion of column control circuitry 216, a microcontroller, a microprocessor, and / or other similar functioned circuits.

[0214] In an embodiment, one physical block includes two logical sub-blocks. For example, FIG. 9A depicts a block of memory' cells divided into a first sub-block SBO and a second sub-block SB1. In an embodiment, during programming, user data are stored in only one of the two sub-blocks. In the example depicted in the left diagram of FIG. 9A. user data are initially programmed in first sub-block SBO.

[0215] After some large number of reads of the same block (e.g., 100 thousand reads), the erase distribution will widen and the erase upper tail will encroach on the program state lower tail, such as depicted in the middle diagram of FIG. 9A. As a result, the margin between the erased state and the programmed state shrinks.

[0216] In an embodiment, just before read failure is detected, instead of finding another block (B) to erase and program, the data in second sub-block SB1 are erased and programmed with data from first sub-block SBO. That is, data are relocated from part of the physical block (first sub-block SBO) to another part of the physical block (second sub-block SB1). This is highly predictable, avoids the need to have to find an available block, and avoids the need to manage the relocated data in a logical-to-physical mapping table.

[0217] An example threshold voltage distribution after the data relocation is depicted in the right diagram of FIG. 9A. In some embodiments, the program order for the upper subblock is from bottom to top, and the program order for the lower sub-block is from top to bottom. Thus, in an embodiment when the data are relocated, the sub-block programming order is followed. That is. data from the highest word line in the lower sub-block is relocated to the lowest word line of the upper sub-block, data from the second highest word line in the lower sub-block is relocated to the second lowest word line of the upper sub-block, and so on. This is depicted using arrows in FIG. 9A.

[0218] This example process can be repeated. For example, after some large number of reads of the same block (e.g., 100 thousand reads), the erase distribution will widen and the erase upper tail will encroach on the program state lower tail, such as depicted in the middle diagram of FIG. 9B. As a result, the margin between the erased state and the programmed state shrinks.

[0219] In an embodiment, just before read failure is detected, instead of finding another block (B) to erase and program, the data in first sub-block SBO are erased and programmed with data from second sub-block SB1. That is, data are relocated from part of the physical block (second sub-block SB1) to another part of the physical block (first sub-block SBO).

[0220] Without wanting to be bound by any particular theory, it is believed that the described sub-block read refresh technique for addressing read disturb eliminates the need and unpredictability of locating an alternative block for relocated data.

[0221] In an embodiment, an apparatus is provided that includes a memory system that includes a plurality of memory die, each comprising a memory array including a plurality of non-volatile memory cells. The memory system has a bandwidth of about 3 TB / s, and each memory array has a power efficiency of about 1 pJ / bit.

[0222] For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0223] For purposes of this document, a connection may be a direct connection or anindirect connection (e.g.. via one or more others parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

[0224] For purposes of this document, the term “based on” may be read as “based at least in part on.”

[0225] For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

[0226] For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

[0227] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology7and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

CLAIMS 1. An apparatus comprising: a memory system comprising a plurality of memory die, each comprising a memory array comprising a plurality' of non-volatile memory cells, wherein: the memory' system comprises a bandwidth of about 3 TB / s; and each memory’ array comprises a power efficiency of about 1 pJ / bit.

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