Systems and methods for stochastic-to-binary number conversion for in-dram deep learning

Abstract

Various aspects for providing systems and methods for stochastic-to-binary number conversion are disclosed. Specifically, a first aspect includes a substrate for stochastic-to-binary number conversion, comprising: a plurality of bitline groups, each bitline group comprising a plurality of bitlines corresponding to an input stochastic operand bit-vector; a plurality of sense amplifiers, each sense amplifier electrically coupled to a respective bitline; a plurality of precharge units electrically coupled to the bitlines; a plurality of stochastic-to-analog units electrically coupled between the sense amplifiers and an analog line of each bitline group; a plurality of analog-to-unary units electrically coupled between the analog line and the bitlines of each bitline group; and an unary-to-binary unit electrically coupled to the bitlines of each bitline group.

Description

SYSTEMS AND METHODS FOR STOCHASTIC-TO-BINARY NUMBER CONVERSION FOR IN-DRAM DEEP LEARNINGGOVERNMENT SUPPORTCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This Application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 552,415, filed on February 12, 2024, the entire contents of which are hereby incorporated by reference.GOVERNMENT SUPPORT

[0002] The present disclosure was made with support from grant 2139167 from the National Science Foundation. The Government may have certain rights to the invention.BACKGROUNDField

[0003] Aspects of the present disclosure relate to stochastic-to-binary number conversion in dynamic random access memory (DRAM).Description of Related Art

[0004] Convolutional Neural Networks (CNNs) have become a cornerstone in the field of machine learning and artificial intelligence, revolutionizing how visual recognition tasks are approached and solved. These networks are designed to emulate the human brain's capacity for visual processing, employing a myriad of complex arithmetic operations such as multiply- accumulate (MAC), nonlinear activation, and pooling to achieve remarkable accuracy in tasks ranging from image classification to object detection. The inherent parallelism in these operations presents an opportunity for acceleration, yet the realization of this potential is hampered by significant challenges when utilizing conventional Application-Specific Integrated Circuit (ASIC) platforms, exemplified by systems like Dadiannao and EIE. These challenges primarily stem from the 0 memory wallO problem, which arises due to the extensive number of operands required by CNNs, thereby constraining computational efficiency.

[0005] In response to the limitations of ASICs, attention has turned towards Processing-In- Memory (PIM) architectures as a promising alternative for accelerating CNNs. PIM designs leverage the proximity of memory and processing elements to mitigate the data movement bottleneck, with various approaches being explored across emerging non-volatile memory (NVM)technologies, traditional DRAM, and Static Random-Access Memory (SRAM) technologies. Among these, DRAM-based PIM solutions have emerged as particularly compelling due to DRAM's dominant role in main memory systems, lower latency, and better tolerance for frequent writes compared to NVM. However, SRAM, despite its prevalence, is often deemed less suitable for large-scale CNN applications due to its high area cost and relatively low capacity.

[0006] Despite the advantages of DRAM-based PIM designs, such as reducing the memory performance bottleneck, they encounter their own set of challenges, particularly in the execution of MAC operations which are both compute and memory intensive. Traditional approaches require a significant number of memory operation cycles (MOCs) per MAC operation, leading to increased latency and energy consumption. Innovations like SCOPE and ATRIA have introduced the use of stochastic arithmetic to substantially reduce the number of required MOCs by simplifying multiplication operations into bit-wise logical AND operations. This reduction in MOCs represents a significant advancement in the efficiency of DRAM-based PIM accelerators.

[0007] However, the implementation of stochastic arithmetic introduces the need for stochastic-to-binary (StoB) number conversions, which in turn, incurs additional latency and energy costs. The methodologies employed by ATRIA and SCOPE for StoB conversions, while innovative, reveal limitations within DRAM-based systems due to the constraints of DRAM processes that are not well-suited for the area, latency, and energy optimizations required for efficient StoB conversion. This highlights a critical area of concern, where the benefits offered by stochastic arithmetic are potentially undermined by the inefficiencies in StoB conversion mechanisms, underscoring the need for further innovation in DRAM-based PIM accelerator designs to fully harness the computational potential of CNNs.SUMMARY

[0008] Systems and method for a substrate that performs stochastic-to-binary number conversion are disclosed. In one aspect, the substrate comprises: a plurality of bitline groups, each bitline group comprising a plurality of bitlines corresponding to an input stochastic operand bitvector; a plurality of sense amplifiers, each sense amplifier electrically coupled to a respective bitline; a plurality of pre-charge units electrically coupled to the bitlines; a plurality of stochastic- to-analog units electrically coupled between the sense amplifiers and an analog line of each bitline group; a plurality of analog-to-unary units electrically coupled between the analog line and the bitlines of each bitline group; and an unary- to-binary unit electrically coupled to the bitlines of each bitline group.

[0009] Another aspect includes a substrate for enabling in-memory stochastic to binary conversion. In one aspect, the substrate comprises a plurality of bitline groups in a DRAM bank, each bitline group comprising a set of bitlines corresponding to an input stochastic bit vector; sense amplifiers electrically coupled to the bitlines; stochastic-to-analog converter circuits electrically coupled between the sense amplifiers and analog lines of each bitline group; analog- to-unary converter circuits electrically coupled between the analog lines and the bitlines of each bitline group; and unary-to-binary converter circuits electrically coupled to the bitlines of each bitline group.

[0010] Another aspect includes a system for stochastic to binary conversion. In one aspect, the system comprises a memory bank having a plurality of bitline groups, each bitline group allocated to an input stochastic bit vector; sense amplifiers electrically coupled to bitlines of each bitline group; converter stages electrically coupled to the sense amplifiers and bitlines of each bitline group, including: stochastic-to-analog converter circuits electrically coupled between the sense amplifiers and analog lines; analog-to-unary converter circuits electrically coupled between the analog lines and the bitlines; and unary-to-binary encoder circuits having inputs electrically coupled to the bitlines; and control logic configured to orchestrate operation of the converter stages using timing signals.

[0011] Another aspect includes a method for in-memory stochastic-to-binary conversion. In one aspect, the method comprises activating bitcells storing an input stochastic bit vector to load corresponding logic states into sense amplifiers of a bitline group; converting the logic states of the sense amplifiers into an analog voltage on an analog line of the bitline group; converting the analog voltage into a unary number represented on bitlines of the bitline group; and converting the unary number into a binary output code.

[0012] Another aspect includes a method for converting a stochastic bit vector to binary performed in a memory bank. In one aspect, the method comprises: loading the stochastic bit vector from activated memory cells into sense amplifiers of an allocated bitline group; turning on first switch devices between ON (e.g., logically activated) state sense amplifiers and a first capacitor to share charge corresponding to logic states of the sense amplifiers; pre-charging bitlines of the bitline group to reference voltages from a resistor ladder; turning on second switch devices between the first capacitor and the pre-charged bitlines to mutually share charge and perturb the pre-charged voltages; amplifying the perturbations on the bitlines to full logic high or full logic low voltages by the sense amplifiers to represent a unary number; transferring the unarynumber on the bitlines to an input of an encoder; and converting, by the encoder, the unary number into a binary code for output.

[0013] Another aspect includes a method for performing unary-to-analog conversion, wherein an addition function can be implemented in the unary number format.

[0014] Another aspect includes where the process of stochastic to binary conversion is performed at a constant latency irrespective of the size or precision of the input and output numbers. Such an aspect is more predictable and significantly superior than the state-of-the-art stochastic to binary conversion methods where the latency of conversion increases exponentially as at least one of size or precision of at least one of input or output increases.

[0015] Other embodiments provide processing systems configured to perform the aforementioned methods as well as those described herein; non-transitory, computer-readable media comprising instructions that, when executed by a processors of a processing system, cause the processing system to perform the aforementioned methods as well as those described herein; a computer program product embodied on a computer readable storage medium comprising code for performing the aforementioned methods as well as those further described herein; and a processing system comprising means for performing the aforementioned methods as well as those further described herein.

[0016] These and additional features provided by the embodiments of the present disclosure will be more fully understood in view of the following detailed description, in conjunction with the drawings.DESCRIPTION OF THE DRAWINGS

[0017] The appended figures depict certain aspects and are therefore not to be considered limiting of the scope of this disclosure.

[0018] FIGS. 1A and IB depict stochastic and transition-coded unary formats, in accordance with examples of the present disclosure.

[0019] FIGS. 1C and ID depict a diagram of flash ADC (analog-to-digital converter) with 3- bit binary output, in accordance with examples of the present disclosure.

[0020] FIGS. 2A-2D depicts aspects of an AGNI substrate configuration as incorporated within a DRAM tile, in accordance with examples of the present disclosure.

[0021] FIG. 3 depicts an example AGNI substrate that performs stochastic-to-binary conversion of input operands, in accordance with examples of the present disclosure.

[0022] FIGS. 4A-4B depict example signals for performing stochastic-to-binary conversion of input operands, in accordance with examples of the present disclosure.

[0023] FIGS. 5A-5H depict example timing diagrams, in accordance with examples of the present disclosure.

[0024] FIG. 6 depicts an example method for performing stochastic-to-binary conversion of input operands, in accordance with examples of the present disclosure.

[0025] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0026] Aspects of the present disclosure provide apparatuses, methods, processing systems, and computer-readable mediums for efficient in- situ binary conversion of stochastic operands within a DRAM substrate.

[0027] Stochastic computing has emerged as an efficient technique for accelerating CNNs, but relies on stochastic-to-binary conversion that can diminish performance gains. Current stochastic-to-binary conversion mechanisms reveal limitations when implemented within DRAMbased processing-in-memory architectures resulting from constraints of DRAM process technology. This highlights the need for an optimized stochastic-to-binary conversion substrate tailored to DRAM processes.

[0028] A technical problem includes that prior stochastic-to-binary conversion techniques exhibit deficiencies within DRAM-based accelerators in terms of area, latency, and energy overhead that can undermine the intended benefits of using stochastic computing for CNN acceleration.

[0029] Aspects of the present disclosure provide an Analog-to-Unary-to-Binary In-situ (AGNI) conversion substrate leveraging modified DRAM peripherals orchestrated by timing signals to perform stochastic-to-binary conversion directly in the DRAM substrate. The substrate divides the conversion into multiple steps that re-purpose native DRAM components for unarycomputation without complex custom circuits. The AGNI substrate provides an area-efficient stochastic-to-binary conversion architecture customized for DRAM process technology to overcome limitations of prior designs. This helps fully realize the acceleration potential of stochastic computing for in-DRAM CNN workloads with reduced latency and increased throughput.

[0030] FIGS. 1A and IB depict a real-valued variable u set at 0.5, in both stochastic (e.g., FIG. 1A) and transition-coded (e.g., FIG. IB) unary formats. In the unipolar format of unary computing, a unary number IF is a bit-stream of N bits that represents a real valued variable u G[0, 1] by encoding u through the ratio Ni / N, where Ah is the number of 10 s in W. As shown in FIG.1A, a unary number (e.g., u=0.5) can be presented in the stochastic format (also known as rate- coded unary format) or in the transition-coded unary format (FIG. IB). As evident from FIGS. 1A and IB, in the stochastic format the 0 IDs in the bit-stream do not appear in a group, whereas in the transition-coded unary format the 0 IDs in the bit-stream appear in group.

[0031] FIGS. 1C and ID depict schematics 102 and 108 of flash ADC (analog-to-digital converter) with 3-bit binary output. FIGS. 1C and ID illustrate the conversion of two example input values. As depicted in FIG. 1C, a B-bit flash ADC uses one voltage divider, a total of 2Bcomparators and one 2B:B priority encoder (e.g., B=3 in FIGS. 1C and ID). Thus, each circuit in FIG. 1C and ID has eight voltage comparators (i.e., Cl, C2, C3, C4, C5, C6, C7, and C8). The positive terminals of all comparators may be electrically coupled to the analog input Vin. The negative terminal of the comparators may be electrically coupled to VREF derived from the resistorladder based voltage divider.

[0032] As depicted in FIG. 1C, in an example scenario where Vin = 0.5 VDD (FIG. 1C), the output 104 of the priority encoder 106 is binary four, where the output of the comparators that are input to the priority encoder 106 (i.e., the bit sequence 00001111) represents 0.5 in the transition- coded unary format. Similarly, in an example scenario where Vin = 0.25 VDD (FIG. ID), the output 110 of the priority encoder 112 is binary two, and the output of the comparators (i.e., the bit sequence 00000011) represents 0.25 in the transition coded unary format. Thus, a flash ADC undertakes analog to binary conversion in two phases: first, analog to unary conversion through the comparators, and second, unary to binary conversion through the priority encoders.

[0033] To address shortcomings described above, aspects of the present disclosure provide a substrate for in-DRAM stochastic-to-binary (StoB) number conversion called Analog-to-Unary-to-Binary In-situ conversion (AGNI). AGNI introduces DRAM peripherals that utilize pass transistors, capacitors, encoders, and charge pumps to divide the StoB conversion into four phases orchestrated by DRAM timing signals: (i) DRAM row activation, (ii) stochastic to analog conversion via charge sharing, (iii) analog to transition-coded unary conversion by repurposing sense amplifiers as comparators, and (iv) transition-coded unary to binary conversion via encoders. Utilizing such timing AGNI enables efficient in-situ binary conversion of stochastic operands of varying sizes directly within the DRAM substrate. In some examples, some existing DRAM components can be re-purposed to implement unary conversion functions; thus avoiding complex custom circuits. AGNI provides a StoB conversion substrate that overcomes challenges with prior DRAM accelerator designs.

[0034] FIG. 2A depicts aspects of an AGNI substrate configuration as it is incorporated within a DRAM tile 204 in accordance with examples of the present disclosure. In examples, this configuration enables the in-situ conversion of stochastic operands into binary numbers by modifying the structure of the DRAM tile 204. The DRAM tile 204 can be modified to include multiple bitline groups 206A to 206C (BLgroups), each corresponding to a distinct input stochastic operand. The bitlines within these BLgroups, identified as 202A to 202N, may be arranged to match the size of the stochastic operand's bit- vector. Thus, a DRAM tile with L bitlines can accommodate LIN BLgroups, each with N bitlines. Additional peripherals, including per bitline SA units 208, per bitline A_to_U units 212, and per BLgroup U_to_B units 214, facilitate the conversion process along with analog lanes 216A to 216N, each terminating with a capacitor 218, enabling efficient signal processing within the BLgroups.

[0035] As depicted in FIG. 2B, the S_to_A unit 210 includes two transistors 220 and 222. As depicted in FIG. 2C, the A_to_U unit 212 includes one transistor 224. As depicted in FIG. 2D, each U_to_B unit 214 includes an isolation transistor (ISO) 226 per bitline (i.e., N ISOs per BLgroup) along with a priority encoder (PE) 228 and a latch 230 converting stochastic inputs into analog signals. The S_to_A and A_to_U units belonging to a BLgroup are coupled to their corresponding bitlines 202 and SAs 208 via a respective LANE 216 having an analog lane capacitor 218. The N S_to_A units 210 of a BLgroup 206 enable stochastic-to-analog number conversion; the N A_to_U units 212 of the same BLgroup 206 enable analog-to-unary (transition coded unary) number conversion; and the U_to_B unit 214 of the same BLgroup 206 enables unary-to-binary number conversion. Thus, the additional peripherals of the AGNI substrate enable one stochastic-to-analog-to-unary-to-binary number conversion per BLgroup 206, thereby enabling a total of LIN such conversions in-parallel per DRAM tile 204.

[0036] FIG. 3 depicts an example AGNI substrate 302 that performs stochastic-to-binary conversion of input operands utilizing the following three stages: (i) stochastic to analog (S_to_A) conversion, (ii) analog to transition-coded unary (A_to_U) conversion, and (iii) transition-coded unary to binary (U_to_B) conversion. Initially, the operand may be read into the sense amplifiers 306 of the corresponding BLgroup prior to performing stochastic to analog (S_to_A) conversion, which can be achieved by activating a corresponding DRAM row that contains the stochastic operand. Thus, in some aspects, a DRAM row activation is to precede the above three stages, constituting a sequence of four stages (e.g., DRAM row activation, and three conversions) for the operation of AGNI substrate to perform stochastic-to-binary number conversion.

[0037] The AGNI substrate 302 utilizes several timing signals to enable the four stages described above. The timing signals for the DRAM row activation may include standard DRAM operation signals that include, but not limited to wordline and sense activation signals. The remaining three stages can use additional timing signals to control the added peripherals of the AGNI substrate 302. Example timing signals for DRAM row activation are depicted in FIG. 4A; example signals for performing stochastic-to-binary conversion of input operands are depicted in 4B. Such signals control various hardware units of the AGNI substrate as depicted in FIG. 3 for an example BLgroup of AGNI substrate 302 with N = 4.

[0038] The BLgroup illustrated in FIG. 3 is depicted with four bitlines 304A-304D (BLo, BLi , BL2, and BL3). These bitlines 304A-304D correspond to four DRAM bit-cells, i.e., mbo, mbi, mbz, and mb?,, respectively. Each bitline 304A-304D may be coupled to a respective sense amplifier 306A-306D and a respective pre-charge unit 3O8A-3O8D. Additionally, each bitline 304A-304D may be coupled to an S_to_A unit 31OA-31OD and an A_to_U unit 312A-312D. Moreover, bitlines 304A-304D of the BLgroup (i.e., BLO, BLI, BL2, and BL3) may be coupled to an U_to_B unit 314, which may include an A:log2A priority encoder 316, an logzA-bit latch 318, A isolation transistors (ISOs) 320A-320D, resistor ladder-based voltage divider 322, and A multiplexers 324A-324D that select VREF values for corresponding sense amplifiers 306A-306D. A VREF value can be VDD / 2 or an appropriate level obtained from the voltage divider 322. The selection of VREF values from the voltage divider 322 enables the sense amplifiers 306A-306D to operate as voltage comparators, providing the ability to perform analog-to-unary conversion in a manner similar to the flash ADC described in FIG. 1C and FIG. ID.

[0039] As previously described, and in accordance with examples of the present disclosure, the process to perform stochastic-to-binary conversion of input operands can include four stages.The first stage generally includes activating the DRAM row. That is, signals EQ, WL, and sense_n (sense_p) signals may be activated to read the input stochastic operands in the sense amplifiers (e.g., 306 of FIG. 3). As depicted in FIG. 5B, EQ 504A is toggled ON (e.g., logically activated), at a time corresponding to 0 ns. As SEL 510 (FIG. 5C) is considered to be ON (e.g., logically activated), at 0 ns, VREF from the sense amplifiers 306 has been selected to be VDD / 2. AS a result, the voltage on the bitlines (e.g., 304A-304D) (e.g., VREFBO 502A, VREFBI 502B, VREFB2 502C, and VREFB3 502D) settles to VDD / 2 after 0 ns, as depicted in FIG. 5A. Such step is conventionally described as bitline precharging. After pre-charing, EQ 504A (FIG. 5B) is toggled OFF (e.g., logically deactivated) at approximately 5 ns. At approximately 7 ns, WL 508 (FIG. 5C) is toggled ON (e.g., logically activated). As a result, the DRAM cells (mbO, mbl, mb2, and mb3) are coupled to their respective bitlines (e.g., 304A-304D) and share their respective charges with their respective bitlines (e.g., 304A-304D). Due to this charge sharing, the voltage on the DRAM cells dips (e.g., 516A-516D) FIG. 5E at 7 ns), depicted at approximately 7 ns, and the voltage on the bitlines (e.g., 304A-304D corresponding to Bo 512A, Bi 512B, B2 512C, and B3 512D) is perturbed (see FIG. 5D at 7 ns). At approximately 9 ns, sense_n 518A (sense p) is toggled ON (e.g., logically activated) (see FIG. 5F), which enables the sense amplifiers to sense the perturbed bitline voltage and amplify it to the full swing.

[0040] In FIG. 5D, since the bitline voltage perturbation is in the positive direction (corresponding to logic 010 stored in the DRAM cells), the bitline voltage swings to VDD by the sense amplifiers. After this full-swing amplification of bitline voltage perturbation, the sense amplifiers complete replenishing the DRAM cell voltage at approximately 11 ns. The perturbation amplification and cell replenishing both occur quickly generally due to the short bitline DRAM architecture for AGNI. At approximately 12 ns, WL 508 (FIG. 5C) is toggled OFF (e.g., logically deactivated), to disconnect the DRAM cells from the bitlines, to mark the end of the DRAM row activation step.

[0041] During this step, the bitline voltage evolution encounters transient noise at two events, due to parasitic effects. First, at approximately 5 ns when EQ 504A is toggled OFF (e.g., logically deactivated). This event is labeled as glitch 514A in FIG. 5D. Second, at approximately 12 ns when WL 508 is toggled OFF (e.g., logically deactivated) (labeled as glitch 514B in Fig. 5D).

[0042] The S_to_A conversion phase generally utilizes sense_n 518A (sense p), and KI 522 (FIG. 5G) signals to conduct the conversion of the stochastic operands (which are read into the sense amplifiers as a result of DRAM row activation described above; the sens_n 518A (sense p)and KI 522 signals are generally analog quantities (analog voltage levels). These analog quantities are accrued on respective analog capacitors (e.g.,one analog voltage level per capacitor per BLgroup). Accordingly, the analog capacitor of each BLgroup accrues charge incoming from respective sense amplifiers by having KI 522 signal to operate the S_to_A peripheral units (e.g., 31OA-31OD) (FIG. 3) of the BLgroup. Each S_to_A unit can include a pass transistor 220 and a diode (realized as the back-biased nmos transistor 222 shown in FIG. 2B and FIG. 3). The presence of diode (e.g., 322) enables the connection of the sense amplifier to the pass transistor 220 if the sense amplifier has latched logic 010 0 that is, if the corresponding bitline is at VDD. Consequently, when KI 522 signal turns ON (e.g., logically activated) the pass transistors (e.g., 220) of all S_to_A units (e.g., 310A) of a BLgroup, the sense amplifiers (e.g., 306 A) of the BLgroup that are storing VDD connect to the corresponding analog capacitor (e.g., 350) via the bitlines and analog LANE 352 (FIG. 3). The sense amplifiers 306, if ON (e.g., logically activated), then can force the analog capacitor 350 to accrue some charge, and consequently, some analog voltage level. If the sense amplifiers 306 are kept ON (e.g., logically activated) for a fixed period of time, the accrued analog voltage level on the analog capacitor 350 would be proportional to the number of sense amplifiers 306 that are electrically coupled to the analog capacitor 350. Since only the sense amplifiers 306 that are storing VDD can connect to the analog capacitor 350, the accrued voltage level on the analog capacitor 350 would be proportional to the number of logic logic 010 s in the stochastic operand that are read into the sense amplifier 306 during DRAM row activation. This is because only the sense amplifiers 306 corresponding to logic DID bits of the stochastic operand would be storing VDD after DRAM row activation. Thus, the voltage level accrued on the analog capacitor 350 provides the analog representation of the stochastic operand.

[0043] In examples, KI 522 is toggled ON (e.g., logically activated) at approximately 13 ns (FIG. 5G). At this time, sense_n and sense_p (e.g., 518A) are already ON (e.g., logically activated), as they were toggled ON (e.g., logically activated) during DRAM row activation at approximately 9 ns. KI 522 and sense_n 518A (sense_p) are maintained ON (e.g., logically activated) for approximately 24 ns, during which the sense amplifiers accrue a voltage level on the analog capacitor 350 (e.g., voltage level 526 (FIG. 5H) corresponding to voltage level of sense capacitor 350). In equilibrium, the analog LANE 352 also accrues the same voltage level as the analog capacitor 350. Then, at approximately 37 ns, both KI 522 and sense_n 518A (sense p) are toggled OFF (e.g., logically deactivated) (see FIGS. 5F and 5G), to mark the end of the S_to_A conversion phase.

[0044] At the conclusion of the S_to_A conversion phase, the voltage level accrued on the analog capacitor and LANE provides the analog representation of the stochastic operand. During this phase, the length of time KI 522 and sense_n 518A (sense p) are ON (e.g., logically activated) can be determined based on providing a sufficient noise margin so that different analog voltage levels accrued on the analog capacitor 350 are unerringly distinguishable. In examples, KI 522 and sense_n 518A are on for approximately 24 ns. Similarly, a 24 ns duration can be sufficient to provide a total of N distinguishable voltage levels on the analog capacitor 350 even for N=256. Thus, regardless of the value N (i.e., the length of the input stochastic operand), this S_to_A step can achieve the analog representation of an input stochastic operand with iso-latency of 24 ns.

[0045] As shown in FIGS. 1C and ID, a flash ADC undertakes analog to digital (binary) conversion in two stages. In the first stage, an input analog voltage is converted into the equivalent transition-coded unary number using an array of voltage comparators. In the second stage, the unary number is then converted into the corresponding binary number using a priority encoder. The A_to_U conversion phase of the AGNI substrate 302 implements a second stage of a flash ADC by re-purposing the sense amplifiers 306 as comparators. This re-purposing of sense amplifiers 306 as comparators is realized using three periods of the A_to_U phase of the AGNI substrate 3020 by relying on signals EQ 504A, SEL 510, Bl 524, and sense_n 518A (sense p).

[0046] More specifically, in a first period, SEL 510 is toggled OFF (e.g., logically deactivated) at approximately 38 ns, as shown in FIG. 5C, to select VREF values from the voltage divider circuit 322 in the precharge units of all N sense amplifiers 306 of a BLgroup (e.g., see VREFBO, VREFBI, VREFB2, and VREFBS in FIG. 3). Then, in the second period, EQ 504A is toggled ON (e.g., logically activated) at approximately 38 ns and then toggled OFF (e.g., logically deactivated) at approximately 42 ns, to precharge the bitlines 304A-304D of all N sense amplifiers 306A-306D to their respective VREF values. As a result, between the approximate 38 ns and approximate 42 ns times, as depicted in FIG. 5D, the bitline voltages 512A, 512B, 512C, and 512D proceed to their respective VREF values. Then, in the next period, Bl 524 is toggled ON (e.g., logically activated) at approximately 43 ns so that the LANE 352 and analog capacitor 350 are electrically coupled to the bitlines 340A-304D to enable mutual charge sharing. As a result, the bitline voltages (e.g., 512A-512D) are perturbed by about 45 ns FIG. 5D. If the bitline 304 corresponding to a sense amplifier 306 (out of a total of N sense amplifiers) was precharged to a voltage level greater (less) than the voltage level accrued on the analog capacitor 350, the perturbation due to charge sharing would increase (decrease) the voltage of that respective bitline 304. To sense and amplify this perturbation, sense_n 518A (sense p) is toggled ON (e.g., logically activated) atapproximately 45 ns. Consequently, the voltages on the bitlines 304 proceed to their full-swing values (VDD or 0V) at approximately 50ns, depending on the direction of the voltage perturbation. Therefore, some of the N sense amplifiers 306 store a logic 010 and the others end up storing a logic 1 01 , where the number of logic > IDs out of N sense amplifiers 306 provides the unary representation of the voltage on the analog capacitor 350.

[0047] In some instances, the positions of the 0 IDs in the unary representation differ compared to the positions of the 010 s in the input stochastic operand. To aid in this explanation, suppose the voltage accrued on the analog capacitor 350 is 0.5V MAX for N=4. This would happen for the case where mbO=l, mbl=0, mb2=0, mb3=l. In this case, the perturbation would increase the voltages on only BLO (e.g., 304D) and BL1 (e.g., 304C) in FIG. 3; the voltages on BL2 (e.g., 304B) and BL3 (e.g., 304A) would actually decrease after the perturbation. As a result, the sense amplifiers 306 would sense and amplify logic 010s for BLO (e.g., 304D) and BL1 (e.g., 304C), thereby providing the positions of 0 IDs in the unary representation to be 0011 (from the left to the right) when the positions of 010 s in the stochastic input operand are 1001. This change in the positions of 010s in the unary representation favors the use of a priority encoder (e.g., 316) to convert from unary to the binary number format. Without this change, converting into the binary number format would require more complex combinational logic, such as a parallel pop counter.

[0048] In the U_to_B phase, timing signals ISO 520, LI 506 and Bl 522 signals as well as a priority encoder 316 can be used to convert the unary number stored in the sense amplifiers 306 at the conclusion of the A_to_U conversion phase, into its corresponding binary number. To accomplish this, ISO 520 is toggled ON (e.g., logically activated) at approximately 45 ns (e.g., FIG. 5F), so that the ISO transistors (e.g., 320A-320D FIG. 3) turn ON (e.g., logically activated) to connect the bitlines 304A-304D to the priority encoder 316. Therefore, when the sense amplifiers 306 complete evolving the bitline voltages according to their stored unary number at approximately 50 ns (as discussed in in the A_to_U conversion phase), the stored unary number reaches the priority encoder 316 at approximately 50 ns through the bitlines 304A-304D via the ISO transistors (e.g., 320A-320D). At approximately 51 ns, the priority encoder 316 starts providing the converted binary number at its output. Therefore, LI 506 is toggled ON (e.g., logically activated) at approximately 51 ns to enable latching of the priority encoder 316 output (i.e., the binary number result). Then, LI 506 is toggled OFF (e.g., logically deactivated) at approximately 52 ns, and Bl 522 and ISO 520 are toggled OFF (e.g., logically deactivated) at approximately 55 ns, to mark the conclusion of the full operation cycle of AGNI. Thus, AGNI can convert input stochastic number into the binary format in approximately 55 ns, irrespective of thesize of the input stochastic operand (i.e., the value of N). Finally, at the end of approximately 55 ns, each BLgroup (e.g., 314) of AGNI substrate 302 becomes available to convert a new stochastic operand.

[0049] In some examples, during the U_to_B phase, bitline voltages (e.g., 512A-512D) experience another glitch at approximately 55 ns time-stamp (labeled as 514C in FIG. 5D), due to the toggling OFF (e.g., logically deactivated) of Bl 522 that disconnects the bitlines 304A- 304D from the LANE 352 and analog capacitor 350.

[0050] FIG. 6 depicts an example method 600 for performing stochastic-to-binary conversion of input operands, in accordance with examples of the present disclosure. In examples, the method 600 may begin at 602, where a DRAM row is activated in a manner as previously described with respect to FIGS. 2A-5H. The method 600 may proceed to 604, and perform stochastic to analog conversion in a manner as previously described with respect to FIGS. 2A-5H. The method 600 may proceed to 606, and perform analog to unary conversion in a manner as previously described with respect to FIGS. 2A-5H. The method 600 may proceed to 608 and perform unary to binary conversion in a manner as previously described with respect to FIGS. 2A-5H.

[0051] The present disclosure provides systems and methods for stochastic-to-binary number conversion for in-DRAM deep learning. Aspects introduce a substrate called AGNI that enables efficient in- situ binary conversion of stochastic operands of varying sizes directly within the DRAM substrate. AGNI modifies DRAM peripherals to divide the conversion process into multiple steps orchestrated by timing signals. This allows re-purposing of some existing DRAM components to implement unary conversion functions, avoiding complex custom circuits. In examples, the AGNI substrate overcome challenges exhibited by prior stochastic computing architectures for CNN acceleration, where benefits of using stochastic arithmetic were diminished due to inefficient stochastic-to-binary conversion mechanisms. By providing an optimized substrate tailored to DRAM processes, AGNI helps unlock the potential computational benefits of in-DRAM stochastic arithmetic for CNN workloads. The apparatus, systems and methods described herein facilitate stochastic-to-binary conversion for reduced latency and increased throughput in DRAM-based PIM accelerator designs. AGNI can be integrated into existing or emerging deep learning accelerators and artificial intelligence systems to advance their performance and efficiency.

[0052] While particular embodiments and aspects of the present disclosure have been illustrated and provided herein, various other changes and modifications can be made withoutdeparting from the spirit and scope of the disclosure. Moreover, although various aspects have been provided herein, such aspects need not be utilized in combination. Accordingly, it is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the embodiments shown and provided herein.

[0053] Various aspects for providing systems and methods for stochastic-to-binary number conversion are disclosed. Specifically, a first aspect includes a substrate for stochastic-to-binary number conversion, comprising: a plurality of bitline groups, each bitline group comprising a plurality of bitlines corresponding to an input stochastic operand bit- vector; a plurality of sense amplifiers, each sense amplifier electrically coupled to a respective bitline; a plurality of precharge units electrically coupled to the bitlines; a plurality of stochastic-to-analog units coupled between the sense amplifiers and an analog line of each bitline group; a plurality of analog-to- unary units electrically coupled between the analog line and the bitlines of each bitline group; and an unary-to-binary unit electrically coupled to the bitlines of each bitline group.

[0054] A second aspect includes the substrate of the first aspect, wherein each stochastic-to- analog unit comprises: a pass transistor having a first terminal electrically coupled to a respective sense amplifier and a second terminal electrically coupled to the analog line; and a diode coupled between the first and second terminals of the pass transistor.

[0055] A third aspect includes the substrate of the second aspect, wherein the diode enables a connection between the respective sense amplifier and the pass transistor when the sense amplifier stores a first logic value.

[0056] A fourth aspect includes the substrate of the first aspect, wherein each analog-to-unary unit comprises a transistor having a first terminal electrically coupled to the analog line and a second terminal electrically coupled to a respective bitline.

[0057] A fifth aspect includes the substrate of the first aspect, wherein the unary-to-binary unit of each bitline group comprises: a priority encoder; a latch electrically coupled to the priority encoder; and a plurality of isolation transistors, each isolation transistor electrically coupled between a respective bitline and the priority encoder.

[0058] A sixth aspect includes the substrate of the fifth aspect, wherein each pre-charge unit comprises a voltage divider circuit and a multiplexer configured to select a reference voltage from the voltage divider circuit for provision to an electrically coupled sense amplifier.

[0059] A seventh aspect includes the substrate of the sixth aspect, wherein selection of the reference voltage from the voltage divider circuit enables the sense amplifier to operate as a voltage comparator.

[0060] An eight aspect includes the substrate of the first aspect, further comprising an analog line capacitor electrically coupled to the analog line of each bitline group.

[0061] A ninth aspect includes the substrate of the eighth aspect, wherein the analog line accumulates an analog voltage level corresponding to a number of sense amplifiers storing a first logic value.

[0062] A tenth aspect includes the substrate of the ninth aspect, wherein the analog voltage level provides an analog representation of the input stochastic operand bit vector.

[0063] An eleventh aspect includes a substrate for enabling in-memory stochastic to binary conversion, comprising: a plurality of bitline groups in a dynamic random access memory (DRAM) bank, each bitline group comprising a set of bitlines corresponding to an input stochastic bit vector; sense amplifiers electrically coupled to the bitlines; stochastic-to-analog converter circuits electrically coupled between the sense amplifiers and analog lines of each bitline group; analog-to-unary converter circuits electrically coupled between the analog lines and the bitlines of each bitline group; and unary- to-binary converter circuits electrically coupled to the bitlines of each bitline group.

[0064] A twelfth aspect includes the substrate of the eleventh aspect, further comprising precharge units electrically coupled to the bitlines of each bitline group.

[0065] A thirteenth aspect includes the substrate of the twelfth aspect, wherein each precharge unit comprises a reference voltage selection circuit configured to enable operation of electrically coupled sense amplifiers as comparators.

[0066] A fourteenth aspect includes the substrate of the eleventh aspect, wherein the stochastic-to-analog converter circuits are configured to convert logic states of the sense amplifiers into an analog voltage on the analog lines.

[0067] A fifteenth aspect includes the substrate of the fourteenth aspect, further comprising capacitors electrically coupled to the analog lines of each bitline group for accumulation of the analog voltages.

[0068] A sixteenth aspect includes the substrate of the eleventh aspect, wherein the analog- to-unary converter circuits comprise transistors to enable mutual charge sharing between the analog lines and the bitlines.

[0069] A seventeenth aspect includes the substrate of the sixteenth aspect, wherein the charge sharing perturbs voltages on the bitlines for subsequent sensing by the sense amplifiers.

[0070] An eighteenth aspect includes the substrate of the eleventh aspect, wherein the unary- to-binary converter circuits comprise encoders electrically coupled to the bitlines via isolation transistors.

[0071] A nineteenth aspect includes the substrate of the eighteenth aspect, wherein the encoders comprise priority encoders.

[0072] A twentieth aspect includes the substrate of the eleventh aspect, wherein the substrate is integrated within a DRAM module.

[0073] A twenty-first aspect includes a system for stochastic to binary conversion, comprising: a memory bank having a plurality of bitline groups, each bitline group allocated to an input stochastic bit vector; sense amplifiers electrically coupled to bitlines of each bitline group; converter stages electrically coupled to the sense amplifiers and bitlines of each bitline group, including: stochastic-to-analog converter circuits electrically coupled between the sense amplifiers and analog lines; analog-to-unary converter circuits electrically coupled between the analog lines and the bitlines; and unary- to-binary encoder circuits having inputs electrically coupled to the bitlines; and control logic configured to orchestrate operation of the converter stages using timing signals.

[0074] A twenty-second aspect includes the system of the twenty-first aspect, wherein orchestration of the converter stages by the control logic comprises: activating a row of memory cells containing the input stochastic bit vector to load into the sense amplifiers; converting logic states of the sense amplifiers into an analog voltage on the analog lines; converting the analog voltage into a unary number on the bitlines; and converting the unary number into a binary output.

[0075] A twenty- third aspect includes the system of the twenty- second aspect, wherein converting the logic states of the sense amplifiers into the analog voltage comprises turning on pass transistors between ON (e.g., logically activated) sense amplifiers and the analog lines to share charge.

[0076] A twenty-fourth aspect includes the system of the twenty-second aspect, wherein converting the analog voltage into the unary number comprises pre-charging the bitlines to reference voltages and mutually sharing charge between the analog lines and the bitlines.

[0077] A twenty-fifth aspect includes the system of the twenty-second aspect, wherein converting the unary number into the binary output comprises connecting bitline voltages corresponding to the unary number to inputs of the encoder circuits.

[0078] A twenty- sixth aspect includes the system of the twenty- first aspect, wherein the converter stages perform the stochastic to binary conversion with uniform latency irrespective of bit- vector sizes of the input stochastic bit vectors.

[0079] A twenty- seventh aspect includes the system of the twenty- first aspect, wherein the system is integrated within a memory module comprising the memory bank.

[0080] A twenty-eighth aspect includes the system of the twenty-first aspect, wherein the system is integrated within a processing system comprising the memory module.

[0081] A twenty-ninth aspect includes the system of the twenty-eighth aspect, wherein the processing system comprises a deep learning accelerator or an artificial intelligence accelerator.

[0082] A thirtieth aspect includes the system of the twenty-first aspect, wherein at least a portion of the system is implemented using DRAM technology.

[0083] A thirty- first aspect includes a method for in-memory stochastic-to-binary conversion, comprising: activating bitcells storing an input stochastic bit vector to load corresponding logic states into sense amplifiers of a bitline group; converting the logic states of the sense amplifiers into an analog voltage on an analog line of the bitline group; converting the analog voltage into a unary number represented on bitlines of the bitline group; and converting the unary number into a binary output code.

[0084] A thirty- second aspect includes the method of the thirty-first aspect, wherein converting the logic states of the sense amplifiers into the analog voltage comprises turning on pass transistors between ON (e.g., logically activated) sense amplifiers and the analog line to share charge.

[0085] A thirty- third aspect includes the method of the thirty- second aspect, further comprising holding the pass transistors ON (e.g., logically activated) for a fixed interval to enable distinguishable accumulation of the analog voltage.

[0086] A thirty-fourth aspect includes the method of the thirty-first aspect, wherein converting the analog voltage into the unary number comprises: pre-charging the bitlines to reference voltages from a resistor ladder; and sharing charge between the analog line and the bitlines to perturb pre-charged voltages.

[0087] A thirty- fifth aspect includes the method of the thirty- fourth aspect, further comprising amplifying the perturbations on the bitlines to full logic high or logic low voltages by the sense amplifiers.

[0088] A thirty-sixth aspect includes the method of the thirty-first aspect, wherein converting the unary number into the binary output code comprises: connecting bitline voltages representing the unary number to inputs of a priority encoder; and latching output bits from the priority encoder.

[0089] A thirty- seventh aspect includes the method of the thirty-first aspect, wherein the stochastic-to-binary conversion achieves uniform latency for different bit- vector sizes of input stochastic operands.

[0090] A thirty-eighth aspect includes the method of the thirty- first aspect, further comprising: allocating a plurality of input stochastic bit vectors to a plurality of bitline groups in a memory bank; and concurrently performing the stochastic-to-binary conversion method for the plurality of input stochastic bit vectors allocated to the plurality of bitline groups.

[0091] A thirty-ninth aspect includes a method for converting a stochastic bit vector to binary, performed in a memory bank, the method comprising: loading the stochastic bit vector from activated memory cells into sense amplifiers of an allocated bitline group; turning on first switch devices between ON (e.g., logically activated) state sense amplifiers and a first capacitor to share charge corresponding to logic states of the sense amplifiers; pre-charging bitlines of the bitline group to reference voltages from a resistor ladder; turning on second switch devices between the first capacitor and the pre-charged bitlines to mutually share charge and perturb the pre-charged voltages; amplifying the perturbations on the bitlines to full logic high or full logic low voltages by the sense amplifiers to represent a unary number; transferring the unary number on the bitlines to an input of an encoder; and converting, by the encoder, the unary number into a binary code for output.

[0092] A fortieth aspect includes the method of the thirty-ninth aspect, wherein the encoder comprises a priority encoder integrated in the memory bank.

[0093] A forty-first aspect includes the method of the thirty-ninth aspect, wherein the first capacitor comprises an analog capacitor electrically coupled to the allocated bitline group via an analog line.

[0094] A forty-second aspect includes the method of the thirty-ninth aspect, further comprising holding the first switch devices ON (e.g., logically activated) for a fixed interval to enable distinguishable accumulation of charge on the first capacitor corresponding to a logic state analog voltage.

[0095] A forty-third aspect includes the method of the thirty-ninth aspect, wherein transferring the unary number comprises turning on third switch devices between the respective bitlines and an input of the encoder.

[0096] A forty- fourth aspect includes the method of the thirty-ninth aspect, further comprising latching the output bits from the encoder.

[0097] A forty-fifth aspect includes the method of the thirty-ninth aspect, wherein switches in the memory bank comprise transistors controlled by timing signals.

[0098] A forty-sixth aspect includes the method of the forty-fifth aspect, further comprising orchestrating operation of the converting using the timing signals provided by control logic.

[0099] A forty-seventh aspect includes the method of the thirty-ninth aspect, wherein the unary-to-binary conversion by the encoder is performed with uniform latency regardless of bit size of the stochastic bit vector.

[0100] A forty-eighth aspect includes the method of the thirty-ninth aspect, wherein the method is performed concurrently for a plurality of stochastic bit vectors loaded into respective allocated bitline groups of the memory bank.

[0101] A forty-ninth aspect includes a method for performing unary-to-analog conversion, wherein an addition function can be implemented in the unary number format.

[0102] A fiftieth aspect includes where the process of stochastic to binary conversion is performed at a constant latency irrespective of the size or precision of the input and output numbers. In accordance with such aspect, it is more predictable and significantly superior than the state-of-the-art stochastic to binary conversion methods where the latency of conversion increases exponentially as at least one of size or precision of at least one of input or output increases.

[0103] A fifty- first aspect may include a substrate for stochastic-to-binary number conversion, comprising: a plurality of bitline groups, each bitline group comprising a plurality of bitlines, wherein the bitlines are configured to store an input stochastic operand bit- vector; a plurality of sense amplifiers, each sense amplifier electrically coupled to a respective bitline and configured to sense and amplify voltage levels corresponding to stored stochastic operand bits; a plurality of pre-charge units electrically coupled to the bitlines and configured to equalize bitline voltages; a plurality of stochastic-to-analog units electrically coupled between the sense amplifiers and an analog line of each bitline group, the stochastic-to-analog units being configured to convert stochastic operand data into an analog representation; a plurality of analog-to-unary units electrically coupled between the analog line and the bitlines of each bitline group, the analog-to- unary units being configured to convert analog representations into transition-coded unary values; and at least one unary-to-binary unit electrically coupled to the bitlines of each bitline group, the unary-to-binary unit being configured to convert transition-coded unary values into binary representations.

[0104] A fifty- second aspect may include a system for stochastic-to-binary conversion, comprising: a memory bank comprising a plurality of bitline groups, each bitline group configured to store an input stochastic bit vector; a plurality of sense amplifiers, each sense amplifier electrically coupled to a respective bitline of one of the bitline groups and configured to sense and amplify a voltage corresponding to a stochastic bit; a plurality of converter stages electrically coupled to the sense amplifiers and the bitlines, each converter stage comprising: stochastic-to- analog converter circuits electrically coupled between the sense amplifiers and one or more analog lines, the stochastic-to-analog converter circuits configured to produce an analog representation of the input stochastic bit vector; analog-to-unary converter circuits electrically coupled between the one or more analog lines and the bitlines, the analog-to-unary converter circuits configured to generate transition-coded unary values from the analog representation; and unary-to-binary encoder circuits, each unary-to-binary encoder circuit electrically coupled to the bitlines and configured to convert the transition-coded unary values into a corresponding binary output; and control logic configured to orchestrate operation of the converter stages via timing signals.

[0105] It should now be understood that embodiments disclosed herein include systems and methods for stochastic-to-binary number conversion. It should also be understood that these embodiments are merely exemplary and are not intended to limit the scope of this disclosure. The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein are not limiting of the scope,applicability, or aspects set forth in the claims. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. For example, changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various actions may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method that is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0106] As used herein, a phrase referring to 0 at least one ofD a list of items refers to any combination of those items, including single members. As an example, 0 at least one of: a, b, or cO is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0107] As used herein, the term 0 determiningO encompasses a wide variety of actions. For example, 0 determiningO may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, 0 determiningO may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, 0 determiningO may include resolving, selecting, choosing, establishing and the like.

[0108] As used herein, 0 coupled toO and 0 coupled withO generally encompass direct coupling and indirect coupling (e.g., including intermediary coupled aspects) unless stated otherwise. For example, stating that a processor is coupled to a memory allows for a direct coupling or a coupling via an intermediary aspect, such as a bus.

[0109] The methods disclosed herein comprise one or more actions for achieving the methods. The method actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions may be modified without departing from the scope of the claims. Further, thevarious operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software component(s) and / or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor.

[0110] The following claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims. Within a claim, reference to an element in the singular is not intended to mean D one and only oneO unless specifically so stated, but rather 0 one or more.O Unless specifically stated otherwise, the term 0 someO refers to one or more. No claim element is to be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited using the phrase 0 means forO . All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims.

Claims

CLAIMS1. A substrate for stochastic-to-binary number conversion, comprising: a plurality of bitline groups, each bitline group comprising a plurality of bitlines; a plurality of sense amplifiers, each sense amplifier electrically coupled to a respective bitline; a plurality of pre-charge units electrically coupled to the bitlines; a plurality of stochastic-to-analog units electrically coupled between the sense amplifiers and an analog line of each bitline group; a plurality of analog-to-unary units electrically coupled between the analog line and the bitlines of each bitline group; and an unary-to-binary unit electrically coupled to the bitlines of each bitline group.

2. The substrate of claim 1, wherein each stochastic-to-analog unit comprises: a pass transistor having a first terminal electrically coupled to a respective sense amplifier and a second terminal electrically coupled to the analog line; and a diode electrically coupled between the first and second terminals of the pass transistor.

3. The substrate of claim 2, wherein the diode is configured to enable a connection between the respective sense amplifier and the pass transistor when the sense amplifier stores a first logic value.

4. The substrate of claim 1, wherein each analog-to-unary unit comprises a transistor having a first terminal electrically coupled to the analog line and a second terminal electrically coupled to a respective bitline.

5. The substrate of claim 1, wherein the unary-to-binary unit of each bitline group comprises: a priority encoder configured to generate a binary output based on a transition- coded unary input; a latch electrically coupled to the priority encoder and configured to store the binary output; and a plurality of isolation transistors, each isolation transistor electrically coupled between a respective bitline and the priority encoder.

6. The substrate of claim 5, wherein each pre-charge unit comprises a voltage divider circuit and a multiplexer configured to select a reference voltage from the voltage divider circuit and provide the selected voltage to an electrically coupled sense amplifier.

7. The substrate of claim 6, wherein selection of the reference voltage from the voltage divider circuit enables the sense amplifier to operate as a voltage comparator.

8. The substrate of claim 1, further comprising an analog line capacitor electrically coupled to the analog line of each bitline group, wherein the analog line capacitor is configured to accumulate charge based on input stochastic operand bit values.

9. The substrate of claim 8, wherein the analog line capacitor is configured to accumulate an analog voltage level corresponding to a number of sense amplifiers storing a first logic value.

10. The substrate of claim 9, wherein the analog voltage level represents an analog encoding of an input stochastic operand bit- vector.

11. A method for in-memory stochastic-to-binary conversion, comprising: activating a row of memory cells storing an input stochastic bit vector, wherein the activation loads logic states corresponding to the stochastic bit vector into sense amplifiers of a bitline group; accumulating charge on an analog line of the bitline group based on the logic states of the sense amplifiers to generate an analog representation of the stochastic bit vector; converting an analog voltage corresponding to the accumulated charge on the analog line into a unary number, wherein the conversion is performed by mapping the analog voltage to bitlines of the bitline group using sense amplifiers operating as voltage comparators; and encoding the unary number into a binary output code.

12. The method of claim 11, wherein converting the logic states of the sense amplifiers into the analog voltage comprises logically activating pass transistors located between sense amplifiers and the analog line to share charge.

13. The method of claim 12, further comprising holding the pass transistors for a fixed interval to enable distinguishable accumulation of the analog voltage.

14. The method of claim 11, wherein converting the analog voltage into the unary number comprises: pre-charging the bitlines to reference voltages from a resistor ladder; and sharing charge between the analog line and the bitlines to perturb pre-charged voltages.

15. The method of claim 14, further comprising amplifying the perturbations on the bitlines to full logic high or logic low voltages by the sense amplifiers.

16. The method of claim 11, wherein converting the unary number into the binary output code comprises: connecting bitline voltages representing the unary number to inputs of a priority encoder; and latching output bits from the priority encoder.

17. The method of claim 11, wherein the stochastic-to-binary conversion achieves uniform latency for different bit- vector sizes of input stochastic operands.

18. The method of claim 11, further comprising: allocating a plurality of input stochastic bit vectors to a plurality of bitline groups in a memory bank; and concurrently performing the stochastic-to-binary conversion method for the plurality of input stochastic bit vectors allocated to the plurality of bitline groups.

19. A system for stochastic to binary conversion, comprising: a memory bank having a plurality of bitline groups, each bitline group allocated to an input stochastic bit vector; sense amplifiers electrically coupled to bitlines of each bitline group; converter stages electrically coupled to the sense amplifiers and bitlines of each bitline group, including: stochastic-to-analog converter circuits electrically coupled between the sense amplifiers and analog lines; analog-to-unary converter circuits electrically coupled between the analog lines and the bitlines; andunary-to-binary encoder circuits having inputs electrically coupled to the bitlines; and control logic configured to orchestrate operation of the converter stages using timing signals.

20. The system of claim 19, wherein orchestration of the converter stages by the control logic comprises logic configured to: activate a row of memory cells containing the input stochastic bit vector to load into the sense amplifiers; convert logic states of the sense amplifiers into an analog voltage on the analog lines; convert the analog voltage into a unary number on the bitlines; and convert the unary number into a binary output.

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