Frequency adjustment method for chip, frequency adjustment apparatus for chip, and chip

Abstract

Provided in the embodiments of the present application are a frequency adjustment method for a chip, a frequency adjustment apparatus for a chip, and a chip. The frequency adjustment method for a chip comprises: acquiring a computing result of a computing core; determining a computing performance indicator of the computing core on the basis of the computing result; and adjusting a clock frequency of the computing core in view of a frequency adjustment and control record and the computing performance indicator of the computing core, wherein the frequency adjustment and control record is used for recording clock frequencies that the computing core has used. By means of the technical solution in the embodiments of the present application, a clock frequency of a computing core can be adjusted in view of a frequency adjustment and control record and a computing performance indicator of the computing core, such that a clock frequency of the computing core with a high cycle error rate can be adjusted, and thus the computing core can operate at a more suitable clock frequency, thereby improving the performance of the computing core or reducing an overall computing power and power consumption ratio of an underperforming computing core on a chip, and increasing the overall computing accuracy rate and energy efficiency ratio of the chip.

Description

Chip frequency modulation method, chip frequency modulation device and chip

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 19, 2024, with application number 202410185112.2 and invention name “Frequency modulation method of chip, frequency modulation device of chip and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a chip frequency modulation method, a chip frequency modulation device and a chip. Background Art

[0003] In the related art, during high-performance computing on chips, due to factors such as process non-uniformity and variability in the operating environment, some computing cores may experience temporary or prolonged errors. Simply reducing the computing speed or shutting down these faulty cores results in a loss of computing power. Therefore, how to improve accuracy while maintaining computing power has become a pressing issue.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a chip frequency modulation method, a chip frequency modulation device, and a chip to solve or alleviate one or more technical problems in the prior art.

[0006] As one aspect of an embodiment of the present application, an embodiment of the present application provides a frequency modulation method for a chip, including: obtaining a calculation result of a computing core; judging a computing performance index of the computing core based on the calculation result; and adjusting the clock frequency of the computing core in combination with a frequency control record and a computing performance index of the computing core, wherein the frequency control record is used to record the clock frequency that the computing core has adopted.

[0007] In one embodiment, when the computing performance index of the computing core is lower than the target expected value, the computing core is marked as a first-state computing core; the target expected value is used to characterize the parameters of the normal operation of the computing core; the clock frequency of the first-state computing core is compared with the minimum operating frequency, and the clock frequency of the first-state computing core is adjusted according to the frequency control record.

[0008] In one embodiment, when the clock frequency of the first-state computing core is greater than the minimum operating frequency and the minimum operating frequency has not been used, the clock frequency of the first-state computing core is lowered; when the clock frequency of the first-state computing core is equal to the minimum operating frequency, or the minimum operating frequency has been used, the clock frequency of the first-state computing core is increased.

[0009] In one embodiment, after adjusting the clock frequency of the first-state computing core, it includes: when the computing performance index of the first-state computing core is greater than the target expected value, controlling the first-state computing core to maintain the adjusted clock frequency; when the computing performance index of the first-state computing core is lower than or equal to the target expected value, traversing all clock frequencies according to the frequency control record.

[0010] In one embodiment, the frequency modulation method of the chip also includes: under all clock frequencies, when there is at least one clock frequency such that the computing performance index of the first-state computing core is equal to the target expected value, adjusting the clock frequency of the first-state computing core to the clock frequency corresponding to the optimal computing performance index, and the optimal computing performance index is the maximum value among the computing performance indicators.

[0011] In one embodiment, the chip frequency modulation method further includes: when the computing performance indicators of the first-state computing core are lower than the target expected value at all clock frequencies, shutting down the first-state computing core or adjusting the clock frequency of the first-state computing core to the lowest.

[0012] In one embodiment, the frequency modulation method of the chip also includes: when the computing performance indicators of the first-state computing core are lower than the target expected value at all clock frequencies, shutting down the first-state computing core or adjusting the clock frequency of the first-state computing core to the clock frequency corresponding to the optimal computing performance indicator, where the optimal computing performance indicator is the maximum value among the computing performance indicators.

[0013] In one embodiment, when the computing performance index of the computing core is greater than the target expected value, the computing core is marked as a second-state computing core, and the clock frequency of the second-state computing core is increased.

[0014] In one embodiment, when the computing performance index of the computing core is equal to the target expected value, the computing core is marked as a third-state computing core, and the clock frequency of the third-state computing core is maintained.

[0015] In one embodiment, the computing performance indicator is used to characterize the cycle accuracy of the computing result of the computing core.

[0016] In one embodiment, the computing performance index of the computing core is judged based on the calculation results, including: obtaining the number of erroneous calculation outputs n1 and the number of correct calculation outputs n2 of the computing core within a preset cycle length; based on n1 and n2, determining the cycle accuracy of the computing core within the preset cycle length.

[0017] As another aspect of the present application, an embodiment of the present application provides a frequency modulation device for a chip, including: a status register for storing computing performance indicators and frequency control records of the computing core; a control unit connected to the status register and used to implement the method of any of the above-mentioned embodiments.

[0018] In one embodiment, the frequency modulation device of the chip also includes: multiple phase-locked loop circuits for providing multiple clock frequencies; a multiplexer, the multiplexer includes multiple first input terminals, first output terminals and first control terminals, the multiple first input terminals are respectively connected to the multiple phase-locked loop circuits one by one, the first output terminals are connected to the computing core, and the first control terminal is connected to the control unit.

[0019] In one embodiment, multiple status registers are set in a one-to-one correspondence with multiple computing cores; there is at least one control unit.

[0020] In one embodiment, the frequency modulation device of the chip also includes: a statistical module, including multiple second input terminals and second output terminals, the multiple second input terminals are connected to multiple computing cores one by one, and the second output terminals are connected to the control unit for outputting inspection data of each computing core, wherein the inspection data of each computing core includes identification information of each computing core and the number of erroneous calculation outputs and correct calculation outputs of each computing core within a preset cycle length.

[0021] In one embodiment, the frequency modulation device of the chip also includes: an input distributor, the input end of the input distributor is connected to the second output end, used to receive inspection data from each computing core, and the output end of the input distributor is connected to the control unit; an output distributor, connected between the control unit and the computing core.

[0022] In one embodiment, the input distributor is further configured to distribute the inspection data of each computing core to a corresponding control unit according to the empty or full status of the multiple control units.

[0023] In one embodiment, the number of control units is less than or equal to the number of status registers.

[0024] As another aspect of the present application, an embodiment of the present application provides a chip, including a frequency modulation device of the chip of any of the above embodiments.

[0025] The embodiment of the present application adopts the above-mentioned technical solution to adjust the clock frequency of the computing core in combination with the frequency control record and computing performance index of the computing core, so that the clock frequency of the computing core with a higher cycle error rate can be adjusted, so that the computing core can run at a more appropriate clock frequency, thereby improving the performance of the computing core or reducing the computing power and power consumption proportion of the low-performing computing core in the overall chip, improving the overall computing accuracy and energy efficiency of the chip, and at the same time allowing the computing core to enter a stable state, ensuring the stability of the load distribution of the entire chip, and avoiding unstable power supply distribution.

[0026] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0028] FIG1 is a schematic flow chart showing a frequency modulation method for a chip according to an embodiment of the present application.

[0029] FIG2 is a schematic flow chart showing a frequency modulation method for a chip according to another embodiment of the present application.

[0030] FIG3 shows an application example diagram of a frequency modulation method for a chip according to an embodiment of the present application.

[0031] FIG4 shows an architecture diagram of a frequency modulation device of a chip according to an embodiment of the present application.

[0032] FIG5 shows an architecture diagram of a frequency modulation device of a chip according to another embodiment of the present application.

[0033] FIG6 shows a partial architecture diagram of a frequency modulation device of a chip according to an embodiment of the present application.

[0034] Description of reference numerals:

[0035] 400: Chip frequency modulation device;

[0036] 410: Status register; 420: Control unit; 430: Phase-locked loop circuit; 440: Multiplexer; 450: Statistics module; 460: Input distributor; 470: Output distributor; 480: Computing core. DETAILED DESCRIPTION

[0037] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0038] In related technologies, the following three solutions are usually used to reduce the overall error rate of the chip:

[0039] The first method is to use clock gating or power gating to shut down faulty cores to reduce the overall error rate. However, this method will reduce the computing power of the cores and may accidentally shut down temporarily faulty cores, resulting in additional computing power loss.

[0040] The second method is to set a threshold to reduce the clock frequency of computing cores with error rates above the threshold, and increase the clock frequency of computing cores with error rates below the threshold. This solution is sensitive to disturbances. Computing cores with working performance near the threshold will frequently switch clock frequencies, and thus cannot enter a stable state, resulting in unstable load distribution across the entire chip, which may lead to unstable power supply distribution. For some voltage-sensitive units, voltage fluctuations in certain computing cores will affect other adjacent computing cores or chips, causing the working state to deteriorate. In addition, frequency reduction does not necessarily improve the working state of the computing core. In some cases, frequency reduction may not reduce the error rate and may also result in a loss of computing power.

[0041] The third approach involves controlling the clock frequency of each core through external software. Compared to the two previous solutions, this approach offers greater flexibility, allowing for policy changes to cover a wider range of error conditions. However, this approach is limited by I / O and bus bandwidth limitations, preventing real-time control of individual cores and addressing clock control requests for large arrays of cores. Furthermore, due to communication latency, this approach exhibits significant lag.

[0042] The frequency modulation method of a chip according to the embodiment of the first aspect of the present application is described below with reference to Figures 1 to 3.

[0043] Specifically, the present application provides a chip frequency modulation method, as shown in FIG1 , the method comprising:

[0044] Step S101: Obtain the calculation result of the calculation core;

[0045] Step S102: determining the computing performance index of the computing core according to the computing result;

[0046] Step S103: adjusting the clock frequency of the computing core in combination with the frequency control record of the computing core and the computing performance index. The frequency control record is used to record the clock frequency that the computing core has adopted.

[0047] In some embodiments, a computing performance index is used to evaluate the performance of a computing core. The lower the computing performance index, the higher the cycle error rate of the computing core, and the lower the cycle accuracy, the worse the performance of the computing core; the higher the computing performance index, the lower the cycle error rate of the computing core, and the higher the cycle accuracy, the better the performance of the computing core. The cycle error rate is the error rate of the computing core within a preset cycle length, and the cycle error rate is the ratio of the number of erroneous calculation outputs within the preset cycle length to the total number of calculation outputs within the preset cycle length. The preset cycle length can be configured in advance according to actual needs. The preset cycle length determines the accuracy of the cycle error rate. The larger the preset cycle length, the higher the accuracy of the cycle error rate; the smaller the preset cycle length, the lower the accuracy of the cycle error rate.

[0048] For example, judging the computing performance index of a computing core based on the computing results may include: presetting a reference node value, a correct calculation weight value, an incorrect calculation weight value, a correct calculation threshold, and an incorrect calculation threshold for the computing core; analyzing whether each computation performed by the computing core is correct; increasing the correct calculation weight value by one time the computing core performs at least one correct computation, and decreasing the incorrect calculation weight value by one time the computing core performs at least one incorrect computation; and judging whether the current reference node value of the computing core reaches the correct calculation threshold or the incorrect calculation threshold. For example, 400,000 is set as the reference node value, the correct calculation weight value is set to 180, the incorrect calculation weight value is set to 9,000, and both the correct calculation threshold and the incorrect calculation threshold are set to 100,000. Each time the calculation core makes a correct calculation, 180 is added to the reference node value (the calculation correct weight value); each time the calculation core makes an incorrect calculation, 9000 is subtracted from the reference node value (the calculation error weight value); based on the reference node value, the calculation frequency of the calculation core is increased for each increase of 100,000 (the calculation correct threshold), and the calculation frequency of the calculation core is decreased for each decrease of 100,000 (the calculation error threshold).

[0049] According to the frequency modulation method of the chip in the embodiment of the present application, the clock frequency of the computing core can be adjusted in combination with the frequency control record and computing performance index of the computing core, so that the clock frequency of the computing core with a higher cycle error rate can be adjusted, so that the computing core can run at a more appropriate clock frequency, thereby improving the performance of the computing core or reducing the computing power and power consumption proportion of the low-performing computing core in the overall chip, improving the overall computing accuracy and energy efficiency of the chip, and at the same time allowing the computing core to enter a stable state, ensuring the stability of the load distribution of the entire chip, and avoiding unstable power supply distribution.

[0050] Optionally, as shown in Figure 2, step S201: when the computing performance index of the computing core is lower than the target expected value, the computing core is marked as a first-state computing core; the target expected value is used to characterize the parameters of the normal operation of the computing core; step S202: compare the clock frequency of the first-state computing core with the minimum operating frequency, and adjust the clock frequency of the first-state computing core according to the frequency control record.

[0051] Exemplarily, the clock frequency of the computing core can be determined by the clock frequency gear. The clock frequency gear may include a preset highest gear, an intermediate gear, and a lowest gear. The clock frequency of the computing core at the preset highest clock frequency gear is A, the clock frequency of the computing core at the preset intermediate clock frequency gear is B, and the clock frequency of the computing core at the preset lowest clock frequency gear is C, where A>B>C. In conjunction with Figure 3, after the computing core is marked as a first-state computing core, the clock frequency gear of the first-state computing core can be adjusted to an unused clock frequency gear based on the relationship between the clock frequency gear of the first-state computing core and the preset lowest gear and the gear control record of this round.

[0052] It should be noted that the target expected value can be an interval with upper and lower limits. For example, when the computing performance indicator is used to characterize the cycle error rate of the computing core's calculation results, the upper and lower limits of the target expected value can be a first preset error rate ρ1 and a second preset error rate ρ2, respectively. The first preset error rate ρ1 is an error rate threshold used to evaluate whether the computing core is in a high-performance state at the current clock frequency level. If the cycle error rate of the computing core at the current clock frequency level is less than or equal to ρ1, the computing performance indicator of the computing core is greater than the target expected value, and the computing core is in a high-performance state with a low error rate and high accuracy. The second preset error rate ρ2 is an error rate threshold used to evaluate whether the computing core is in a low-performance state at the current clock frequency level. If the cycle error rate of the computing core at the current clock frequency level is greater than the second preset error rate ρ2, the computing performance indicator of the computing core is lower than the target expected value, and the computing core is in a low-performance state with a high error rate and low accuracy. If the cycle error rate of the computing core at the current clock frequency level is greater than ρ1 and less than or equal to ρ2, the computing performance indicator of the computing core meets the target expected value, and the computing core is in normal working condition. The settings of ρ1 and ρ2 can effectively improve the problem of frequent switching of the clock frequency gear of the computing core, thereby avoiding the impact of clock frequency oscillation and making the chip power supply distribution more stable.

[0053] 3 , when the period error rate DH rate1 of the computing core is greater than ρ2, it indicates that the computing core is in a low performance state with a high error rate and a low accuracy rate. In this case, the computing core is marked as a first-state computing core.

[0054] In this embodiment, by comparing the clock frequency of the first-state computing core with the minimum operating frequency and adjusting the clock frequency of the first-state computing core in a targeted manner based on the frequency control record, the overall error rate of the chip can be reduced while avoiding the loss of computing power of the computing core.

[0055] Optionally, when the clock frequency of the first-state computing core is greater than the minimum operating frequency and the minimum operating frequency has not been used, the clock frequency of the first-state computing core is lowered; when the clock frequency of the first-state computing core is equal to the minimum operating frequency, or the minimum operating frequency has been used, the clock frequency of the first-state computing core is increased.

[0056] Exemplarily, when the clock frequency gear of the first-state computing core is not the lowest gear and the lowest gear has not been used in this round of regulation, the operation of downgrading one gear is preferred. For example, when the clock frequency gear of the first-state computing core is the preset highest gear, the clock frequency gear of the first-state computing core is adjusted to the preset middle gear; when the clock frequency gear of the first-state computing core is the preset middle gear, the clock frequency gear of the first-state computing core is adjusted to the preset lowest gear. When the clock frequency gear of the first-state computing core is the lowest gear, or when the lowest gear has been used in this round of regulation, the operation of increasing the clock frequency gear step by step can be adopted, that is, first increasing the clock frequency gear of the first-state computing core to the preset middle gear, and then increasing the clock frequency gear of the first-state computing core from the preset middle gear to the highest gear, so as to verify whether the cycle error rate of the first-state computing core is repaired or improved.

[0057] In this embodiment, when a computing core whose computing performance index is lower than the target expected value is marked as a first-state computing core, frequency modulation of the first-state computing core begins. At this time, there is a regulation cycle. During this round of regulation cycle, the clock frequency already adopted by the first-state computing core will be recorded. During the frequency modulation process, the computing performance index of the first-state computing core may be lower than or equal to the target expected value even when the frequency is reduced to the lowest operating frequency. At this time, it is necessary to increase the clock frequency of the first-state computing core and continue frequency modulation to compare all clock frequencies and find a clock frequency with a higher computing performance index.

[0058] Therefore, by increasing the clock frequency of the first-state computing core when the clock frequency of the first-state computing core is equal to the minimum operating frequency, or when the minimum operating frequency has been used, the optimal computing performance indicators of all clock frequencies of the first-state computing core can be further screened out, thereby effectively improving the computing performance indicators of the first-state computing core. Compared with the method of directly shutting down the computing core in the existing technology, the computing power of the computing core can be guaranteed while reducing the overall error rate of the chip, thereby avoiding additional computing power loss.

[0059] Optionally, after adjusting the clock frequency of the first-state computing core, it includes: when the computing performance index of the first-state computing core is greater than the target expected value, controlling the first-state computing core to maintain the adjusted clock frequency; when the computing performance index of the first-state computing core is lower than or equal to the target expected value, traversing all clock frequencies according to the frequency control record.

[0060] It should be noted that "traversal" can be understood as accessing all clock frequencies one by one in a certain order. For example, the clock frequencies are 300Hz, 400Hz, 500Hz, and 600Hz. When the current clock frequency of the first-state computing core is 300Hz, it can access 400Hz, 500Hz, and 600Hz in sequence to traverse all clock frequencies. When the current clock frequency of the first-state computing core is 500Hz, it can access 400Hz, 300Hz, and 600Hz in sequence to traverse all clock frequencies.

[0061] For example, in conjunction with FIG3 , when the computing performance index of the computing core in the first state is greater than the target expected value, the cycle error rate of the computing core in the first state is less than or equal to ρ1. When the computing performance index of the computing core in the first state is less than or equal to the target expected value, after traversing all clock frequencies, the cycle error rate DH rate2 of the computing core within a preset cycle length can be obtained. When the adjusted cycle error rate DH rate2 of the computing core in the first state is less than or equal to ρ1, it indicates that the computing core in the first state has recovered to a high-performance state with a low error rate and a high accuracy rate. At this time, the mark of the computing core in the first state can be cleared so that it can operate at the current clock frequency.

[0062] If the adjusted cycle error rate DH rate2 of the first-state computing core is greater than ρ1, it indicates that the first-state computing core has not recovered to a high-performance state with a low error rate and high accuracy. At this point, it can be determined whether all clock frequency gears have been traversed. If not all clock frequency gears have been traversed, that is, if there are unused clock frequency gears, the clock frequency gear of the first-state computing core is adjusted to an unused clock frequency gear. For example, if the current clock frequency gear of the first-state computing core is adjusted from the highest gear to the middle gear, and the unused clock frequency gear is the lowest gear, the clock frequency gear of the first-state computing core is adjusted from the middle gear to the lowest gear. If the current clock frequency gear of the first-state computing core is adjusted from the middle gear to the lowest gear, and the unused clock frequency gear is the highest gear, the clock frequency gear of the first-state computing core is adjusted from the lowest gear to the highest gear. If the current clock frequency gear of the first-state computing core is adjusted from the lowest gear to the middle gear, and the unused clock frequency gear is the highest gear, the clock frequency gear of the first-state computing core is adjusted from the middle gear to the highest gear.

[0063] Therefore, when the computing performance index of the first-state computing core is lower than or equal to the target expected value, the clock frequency of the first-state computing core can be further adjusted, thereby traversing all clock frequencies and enabling the first-state computing core to operate at a more appropriate clock frequency. In addition, the chip's frequency modulation method has a short-term memory function, which can determine and control the current working state of the computing core based on its past working state.

[0064] Optionally, the frequency modulation method of the chip also includes: under all clock frequencies, when there is at least one clock frequency such that the computing performance index of the first-state computing core is equal to the target expected value, adjusting the clock frequency of the first-state computing core to the clock frequency corresponding to the optimal computing performance index, and the optimal computing performance index is the maximum value among the computing performance indicators.

[0065] Exemplarily, referring to FIG3 , when all clock frequency gears have been traversed, the cycle error rate DH rate3 of the computing core within a preset cycle length is obtained, and when there is a target clock frequency gear that makes the cycle error rate DH rate3 of the computing core in the first state less than or equal to ρ2, the clock frequency gear of the computing core in the first state is adjusted to the clock frequency gear corresponding to the lowest cycle error rate in the target clock frequency gear. For example, when the cycle error rate of the computing core in the first state is greater than ρ1 at all clock frequency gears, and the clock frequency gear of the computing core in the first state is the preset lowest gear, the cycle error rate of the computing core in the first state is less than or equal to ρ2, indicating that the computing core in the first state can be in a normal working state at the preset lowest gear, then the preset lowest gear is the target clock frequency gear. At this time, the clock frequency gear of the computing core in the first state can be adjusted to the lowest gear, and the mark of the computing core in the first state is cleared.

[0066] Therefore, when all clock frequency levels are traversed and the computing performance indicators of the first-state computing core at all clock frequency levels cannot be greater than the target expected value, the judgment criteria can be lowered and the clock frequency of the first-state computing core can be adjusted to the clock frequency corresponding to the optimal computing performance indicator, thereby improving the computing accuracy and energy efficiency of the chip.

[0067] As a specific example: all clock frequencies are 300Hz, 400Hz, 500Hz, and 600Hz, respectively, with ρ1 being 5% and ρ2 being 15%. In the first state, the computing core operates at 500Hz, with a corresponding computing performance indicator of an error rate of 18%. It is first lowered to 400Hz, with a corresponding computing performance indicator of an error rate of 12%. It is then lowered to 300Hz, with a corresponding computing performance indicator of an error rate of 10%. It is then raised to 600Hz, with a corresponding computing performance indicator of an error rate of 20%. After traversing all clock frequency levels, if no value exceeds the target expected value, the clock frequency corresponding to the optimal computing performance indicator is 300Hz.

[0068] It should be added that the above traversal may be more than one round, and may be multiple rounds. If the situation where the value is greater than the target expected value does not appear, the clock frequency corresponding to the optimal computing performance indicator is selected from the clock frequencies that meet the target expected value.

[0069] Optionally, the chip frequency modulation method may further include: when the computing performance index of the first-state computing core is lower than the target expected value at all clock frequencies, shutting down the first-state computing core or adjusting the clock frequency of the first-state computing core to the lowest.

[0070] For example, after all clock frequency levels have been traversed, the cycle error rate DH rate3 of the computing core within a preset cycle length is obtained. If the cycle error rate DH rate3 of the computing core in the first state at all clock frequency levels is greater than ρ2, it indicates that the computing core in the first state is in a low-performance state with a high error rate and low accuracy at all clock frequency levels. At this point, it can be determined whether the computing core in the first state has temporarily failed due to fluctuations in the working environment. The computing core in the first state can be re-traversed through multiple rounds of clock frequency levels, and the cycle error rate of the computing core in the first state at each clock frequency level can be obtained to ensure recovery time for the working environment. If the computing core in the first state temporarily failed due to fluctuations in the working environment, the working environment has sufficient time to return to stability during the process of re-traversing the computing core in the first state through multiple rounds of clock frequency levels. At this time, if there is a clock frequency level at which the cycle error rate of the computing core in the first state is less than or equal to ρ2, the clock frequency level of the computing core in the first state is adjusted to the clock frequency level corresponding to the minimum cycle error rate, and the flag for the computing core in the first state is cleared. If the first-state computing core is re-traversed through multiple rounds of clock frequency gears, and the cycle error rate of the first-state computing core at all clock frequency gears is greater than ρ2, it is determined that the first-state computing core is unlikely to return to normal. At this time, the first-state computing core can be shut down or the clock frequency gear of the first-state computing core can be adjusted to the lowest gear.

[0071] After shutting down the first-state computing core or adjusting the clock frequency gear of the first-state computing core to the lowest gear, the cycle error rate DH rate4 of the computing core within the preset cycle length can be cyclically obtained. When DH rate4 is less than or equal to ρ1 or ρ2, the mark of the first-state computing core can be cleared and the first-state computing core can be released.

[0072] In this embodiment, when the computing performance indicators of the first-state computing core are lower than the target expected values ​​at all clock frequencies, the first-state computing core is a low-performance computing core. By shutting down the first-state computing core or adjusting the clock frequency of the first-state computing core to the lowest, the computing power and power consumption ratio of the low-performance computing core in the overall chip can be effectively reduced, thereby improving the overall computing accuracy and energy efficiency of the chip.

[0073] As a specific embodiment: all clock frequencies are 300Hz, 400Hz, 500Hz, and 600Hz, respectively, with ρ1 being 5% and ρ2 being 15%. The first-state computing core first operates at 500Hz, with a corresponding computing performance indicator of an error rate of 20%. It is first lowered to 400Hz, with a corresponding computing performance indicator of an error rate of 18%. It is then lowered to 300Hz, with a corresponding computing performance indicator of an error rate of 16%. It is then raised to 600Hz, with a corresponding computing performance indicator of an error rate of 22%. After traversing all clock frequency levels, if no value is greater than or equal to the target expected value, the first-state computing core is shut down or its clock frequency is adjusted to the lowest.

[0074] It should be added that the above traversal may be more than one round, and if the value is not greater than or equal to the target expected value, the first state computing core is shut down or the clock frequency of the first state computing core is adjusted to the lowest.

[0075] Optionally, the frequency modulation method of the chip may also include: when the computing performance indicators of the first-state computing core are lower than the target expected value at all clock frequencies, shutting down the first-state computing core or adjusting the clock frequency of the first-state computing core to the clock frequency corresponding to the optimal computing performance indicator, and the optimal computing performance indicator is the maximum value among the computing performance indicators.

[0076] For example, if the first-state computing core is subjected to multiple rounds of clock frequency gear traversal, and the cycle error rate of the first-state computing core at all clock frequency gears is greater than ρ2, it is determined that the first-state computing core is unlikely to return to normal. At this time, the clock frequency gear of the first-state computing core can be adjusted to the clock frequency gear corresponding to the lowest cycle error rate. After the clock frequency gear of the first-state computing core is adjusted to the clock frequency gear corresponding to the lowest cycle error rate, the cycle error rate DH rate4 of the computing core within a preset cycle length can be cyclically obtained. When DH rate4 is less than or equal to ρ1 or ρ2, the mark of the first-state computing core can be cleared, and the first-state computing core can be released.

[0077] Therefore, by adjusting the clock frequency of the first-state computing core to the clock frequency corresponding to the optimal computing performance index, the computing power of the first-state computing core can be avoided from being lost, thereby improving the performance of the entire chip.

[0078] As a specific embodiment: all clock frequencies are 300Hz, 400Hz, 500Hz and 600Hz, ρ1 is 5%, and ρ2 is 15%. The first-state computing core first works at 500Hz, and the corresponding computing performance index is an error rate of 20%; first it is lowered to 400Hz, and the corresponding computing performance index is an error rate of 16%; then it is lowered to 300Hz, and the corresponding computing performance index is an error rate of 18%; then it is raised to 600Hz, and the corresponding computing performance index is an error rate of 22%. After traversing all clock frequency gears, if no value is greater than or equal to the target expected value, the first-state computing core is turned off or the clock frequency corresponding to the optimal computing performance index is selected from all clock frequencies, that is, 400Hz.

[0079] It should be added that the above traversal may be more than one round, and may be multiple rounds. If a situation where the value is greater than or equal to the target expected value does not appear, the first state computing core is shut down or the clock frequency corresponding to the optimal computing performance indicator is selected from all clock frequencies.

[0080] As a supplement, optionally, after adjusting the clock frequency of the first-state computing core, it includes: when the computing performance index of the first-state computing core is greater than or equal to the target expected value, controlling the first-state computing core to maintain the adjusted clock frequency; when the computing performance index of the first-state computing core is lower than the target expected value, traversing all clock frequencies according to the frequency control record.

[0081] When the computing performance indicator of the computing core in the first state is lower than or equal to the target expected value, after traversing all clock frequencies, the cycle error rate DH rate2 of the computing core within the preset cycle length can be obtained. If the adjusted cycle error rate DH rate2 of the computing core in the first state is less than or equal to ρ2, it indicates that the computing core in the first state has recovered to a high-performance state with a low error rate and high accuracy. At this time, the flag for the computing core in the first state can be cleared, allowing it to operate at the current clock frequency.

[0082] If the adjusted cycle error rate DH rate2 of the first-state computing core is greater than ρ2, it indicates that the first-state computing core has not recovered the high-performance state of low error rate and high accuracy. At this time, it can be determined whether to traverse all clock frequency gears. If, at all clock frequencies, the computing performance index of the first-state computing core is lower than the target expected value, the first-state computing core is shut down, the clock frequency of the first-state computing core is adjusted to the lowest, or the clock frequency corresponding to the optimal computing performance index is selected from all clock frequencies.

[0083] Optionally, when the computing performance index of the computing core is greater than the target expected value, the computing core is marked as a second-state computing core, and the clock frequency of the second-state computing core is increased.

[0084] For example, in conjunction with FIG3 , when the cycle error rate DH rate1 of the computing core is less than or equal to ρ1, it indicates that the computing core is in a high-performance state with low error rate and high accuracy. If the clock frequency gear of the computing core is at the preset lowest gear, the clock frequency gear of the computing core can be increased to the middle gear or adjusted to the highest gear step by step; if the clock frequency gear of the computing core is at the preset middle gear, the clock frequency gear of the computing core can be increased to the highest gear; if the clock frequency gear of the computing core is the same as the preset highest gear, the computing core can maintain the current clock frequency gear.

[0085] Therefore, by increasing the clock frequency of the second-state computing core, the computing efficiency of the computing core can be improved while ensuring the computing accuracy of the chip, thereby improving the energy efficiency ratio of the chip.

[0086] Optionally, when the computing performance index of the computing core is equal to the target expected value, the computing core is marked as a third-state computing core, and the clock frequency of the third-state computing core is maintained. Thus, when the computing performance index of the computing core is equal to the target expected value, it indicates that the computing core is in a normal working state. By maintaining the clock frequency of the third-state computing core, the accuracy of the third-state computing core can be guaranteed while minimizing computing power loss.

[0087] As a specific example, all clock frequencies are 300Hz, 400Hz, 500Hz, and 600Hz, respectively, with ρ1 being 5% and ρ2 being 15%. The second-state computing core first operates at 300Hz, corresponding to a 2% error rate. It is then raised to 400Hz, corresponding to a 3% error rate. It is then lowered to 500Hz, corresponding to a 4% error rate. It is then raised to 600Hz, corresponding to a 6% error rate. At this point, the clock frequency of the third-state computing core is maintained, and the core enters a stable state, ensuring a stable load distribution across the chip and preventing unstable power distribution.

[0088] As a special example: all clock frequencies are 300Hz, 400Hz, 500Hz, and 600Hz, respectively, with ρ1 being 5% and ρ2 being 15%. The second-state computing core first operates at 300Hz, corresponding to a computing performance indicator of a 2% error rate. It is first increased to 400Hz, corresponding to a 3% error rate. It is then lowered to 500Hz, corresponding to a 4% error rate. It is then increased to 600Hz, corresponding to a 16% error rate. At this point, the computing core becomes the first-state computing core. Frequency modulation is required. When it is lowered to 500Hz, the corresponding computing performance indicator returns to a 4% error rate. Then, when it is increased to 600Hz, the corresponding computing performance indicator returns to a 16% error rate. When this type of repeatedly switching frequency modulation occurs, the control unit fixes it to the clock frequency corresponding to the optimal computing performance indicator, or the clock frequency corresponding to the optimal computing performance indicator when it meets the target expected value.

[0089] Optionally, the computing performance index can be used to characterize the cycle accuracy of the computing core's calculation results. A higher computing performance index indicates a higher cycle accuracy of the computing core's calculation results, and thus higher performance of the computing core. A lower computing performance index indicates a lower cycle accuracy of the computing core's calculation results, and thus lower performance of the computing core.

[0090] Of course, the computing performance index can also be used to characterize the cycle error rate of the computing core's calculation results. A higher computing performance index indicates a lower cycle error rate of the computing core's calculation results, and thus higher performance of the computing core. A lower computing performance index indicates a higher cycle error rate of the computing core's calculation results, and thus worse performance of the computing core.

[0091] Optionally, in step S102, judging the computing performance index of the computing core based on the calculation results may include: obtaining the number of erroneous calculation outputs n1 and the number of correct calculation outputs n2 of the computing core within a preset cycle length; and determining the cycle accuracy of the computing core within the preset cycle length based on n1 and n2.

[0092] For example, when there are multiple computing cores forming a large-scale computing core array, each computing core has identification information, and the identification information of the multiple computing cores is different. Within a preset cycle length, the sum of the number of incorrect computational outputs n1 and the number of correct computational outputs n2 of each computing core is the total number of computational outputs of the computing core. The cycle accuracy of the computing core is the ratio of the number of correct computational outputs n2 to the total number of computational outputs; the cycle error rate of the computing core is the ratio of the number of incorrect computational outputs n1 to the total number of computational outputs.

[0093] In this embodiment, the cycle accuracy of each computing core can be determined based on n1 and n2, thereby determining the working status of the computing core, adjusting the clock frequency of the computing core with lower cycle accuracy, and realizing independent clock frequency control of each computing core in the computing core array.

[0094] In a second aspect, the present application provides a frequency modulation device 400 for a chip, as shown in FIG4 , comprising a status register 410 and a control unit 420. The status register 410 is used to store computing core performance indicators and frequency control records; the control unit 420 is connected to the status register 410 and is used to implement the method according to any embodiment of the first aspect of the present application.

[0095] According to the frequency modulation device 400 of the chip of the embodiment of the present application, the clock frequency of the computing core can be adjusted in combination with the frequency control record and computing performance index of the computing core, so that the clock frequency of the computing core with a higher cycle error rate can be adjusted, so that the computing core can run at a more appropriate clock frequency, thereby improving the performance of the computing core or reducing the computing power and power consumption proportion of the low-performance computing core in the overall chip, improving the overall computing accuracy and energy efficiency of the chip, and at the same time allowing the computing core to enter a stable state, ensuring the stability of the load distribution of the entire chip, and avoiding unstable power supply distribution.

[0096] Optionally, the chip's frequency modulation device 400 further includes: multiple phase-locked loop circuits 430 and a multiplexer 440. The multiple phase-locked loop circuits 430 are used to provide multiple clock frequencies. The multiplexer 440 includes multiple first input terminals, a first output terminal, and a first control terminal. The multiple first input terminals are connected to the multiple phase-locked loop circuits 430 in a one-to-one correspondence, the first output terminal is connected to the computing core 480, and the first control terminal is connected to the control unit 420. In the description of this application, "multiple" means two or more.

[0097] For example, three phase-locked loop circuits 430 are shown in FIG5 , and the three phase-locked loop circuits 430 can be used to provide a preset lowest clock frequency gear, an intermediate clock frequency gear, and a highest clock frequency gear, respectively. After determining the computing performance index of the computing core, the control unit 420 can output a frequency gear adjustment signal in combination with the frequency control record and computing performance index of the computing core. The first control terminal is used to input the frequency gear adjustment signal, and the three first input terminals are used to input three clock frequency gears, respectively. The multiplexer 440 is used to select one of the three clock frequency gears as a preselected clock frequency gear according to the frequency gear adjustment signal, and output the preselected clock frequency gear from the first output terminal, so that the clock frequency gear of the computing core is adjusted to the preselected clock frequency gear.

[0098] Therefore, by setting the above-mentioned phase-locked loop circuit 430 and multiplexer 440, the control unit 420 can adjust the clock frequency of the computing core 480 in combination with the frequency control record and computing performance indicators of the computing core, so that the computing core 480 can run at a more appropriate clock frequency, thereby improving the performance of the computing core 480 or reducing the computing power and power consumption ratio of the low-performance computing core 480 in the overall chip, thereby improving the overall computing accuracy and energy efficiency of the chip.

[0099] Optionally, as shown in FIG5 and FIG6, a plurality of status registers 410 are provided in a one-to-one correspondence with a plurality of computing cores 480; and there is at least one control unit 420. Optionally, the number of control units 420 may be less than or equal to the number of status registers 410. Each status register 410 may be used to record the identification information of the corresponding computing core 480 and the current cycle error rate of the computing core 480. With such a configuration, when there are multiple computing cores 480 and a large-scale computing core array is formed, each status register 410 may be used to store the cycle error rate of the corresponding computing core 480 within a preset cycle length, so that the unoccupied control unit 420 can timely adjust the clock frequency gear of the computing core 480 with a higher cycle error rate, thereby realizing independent clock frequency control of each computing core 480 in the computing core array with higher control efficiency.

[0100] Optionally, as shown in Figures 5 and 6, the frequency modulation device 400 of the chip may further include: a statistical module 450, the statistical module 450 including a plurality of second input terminals and a second output terminal, the plurality of second input terminals being connected to the plurality of computing cores 480 in a one-to-one correspondence, the second output terminal being connected to the control unit 420, and being configured to output inspection data of each computing core 480, wherein the inspection data of each computing core 480 includes identification information of each computing core 480 and the number of incorrect and correct computational outputs of each computing core 480 within a preset cycle length. For example, each second input terminal may be used to input the output result of each computing core 480, and the statistical module 450 may be configured to determine whether the output result of each computing core 480 is correct or not, and to verify whether a timeout has occurred.

[0101] Therefore, by setting the above-mentioned statistical module 450, the inspection data of each computing core 480 can be output to the control unit 420, so that the control unit 420 can judge the computing performance indicators of each computing core 480, and adjust the clock frequency of the computing core 480 in combination with the frequency control record and computing performance indicators of the computing core 480, so as to realize independent clock frequency control of each computing core 480 in the computing core array.

[0102] 5 and 6 , the frequency modulation device 400 of the chip may further include an input distributor 460 and an output distributor 470. The input end of the input distributor 460 is connected to the second output end for receiving inspection data from each computing core 480, and the output end of the input distributor 460 is connected to the control unit 420. The output distributor 470 is connected between the control unit 420 and the computing core 480.

[0103] In this embodiment, the input distributor 460 can distribute the inspection data received from each computing core 480 to the control unit 420, so that the control unit 420 can query the corresponding status register 410 according to the identification information of each computing core 480, and update the computing performance index of the computing core 480 in the corresponding status register 410, determine the clock frequency of the computing core 480 according to the updated computing performance index, and feed it back to the corresponding computing core 480 through the output distributor 470, thereby adjusting the clock frequency of the computing core 480.

[0104] Optionally, the input distributor 460 is further configured to distribute the inspection data of each computing core 480 to the corresponding control unit 420 according to the fullness or vacancy status of the multiple control units 420. In this way, the inspection data of each computing core 480 can be distributed to an unoccupied control unit 420, enabling the control unit 420 to promptly adjust the clock frequency level of the computing core 480 with a higher cycle error rate, thereby achieving higher control efficiency.

[0105] A third aspect of the present application provides a chip, comprising a frequency modulation device 400 of the chip according to any embodiment of the second aspect.

[0106] For example, a chip may include a control core and multiple computing cores 480. The control core includes a status register 410, a control unit 420, an input distributor 460, and an output distributor 470. Thus, the chip's internal control unit 420 can autonomously determine the operating status of the computing cores 480, thereby independently controlling the clock frequency of each computing core 480 and improving the chip's computing power without requiring external software. Furthermore, multiple computing cores 480 on a chip can share the control core, effectively reducing footprint and enabling the control core to handle clock control requests from a large array of computing cores while avoiding additional latency.

[0107] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0108] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0109] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0110] Any process or method description in a flow chart or otherwise described herein can be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process. The scope of the preferred embodiments of the present application includes additional implementations in which the functions may be performed in a different order than shown or discussed, including in a substantially simultaneous manner or in a reverse order depending on the functions involved.

[0111] The logic and / or steps represented in the flowchart or otherwise described herein may be considered, for example, as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device).

[0112] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above embodiment method can be completed by instructing the relevant hardware through a program, which can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0113] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing module, or each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the aforementioned integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic disk, or an optical disk, etc.

[0114] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A chip frequency modulation method, characterized in that: include: Get the calculation results of the calculation kernel; Determining a computing performance index of the computing core according to the computing result; The clock frequency of the computing core is adjusted in combination with the frequency control record of the computing core and the computing performance indicator, wherein the frequency control record is used to record the clock frequency that the computing core has adopted.

2. The chip frequency modulation method according to claim 1, characterized in that: When the computing performance index of the computing core is lower than the target expected value, marking the computing core as a first-state computing core; the target expected value is used to characterize the parameters of the normal operation of the computing core; The clock frequency of the first-state computing core is compared with the minimum operating frequency, and the clock frequency of the first-state computing core is adjusted according to the frequency control record.

3. The chip frequency modulation method according to claim 2, characterized in that: When the clock frequency of the first-state computing core is greater than the minimum operating frequency and the minimum operating frequency has not been used, lowering the clock frequency of the first-state computing core; When the clock frequency of the first-state computing core is equal to the minimum operating frequency, or the minimum operating frequency has been used, the clock frequency of the first-state computing core is increased.

4. The chip frequency modulation method according to claim 2, characterized in that: After adjusting the clock frequency of the first state computing core, the method includes: When the computing performance index of the first-state computing core is greater than the target expected value, controlling the first-state computing core to maintain the adjusted clock frequency; When the computing performance index of the computing core in the first state is lower than or equal to the target expected value, all clock frequencies are traversed according to the frequency control record.

5. The chip frequency modulation method according to claim 4, characterized in that: Also includes: Among all clock frequencies, when there is at least one such clock frequency such that the computing performance index of the first-state computing core is equal to the target expected value, the clock frequency of the first-state computing core is adjusted to the clock frequency corresponding to the optimal computing performance index, and the optimal computing performance index is the maximum value among the computing performance indicators.

6. The chip frequency modulation method according to claim 4, characterized in that: Also includes: When the computing performance index of the first-state computing core is lower than the target expected value at all clock frequencies, the first-state computing core is shut down or the clock frequency of the first-state computing core is adjusted to the lowest.

7. The chip frequency modulation method according to claim 4, characterized in that: Also includes: When the computing performance indicators of the first-state computing core are lower than the target expected values ​​at all clock frequencies, the first-state computing core is shut down or the clock frequency of the first-state computing core is adjusted to the clock frequency corresponding to the optimal computing performance indicator, where the optimal computing performance indicator is the maximum value of the computing performance indicators.

8. The chip frequency modulation method according to claim 1, characterized in that: When the computing performance index of the computing core is greater than the target expected value, the computing core is marked as a second-state computing core, and the clock frequency of the second-state computing core is increased.

9. The chip frequency modulation method according to claim 1, characterized in that: When the computing performance index of the computing core is equal to the target expected value, the computing core is marked as the third state computing The core maintains the clock frequency of the third state calculation core.

10. The chip frequency modulation method according to claim 1, characterized in that: The computing performance indicator is used to characterize the periodic accuracy of the computing result of the computing core.

11. The chip frequency modulation method according to claim 10, characterized in that: The determining of the computing performance index of the computing core according to the computing result includes: Obtaining the number n1 of incorrect calculation outputs and the number n2 of correct calculation outputs of the calculation core within a preset cycle length; The cycle accuracy of the computing core within a preset cycle length is determined based on n1 and n2.

12. A frequency modulation device for a chip, characterized in that: include: Status register, used to store the computing performance indicators and frequency control records of the computing core; A control unit is connected to the status register and is used to implement the method according to any one of claims 1 to 11.

13. The frequency modulation device of a chip according to claim 12, characterized in that: Also includes: Multiple phase-locked loop circuits for providing multiple clock frequencies; A multiplexer, the multiplexer comprising a plurality of first input terminals, a first output terminal and a first control terminal, the plurality of first input terminals being respectively connected to the plurality of phase-locked loop circuits, the first output terminal being connected to the computing core, and the first control terminal being connected to the control unit.

14. The frequency modulation device of a chip according to claim 12, characterized in that: The plurality of status registers are arranged in one-to-one correspondence with the plurality of computing cores; and there is at least one control unit.

15. The frequency modulation device of a chip according to claim 12, characterized in that: Also includes: The statistical module includes multiple second input terminals and second output terminals, wherein the multiple second input terminals are connected to the multiple computing cores one by one, and the second output terminal is connected to the control unit for outputting the inspection data of each computing core, wherein the inspection data of each computing core includes the identification information of each computing core and the number of incorrect calculation outputs and correct calculation outputs of each computing core within a preset cycle length.

16. The frequency modulation device of a chip according to claim 15, characterized in that: Also includes: an input distributor, wherein the input end of the input distributor is connected to the second output end, and is used to receive the inspection data of each of the computing cores, and the output end of the input distributor is connected to the control unit; An output distributor is connected between the control unit and the computing core.

17. The frequency modulation device of a chip according to claim 16, characterized in that: The input distributor is further configured to distribute the inspection data of each computing core to a corresponding control unit according to the empty or full status of the plurality of control units.

18. The frequency modulation device of a chip according to claim 14, characterized in that: The number of the control units is less than or equal to the number of the status registers.

19. A chip, characterized in that: A frequency modulation device comprising the chip according to any one of claims 12 to 18.

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