ESD protection device and manufacturing method therefor

Abstract

The present invention relates to an ESD protection device and a manufacturing method therefor. The device comprises: a P-type substrate; a first P-type well region; a first insulating structure, which extends into the P-type substrate and is located on a side surface of the first P-type well region; an N-type region, comprising a lower layer located at the bottom of the first P-type well region and an upper layer located on the lower layer, at least part of the P-type substrate being located below the lower layer; a conductive structure, at least part of the first insulating structure being located between the conductive structure and the first P-type well region and between the conductive structure and the lower layer; a first N-type doped region, located at the bottom of the conductive structure; a second insulating structure, the conductive structure being located between the first insulating structure and the second insulating structure; and a second P-type well region, located on the side of the second insulating structure opposite to the conductive structure, part of the P-type substrate being located below the second P-type well region. The present invention can reduce a trigger voltage of SCRs.

Description

An ESD protection device and a manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to application number 202410202674.3, filed on February 23, 2024, entitled “AN ESD PROTECTION DEVICE AND METHOD OF MANUFACTURING THE SAME,” and the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to an ESD protection device and a method for manufacturing the ESD protection device. Background Art

[0004] ESD (Electro-Static Discharge) protection is an important part of IC (Integrated Circuit) design. ESD protection devices play a role in protecting internal circuits from damage by static electricity.

[0005] As an ESD protection device, SCRs (Silicon Controlled Rectifiers) offer low on-resistance and high overcurrent capability per unit area. However, their application as ESD protection devices is limited by the difficulty of triggering SCRs and their high trigger voltage. Summary of the Invention

[0006] Based on this, it is necessary to provide an ESD protection device with a lower trigger voltage and a manufacturing method thereof.

[0007] An ESD protection device comprises: a P-type substrate; a first P-type well region; a first insulating structure extending into the P-type substrate and located on a side of the first P-type well region; an N-type region comprising a lower layer located at the bottom of the first P-type well region and an upper layer located on the lower layer, with at least a portion of the P-type substrate located below the lower layer; a conductive structure, with at least a portion of the first insulating structure located between the conductive structure and the first P-type well region, and between the conductive structure and the lower layer of the N-type region; a first N-type doped region located at the bottom of the conductive structure and separating the bottom of the conductive structure from the P-type substrate; a second insulating structure located on a side of the conductive structure opposite to the first insulating structure, with the conductive structure located between the first insulating structure and the second insulating structure; a second P-type well region located on a side of the second insulating structure opposite to the conductive structure, with a portion of the P-type substrate located below the second P-type well region; wherein the top of the conductive structure and the top of the second P-type well region are used for grounding, and the top of the first P-type well region and the top of the upper layer of the N-type region are used for connecting to an ESD port.

[0008] In the above-mentioned ESD protection device, when an electrostatic surge arrives at the ESD port, the vertical PMOS tube is turned on (the first P-type well region serves as the source region of the PMOS tube, the P-type substrate below the N-type region serves as the drain region of the PMOS tube, the conductive structure serves as the gate of the PMOS tube, and the first insulating structure serves as the gate dielectric layer), and the hole current bypasses the first insulating structure, the first N-type doped region, and the second insulating structure to reach the second P-type well region. This hole current flows through the P-type substrate below the first insulating structure and the second insulating structure to generate a positive voltage, thereby triggering the PN junction formed by the P-type substrate and the first N-type doped region to turn on, ultimately forming the conduction path of the SCR. Since the turn-on voltage of the vertical PMOS tube serves as the trigger voltage of the SCR, the trigger voltage of the SCR device can be flexibly controlled by reasonably designing the turn-on voltage of the PMOS tube, thereby reducing the trigger voltage of the SCR. Therefore, the trigger voltage of the ESD protection device is relatively low.

[0009] In one embodiment, a bottom depth of the first insulating structure is deeper than a bottom depth of a lower layer of the N-type region.

[0010] In one embodiment, a bottom depth of the second insulating structure is deeper than a bottom depth of a lower layer of the N-type region.

[0011] In one embodiment, the first insulating structure and the second insulating structure are formed on sidewalls of the trench, the conductive structure is formed in the trench, and the first insulating structure and the second insulating structure are respectively located on two sides of the conductive structure.

[0012] In one embodiment, the first P-type well region is a closed surrounding structure in the laterally direction, and the upper layer of the N-type region is laterally surrounded by the first P-type well region.

[0013] In one embodiment, the first insulating structure is a closed surrounding structure in the laterally direction, and the first P-type well region is laterally surrounded by the first insulating structure.

[0014] In one embodiment, the second P-type well region is a closed enclosing structure in the laterally direction, and the second insulating structure is laterally enclosed by the second P-type well region.

[0015] In one embodiment, the ESD protection device further includes: a second N-type doped region located on top of the upper layer of the N-type region, the doping concentration of the second N-type doped region is greater than the doping concentration of the N-type region, and the upper layer of the N-type region is connected to the ESD port through the second N-type doped region.

[0016] In one embodiment, the ESD protection device further includes: a first P-type doped region, located on top of the first P-type well region, the doping concentration of the first P-type doped region is greater than the doping concentration of the first P-type well region, and the first P-type well region is connected to the ESD port through the first P-type doped region.

[0017] In one embodiment, the ESD protection device further includes: a second P-type doped region located on top of the second P-type well region, the doping concentration of the second P-type doped region is greater than the doping concentration of the second P-type well region, and the second P-type well region is grounded through the second P-type doped region.

[0018] In one embodiment, the doping concentration of the first N-type doping region is greater than the doping concentration of the N-type region.

[0019] In one embodiment, the upper layer of the N-type region includes an N-well located on the side of the first P-type well region, and the lower layer of the N-type region includes an N-type buried layer located below the N-well and below the first P-type well region.

[0020] A method for manufacturing an ESD protection device comprises: obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate; at least a portion of the P-type substrate being located below the N-type region and below the P-type well region, respectively, the N-type region comprising a lower layer located at the bottom of the P-type well region and an upper layer located above the lower layer; forming a trench penetrating the P-type well region, the lower layer of the N-type region being located on a side of the trench, the P-type well region being separated by the trench into a first P-type well region and a second P-type well region; forming a first insulating structure and a second insulating structure on an inner wall of the trench, the first insulating structure being located on a side of the trench close to the N-type region, and the second insulating structure being located on a side of the trench opposite the first insulating structure; forming a first N-type doped region in the P-type substrate at the bottom of the trench; and forming a conductive structure in the trench, the first N-type doped region separating the bottom of the conductive structure from the P-type substrate; wherein a top of the conductive structure and a top of the second P-type well region are used for grounding, and a top of the first P-type well region and a top of the upper layer of the N-type region are used for connecting to an ESD port.

[0021] In the ESD protection device manufactured using the aforementioned method, when an electrostatic surge is applied to the ESD port, the vertical PMOS transistor turns on, allowing hole current to bypass the first insulating structure, the first N-type doped region, and the second insulating structure and reach the second P-type well region. This hole current flows through the P-type substrate beneath the first and second insulating structures, generating a positive voltage, which triggers the PN junction formed between the P-type substrate and the first N-type doped region to turn on, ultimately forming a conduction path for the SCR. Because the turn-on voltage of the vertical PMOS transistor serves as the trigger voltage of the SCR, rationally designing the turn-on voltage of the PMOS transistor allows for flexible control of the SCR device's trigger voltage, thereby reducing the SCR's trigger voltage.

[0022] In one embodiment, the step of obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate includes: forming an N-type buried layer in the P-type substrate as a lower layer of the N-type region; forming an epitaxial layer on the P-type substrate; forming the P-type well region and an N-well as an upper layer of the N-type region in the epitaxial layer, wherein the N-well is located on the side of the P-type well region.

[0023] In one embodiment, the step of forming a trench passing through the P-type well region includes: forming a shallow trench isolation structure, the bottom of the shallow trench isolation structure extends into the P-type well region, and the shallow trench isolation structure is not formed on at least a portion of the top of the first P-type well region, at least a portion of the top of the second P-type well region, and at least a portion of the top of the upper layer of the N-type region; forming a patterned hard mask layer on the upper layer of the N-type region, on the first P-type well region, and on the second P-type well region; using the hard mask layer as an etching barrier layer, etching the shallow trench isolation structure, and continuing to etch the P-type well region downward to form the trench.

[0024] In one embodiment, after the step of forming a conductive structure in the groove, the step further includes: removing the hard mask layer; forming a second N-type doping region on the top of the upper layer of the N-type region, forming a first P-type doping region on the top of the first P-type well region, and forming a second P-type doping region on the top of the second P-type well region; wherein the doping concentration of the second N-type doping region is greater than the doping concentration of the N-type region, the doping concentration of the first P-type doping region is greater than the doping concentration of the first P-type well region, and the doping concentration of the second P-type doping region is greater than the doping concentration of the second P-type well region; the N-type region is connected to the ESD port through the second N-type doping region, the first P-type well region is connected to the ESD port through the first P-type doping region, and the second P-type well region is grounded through the second P-type doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0026] FIG1 is a schematic structural diagram of an ESD protection device according to an embodiment of the present application;

[0027] FIG2 is a schematic diagram of an SCR turn-on current path of the ESD protection device shown in FIG1 ;

[0028] FIG3 is a circuit diagram of an SCR in the ESD protection device shown in FIG2 ;

[0029] FIG4a is a top view of the groove in an embodiment in which the groove 141 is in a square shape in the transverse direction, and FIG4b is a top view of the groove in an embodiment in which the groove 141 is in a circular shape in the transverse direction;

[0030] FIG5 a is a top view of the first insulating structure 142, the second insulating structure 144, and the conductive structure 150 in an embodiment in which the trench 141 is in a transverse square shape. FIG5 b is a top view of the first insulating structure 142, the second insulating structure 144, and the conductive structure 150 in an embodiment in which the trench 141 is in a transverse circular shape.

[0031] FIG6 is a flow chart of a method for manufacturing an ESD protection device according to an embodiment of the present application;

[0032] FIG7 is a flowchart of sub-steps of step S610 in one embodiment of the present application;

[0033] 8a to 8h are schematic cross-sectional views of the device during the process of manufacturing the ESD protection device using the method shown in FIG6 ;

[0034] FIG9 is a flowchart of sub-steps of step S620 in an embodiment of the present application. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0041] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0042] This application proposes a new ESD protection device, which uses the turn-on voltage of the vertical PMOS tube in the device as the trigger voltage of the SCR, thereby reducing the trigger voltage of the SCR.

[0043] FIG1 is a schematic diagram of the structure of an ESD protection device according to one embodiment of the present application. The ESD protection device shown in FIG1 is bilaterally symmetrical, so some structures are numbered only on one side. In the embodiment shown in FIG1 , the ESD protection device includes a P-type substrate 110, an N-type region 120, a first P-type well region 132, a second P-type well region 134, a first insulating structure 142, a second insulating structure 144, a first N-type doped region 121, and a conductive structure 150. The first insulating structure 142 extends into the P-type substrate 110 and is located on the side of the first P-type well region 132. The N-type region 120 includes a lower layer 122 located at the bottom of the first P-type well region 132, and an upper layer 124 located on a side of the first P-type well region 132 opposite the first insulating structure 142 and located above the lower layer 122. At least a portion of the P-type substrate 110 is located below the lower layer 122. At least a portion of the first insulating structure 142 is located between the conductive structure 150 and the first P-type well region 132, and between the conductive structure 150 and the lower layer 122. The first N-type doped region 121 is located at the bottom of the conductive structure 150, separating the bottom of the conductive structure 150 from the P-type substrate 110. A second insulating structure 144 is located on a side of the conductive structure 150 opposite the first insulating structure 142, with the conductive structure 150 located between the first insulating structure 142 and the second insulating structure 144. The second P-type well region 134 is located on a side of the second insulating structure 144 opposite the conductive structure 150, with a portion of the P-type substrate 110 located below the second P-type well region 134. The top of the conductive structure 150 and the top of the second P-type well region 134 are connected to ground (GND), that is, to the cathode electrode; the top of the first P-type well region 132 and the top of the upper layer 124 are connected to the ESD port, that is, to the anode electrode.

[0044] In the aforementioned ESD protection device, when an electrostatic surge arrives at the ESD port, the vertical PMOS transistor turns on, wherein the first P-type well region 132 serves as the source region of the PMOS transistor, the P-type substrate 110 below the N-type region 120 serves as the drain region of the PMOS transistor, the conductive structure 150 serves as the gate of the PMOS transistor, and the first insulating structure 142 serves as the gate dielectric layer. Hole current bypasses the first insulating structure 142, the first N-type doped region 121, and the second insulating structure 144 to reach the second P-type well region 134, as indicated by the arrows in FIG1 . This hole current flows through the P-type substrate 110 below the first insulating structure 142 and the second insulating structure 144, generating a positive voltage, thereby triggering the PN junction formed by the P-type substrate 110 and the first N-type doped region 121 to turn on, ultimately forming the conduction path of the SCR (see FIG3 ), as indicated by the arrows in FIG2 . Since the turn-on voltage of the vertical PMOS tube serves as the trigger voltage of the SCR, the trigger voltage of the SCR device can be flexibly controlled by reasonably designing the turn-on voltage of the PMOS tube, thereby reducing the trigger voltage of the SCR.

[0045] In one embodiment of the present application, the bottom depth of the first insulating structure 142 is deeper than the bottom depth of the lower layer 122, that is, the first insulating structure 142 extends deeper into the P-type substrate 110 than the lower layer 122. Furthermore, the bottom depth of the second insulating structure 144 is deeper than the bottom depth of the lower layer 122, that is, the second insulating structure 144 extends deeper into the P-type substrate 110 than the lower layer 122.

[0046] In one embodiment of the present application, the upper layer 124 is an N-well located on the side of the first P-type well region, and the lower layer 122 is an N-bury located below the N-well and below the first P-type well region 132 .

[0047] In one embodiment of the present application, a first insulating structure 142 and a second insulating structure 144 are formed on the sidewalls of a trench 141 (not shown in FIG1 ), and a conductive structure 150 is formed in the trench 141, with the first insulating structure 142 and the second insulating structure 144 respectively located on either side of the conductive structure 150. In one embodiment of the present application, the trench 141 is a closed, enclosing structure in a transverse direction. FIG4 a is a top view of the trench 141 in an embodiment in which the trench 141 is in a transverse frame shape, and FIG4 b is a top view of the trench 141 in an embodiment in which the trench 141 is in a transverse ring shape. In other embodiments of the present application, the trench 141 may also be a closed, enclosing structure in other shapes, such as an elliptical ring or a racetrack shape. Figure 5a is a top view of the first insulating structure 142, the second insulating structure 144 and the conductive structure 150 in an embodiment in which the groove 141 (not shown in Figure 5a) is a square frame in the horizontal direction. Figure 5b is a top view of the first insulating structure 142, the second insulating structure 144 and the conductive structure 150 in an embodiment in which the groove 141 is a circular ring in the horizontal direction.

[0048] In one embodiment of the present application, the first P-type well region 132 is a laterally closed, surrounding structure, and the upper layer 124 is laterally surrounded by the first P-type well region 132. The first insulating structure 142 is a laterally closed, surrounding structure, and the first P-type well region 132 is laterally surrounded by the first insulating structure 142. The second P-type well region 134 is a laterally closed, surrounding structure, and the second insulating structure 144 is laterally surrounded by the second P-type well region 134.

[0049] In one embodiment of the present application, the ESD protection device further includes a second N-type doped region 125 located on top of the upper layer 124. The doping concentration of the second N-type doped region 125 is greater than that of the N-type region 120, thereby reducing contact resistance. The upper layer 124 is connected to the ESD port via the second N-type doped region 125.

[0050] In one embodiment of the present application, the ESD protection device further includes a first P-type doped region 133 located on top of the first P-type well region 132. The doping concentration of the first P-type doped region 133 is greater than the doping concentration of the first P-type well region 132, thereby reducing contact resistance. The first P-type well region 132 is connected to the ESD port via the first P-type doped region 133.

[0051] In one embodiment of the present application, the ESD protection device further includes a second P-type doping region 135 located on top of the second P-type well region 134. The doping concentration of the second P-type doping region 135 is greater than the doping concentration of the second P-type well region 134, thereby reducing contact resistance. The second P-type well region 134 is grounded through the second P-type doping region 135.

[0052] In one embodiment of the present application, the doping concentration of the first N-type doping region 121 is greater than the doping concentration of the N-type region 120 .

[0053] In some embodiments of the present application, the conductive structure 150 may be made of polysilicon, metal, or alloy. In one embodiment of the present application, the first insulating structure 142 and the second insulating structure 144 are made of silicon oxide, such as silicon dioxide.

[0054] The present application accordingly provides a method for manufacturing an ESD protection device, which is used to manufacture the ESD protection device described in any of the above embodiments. FIG6 is a flow chart of the method for manufacturing an ESD protection device in an embodiment of the present application, comprising the following steps:

[0055] S610 , obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate.

[0056] At least part of the P-type substrate 110 is located under the N-type region and the P-type well region, respectively. The N-type region includes a lower layer located at the bottom of the P-type well region and an upper layer located on the side of the P-type well region and on the lower layer.

[0057] Referring to FIG. 7 , in one embodiment of the present application, step S610 includes:

[0058] S612, forming an N-type buried layer in the P-type substrate.

[0059] Referring to FIG. 8 a , in one embodiment of the present application, a pad oxide layer (PAD Oxide) 143 can be first formed on the surface of the P-type substrate 110 of the wafer by thermal oxidation, and then an N-type buried layer (N-bury) is formed in the P-type substrate 110 by patterning (e.g., photolithography) and ion implantation (implanting N-type ions), and a well is pushed to serve as the lower layer 122 of the N-type region.

[0060] S614, forming an epitaxial layer on the P-type substrate.

[0061] In one embodiment of the present application, after the pad oxide layer 143 is removed, an epitaxial layer is grown on the P-type substrate 110 and the lower layer 122 .

[0062] S616 , forming a P-type well region and an N-type well in the epitaxial layer.

[0063] 8b, N-type ions and P-type ions are respectively implanted into the epitaxial layer through patterning (e.g., photolithography) and ion implantation to form a P-type well region (P-Well) 130 and an N-well (N-Well) in the upper layer 124 serving as an N-type region in the epitaxial layer on the lower layer 122.

[0064] At this point, step S610 is completed and the process proceeds to step S620.

[0065] S620 , forming a trench penetrating the P-type well region.

[0066] After the trench 141 is formed, the lower layer 122 is located on the side of the trench 141 , and the P-type well region 130 is divided by the trench 141 into a first P-type well region 132 close to the upper layer 124 and a second P-type well region 134 away from the upper layer 124 .

[0067] Referring to FIG. 9 , in one embodiment of the present application, step S620 includes:

[0068] S622, forming a shallow trench isolation structure.

[0069] The front side of the wafer is patterned (e.g., by photolithography and etching) to form shallow trenches, and then an oxide layer is deposited to form shallow trench isolation structures 145 (see FIG8c ). The bottom of shallow trench isolation structures 145 extends into P-type well region 130 , while at least a portion of the top of first P-type well region 132 , at least a portion of the top of second P-type well region 134 , and at least a portion of the top of upper layer 124 are not covered by shallow trench isolation structures 145 , thereby exposing these areas on the top surface of the wafer.

[0070] S624 , forming a patterned hard mask layer on the P-type well region and the N-type region.

[0071] In one embodiment of the present application, silicon nitride is deposited on the front side of the wafer (i.e., on the P-type well region 130, the upper layer 124, and the shallow trench isolation structure 145), and then patterned (photolithography and etching) to form a hard mask layer 152 (see Figure 8d). The window exposed by the hard mask layer 152 is located on the shallow trench isolation structure 145. In one embodiment of the present application, before depositing silicon nitride, a step of forming a PAD oxide on the front side of the wafer is also included, and the silicon nitride is deposited on the PAD oxide.

[0072] S626 , using the hard mask layer as an etching barrier layer, etching to form a trench.

[0073] After etching through the shallow trench isolation structure 145 , the P-type well region 130 is further etched downward to form a trench 141 , as shown in FIG. 8 e .

[0074] At this point, step S620 is completed and the process proceeds to step S630.

[0075] S630 , forming a first insulating structure and a second insulating structure on the inner wall of the trench.

[0076] In one embodiment of the present application, an oxide layer is deposited on the front side of the wafer, and the inner surface of trench 141 is also covered by the deposited oxide layer (see FIG8f ). In one embodiment of the present application, after the oxide layer is deposited, the oxide layer at the bottom of trench 141 is removed by etching, exposing the P-type substrate 110 at the bottom of trench 141. The oxide layer on the side of trench 141 adjacent to the first P-type well region 132 serves as the first insulating structure 142, and the oxide layer on the side adjacent to the second P-type well region 134 serves as the second insulating structure 144.

[0077] S640 , forming a first N-type doping region in the P-type substrate at the bottom of the trench.

[0078] The first N-type doping region 121 is formed by ion implantation (implanting N-type ions), see FIG. 8 g .

[0079] S650 , forming a conductive structure in the trench.

[0080] In one embodiment of the present application, N-type polysilicon is deposited into the trench 141 (not shown in FIG8 h ) to form the conductive structure 150 . The first N-type doped region 121 separates the bottom of the conductive structure 150 from the P-type substrate 110 .

[0081] The top of the conductive structure 150 and the top of the second P-type well region 134 are used for grounding, and the top of the first P-type well region 132 and the top of the upper layer 124 are used for connecting to the ESD port.

[0082] In one embodiment of the present application, after depositing N-type polysilicon, excess conductive structure 150 on the wafer surface can be removed by chemical mechanical polishing (CMP). In one embodiment of the present application, CMP causes the upper surface of conductive structure 150 to be slightly lower than the upper surface of hard mask layer 152.

[0083] In the ESD protection device manufactured by the above-described manufacturing method for an ESD protection device, when an electrostatic surge arrives at the ESD port, the vertical PMOS transistor turns on, and the hole current bypasses the first insulating structure 142, the first N-type doped region 121, and the second insulating structure 144 to reach the second P-type well region 134. This hole current flows through the P-type substrate 110 below the first insulating structure 142 and the second insulating structure 144, generating a positive voltage, thereby triggering the PN junction formed by the P-type substrate 110 and the first N-type doped region 121 to turn on, ultimately forming a conduction path for the SCR. Since the turn-on voltage of the vertical PMOS transistor serves as the trigger voltage of the SCR, the trigger voltage of the SCR device can be flexibly controlled by rationally designing the turn-on voltage of the PMOS transistor, thereby reducing the trigger voltage of the SCR.

[0084] In one embodiment of the present application, after step S650, the method further includes:

[0085] removing the hard mask layer 152;

[0086] A second N-type doped region 125 is formed on top of the upper layer 124, a first P-type doped region 133 is formed on top of the first P-type well region 132, and a second P-type doped region 135 is formed on top of the second P-type well region 134. These can be formed by patterning (e.g., photolithography) and ion implantation. The resulting device structure is shown in FIG1 .

[0087] The doping concentration of the second N-type doping region 125 is greater than that of the N-type region 120, the doping concentration of the first P-type doping region 133 is greater than that of the first P-type well region 132, and the doping concentration of the second P-type doping region 135 is greater than that of the second P-type well region 134. The upper layer 124 is connected to the ESD port via the second N-type doping region 125, the first P-type well region 132 is connected to the ESD port via the first P-type doping region 133, and the second P-type well region 134 is grounded via the second P-type doping region 135.

[0088] The manufacturing method of the ESD protection device of the present application and the ESD protection device are based on the same inventive concept. For matters not specifically described in the manufacturing method of the ESD protection device, please refer to the above introduction to the ESD protection device.

[0089] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0090] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0091] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An ESD protection device, characterized in that: include: P-type substrate; a first P-type well region; a first insulating structure extending into the P-type substrate and located on a side of the first P-type well region; An N-type region, comprising a lower layer located at the bottom of the first P-type well region, and an upper layer located on the lower layer, wherein at least a portion of the P-type substrate is located below the lower layer; a conductive structure, wherein at least a portion of the first insulating structure is located between the conductive structure and the first P-type well region, and between the conductive structure and a lower layer of the N-type region; a first N-type doped region, located at the bottom of the conductive structure and separating the bottom of the conductive structure from the P-type substrate; a second insulating structure located on a side of the conductive structure opposite to the first insulating structure, wherein the conductive structure is located between the first insulating structure and the second insulating structure; a second P-type well region, located on a side of the second insulating structure opposite to the conductive structure, with a portion of the P-type substrate located below the second P-type well region; The top of the conductive structure and the top of the second P-type well region are used for grounding, and the top of the first P-type well region and the top of the upper layer of the N-type region are used for connecting to an ESD port.

2. The ESD protection device according to claim 1, wherein: A bottom depth of the first insulating structure is deeper than a bottom depth of a lower layer of the N-type region.

3. The ESD protection device according to claim 1, wherein: A bottom depth of the second insulating structure is deeper than a bottom depth of a lower layer of the N-type region.

4. The ESD protection device according to claim 1, wherein: The first insulating structure and the second insulating structure are formed on sidewalls of the trench, the conductive structure is formed in the trench, and the first insulating structure and the second insulating structure are respectively located on two sides of the conductive structure.

5. The ESD protection device according to claim 4, characterized in that: The first P-type well region is a closed enclosing structure in the laterally direction, and the upper layer of the N-type region is laterally enclosed by the first P-type well region; The first insulating structure is a closed surrounding structure in the lateral direction, and the first P-type well region is Surrounded upward by the first insulating structure; The second P-type well region is a closed enclosing structure in the laterally direction, and the second insulating structure is laterally enclosed by the second P-type well region.

6. The ESD protection device according to claim 1, wherein: Also includes: A second N-type doping region is located on top of the upper layer of the N-type region. The doping concentration of the second N-type doping region is greater than the doping concentration of the N-type region. The upper layer of the N-type region is connected to the ESD port through the second N-type doping region.

7. The ESD protection device according to claim 1, wherein: Also includes: A first P-type doped region is located on top of the first P-type well region. The doping concentration of the first P-type doped region is greater than the doping concentration of the first P-type well region. The first P-type well region is connected to the ESD port through the first P-type doped region.

8. The ESD protection device according to claim 1, wherein: Also includes: The second P-type doping region is located on the top of the second P-type well region. The doping concentration of the second P-type doping region is greater than the doping concentration of the second P-type well region. The second P-type well region is grounded through the second P-type doping region.

9. The ESD protection device according to claim 1, wherein: The doping concentration of the first N-type doping region is greater than the doping concentration of the N-type region.

10. The ESD protection device according to claim 1, wherein: The upper layer of the N-type region includes an N-well located on the side of the first P-type well region, and the lower layer of the N-type region includes an N-type buried layer located below the N-well and below the first P-type well region.

11. A method for manufacturing an ESD protection device, characterized in that: include: Obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate; at least a portion of the P-type substrate is located below the N-type region and below the P-type well region, respectively, and the N-type region includes a lower layer located at the bottom of the P-type well region and an upper layer located above the lower layer; forming a trench penetrating the P-type well region, wherein the lower layer of the N-type region is located on a side of the trench, and the P-type well region is divided into a first P-type well region and a second P-type well region by the trench; forming a first insulating structure and a second insulating structure on an inner wall of the trench, wherein the first insulating structure is located on a side of the trench close to the N-type region, and the second insulating structure is located on a side of the trench opposite to the first insulating structure; forming a first N-type doping region in the P-type substrate at the bottom of the trench; forming a conductive structure in the trench, wherein the first N-type doped region separates a bottom of the conductive structure from the P-type substrate; The top of the conductive structure and the top of the second P-type well region are used for grounding, and the top of the first P-type well region and the top of the upper layer of the N-type region are used for connecting to an ESD port.

12. The method for manufacturing an ESD protection device according to claim 11, wherein: The step of obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate comprises: forming an N-type buried layer in the P-type substrate as a lower layer of the N-type region; forming an epitaxial layer on the P-type substrate; The P-type well region and an N-well as an upper layer of the N-type region are formed in the epitaxial layer, and the N-well is located on a side of the P-type well region.

13. The method for manufacturing an ESD protection device according to claim 11, wherein: The step of forming a trench penetrating the P-type well region comprises: forming a shallow trench isolation structure, wherein the bottom of the shallow trench isolation structure extends into the P-type well region, and the shallow trench isolation structure is not formed on at least a portion of the top of the first P-type well region, at least a portion of the top of the second P-type well region, and at least a portion of the top of the upper layer of the N-type region; forming a patterned hard mask layer on the upper layer of the N-type region, on the first P-type well region, and on the second P-type well region; The shallow trench isolation structure is etched using the hard mask layer as an etching barrier, and the P-type well region is further etched downward to form the trench.

14. The method for manufacturing an ESD protection device according to claim 13, wherein: After the step of forming a conductive structure in the trench, the method further includes: removing the hard mask layer; forming a second N-type doping region on the top of the upper layer of the N-type region, forming a first P-type doping region on the top of the first P-type well region, and forming a second P-type doping region on the top of the second P-type well region; The doping concentration of the second N-type doping region is greater than the doping concentration of the N-type region, the doping concentration of the first P-type doping region is greater than the doping concentration of the first P-type well region, and the doping concentration of the second P-type doping region is greater than the doping concentration of the second P-type well region; the N-type region is connected to the ESD port through the second N-type doping region, and the first P-type well region is connected to the first The P-type doped region is connected to the ESD port, and the second P-type well region is grounded through the second P-type doped region.

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