Memory controller and method for mapping interval of memory pages

Abstract

A memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages stored sequentially in a cache memory. Moreover, the memory controller is configured to map the number of memory pages by indicating the cache memory address of a first memory page of the interval of memory pages and indicating the number of memory pages in the interval of memory pages. Moreover, the interval of memory pages is stored sequentially in the cache memory to provide an optimized and efficient mapping of the interval of memory pages stored in the backend storage and the interval of memory pages in the cache memory.

Description

[0001] MEMORY CONTROLLER AND METHOD FOR MAPPING INTERVAL OF MEMORY PAGES

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of data storage management and more specifically, to a memory controller and a method for the memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages stored sequentially in a cache memory.

[0004] BACKGROUND

[0005] Generally, cache plays a pivotal role in accelerating data retrieval by storing frequently accessed data in data storage systems. The cache is a hardware or software component that is configured to copy pages from a backend storage device, such as a hard disk drive (HDD) or a solid-state drive (SSD), to smaller and faster cache storage, like an SSD or random access memory (RAM). The one-to-one mapping of cache pages to backend storage pages is governed by cache metadata, which is required to be organized and maintained correctly to provide data retrieval with reduced overall processing time. Additionally, a constant increase over time in the backend storage capacity has resulted in progressively larger memory requirements for the cache metadata. However, it is difficult to fulfil such an increase in the memory requirement as the increased memory consumption of the cache metadata uses a random access memory (RAM), which could otherwise be used as the cache pages or can be used to perform different tasks of the data storage systems thereby, consequently slowing down the data storage systems along with the cache itself.

[0006] Currently, conventional cache metadata methods commonly use hash tables or similar data structures, where each mapping between a cache page (Pc) and a backend page (Pr) is individually stored. However, the size of such data structures scales proportionally with the total number of pages in the cache, leading to substantial memory consumption. Therefore, the conventional cache metadata methods involve enlarging page sizes to reduce the size of the cache metadata, thereby decreasing the total number of pages, and reducing the memory requirements of the cache metadata. For example, if a cache size is 320 Gigabytes (GB) and a page size is 4 Kilobytes (KB), then, in that case, 80M pages can be created. Moreover, for the sake of example, assume that each page requires 32 bytes in the cache metadata. Thus, the size of the cache metadata is 2560MB.

[0007] Furthermore, if the page size is increased by 16 times to 64KB, then, in that case, the number of pages is accordingly decreased by 16 times to 5M, and the size of the cache metadata is reduced to 160 Megabytes (MB). However, large cache pages may remain unused, leading to an inefficient utilization of the cache memory. For example, using a 64KB page size, if only 4KB of data is read from the backend and stored in the cache, a significant portion of the cache (i.e., the entire 64KB page) is allocated for just 4KB of the data. Therefore, such an inefficiency becomes more pronounced when dealing with isolated 4KB blocks and the like, each requiring a new page in the cache. Consequently, a substantial portion of the available cache space remains unutilized. Thus, there exists a technical problem of how to optimize cache memory utilization and handle cache memory address inefficiencies related to large cache pages.

[0008] Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with conventional memory controllers and conventional methods to provide a cache metadata compression scheme.

[0009] SUMMARY

[0010] The present disclosure provides a memory controller and a method for the memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages stored sequentially in a cache memory. The present disclosure provides a solution to the existing problem of how to optimize cache memory utilization and handle cache memory address inefficiencies related to large cache pages. An objective of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides an improved memory controller and an improved method for the memory controller configured to map an interval of memory pages stored sequentially in the backend storage to an interval of memory pages in the cache memory.

[0011] One or more objectives of the present disclosure are achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

[0012] In one aspect, the present disclosure provides a memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages stored sequentially in a cache memory. The memory controller is configured to map the number of memory pages by indicating the cache memory address of the first memory page of the interval of memory pages and indicating the number of memory pages in the interval of memory pages. Moreover, the interval of memory pages is stored sequentially in the cache memory.

[0013] Advantageously, the memory controller enables an optimized and efficient mapping of the interval of memory pages stored in the backend storage and the interval of memory pages in the cache memory. By indicating the cache memory address of the first memory page and specifying the number of memory pages in the interval of the memory pages, the memory controller is configured to reduce the mapping overhead, which improves the overall performance of the memory controller with reduced memory footprint. Additionally, the remaining memory, which is saved due to mapping of the interval of memory pages of the backend storage to the interval of the memory pages of the cache memory, can be used for additional cache pages or for the other tasks of the system to speed up a data management system.

[0014] In an implementation form, the memory controller is further configured to access a memory page in the cache memory by retrieving the first memory address of a first page in the interval of memory pages, retrieving the ordering of the memory page to be accessed, and access the memory page to be accessed at a memory address equaling the first memory address adapted based on the ordering.

[0015] In such an implementation, the memory pages to be accessed at the memory address equaling the first memory address adapted based on the ordering are used to ensure a systematic and ordered retrieval of the memory page within the cache memory, incorporating the specified order within the interval of memory pages.

[0016] In another implementation form, the memory controller is further configured to adapt the first memory address based on the ordering by adding a memory address offset equaling one memory page to the first memory address times the ordering.

[0017] In such an implementation, the adoption of the first memory address based on the ordering by adding a memory address offset equaling one memory page to the first memory address times the ordering is used to ensure an optimized, precise, and systematic data retrieval with reduced latency.

[0018] In yet another implementation form, the memory controller is further configured to indicate the cache memory address of the first memory page and indicate the number of memory pages by storing the cache memory address of the first memory page and the number of memory pages in a hash table and to resolve collisions utilizing chaining.

[0019] Additionally, the memory controller is configured to manage and access memory pages efficiently and effectively with reduced overall processing time required for retrieving the data from the cache memory.

[0020] In another aspect, the present disclosure provides a method for a memory controller for mapping an interval of memory pages stored sequentially in a backend storage to an interval of memory pages in a cache memory. Furthermore, the method comprises mapping the interval of memory pages by indicating the cache memory address of the first memory page of the interval of memory pages and indicating the number of memory pages in tire interval of memory pages. The interval of memory pages is stored sequentially in the cache memory.

[0021] The method achieves all the advantages and technical effects of the memory controller of the present disclosure.

[0022] It is to be appreciated that all the aforementioned implementation forms can be combined.

[0023] It has to be noted that all devices, elements, circuitry, units, and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application, as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

[0024] Additional aspects, advantages, features, and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations constmed in conjunction with the appended claims that follow.

[0025] BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, tike elements have been indicated by identical numbers.

[0027] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

[0028] FIG. 1 is a block diagram that depicts a memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages in a cache memory, in accordance with an embodiment of the present disclosure;

[0029] FIG. 2 is a flowchart depicting a method for the memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages in a cache memory, in accordance with an embodiment of the present disclosure;

[0030] FIG. 3 A is a diagram depicting an exemplary scenario for mapping an individual mapping of memory pages stored in a backend storage to an individual mapping of memory pages stored in a cache memory, in accordance with an embodiment of the present disclosure;

[0031] FIG. 3B is a diagram depicting an exemplary scenario for mapping an interval of memory pages stored in a backend storage to an interval of memory pages stored in a cache memory, in accordance with an embodiment of the present disclosure;

[0032] FIG. 4 is a diagram that depicts a mapping structure of an interval of memory pages, in accordance with an embodiment of the present disclosure;

[0033] FIG. 5 is a diagram that depicts a mapping structure of a hash table of an interval of memory pages, in accordance with an embodiment of the present disclosure; and FIG. 6 is a diagram that depicts a metadata memory layout of an interval of memory pages, in accordance with an embodiment of the present disclosure.

[0034] In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

[0035] DETAILED DESCRIPTION OF EMBODIMENTS

[0036] The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

[0037] FIG. 1 is a block diagram that depicts a memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages stored sequentially in a cache memory, in accordance with an embodiment of the present disclosure. With reference to FIG.1, there is shown a block diagram 100 that includes a memory controller 102, a backend storage 104, a cache memory 106, a memory 108, and a network interface 110. The cache memory 106 includes a cache memory address 112.

[0038] The memory controller 102 is configured to map the interval of memory pages stored sequentially in the backend storage 104 to the interval of memory pages stored sequentially in the cache memory 106. Examples of the memory controller 102 may include, but are not limited to, a microcontroller, a microprocessor, a central processing unit (CPU), a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set (RISC) processor, a very long instruction word (VLIW) processor, a data processing unit, and other processors or control circuitry.

[0039] The backend storage 104 is a data storage that includes the interval of memory pages stored sequentially. Examples of the backend storage 104 may include, but are not limited to, a hard disk drive (HDD), a solid-state drive (SSD), a network attached storage (NAS), a Storage Area Network (SAN), a cloud storage, a tape storage, an optical storage (e.g., Blu-ray Discs), and the like.

[0040] The memory 108 is configured to store instructions to be executed by the memory controller 102. In an implementation, the memory 108 corresponds to a local memory, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM), Random Access Memory (RAM), Read-Only Memory (ROM), a central processing unit (CPU) cache memory, and the like.

[0041] The network interface 110 may include hardware or software configured to establish communication among the memory controller 102, the cache memory 106, the memory 108, and the backend storage 104. Examples of the network interface 110 may include but are not limited to a computer port, a network socket, a network interface controller (NIC), and any other network interface device.

[0042] There is provided the memory controller 102 that is configured to map the interval of memory pages stored sequentially in the backend storage 104 to the interval of memory pages stored sequentially in the cache memory 106. The cache memory 106 serves as a storage unit that temporarily holds frequently accessed data, enhancing the speed of the data retrieval. In an implementation, the interval of memory pages refers to a number of memory pages sequentially stored within the backend storage 104 and is mapped to a corresponding series of memory pages in the cache memory 106. Moreover, the interval of memory pages could be represented by the starting address of the first memory page in the sequence and the number of consecutive memory pages that follow. For example, if the interval of memory pages starts with a memory page address of 'X' and includes 'N' pages, then, in that case, the interval of memory pages can be represented by the range 'X', 'X+T, 'X+2', ..., 'X+N-l'. The memory controller 102 maps and manages the flow of data between the backend storage 104 and the cache memory 106 by mapping the interval of memory pages stored sequentially in the backend storage 104 to the interval of memory pages in the cache memory 106 to allow an efficient mapping and retrieval of the data, ensuring that a continuous range of memory pages is handled collectively as a unit, rather than individually. Additionally, by mapping the interval of memory pages, the memory controller 102 is configured to streamline the data accessibility operation, facilitating faster data retrieval from backend storage 104 to cache memory 106 with an improved overall performance of a system with reduced memory footprint.

[0043] In an implementation, the number of memory pages in the interval of memory pages is one or more. In an example, the number of memory pages in the interval of memory pages is one. In another example, the number of memory pages in the interval of memory pages is more than one, such as two, three, four, and the like. In another implementation, the number of memory pages in the interval of memory pages is two or more. In an example, the number of memory pages in the interval of memory pages is two. In another example, the number of memory pages in the interval of memory pages is more than two, such as three, four, five, six, and the like. As a result, the interval of memory pages allows for dynamic and adaptable mapping of the memory pages by accommodating diverse intervals of memory pages, thereby contributing to an optimized memory utilization, efficient memory resource utilization, preventing unnecessary fragmentation, and ensuring that the cache memory 106 is effectively organized to meet the demands of applications miming on the system.

[0044] The memory controller 102 is configured to map the number of memory pages by indicating the cache memory address 112 of the first memory page of the interval of memory pages and indicating the number of memory pages in the interval of memory pages. Moreover, the interval of memory pages is stored sequentially in the cache memory 106. The cache memory address 112 corresponds to an address within the cache memory 106 where the mapping starts. Moreover, the cache memory address 112 is configured to point to the first memory page within the interval of memory pages. Firstly, the memory controller 102 is configured to point to the cache memory address 112 of the first memory page within the interval of memory pages. The cache memory address 112 is configured to serve as a starting point for the mapping of the interval of memory pages that are sequentially stored in the backend storage 104 to the interval of memory pages in the cache memory 106. Secondly, the memory controller 102 is configured to specify the total number of memory pages encompassed by the interval of memory pages. For example, if the cache memory address 112 is '5000' and the number of pages is '3', then, in that case, the mapping of the interval of memory pages will start at '5000' and include three sequentially arranged memory pages in the cache memory 106. The memory pages are stored in the cache memory 106 in a sequential order to ensure efficient data retrieval, allowing the memory controller 102 to access a continuous range of memory pages based on the starting address and the indicated number of pages. As a result, the memory controller 102 is configured to provide an organized, effective data management system, optimizing memory utilization and facilitating streamlined data access.

[0045] In accordance with an embodiment, the memory controller 102 is further configured to access a memory page in the cache memory 106 by retrieving a first memory address of a first page in the interval of memory pages, retrieving the ordering of the memory page to be accessed, and access the memory page to be accessed at a memory address equaling the first memory address adapted based on the ordering. Firstly, the memory controller 102 is configured to access a memory page in the cache memory 106 by retrieving the first memory address of the first page in the interval of memory pages. Thereafter, the memory controller 102 is configured to retrieve the ordering of the memory page to be accessed. Finally, the memory controller 102 is configured to access the memory page to be accessed at the memory address, equaling the first memory address adapted based on the ordering. In an implementation, the ordering of the memory pages refers to the number of memory pages that are included in the interval of memory pages. By accessing the memory pages to be accessed at the memory address equaling the first memory address adapted based on the ordering is used to ensure a systematic and ordered retrieval of the memory page within the cache memory 106, incorporating the specified order within the interval of memory pages. In accordance with an embodiment, the memory controller 102 is further configured to adapt the first memory address based on the ordering by adding a memory address offset equaling one memory page to the first memory address times the ordering. The first memory address offset corresponds to an additional value added to the memory address, which is used to locate the memory pages based on the ordering and the size of the one memory page. In other words, the memory controller 102 is configured to calculate the memory address offset by multiplying the ordering of the first memory page by the size of one memory page. Thereafter, the memory address offset is added to the retrieved first memory address of the first page within the interval of memory pages. Furthermore, the adapted memory address is utilized for accessing the required memory pages stored sequentially in the cache memory 106. As a result, the memory controller 102 is configured to ensure an optimized, precise, and systematic data retrieval with reduced latency.

[0046] In accordance with an embodiment, the memory controller 102 is further configured to indicate the cache memory address 112 of the first memory page and indicate the number of memory pages by storing the cache memory address 112 of the first memory page and the number of memory pages in a hash table and to resolve collisions utilizing chaining. The hash table corresponds to a data structure that is used to store a reference of the number of memory pages, such as by storing a collection of key-value pairs, where each key is unique, and the data associated with each key is stored in the form of a value. For example, the hash table stores the cache memory address 112 of the first memory page and the number of memory pages. Furthermore, the hash table is used to indicate the cache memory address 112 of the first memory page and the number of memory pages in order to resolve collisions utilizing chaining. Moreover, the chaining corresponds to a collision resolution technique, which is used to handle multiple key -value pairs having the same hash values, such as by linking the colliding entries together in a linked list within the hash table. As a result, the memory controller 102 is configured to manage and access memory pages efficiently and effectively with reduced overall processing time that is required for retrieving the data from the cache memory 106.

[0047] In accordance with an embodiment, each collision list cell of the hash table corresponds to the interval of memory pages. In an implementation, the collision list corresponds to a group of memory pages that have the same hash values in the hash table. For example, if two memory pages have the same hash, then, in that case, the corresponding memory pages are grouped together into one linked list called collision list. Moreover, each cell in the collision list corresponds to an interval of memory pages. As a result, the memory controller 102 is configured to maintain clarity and precision by grouping together each of the memory pages having the same hash values in order to handle collisions.

[0048] In accordance with an embodiment, the memory controller 102 is further configured to store an entry in the collision list for each interval of memory pages. Moreover, each entry includes an identifier for the backend storage 104 storing the memory pages, an identifier for the first memory page of the number of memory pages in the backend memory (1stcore line), an identifier for the first memory page of the number of memory pages in a cache memory (1stcache line), and the number of memory pages in the interval of memory pages. In an implementation, the identifier for the backend storage refers to a unique identifier specifying the backend storage 104 responsible for storing the memory pages in the designated interval, and the identifier for the first memory page in the backend memory (1stcore line) corresponds to an identifier that designates the first memory page within the specified interval in the backend memory. Moreover, the identifier for the first memory page in the backend memory (1stcore line) serves as a reference point for the beginning of the interval in the backend storage 104. Additionally, the identifier for the first memory page in the cache memory (1stcache line) corresponds to an identifier that points to the first memory page within the designated interval as stored in the cache memory 106 and serves as a reference point for the beginning of the interval in the cache memory 106. The memory controller 102 is configured to store entries in the collision list for each distinct interval of memory pages. Each entry encapsulates information, such as identifiers for the backend storage 104, the first memory page in both backend storage 104, and the cache memory 106, along with the total number of memory pages within the interval. Therefore, storing entries for each interval in a collision list allows the memory controller to efficiently manage and distinguish these overlapping intervals. For example, when a collision occurs, indicating that multiple intervals share the same hash value, the memory controller 102 is configured to create a collision list. For each unique interval involved in the collision, an entry is added to this list. Each entry includes identifiers for the backend storage 104, the first memory pages in both backend storage 104, and the cache memory 106, along with the total number of memory pages in the interval. As a result, the memory controller 102 is configured to provide efficient data retrieval, thereby contributing to an optimized memory operation.

[0049] In accordance with an embodiment, each entry further includes a reference counter, and the reference counter indicates the number of memory pages in the interval of memory pages that are currently active . The reference counter is used by the memory controller 102 to provide an insight into the active memory pages within the interval of memory pages, thereby optimizing the allocation and utilization of memory resources, ensuring that the active memory pages are prioritized while inactive ones may be subject to specific management actions, such as eviction or other optimization processes.

[0050] In accordance with an embodiment, the memory controller 102 is further configured to determine that a page in the interval of memory pages is to be evicted and in response thereto, reduce the reference count. In other words, the memory controller 102 is configured to identify when a memory page within the specified interval is scheduled for eviction. Thereafter, in response to such identification, the memory controller 102 is configured to reduce the reference count. As a result, by reducing the reference count, the memory controller 102 is configured to update the current status of the interval of memory pages for efficient identification and management of the memory pages that can be safely evicted without impacting any active processes or data retrieval requirements.

[0051] In accordance with an embodiment, the memory controller 102 is further configured to determine that the reference count equals 0 and, in response thereto, reassign the collision list cell in the hash table. In an implementation, if the reference count equals 0, then the memory controller 102 is configured to reassign the collision list cell in the hash table. In another implementation, if the reference count does not equal 0, then the memory controller 102 does not reassign the collision list cell in the hash table. Therefore, by reassigning the collision list cell for intervals with zero reference counts, the memory controller 102 is configured to ensure an efficient utilization of memory resources, thereby contributing to an effective and resourceconscious memory management system.

[0052] Advantageously, the memory controller 102 enables an optimized and efficient mapping of the interval of memory pages stored in the backend storage 104 and the interval of memory pages in the cache memory 106. The mapping of the interval of memory pages stored sequentially in the backend storage 104 to a corresponding interval of memory pages in the cache memory 106, the memory controller 102 is configured to streamline the data retrieval process with reduced overall data processing time and with reduced memory utilization. Furthermore, by indicating the cache memory address 112 of the first memory page and specifying the number of memory pages in the interval of the memory pages, the memory controller 102 is configured to reduce the mapping overhead that improves the overall performance of the memory controller 102 with reduced memory footprint. Additionally, the remaining memory, which is saved due to the mapping of the interval of memory pages of the backend storage 104 to the interval of the memory pages of the cache memory 106 can be used as additional cache pages or for the other machine tasks to speed up a data management system.

[0053] FIG. 2 is a flowchart depicting a method for a memory controller configured to map an interval of memory pages stored sequentially in a backend storage to an interval of memory pages in a cache memory, in accordance with an embodiment of the present disclosure. With reference to FIG. 2, there is shown a flowchart of a method 200 for the memory controller 102 configured to map an interval of memory pages stored sequentially in the backend storage 104 to an interval of memory pages in the cache memory 106. The method 200 includes steps 202 to 204.

[0054] There is provided the method 200 for a memory controller 102 for mapping an interval of memory pages stored sequentially in the backend storage 104 to an interval of memory pages in the cache memory 106. The memory controller 102 maps and manages the flow of data between the backend storage 104 and the cache memory 106 by mapping the interval of memory pages stored sequentially in the backend storage 104 to the interval of memory pages in the cache memory 106 to allow an efficient mapping and retrieval of the data, ensuring that a continuous range of memory pages is handled collectively as a unit. Additionally, by mapping the interval of memory pages, the memory controller 102 is configured to streamline the data accessibility operation, facilitating faster data retrieval from backend storage 104 to cache memory 106 with an improved overall performance of a system along with a reduced memory footprint.

[0055] In operation, at step 202, the method 200 includes mapping the interval of memory pages by indicating the cache memory address of the first memory page of the interval of memory pages and at step 204, the method 200 further includes mapping the interval of memory pages by indicating the number of memory pages in the interval of memory pages, wherein the interval of memory pages is stored sequentially in the cache memory. The cache memory address 112 corresponds to an address within the cache memory 106 where the mapping starts. Moreover, the cache memory address 112 is configured to point to the first memory page within the interval of memory pages. Firstly, the memory controller 102 is configured to point to the cache memory address 112 of the first memory page within the interval of memory pages. The cache memory address 112 is configured to serve as a starting point for the mapping of the interval of memory pages that are sequentially stored in the backend storage 104 to the interval of memory pages in the cache memory 106. Secondly, the memory controller 102 is configured to specify the total number of memory pages encompassed by the interval of memory pages. For example, if the cache memory address 112 is '5000' and the number of pages is '3', then, in that case, the mapping of the interval of memory pages will start at '5000' and include three sequentially arranged memory pages in the cache memory 106. The memory pages are stored in the cache memory 106 in a sequential order to ensure efficient data retrieval, allowing the memory controller 102 to access a continuous range of memory pages based on the starting address and the indicated number of pages. As a result, the memory controller 102 is configured to provide an organized and effective data management system, optimizing memory utilization, and facilitating streamlined data access.

[0056] Advantageously, the method 200 enables an optimized and efficient mapping of the interval of memory pages stored in the backend storage 104 and the interval of memory pages in the cache memory 106. The mapping of the interval of memory pages stored sequentially in the backend storage 104 to a corresponding interval of memory pages in the cache memory 106, the method 200 is further used to streamline the data retrieval process with reduced overall data processing time and with reduced memory utilization. Furthermore, by indicating the cache memory address 112 of the first memory page and specifying the number of memory pages in the interval of the memory pages, the method 200 is used to reduce the mapping overhead with reduced memory footprint. Additionally, the remaining memory, which is saved due to the mapping of the interval of memory pages of the backend storage 104 to the interval of the memory pages of the cache memory 106, can be used as additional cache pages or for the other machine tasks to speed up a data management system.

[0057] The steps 202 to 204 are only illustrative, and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

[0058] There is provided a computer program product comprising instructions that, when executed by a computer system, cause the computer system to implement the method 200. In an example, the instructions are implemented on the computer-readable media, which include, but are not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Random Access Memory (RAM), Read-Only Memory (ROM), Hard Disk Drive (HDD), Flash memory, a Secure Digital (SD) card, Solid-State Drive (SSD), a computer-readable storage medium, and / or CPU cache memory. In an example, the instructions are generated by a computer program, which is implemented in view of the method 200 for a memory system. FIG. 3 A is a diagram depicting an exemplary scenario for mapping an individual mapping of memory pages stored in a backend storage to an individual mapping of memory pages stored in a cache memory, in accordance with an embodiment of the present disclosure. FIG.3A is described in conjunction with elements from FIG. 1. With reference to FIG. 3 A, there is shown a diagram 300A that includes the mapping of individual memory pages stored in the backend storage 104 (i.e., the backend storage of FIG. 1) and the individual memory pages stored in the cache memory 106 (i.e., the cache memory 106 of FIG. 1).

[0059] In an exemplary scenario, the backend storage 104 includes a number of memory pages, such as the memory pages labelled as 'O', '1', '2', '3', '4', '5', '6', '7', '8', 9', '10', '11', '12', '13', '15', '16', '17' and '18'. Similarly, the cache memory 106 includes a number of memory pages, such as the memory pages labelled as 'O', '1', '2', '3', '4', '5', '6', '7', '8', and 9'. The metadata for the mapping (i.e., (Pc, Pc + 1, ..., Pc + n - 1) <-> (Pr, Pr + 1, ..., Pr + n - 1)) of each of the individual memory pages that are stored in the cache memory 106 to the individual memory pages that are stored in the backend storage 104 can be denoted by a pair of numbers (i.e., Pc + i, Pr + i), where 'i' ranges from 0 to n-1, for example, (2,9), (3,10), (4, 11), (5,12). In such representation, the first number (i.e., '2', '3', '4', and '5') in each metadata representation signifies the memory address of the mapped page in the cache memory 106 and the second number (i.e., '9', TO', 'l l', and '12') signifies the memory address of the corresponding memory pages in the backend storage 104. As a result, such representation of the metadata leads to an increase in the size of the metadata that adversely affects the memory space utilization.

[0060] FIG. 3B is a diagram depicting an exemplary scenario for mapping an interval of memory pages stored in a backend storage to an interval of memory pages stored in a cache memory, in accordance with an embodiment of the present disclosure. FIG.3B is described in conjunction with elements from FIG. 1 and FIG. 3 A. With reference to FIG. 3B, there is shown a diagram 300B that includes the interval of memory pages stored in the backend storage 104 (i.e., the backend storage of FIG. 1) and the interval of memory pages stored in the cache memory 106 (i.e., the cache memory 106 of FIG. 1).

[0061] In such an exemplary scenario, the interval of memory pages is represented by using three numbers (i.e., Pc, Pr, n), where the first number (i.e., '2') represents the first memory page of the interval of memory pages stored in the cache memory 106, the second number (i.e., '9') represents the first memory page of the interval of memory pages stored in the backend storage 104, and a third number (i.e., 4) represents the total number of memory pages in the interval of memory pages. As a result, the mapping of the interval of memory pages of the backend storage 104 to the interval of memory pages of the cache memory 106 reduces the metadata size without compromising on space efficiency.

[0062] FIG. 4 is a diagram that depicts a mapping structure of an interval of memory pages, in accordance with an embodiment of the present disclosure. FIG.4 is described in conjunction with elements from FIG. 1, FIG. 3 A, and FIG. 3B. With reference to FIG. 4, there is shown a diagram 400 that includes the mapping structure of the interval of memory pages.

[0063] In an implementation, the mapping structure of the interval of memory pages includes a core ID 402, a 1stcore line 404, a 1stCache line 406, a sequence length 408, and a reference counter 410. The open cache acceleration software (CAS) framework (OCF) cache system utilizes individual mappings (i.e., 1: 1 mapping) that are stored in a hash table. Moreover, the collision resolution is managed through chaining. Each individual mapping associates the 1stcache line 406 that represents a memory page stored in the cache memory 106. Furthermore, each of the individual mappings is also associated with the 1stcore line 404, which represents a memory page stored in the backend storage 104. The sequence length 408 represents the length of the interval of the memory pages, while the reference counter 410 indicates the number of memory pages in the interval of memory pages that are currently active. Additionally, the mapping structure also includes a previous node 412 and a next node 414. Furthermore, the hash table represents the entries that represent the mapping of the intervals of memory pages stored in the cache memory 106 to the interval of memory pages that are stored in the backend storage 104 in order to provide a unique approach for cache management with reduced memory space utilization. FIG. 5 is a diagram that depicts a mapping structure of a hash table of an interval of memory pages, in accordance with an embodiment of the present disclosure. FIG.5 is described in conjunction with elements from FIG. 1, FIG. 3A, FIG. 3B, and FIG. 4. With reference to FIG. 5, there is shown a diagram 500 that includes the mapping structure of the hash table of the interval of memory pages.

[0064] In an exemplary scenario, each entry of the hash table includes an identifier for the backend storage 104 storing the memory pages (i.e., the core ID 402), for example, '1', '1', '2', ‘ 1’, and the like. Furthermore, each entry of the hash table includes an identifier for the first memory page of the number of memory pages in the backend storage 104 (i.e., the 1stcore line 404), for example, '1000', '1003', '23', '1006', and the like. Moreover, each entry also includes an identifier for the first memory page of the number of memory pages in the cache memory 106 (i.e., the 1stcache line 406), for example, '50', '53', '5', '56', and the like, and the number of memory pages in the interval of memory pages (i.e., the sequence length 408) for example, '3', '3', '3', '3', and the like along with the reference counter 410, for example, '3', '3', '3', '3', and the like. However, each entry in a conventional hash table maps one cache line to one core line to increase the size of the metadata along with an increased memory space utilization as compared to the hash table as shown in the present disclosure that maps three cache lines to three core lines in order to reduce the size of the metadata with reduced memory space utilization. As a result, the memory controller 102 is configured to provide an optimized memory space utilization.

[0065] FIG. 6 is a diagram that depicts a metadata memory layout of an interval of memory pages, in accordance with an embodiment of the present disclosure. FIG.6 is described in conjunction with elements from FIG. 1, FIG. 3 A, FIG. 3B, FIG. 4, and FIG. 5. With reference to FIG. 6, there is shown a diagram 600 that includes the metadata memory layout of the interval of memory pages. Combined together, the different tables of this layout form a hash table. In an exemplary scenario, the metadata memory layout includes a list of nodes 602, a list of first nodes 604 that includes the list of the first nodes, such as a first node 602A of each collision list in a bucket, and a list of reverse mappings of the cache lines to nodes 606. The node list 602 includes the core ID 402, the 1stcore line 404, the 1stCache line 406, the sequence length 408, the reference counter 410, the previous node 412, and the next node 414. As a result, the metadata memory layout of the interval of memory pages requires 8-15 bytes per cache line, which reduces the overall memory utilization as compared to conventional data storage systems, which require at least 19 bytes per cache line. Therefore, the overall memory utilization and the overall performance of the memory controller 102 is improved with reduced data processing time.

[0066] Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe, and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be constmed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as "exemplary" is not necessarily to be constmed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

CLAIMS1. A memory controller (102) configured to map an interval of memory pages stored sequentially in a backend storage (104) to an interval of memory pages stored sequentially in a cache memory (106), wherein the memory controller (102) is configured to map the number of memory pages by indicating the cache memory address (112) of a first memory page of the interval of memory pages, and indicating the number of memory pages in the interval of memory pages, wherein the interval of memory pages is stored sequentially in the cache memory (106).

2. The memory controller (102) according to claim 1, wherein the memory controller (102) is further configured to access a memory page in the cache memory (102) by retrieving a first memory address of a first page in the interval of memory pages, retrieving the ordering of the memory page to be accessed, and access the memory page to be accessed at a memory address equalling the first memory address adapted based on the ordering.

3. The memory controller (102) according to claim 2, wherein the memory controller (102) is further configured to adapt the first memory address based on the ordering by adding a memory address offset equalling one memory page to the first memory address times the ordering.

4. The memory controller (102) according to any preceding claim, wherein the memory controller (102) is further configured to indicate the cache memory address of the first memory page and indicate the number of memory pages by storing the cache memory address (112) of the first memory page and the number of memory pages in a hash table and to resolve collisions utilizing chaining.

5. The memory controller (102) according to claim 4, wherein each bucket collision list cell of the hash table corresponds to the interval of memory pages.

6. The memory controller (102) according to claim 4 or 5, wherein the memory controller (102) is further configured to store an entry in a collision list for each interval of memory pages, wherein each entry comprises: an identifier for the computer core backend device accessing storing the memory pages, an identifier for the first memory page of the number of memory pages in the backend memory (1stcore line), an identifier for the first memory page of the number of memory pages in the cache memory (1stcache line), and the number of memory pages in the interval of memory pages.

7. The memory controller (102) according to claim 6, wherein each entry further comprises a reference counter, wherein the reference counter indicates the number of memory pages in the interval of memory pages is currently active.

8. The memory controller (102) according to claim 7, wherein the memory controller (102) is further configured to determine that a page in the interval of memory pages is to be evicted and in response thereto reduce the reference count.

9. The memory controller (102) according to claim 8, wherein the memory controller (102) is further configured to determine that the reference count equals 0 and in response thereto reassign the bucket collision list cell in the hash table.

10. The memory controller (102) according to any preceding claim, wherein the number of memory pages in an interval of memory pages is one or more.

11. The memory controller (102) according to claim 10, wherein the number of memory pages in an interval of memory pages is two or more.

12. A method (200) for a memory controller (102) for mapping an interval of memory pages stored sequentially in a backend storage (104) to an interval of memory pages in a cache memory (106), wherein the method (200) comprises mapping the interval of memory pages by indicating the cache memory address of a first memory page of the interval of memory pages, and indicating the number of memory pages in the interval of memory pages, wherein the interval of memory pages is stored sequentially in the cache memory (106).

13. A computer program product comprising program instructions for performing the method (200) according to claim 12, when executed by one or more processors in a memory system.

Images