Semiconductor device and semiconductor device manufacturing method

Abstract

Provided is a highly reliable semiconductor device. This semiconductor device includes a transistor. The transistor includes: a first insulation layer; a second insulation layer; an oxide semiconductor layer that is located between the first insulation layer and the second insulation layer and that has a portion in contact with the first insulation layer and a portion in contact with the second insulation layer; and a conductive layer overlapping the oxide semiconductor layer with the second insulation layer interposed therebetween. The first insulation layer has a function of supplying oxygen to the oxide semiconductor layer. The oxide semiconductor layer has an indium oxide film. The second insulation layer has a function of capturing either or both of oxygen and hydrogen from the oxide semiconductor layer. The concentration of gallium in a channel formation region of the oxide semiconductor layer is at most 0.1 atomic%.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first insulating layer, a second insulating layer, an oxide semiconductor layer located between the first insulating layer and the second insulating layer and having a portion in contact with the first insulating layer and a portion in contact with the second insulating layer, and a conductive layer overlapping with the oxide semiconductor layer with the second insulating layer sandwiched therebetween. The first insulating layer has a function of supplying oxygen to the oxide semiconductor layer. The oxide semiconductor layer includes an indium oxide film. The second insulating layer has a function of capturing oxygen and / or hydrogen from the oxide semiconductor layer. The concentration of gallium in a channel formation region of the oxide semiconductor layer is 0.1 atomic % or less.

[0014] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first insulating layer, a second insulating layer, an oxide semiconductor layer located between the first insulating layer and the second insulating layer and having a portion in contact with the first insulating layer and a portion in contact with the second insulating layer, and a conductive layer overlapping with the oxide semiconductor layer with the second insulating layer sandwiched therebetween. The first insulating layer includes a silicon oxide film. The oxide semiconductor layer includes an indium oxide film. The second insulating layer includes an aluminum oxide film or a hafnium oxide film. The concentration of gallium in a channel formation region of the oxide semiconductor layer is 0.1 atomic % or less.

[0015] In the semiconductor device, the concentration of gallium in the channel formation region of the oxide semiconductor layer is preferably measured by analysis using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA), or inductively coupled plasma mass spectrometry (ICP-MS).

[0016] In the above semiconductor device, the concentration of gallium in the first insulating layer is preferably 0.1 atomic % or less, and the concentration of gallium in the second insulating layer is preferably 0.1 atomic % or less.

[0017] In the above semiconductor device, the oxide semiconductor layer preferably has a region with a thickness of 2.5 nm to 20 nm.

[0018] In the above semiconductor device, the oxide semiconductor layer preferably has a crystalline part.

[0019] In the above semiconductor device, the oxide semiconductor layer preferably has a polycrystalline structure.

[0020] Another embodiment of the present invention is a method for manufacturing a semiconductor device including a first insulating layer, a second insulating layer, and an oxide semiconductor layer located between the first insulating layer and the second insulating layer, the oxide semiconductor layer having a portion in contact with the first insulating layer and a portion in contact with the second insulating layer. The first insulating layer is formed by an atomic layer deposition (ALD) method using a first precursor containing silicon and a first oxidant. The oxide semiconductor layer is formed by an ALD method using a second precursor containing indium and a second oxidant. The second insulating layer is formed by an ALD method using a third precursor containing aluminum or hafnium and a third oxidant.

[0021] In the above-described method for manufacturing a semiconductor device, it is preferable that after the oxide semiconductor layer is formed by a thermal ALD method, the second insulating layer be formed by a thermal ALD method in succession without exposure to the air.

[0022] In the method for manufacturing a semiconductor device, the purity of the source gas containing the second precursor is preferably 5N or more.

[0023] In the above-described method for manufacturing a semiconductor device, the second oxidizing agent preferably contains ozone.

[0024] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] 1A to 1F are cross-sectional views showing an example of a stacked structure. FIGS. 1G and 1H are perspective views showing an example of a stacked structure. FIGS. 2A and 2B are perspective views showing an example of a semiconductor device. FIGS. 3A1 and 3A2 are plan views showing an example of a semiconductor device. FIGS. 3B to 3D are cross-sectional views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A to 5C are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A1 and 9A2 are plan views showing an example of a semiconductor device. FIGS. 9B and 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIGS. 11A1 and 11A2 are plan views showing an example of a semiconductor device. FIGS. 11B to 11D are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIG. 14 is a cross-sectional view showing an example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIGS. 17A1 and 17A2 are plan views showing an example of a semiconductor device. FIGS. 17B to 17D are cross-sectional views showing an example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a plan view showing an example of a semiconductor device. FIGS. 19B to 19D are cross-sectional views showing an example of a semiconductor device. FIGS. 20A and 20B are cross-sectional views showing an example of a semiconductor device. FIG. 21A is a plan view showing an example of a semiconductor device. FIGS. 21B to 21D are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a plan view showing an example of a semiconductor device. FIGS. 22B to 22D are cross-sectional views showing an example of a semiconductor device. FIGS. 23A to 23C are cross-sectional views showing an example of a semiconductor device. FIG. 24A is a plan view showing an example of a semiconductor device. 24B to 24D are cross-sectional views showing an example of a semiconductor device, and Fig. 25 is a cross-sectional view showing an example of a semiconductor device.FIG. 26A is a plan view showing an example of a memory device. FIGS. 26B and 26C are cross-sectional views showing an example of a memory device. FIG. 27A is a plan view showing an example of a memory device. FIGS. 27B and 27C are cross-sectional views showing an example of a memory device. FIGS. 28A to 28C are cross-sectional views showing an example of a memory device. FIGS. 29A and 29B are cross-sectional views showing an example of a memory device. FIG. 30A is a plan view showing an example of a memory device. FIG. 30B is a cross-sectional view showing an example of a memory device. FIG. 31 is a cross-sectional view showing an example of a memory device. FIG. 32 is a cross-sectional view showing an example of a memory device. FIG. 33 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 34A to 34G are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 35A and 35B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 36 is a block diagram illustrating a CPU. FIGS. 37A and 37B are perspective views of a semiconductor device. FIGS. 38A and 38B are perspective views of a semiconductor device. FIGS. 39A and 39B are perspective views showing an example of a display device. FIG. 40 is a cross-sectional view showing an example of a display device. FIG. 41 is a cross-sectional view showing an example of a display device. FIGS. 42A to 42C are diagrams showing an example of the configuration of a display device. FIGS. 43A and 43B are diagrams showing an example of an electronic component. FIGS. 44A to 44C are diagrams showing an example of a mainframe computer. FIG. 44D is a diagram showing an example of space equipment. FIG. 44E is a diagram showing an example of a storage system applicable to a data center. FIGS. 45A to 45F are diagrams showing an example of electronic equipment. FIGS. 46A to 46G are diagrams showing an example of electronic equipment. FIGS. 47A to 47F are diagrams showing an example of electronic equipment. FIG. 48 is a diagram showing the optical absorption spectrum of a sample. FIGS. 49A1, 49A2, and 49A3 are diagrams showing cross-sectional TEM images of an oxide film, and FIGS. 49B1, 49B2, 49C1, and 49C2 are diagrams showing electron diffraction patterns in each region. FIGS. 50A and 50B are diagrams explaining the layered structure of a layered film. Figures 51A to 51C show the results of SIMS analysis of the fabricated sample. Figures 52A to 52C show the results of SIMS analysis of the fabricated sample. Figure 53 is a cross-sectional TEM image of the fabricated sample.54A to 54C show the results of SIMS analysis of the fabricated samples.

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0030] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0031] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0033] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0034] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0035] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0036] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0037] For example, SIMS, XPS, or ESCA can be used to analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in the film. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0038] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0039] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0040] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0041] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0042] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0044] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0045] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0046] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source potential is 0 V.

[0047] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0048] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0049] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0050] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0051] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0052] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0053] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0054] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0055] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0056] Embodiment 1 In this embodiment, a stacked layer structure included in a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 1H. FIG.

[0057] 1A illustrates a cross-sectional view of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. The stacked layer structure illustrated in FIG. 1A includes an insulating layer 20, an oxide semiconductor layer 30, an insulating layer 50, and a conductive layer 60. A transistor included in the semiconductor device of one embodiment of the present invention has the stacked layer structure.

[0058] The oxide semiconductor layer 30 is located between the insulating layer 20 and the insulating layer 50. The oxide semiconductor layer 30 has a portion in contact with the insulating layer 20 and a portion in contact with the insulating layer 50.

[0059] The conductive layer 60 has a portion overlapping with the oxide semiconductor layer 30 with the insulating layer 50 sandwiched therebetween.

[0060] In the transistor according to one embodiment of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The oxide semiconductor layer 30 has a channel formation region. The oxide semiconductor layer 30 has a region that overlaps with the conductive layer 60 with the insulating layer 50 interposed therebetween. At least part of the region functions as the channel formation region of the transistor.

[0061] The transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide semiconductor layer 30 including a channel formation region. That is, the transistor can be referred to as an OS transistor.

[0062] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. ＯH) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0063] Furthermore, when an excessive amount of oxygen is supplied to the oxide semiconductor layer 30, electron traps due to the excess oxygen are formed in the insulating layer 50. As a result, the OS transistor is more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0064] Furthermore, when the oxide semiconductor layer 30 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor having an oxide semiconductor layer 30 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a positive bias temperature stress (PBTS) test.

[0065] Therefore, in the semiconductor device of one embodiment of the present invention, the hydrogen concentration in the oxide semiconductor layer 30 is preferably low. An appropriate amount of oxygen is preferably supplied to the oxide semiconductor layer 30. An excessive amount of oxygen in the oxide semiconductor layer 30 is preferably reduced. The gallium content in the oxide semiconductor layer 30 is preferably low. Furthermore, the gallium content in a layer in contact with the oxide semiconductor layer 30 is preferably low.

[0066] Indium oxide is preferably used as the metal oxide used for the oxide semiconductor layer 30. For example, the oxide semiconductor layer 30 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the oxide semiconductor layer 30, the transistor can have a large on-state current and high frequency characteristics.

[0067] Indium oxide has a band gap of 2.5 eV or more. By using indium oxide with a wide band gap for the oxide semiconductor layer 30, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0068] Indium oxide is a metal oxide that does not contain gallium or has a low gallium content. By using such a metal oxide for the oxide semiconductor layer 30, the amount of variation in threshold voltage in a PBTS test can be reduced. Therefore, a transistor with high reliability when a positive bias is applied can be obtained.

[0069] For example, the concentration of gallium in the oxide semiconductor layer 30 obtained by analysis using ICP-MS is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0070] The method for evaluating the gallium concentration is not limited to ICP-MS. The gallium concentration can be evaluated using, for example, XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), inductively coupled plasma atomic emission spectroscopy (ICP-AES), or the like.

[0071] Furthermore, the aluminum concentration in the oxide semiconductor layer 30 is preferably low. Reducing the aluminum concentration in the oxide semiconductor layer 30 can improve the crystallinity of the oxide semiconductor layer 30. The aluminum concentration in the oxide semiconductor layer 30 is, for example, preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0072] The thickness of the oxide semiconductor layer 30 is preferably 1.5 nm to 50 nm, more preferably 2 nm to 50 nm, still more preferably 2.5 nm to 30 nm, and even more preferably 2.5 nm to 20 nm. It is sufficient that at least a portion of the oxide semiconductor layer 30 has a region with the above-described thickness. For example, the channel formation region of the oxide semiconductor layer 30 may have a region with the above-described thickness.

[0073] Setting the film thickness of the oxide semiconductor layer 30 within the above range can improve the crystallinity of the oxide semiconductor layer 30. By improving the crystallinity of the oxide semiconductor layer 30, the oxide semiconductor layer 30 can have a crystalline portion. In particular, when indium oxide is used for the oxide semiconductor layer 30, the oxide semiconductor layer 30 can have a polycrystalline structure. When the oxide semiconductor layer 30 has a polycrystalline structure, oxygen and hydrogen may diffuse through crystal grain boundaries within the polycrystalline structure.

[0074] When a metal oxide contains indium and zinc, the metal oxide may have a high crystallinity, for example, a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0075] Therefore, in the film thickness range, the indium oxide film is a film through which hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that the indium oxide film is a film through which hydrogen and oxygen are more easily supplied and from which hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Furthermore, it can be said that the indium oxide film is a film that is more permeable to hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that the indium oxide film is a film that has a lower barrier property against hydrogen and oxygen than, for example, an IGZO film.

[0076] The crystallinity of the oxide semiconductor layer 30 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these techniques may be used for analysis.

[0077] The insulating layer 20 preferably has a function of supplying oxygen to the oxide semiconductor layer 30. The insulating layer 20 preferably has a region containing oxygen that is desorbed by heating (hereinafter, sometimes referred to as excess oxygen), for example. When an insulating layer having a region containing excess oxygen is in contact with the oxide semiconductor layer 30, oxygen can be supplied to the oxide semiconductor layer 30. The oxygen supplied to the oxide semiconductor layer 30 repairs oxygen vacancies, thereby reducing the amount of oxygen vacancies in the oxide semiconductor layer 30. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film having vacancies.

[0078] The insulating layer 50 preferably has a function of capturing or fixing (also referred to as gettering) oxygen. As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, when the insulating layer 50 has the function of capturing or fixing oxygen, excess oxygen in the oxide semiconductor layer 30 can diffuse into the insulating layer 50 and the oxygen can be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by excess oxygen. Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate). Examples of insulating layers having a function of capturing or fixing oxygen include an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film.

[0079] Note that an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, when the insulating layer 50 has the function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 30 diffuses into the insulating layer 50, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 30 can be reduced.

[0080] Furthermore, the gallium content in each of the insulating layer 20 and the insulating layer 50 is preferably low, and each of the insulating layer 20 and the insulating layer 50 preferably does not contain gallium. For example, the gallium concentration in each of the insulating layer 20 and the insulating layer 50 obtained by analysis using ICP-MS is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. With such a configuration, it is possible to suppress the incorporation of gallium into the oxide semiconductor layer 30 and improve the reliability of the transistor.

[0081] The configuration in which the insulating layer 20 and the insulating layer 50 each have a low gallium content can be rephrased as a configuration in which the gallium content is low at the interface between the oxide semiconductor layer 30 and the insulating layer 20 and in the vicinity thereof, and at the interface between the oxide semiconductor layer 30 and the insulating layer 50 and in the vicinity thereof, a configuration in which gallium is not contained on the front and back sides of the oxide semiconductor layer 30, or a configuration in which the oxide semiconductor layer 30 is not in contact with an insulating layer containing gallium, etc.

[0082] The conductive layer 60 is preferably made of a highly conductive material such as tungsten. Furthermore, it is also preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 60. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can prevent the conductivity of the conductive layer 60 from decreasing.

[0083] The conductive layer 60 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) may be used. Alternatively, one or more selected from indium tin oxide (In—Sn oxide, also referred to as ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and indium tin oxide containing silicon oxide (also referred to as ITSO) may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0084] 1A shows an example in which the oxide semiconductor layer 30 has a single layer structure. The oxide semiconductor layer 30 can have a stacked structure of two or more layers. FIG. 1B shows an example in which the oxide semiconductor layer 30 has a two-layer structure of an oxide semiconductor layer 30a and an oxide semiconductor layer 30b on the oxide semiconductor layer 30a.

[0085] 1B , it is preferable that the oxide semiconductor layer 30a is made of a metal oxide (typically indium oxide) applicable to the oxide semiconductor layer 30 described above, and that the oxide semiconductor layer 30b in contact with the insulating layer 50 is made of a material having high oxygen permeability. With this configuration, excess oxygen in the oxide semiconductor layer 30a can be discharged to the insulating layer 50.

[0086] Note that reducing the thickness of the oxide semiconductor layer 30b increases the oxygen permeability of the oxide semiconductor layer 30b. Therefore, the same effect can be achieved even when the thickness of the oxide semiconductor layer 30b is reduced. The thickness of the oxide semiconductor layer 30b is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and even more preferably 0.1 nm to 0.5 nm.

[0087] Examples of metal oxides that can be used for the oxide semiconductor layer 30b include In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), and ITSO. Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0088] Specifically, the In-Zn oxide used in the oxide semiconductor layer 30b can have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0089] The crystallinity of the metal oxide contained in the oxide semiconductor layer 30b is not particularly limited. For example, the oxide semiconductor layer 30b may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0090] 1C , the oxide semiconductor layer 30 can have a two-layer structure including an oxide semiconductor layer 30 b and an oxide semiconductor layer 30 a on the oxide semiconductor layer 30 b. With this structure, oxygen can be supplied to the oxide semiconductor layer 30.

[0091] 1A shows an example in which the insulating layer 20 has a single layer structure. The insulating layer 20 can have a stacked structure of two or more layers. When the insulating layer 20 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically silicon oxide) applicable to the insulating layer 20 described above as a layer in contact with the oxide semiconductor layer 30 among the two or more layers included in the insulating layer 20. With such a structure, oxygen can be supplied to the oxide semiconductor layer 30.

[0092] Of the two or more layers included in the insulating layer 20, the layer in contact with the oxide semiconductor layer 30 preferably has a low gallium content.

[0093] Of the two or more layers included in the insulating layer 20, the layer that is not in contact with the oxide semiconductor layer 30 can be formed using an insulating material described in the "Insulating Layer" section below.

[0094] As shown in FIG. 1D , the insulating layer 20 can have a two-layer structure of an insulating layer 20a and an insulating layer 20b on the insulating layer 20a. That is, the stacked structure shown in FIG. 1D has an insulating layer 20b between the insulating layer 20a and the oxide semiconductor layer 30. The insulating layer 20a can be made of an insulating material (typically, silicon oxide) that can be used for the insulating layer 20 described above. In this case, it is preferable that the insulating layer 20b has high oxygen permeability. In other words, it is preferable that the insulating layer 20b has low oxygen barrier properties. With this configuration, oxygen contained in the insulating layer 20a can be supplied to the oxide semiconductor layer 30.

[0095] Note that reducing the thickness of the insulating layer 20b increases the oxygen permeability of the insulating layer 20b. Therefore, the same effect can be achieved even when the thickness of the insulating layer 20b is reduced. The thickness of the insulating layer 20b is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and even more preferably 0.1 nm to 0.5 nm. In this case, the insulating layer 20b can be made of an insulating material described in the "Insulating Layer" section below. However, it is preferable that the gallium content of the insulating layer 20b be low.

[0096] FIG. 1A shows an example in which the insulating layer 50 has a single-layer structure. Note that the insulating layer 50 can have a stacked structure of two or more layers. When the insulating layer 50 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically, aluminum oxide) applicable to the insulating layer 50 described above as a layer in contact with the oxide semiconductor layer 30 among the two or more layers included in the insulating layer 50. With such a structure, excess oxygen in the oxide semiconductor layer 30 can be discharged to the insulating layer 50. Furthermore, hydrogen in the oxide semiconductor layer 30 can be captured or fixed.

[0097] Of the two or more layers included in the insulating layer 50, the layer in contact with the oxide semiconductor layer 30 preferably has a low gallium content.

[0098] Of the two or more layers included in the insulating layer 50, the layer that is not in contact with the oxide semiconductor layer 30 can be formed using an insulating material described in the "Insulating Layer" section below.

[0099] As shown in FIG. 1E , the insulating layer 50 can have a two-layer structure including an insulating layer 50b and an insulating layer 50a on the insulating layer 50b. That is, the stacked structure shown in FIG. 1E has the insulating layer 50b between the oxide semiconductor layer 30 and the insulating layer 50a. The insulating layer 50a can be made of an insulating material (typically, aluminum oxide) that can be used for the insulating layer 50. In this case, the insulating layer 50b preferably has high oxygen permeability. In other words, the insulating layer 50b preferably has low oxygen barrier properties. With this structure, excess oxygen in the oxide semiconductor layer 30 can diffuse into the insulating layer 50a and be captured or fixed.

[0100] Furthermore, it is preferable that the insulating layer 50b has high hydrogen permeability. In other words, it is preferable that the insulating layer 50b has low hydrogen barrier properties. With this configuration, hydrogen in the oxide semiconductor layer 30 diffuses into the insulating layer 50a, and the hydrogen can be captured or fixed.

[0101] Note that reducing the thickness of the insulating layer 50b increases the oxygen and hydrogen permeability of the insulating layer 50b. Therefore, the same effect can be achieved even when the thickness of the insulating layer 50b is reduced. The thickness of the insulating layer 50b is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and even more preferably 0.1 nm to 0.5 nm. In this case, the insulating layer 50b can be made of an insulating material described in the "Insulating Layer" section below. However, it is preferable that the gallium content of the insulating layer 50b be low.

[0102] As described above, oxygen is pushed into the oxide semiconductor layer 30 from the insulating layer 20 side, reducing the amount of oxygen vacancies in the oxide semiconductor layer 30, and excess oxygen in the oxide semiconductor layer 30 is pulled from the insulating layer 50 side, reducing the amount of excess oxygen in the oxide semiconductor layer 30. Therefore, a semiconductor device with excellent reliability can be provided.

[0103] 1A shows a configuration in which the insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 are stacked in a direction perpendicular or substantially perpendicular to the substrate surface (not shown). However, the present invention is not limited to this. For example, as shown in FIG. 1F, the insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be stacked in a direction parallel or substantially parallel to the substrate surface (not shown).

[0104] 1G , for example, the insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be provided concentrically. Note that FIG. 1G is a perspective view in which a part of the stacked layer structure of one embodiment of the present invention is cut away.

[0105] 1H , for example, an opening can be provided in the insulating layer 20, and the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be provided concentrically in the opening. Note that FIG. 1H is a perspective view in which a part of the stacked layer structure of one embodiment of the present invention is cut away.

[0106] [Example of Method for Forming Stacked Layer Structure] The insulating layer 20, the oxide semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. In particular, the insulating layer 20, the oxide semiconductor layer 30, and the insulating layer 50 are preferably formed by an ALD method.

[0107] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or recesses with high aspect ratios.

[0108] Some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Quantitative determination of these elements can be performed using XPS or SIMS. When the ALD method is used, the amount of carbon and chlorine contained in the film may be lower by adopting a high substrate temperature during film formation and / or by performing an impurity removal process, compared to when the ALD method is used without these procedures.

[0109] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0110] In a film forming apparatus using the ALD method, a first source gas (sometimes called a precursor, precursor, or metal precursor) and a second source gas (sometimes called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction are alternately introduced into a chamber, and film formation is performed by repeating the introduction of these source gases. Note that the introduction of the source gases can be switched by, for example, switching the respective switching valves (sometimes called high-speed valves). In addition, when introducing the source gases, nitrogen (N ２ An inert gas such as argon (Ar), argon (Ar), or helium (He) may be introduced into the chamber together with the source gas as a carrier gas. By using a carrier gas, even if the source gas has low volatility or a low vapor pressure, it is possible to suppress the source gas from being adsorbed inside the piping and the valve, and to introduce the source gas into the chamber. This also improves the uniformity of the film formed, which is preferable.

[0111] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0112] First, an insulating layer 20 is formed on a structure (not shown). That is, the structure includes a surface on which the insulating layer 20 is to be formed. The surface may have a flat shape, or may have a convex portion, a convex curved surface, a concave curved surface, a recess, an opening, or the like. For example, when the surface has a flat shape, the layered structure shown in FIG. 1A can be formed. Furthermore, when the surface has an opening that is circular in a plan view, the layered structure shown in FIG. 1G can be formed inside the opening.

[0113] The insulating layer 20 is preferably formed using an ALD method. A first precursor and a first oxidizing agent can be used to form the insulating layer 20. The first precursor preferably contains silicon. In this case, a silicon oxide film is formed as the insulating layer 20. That is, an oxide film containing a single element other than oxygen is formed. Note that when the first precursor contains silicon, a PEALD method can be used as the ALD method.

[0114] Examples of the silicon-containing precursor that can be used include trisilylamine, bis(diethylamino)silane, tris(dimethylamino)silane, bis(tert-butylamino)silane, and bis(ethylmethylamino)silane.

[0115] As the first oxidant, ozone (O ３ ), oxygen (O ２ ), water (H ２ By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidizing agent, the amount of hydrogen that gets mixed into the insulating layer 20 can be reduced.

[0116] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0117] The insulating layer 20 can be formed by sputtering in an atmosphere containing oxygen. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 20 can be reduced. Furthermore, by forming the insulating layer 20 by sputtering in an atmosphere containing oxygen, oxygen can be added to the insulating layer 20. Oxygen is supplied from the insulating layer 20 to the channel formation region of the oxide semiconductor layer 30 by heat or the like applied after the formation of the oxide semiconductor layer 30, and oxygen vacancies and V Ｏ H can be reduced.

[0118] Heat treatment is preferably performed before forming the oxide semiconductor layer 30. The heat treatment is performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0119] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 20 or the like can be reduced before the formation of the oxide semiconductor layer 30.

[0120] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 20 and the like as much as possible.

[0121] Furthermore, it is preferable to perform a process of supplying oxygen before forming the oxide semiconductor layer 30. As a result, oxygen is supplied to the insulating layer 20, and oxygen can be supplied from the insulating layer 20 to the oxide semiconductor layer 30 by heat or the like applied after the formation of the oxide semiconductor layer 30.

[0122] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 20 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately after deposition or may be left as it is. In the case where the deposited oxide film is left as it is, the oxide film can be used as part of the oxide semiconductor layer 30. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0123] Furthermore, an opening may be formed in the insulating layer 20 before depositing the oxide semiconductor layer 30. By forming the opening, the stacked structure shown in FIG. 1H can be formed.

[0124] Next, the oxide semiconductor layer 30 is formed on the insulating layer 20. The oxide semiconductor layer 30 is preferably formed by ALD. A second precursor and a second oxidizing agent can be used to form the oxide semiconductor layer 30. The second precursor preferably contains indium. In this case, an indium oxide film is formed as the oxide semiconductor layer 30. That is, an oxide film containing a single element other than oxygen is formed. Note that when the second precursor contains indium, a thermal ALD method can be used as the ALD method.

[0125] It is preferable to use a source gas with a low impurity concentration, i.e., a high purity, in the method for forming the oxide semiconductor layer 30. For example, by using a source gas with a purity of 3N (99.9%) or more, preferably 4N (99.99%) or more, more preferably 5N (99.999%) or more, and even more preferably 6N (99.9999%) or more, the impurities in the oxide semiconductor layer 30 can be reduced.

[0126] The gallium content in the source gas containing the indium-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a source gas with a low gallium content, it is possible to form an oxide semiconductor layer 30 with a low gallium concentration.

[0127] Furthermore, the aluminum content in the source gas containing the indium-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a source gas with a low aluminum content, the aluminum concentration in the oxide semiconductor layer 30 can be reduced, and the crystallinity of the oxide semiconductor layer 30 can be improved.

[0128] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0129] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0130] The second oxidizing agent preferably contains ozone. Note that the above-described materials that can be used for the first oxidizing agent can be used for the second oxidizing agent. By using ozone, oxygen, or the like that does not contain hydrogen as the second oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer 30 can be reduced.

[0131] Here, the temperature to which the substrate is heated when the second precursor is introduced into the reaction chamber is defined as a first temperature, and the temperature to which the substrate is heated when the second oxidizing agent is introduced into the reaction chamber is defined as a second temperature.

[0132] The first temperature is preferably a temperature corresponding to the decomposition temperature of the second precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, the first temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0133] Note that the second temperature is preferably higher than the first temperature. For example, when the second oxidant contains ozone, the second temperature is preferably higher than 200° C. and lower than 450° C., more preferably higher than or equal to 250° C. and lower than or equal to 400° C., and further preferably higher than or equal to 300° C. and lower than or equal to 350° C. With such a configuration, the hydrogen concentration in the oxide semiconductor layer can be reduced. Furthermore, by setting the first temperature lower than the second temperature, particles generated by decomposition of the second precursor can be suppressed.

[0134] It is preferable that the reaction chamber into which the second precursor is introduced and the reaction chamber into which the second oxidizing agent is introduced are the same. This configuration allows for film formation without the need to load and unload the substrate, thereby improving productivity. It is also possible to use different reaction chambers for the introduction of the second precursor and the introduction of the second oxidizing agent. By providing a first reaction chamber set to the first temperature and a second reaction chamber set to the second temperature, the first temperature and the second temperature can be maintained, respectively. This facilitates temperature control, improving work efficiency and safety.

[0135] Note that the oxide semiconductor layer 30 can be formed by a sputtering method in an atmosphere containing oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in a deposition gas, the hydrogen concentration in the oxide semiconductor layer 30 can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas may be used as a sputtering gas.

[0136] The oxide semiconductor layer 30 can be formed by, for example, a sputtering method or an ALD method. For example, when the oxide semiconductor layer 30 has a two-layer structure, the lower layer may be formed by a sputtering method and the upper layer may be formed by an ALD method. An oxide semiconductor layer formed by a sputtering method is likely to have crystallinity. Therefore, by providing a crystalline oxide semiconductor layer as the lower layer, the crystallinity of the upper layer can be improved. Furthermore, even if pinholes or discontinuities are formed in the lower layer formed by a sputtering method, the overlapping portions can be blocked by the upper layer formed by an ALD method, which has good coverage.

[0137] Alternatively, for example, when the oxide semiconductor layer 30 has a two-layer structure, the lower layer may be deposited by the ALD method and the upper layer may be deposited by the sputtering method. Since the ALD method is a film deposition method with superior coverage compared to the sputtering method, depositing the lower layer by the ALD method can improve the coverage of the oxide semiconductor layer 30. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio. Furthermore, depositing the upper layer by the sputtering method can improve productivity. Furthermore, an oxide semiconductor layer 30 with high crystallinity or high film density can be formed.

[0138] After the oxide semiconductor layer 30 is formed, a process of supplying oxygen to the oxide semiconductor layer 30 may be performed. This allows oxygen to be supplied to the oxide semiconductor layer 30 by heat or the like applied after this process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0139] Next, heat treatment is preferably performed. By performing the heat treatment, impurities such as hydrogen or water contained in the oxide semiconductor layer 30 can be reduced. The temperature of the heat treatment is preferably 100° C. to 650° C., more preferably 250° C. to 600° C., and still more preferably 300° C. to 500° C. or 350° C. to 550° C. For details of the heat treatment, refer to the above description.

[0140] The gas used in the heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 30 as much as possible.

[0141] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 30. Reducing the impurities in the film in this manner improves the crystallinity of the oxide semiconductor layer 30, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor layer 30, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 30. This reduces in-plane variations in the electrical characteristics of the transistor.

[0142] In addition, in the case where the insulating layer 20 contains oxygen, the heat treatment preferably supplies oxygen from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 30. As a result, oxygen vacancies and V Ｏ H can be reduced.

[0143] Note that microwave plasma treatment may be performed after the formation of the oxide semiconductor layer 30. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 30 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 30 may grow.

[0144] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0145] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 30 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the oxide semiconductor layer.

[0146] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0147] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0148] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋ ) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0149] The shorter the processing time of the microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably from 1 minute to 60 minutes, more preferably from 1 minute to 30 minutes, and even more preferably from 1 minute to 10 minutes.

[0150] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0151] Furthermore, a reaction occurs between part of oxygen present in the oxide semiconductor before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0152] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0153] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0154] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0155] In this manner, it is possible to reduce impurities in the oxide semiconductor layer 30. Furthermore, it is possible to improve the crystallinity of the oxide semiconductor layer 30.

[0156] Subsequently, the insulating layer 50 is formed on the oxide semiconductor layer 30. The insulating layer 50 is preferably formed by ALD. A third precursor and a third oxidizing agent can be used to form the insulating layer 50. The third precursor preferably contains one of aluminum and hafnium. In this case, an aluminum oxide film or a hafnium oxide film is formed as the insulating layer 50. In other words, an oxide film containing a single element other than oxygen is formed. Note that when the third precursor contains one of aluminum and hafnium, a thermal ALD method can be used as the ALD method.

[0157] Examples of precursors that can be used include aluminum chloride and trimethylaluminum, and examples of precursors that can be used include hafnium tetrachloride and tetrakis(ethylmethylamido)hafnium (TEMAHf).

[0158] The third oxidizing agent may be any of the materials that can be used for the first oxidizing agent.

[0159] In the ALD process, a precursor is introduced into a chamber and adsorbed onto the substrate surface. The adsorption of the precursor onto the substrate surface activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the precursor layer on the substrate. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors. In other words, the ALD window varies depending on the precursor. Therefore, when depositing an oxide film containing multiple elements other than oxygen, it is necessary to adjust the film formation conditions taking into account the ALD window of each precursor. On the other hand, when depositing an oxide film containing a single element other than oxygen, such as indium oxide or aluminum oxide, the film formation conditions can be adjusted by considering only the ALD window of one precursor, which facilitates the adjustment of the film formation conditions and allows for the formation of a high-quality oxide film.

[0160] The first oxidizing agent, the second oxidizing agent, and the third oxidizing agent may all be the same oxidizing agent, or at least one of them may be a different oxidizing agent.

[0161] Furthermore, when the insulating layer 20 and the oxide semiconductor layer 30 are formed using the same film formation method, it is preferable to form the insulating layer 20 and the oxide semiconductor layer 30 consecutively without exposing them to the atmosphere. Alternatively, when the oxide semiconductor layer 30 and the insulating layer 50 are formed using the same film formation method, it is preferable to form the oxide semiconductor layer 30 and the insulating layer 50 consecutively without exposing them to the atmosphere. Alternatively, when the insulating layer 20, the oxide semiconductor layer 30, and the insulating layer 50 are formed using the same film formation method, it is preferable to form the insulating layer 20, the oxide semiconductor layer 30, and the insulating layer 50 consecutively without exposing them to the atmosphere. By forming two or more types of films consecutively without exposing them to the atmosphere, it is possible to increase productivity. Furthermore, it is possible to reduce impurities (typically moisture, etc.) that are introduced into the interface between the two types of films and its vicinity.

[0162] As an example, it is preferable to form the oxide semiconductor layer 30 by thermal ALD, and then continuously form the insulating layer 50 by thermal ALD without exposing the process to the atmosphere. In this case, by using the same oxidizing agent for the second oxidizing agent and the third oxidizing agent and using a reaction chamber into which the second precursor and the third precursor can be introduced, the oxide semiconductor layer 30 and the insulating layer 50 can be formed without carrying in and out the substrate, thereby improving productivity.

[0163] Microwave plasma treatment is preferably performed after the insulating layer 50 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 30 can be reduced. For details of the microwave plasma treatment, refer to the above description.

[0164] Subsequently, the conductive layer 60 is formed on the insulating layer 50 .

[0165] In this manner, the stacked structure of one embodiment of the present invention can be manufactured.

[0166] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0167] Embodiment 2 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0168] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 2A to 18B. FIG.

[0169] 2A and 2B are schematic perspective views of a semiconductor device having a transistor 200. Fig. 2B is a perspective view in which a part of Fig. 2A is cut away. In Fig. 2A and 2B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0170] 2A and 2B, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both FIGS. 2A and 2B, the directions do not necessarily have to match.

[0171] FIG. 3A1 is a plan view of a semiconductor device having a transistor 200. FIG. 3A2 is a plan view showing an example in which a plurality of transistors 200 are arranged. FIG. 3B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 3A1. FIG. 3C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 3A1. FIG. 3D is a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 3C. Note that some elements are omitted in the plan views of FIGS. 3A1 and 3A2 for clarity. Some elements may also be omitted in the subsequent plan views.

[0172] 4A is a cross-sectional view taken along dashed lines A3-A4 in FIG. 3A1. FIG. 4B is a cross-sectional view taken along dashed lines A5-A6 in FIG. 3C. FIG. 4A and FIG. 4B correspond to examples of enlarged views of FIG. 3C and FIG. 3D, respectively.

[0173] The semiconductor device shown in FIGS. 3A1 to 3D includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0174] [Transistor 200] The transistor 200 includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is located over the conductive layer 220.

[0175] 3B and 3C show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1, and the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1.

[0176] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode. The conductive layer 260 has a region that functions as a gate wiring.

[0177] In the transistor 200, the source electrode and the drain electrode are located at different heights, and a current flows in the height direction of the oxide semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0178] The oxide semiconductor layer 230, the insulating layer 280, the insulating layer 250, and the conductive layer 260 included in the transistor 200 correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 280, the insulating layer 250, and the conductive layer 260.

[0179] As shown in FIGS. 3B and 3C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0180] The openings 290 include an opening in the insulating layer 280 and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the top surface shape of the openings 290 is circular, the openings in each layer may or may not be concentric.

[0181] The oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each arranged so that at least a portion thereof is located within the opening 290. Furthermore, the portions of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are arranged within the opening 290 are provided so as to reflect the shape of the opening 290.

[0182] The oxide semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290. The oxide semiconductor layer 230 has a recess that reflects the shape of the opening 290. The oxide semiconductor layer 230 has a portion that contacts the top surface of the conductive layer 240 and a portion that contacts the top surface of the conductive layer 220 within the opening 290.

[0183] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230 and the side surfaces of the conductive layer 240. The insulating layer 250 has a recess that reflects the shape of the recess that the oxide semiconductor layer 230 has.

[0184] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. In addition, the conductive layer 260 has a region in the opening 290 that overlaps with the oxide semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0185] The oxide semiconductor layer 230 has a region overlapping with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200. One of a region of the oxide semiconductor layer 230 near the conductive layer 220 and a region of the oxide semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0186] The oxide semiconductor layer 230 is provided inside the opening 290. The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, and thus current flows vertically. That is, a channel is formed along the sidewall of the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.

[0187] The transistor 200 includes a metal oxide functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0188] As shown in FIG. 4A , the conductive layer 220 has a recess overlapping the opening 290. Specifically, the recess is provided in the conductive layer 220_2 at a position overlapping the opening 290. By having the recess overlapping the opening 290 in the conductive layer 220_2, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0189] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220_2. The recessed portion in the conductive layer 220_2 can increase the area where the oxide semiconductor layer 230 and the conductive layer 220_2 are in contact with each other. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0190] 3B shows a structure in which the end of the conductive layer 240 and the end of the oxide semiconductor layer 230 are aligned or substantially aligned outside the opening 290. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing a semiconductor device can be reduced. Note that the present invention is not limited to this. For example, a structure may be possible in which any one of the end of the oxide semiconductor layer 230, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0191] The conductive layer 240 is preferably not located inside the opening 290. That is, the conductive layer 240 preferably does not have a region in contact with the side surface of the insulating layer 280 inside the opening 290. With this configuration, the opening 290 can be formed in the conductive layer 240 and the insulating layer 280 at the same time. Furthermore, if the side surface of the conductive layer 240 and the side surface of the insulating layer 280 are aligned or substantially aligned inside the opening 290, the film thickness distribution of the oxide semiconductor layer 230 and the like provided inside the opening 290 can be made uniform. Furthermore, the oxide semiconductor layer 230 and the like can be prevented from being divided by a step or the like between the conductive layer 240 and the insulating layer 280.

[0192] 3A2 shows an example in which a plurality of transistors 200 are arranged in a matrix. Specifically, FIG. 3A2 shows an example in which 4×4 transistors are arranged in the X and Y directions. As shown in FIG. 3A2, the transistor 200 is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 3A2, the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200 can be said to have a structure that allows for high integration and miniaturization.

[0193] As shown in FIG. 4B , by forming the opening 290 to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 provided at the center of the opening 290 faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the periphery length of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 4A and 4B , the width D of the opening 290 is shown, and in FIG. 4B , the channel width W of the transistor 200 is shown.

[0194] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200, thereby enabling a semiconductor device to be highly integrated.

[0195] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening at the highest position in the conductive layer 240, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 is determined using the width of the opening in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening side may be used as the width D. Alternatively, the width of the opening at the highest position in the insulating layer 280, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D of the opening 290.

[0196] When the opening 290 is formed using photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. The width D of the opening 290 is set depending on the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0197] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, the channel length of the transistor 200 can be determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 4A , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. Note that the channel length L can be considered as the distance between the edge of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0198] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0199] Note that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 over the conductive layer 220, and therefore the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. Setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0200] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and 1 μm or less, 500 nm or less, or 300 nm or less.

[0201] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0202] As described above, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, allowing a gate electric field to be applied to the oxide semiconductor layer 230 approximately uniformly.

[0203] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0204] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0205] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0206] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0207] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0208] 4A shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0209] The insulating layer 250 is in contact with the oxide semiconductor layer 230 and therefore preferably has a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0210] 4A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the oxide semiconductor layer 230, a function of extracting hydrogen from the oxide semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0211] 5A to 5C are enlarged views of the insulating layer 250 and its vicinity, which are also enlarged views of the region P surrounded by the dashed line in FIG. 4A.

[0212] 5A shows an example in which the insulating layer 250 has a two-layer structure including an insulating layer 250a and an insulating layer 250c over the insulating layer 250a. In this case, the insulating layer 250a is in contact with the oxide semiconductor layer 230. For example, the insulating layer 250a preferably has a function of capturing or adhering oxygen, and the insulating layer 250c preferably has a barrier property against hydrogen. With such a structure, the amount of excess oxygen in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Furthermore, an insulating layer having a function of capturing or adhering oxygen may also have a function of capturing or adhering hydrogen, which may reduce the hydrogen concentration in the oxide semiconductor layer 230. Therefore, a highly reliable transistor can be realized. Note that the insulating layer 250a can be formed using a material applicable to the insulating layer 50 described in Embodiment 1.

[0213] 5B shows an example of the insulating layer 250 having a three-layer structure including an insulating layer 250a, an insulating layer 250b on the insulating layer 250a, and an insulating layer 250c on the insulating layer 250b. For example, it is preferable to use a material with a low dielectric constant for the insulating layer 250b. For example, it is preferable that the insulating layer 250b include a silicon oxide film or a silicon oxynitride film.

[0214] Note that a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250b, an insulating layer 250a on the insulating layer 250b, and an insulating layer 250c on the insulating layer 250a. With such a structure, hydrogen in the oxide semiconductor layer 230 can diffuse into the insulating layer 250a through the insulating layer 250b and be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0215] 5C shows an example in which the insulating layer 250 has a four-layer structure including an insulating layer 250a, an insulating layer 250b on the insulating layer 250a, an insulating layer 250d on the insulating layer 250b, and an insulating layer 250c on the insulating layer 250d. The insulating layer 250d preferably has a function of capturing or fixing hydrogen. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side. With this structure, hydrogen in the oxide semiconductor layer 230 can diffuse to the insulating layer 250a or the insulating layer 250d and be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0216] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0217] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0218] Typically, the thicknesses of the insulating layers 250a, 250b, 250d, and 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0219] Note that the insulating layer 250c may not be provided in the four-layer insulating layer 250. For example, an insulating layer having a function of capturing or fixing oxygen can be used as the insulating layer 250a, an insulating layer containing a material with a low dielectric constant can be used as the insulating layer 250b, and an insulating layer having a function of capturing or fixing hydrogen can be used as the insulating layer 250d. Specifically, the insulating layer 250 can have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0220] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0221] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0222] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0223] FIG. 4A illustrates an example in which the insulating layer 280 has a single-layer structure. The insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 6A , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use a material with a low dielectric constant as the insulating layer 280_2, and to use oxygen barrier insulating layers as the insulating layers 280_1 and 280_3. This can prevent the conductive layer 220 and the conductive layer 240 from being oxidized and thus prevent high resistance. In the configuration shown in FIG. 6A , the insulating layer 280_2 corresponds to the insulating layer 20 described in embodiment 1.

[0224] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 280_1 and the insulating layer 280_3, and to use silicon oxide for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0225] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0226] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulator containing oxygen such as hafnium oxide is used for the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, In—Zn oxide, or the like.

[0227] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0228] 6A shows an example in which the conductive layer 220_1 has a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11. In other words, the conductive layer 220 shown in FIG. 6A has a three-layer structure including a conductive layer 220_11, a conductive layer 220_12 over the conductive layer 220_11, and a conductive layer 220_2 over the conductive layer 220_12. In this case, for example, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_11, a material with high conductivity as the conductive layer 220_12, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230, and therefore the current path between the source and drain can be shortened, and the on-state current of the transistor 200 can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. Furthermore, when a metal material (tungsten here) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0229] 4A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0230] Note that the conductive layer 240_1 may be formed using a conductive material containing oxygen, and the conductive layer 240_2 may be formed using a material having higher conductivity than the conductive layer 240_1. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0231] 4A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0232] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0233] 6A , the semiconductor device of one embodiment of the present invention may include an insulating layer 283 over the transistor 200. Specifically, the insulating layer 283 may be provided over the conductive layer 260 and the insulating layer 250.

[0234] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0235] 4A , both the conductive layer 260_1 and the conductive layer 260_2 are located in the opening 290. Note that as the transistor 200 is miniaturized and the width of the opening 290 becomes smaller, it becomes more difficult to arrange all of the layers that form the conductive layer 260 in the opening 290. Depending on the width of the opening 290 and the thicknesses of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_2 may be provided so as to overlap with the opening 290 (see FIG. 6B ).

[0236] 6A shows a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 are aligned or approximately aligned, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 in the opening 290 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0237] 7A and 7B show examples in which at least a portion of the sidewall of the opening 290 is tapered. Fig. 7A shows an example in which the side surface of the conductive layer 240 in the opening 290 is tapered, and Fig. 7B shows an example in which the side surface of the conductive layer 240 and the side surface of the insulating layer 280 in the opening 290 are both tapered.

[0238] By tapering the sidewall of the opening 290, the coverage of the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the sidewall of the opening 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 in the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the opening 290.

[0239] Furthermore, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, coverage of the oxide semiconductor layer 230 and the like on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different. Similarly, when the conductive layer 240 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different.

[0240] 8A , the oxide semiconductor layer 230 may have a different ratio between the film thickness (hereinafter referred to as the first film thickness) of a portion where the top surface of the conductive layer 240 or the conductive layer 220 is to be formed and the film thickness (hereinafter referred to as the second film thickness) of a portion where the sidewall of the opening 290 is to be formed. For example, when a portion of the oxide semiconductor layer 230 is formed by sputtering, the oxide semiconductor layer 230 may have a different ratio between the first film thickness and the second film thickness. For example, as shown in FIG. 8A , the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the angle θ 280 is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness in the oxide semiconductor layer 230 tends to be.

[0241] 8B , the recess of the conductive layer 220_2 preferably has a curved portion. When the recess has a curved portion, the portions of the oxide semiconductor layer 230, the insulating layer 250, and the like provided on the recess near the recess may also have a curved portion. In other words, the portions may have a curved or concave surface in cross-sectional view. Furthermore, the portions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recess, improves the withstand voltage of the transistor 200, and suppresses electrostatic breakdown of the transistor 200. Therefore, the reliability of the semiconductor device can be improved.

[0242] 9A1 to 18B, examples of the configuration of a transistor that is partially different from the configuration of transistor 200 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0243] [Transistor 200A] Fig. 9A1 is a plan view of a semiconductor device including a transistor 200A. Fig. 9A2 is a plan view showing an example of arranging a plurality of transistors 200A. Fig. 9B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 9A1. Fig. 9C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 9A1. For a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 9C, refer to Fig. 3D. An enlarged view of Fig. 9C is shown in Fig. 10A.

[0244] The semiconductor device shown in Figures 9A1 to 9C includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 284, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the transistor 200A, the insulating layer 284, and the insulating layer 285.

[0245] The semiconductor device shown in FIGS. 9A1 to 9C differs from the semiconductor device shown in FIGS. 3A1 to 3D in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0246] The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0247] The transistor 200A includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. In the transistor 200A, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the above-described transistor 200, and therefore detailed description thereof will be omitted.

[0248] 9B and 9C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with openings 270 that reach insulating layer 250 at positions overlapping openings 290. Conductive layer 260 is disposed so that at least a portion thereof is located within opening 270. Conductive layer 260 contacts insulating layer 250 within opening 270.

[0249] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0250] 9B and 9C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that as transistors are miniaturized and the widths of the openings 290 and 270 become smaller, it becomes more difficult to arrange all of the layers constituting the conductive layer 260 in the openings 290 and 270. For example, there is a case in which only the conductive layer 260_1 is provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 270. There is also a case in which only the conductive layer 260_1 is provided in the opening 270.

[0251] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0252] 10A shows an example in which the width of the opening 270 is smaller than the width D of the opening 290. The smaller the width of the opening 270, the greater the physical distance between the conductive layer 240 and the conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 240 and the conductive layer 260 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0253] The height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are preferably the same or approximately the same. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The conductive layer 265 may be considered a component of the transistor 200A.

[0254] The transistor 200A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0255] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0256] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0257] The insulating layer 284 preferably has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. The insulating layer 284 can be formed using aluminum oxide, hafnium oxide, hafnium zirconium oxide, hafnium silicate, or the like.

[0258] The insulating layer 284 can also serve as a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. Silicon nitride and silicon nitride oxide are suitable for the insulating layer 284 because they are less permeable to oxygen and hydrogen, respectively.

[0259] When the insulating layer 284 includes a silicon nitride film, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0260] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may have a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0261] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0262] Note that a structure similar to that of the transistor 200 can also be applied to the transistor 200A. For example, as shown in FIG. 10B , the insulating layer 280 can have a three-layer structure of insulating layers 280_1 to 280_3. An insulating layer 283 can be provided over the insulating layer 285 and the conductive layer 265. The conductive layer 220_1 can have a two-layer structure of a conductive layer 220_11 and a conductive layer 220_12.

[0263] [Transistor 200B] Fig. 11A1 is a plan view of a semiconductor device including transistor 200B. Fig. 11A2 is a plan view showing an example of arranging a plurality of transistors 200B. Fig. 11B is a cross-sectional view taken along dashed line A1-A2 in Fig. 11A1. Fig. 11C is a cross-sectional view taken along dashed line A3-A4 in Fig. 11A1. Fig. 11D is a cross-sectional view taken along dashed line A5-A6 in Fig. 11C.

[0264] 11C is shown in FIG. 12A, and an enlarged view of FIG. 11D is shown in FIG. 12B. Also, FIGS. 13A and 13B are cross-sectional views taken along dashed line A3-A4 in FIG. 11A1. Each of FIGS. 13A and 13B corresponds to an example of an enlarged view of FIG. 11C, and shows an example of the configuration of each layer in more detail.

[0265] The semiconductor device shown in FIGS. 11A1 to 11D includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0266] The transistor 200B includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an insulating layer 225, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0267] The transistor 200B shown in FIGS. 11A1 to 11D differs from the transistor 200 shown in FIGS. 3A1 to 3D in that it includes an insulating layer 225.

[0268] The oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260 included in the transistor 200B correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260.

[0269] As illustrated in FIG. 11D, the transistor 200B has a configuration in which an insulating layer 225 is disposed between the insulating layer 280 and the oxide semiconductor layer 230 in a plan view.

[0270] The insulating layer 225 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, since it is a layer provided in the opening 290. This allows the insulating layer 225 to be provided with good coverage.

[0271] As shown in FIG. 11B and other figures, the conductive layer 220_2 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220_2, and then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in FIG. 11B and other figures, the side surface of the second recess and the side surface of the insulating layer 280 in the opening 290 coincide or approximately coincide, and the side surface of the first recess and the surface of the insulating layer 225 facing the oxide semiconductor layer 230 coincide or approximately coincide. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0272] 11B and other figures, the insulating layer 225 is in contact with the bottom surface and side surfaces of the second recessed portion of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280 and the conductive layer 240 within the opening 290. The oxide semiconductor layer 230 is in contact with the bottom surface and side surfaces of the first recessed portion of the conductive layer 220, the insulating layer 225, and the top surface of the conductive layer 240_2. The insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0273] 12A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area where the side surface of the conductive layer 220_2 is in contact with the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200B due to the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening 290.

[0274] 12A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B. Furthermore, the gate electric field is also easier to apply to a region of the oxide semiconductor layer 230 in contact with the conductive layer 220_2, thereby increasing the on-state current of the transistor 200B. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200B can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 in the opening 290.

[0275] Here, as shown in FIG. 12A, the width (film thickness) of the insulating layer 225 is set to width T ＳＷ Width T ＳＷ It is preferable that the width TＳＷ By reducing the width T ＳＷ By increasing the width T ＳＷ is, for example, preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0276] 12B also shows the channel width W of transistor 200B. When opening 290 is circular in plan view, width D of opening 290 corresponds to the diameter of opening 290, and channel width W is "(D-2×T ＳＷ ) × π”.

[0277] The channel length of transistor 200B can be considered to be the distance between the source region and the drain region. In other words, the channel length of transistor 200B can be said to be determined by the height of insulating layer 225. Furthermore, the channel length of transistor 200B can be said to be determined by the depth of the recess (specifically, the second recess) in conductive layer 220, the thickness of insulating layer 280 on conductive layer 220, and the thickness of conductive layer 240. When the channel length of transistor 200B is considered to be the distance between the source region and the drain region, the channel length of transistor 200B can be considered to be the length L shown in FIG. 12A .

[0278] 12A illustrates a configuration in which the conductive layer 220_2 has a first recess and a second recess, but the present invention is not limited to this. For example, as illustrated in FIG. 13A , the transistor 200B may have a configuration in which only the first recess is provided in the conductive layer 220_2.

[0279] A recess can be formed in the conductive layer 220_2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225. The transistor 200B illustrated in Figure 12A shows an example in which a recess is formed in the conductive layer 220_2 in both steps, whereas the transistor 200B illustrated in Figure 13A shows an example in which a recess is not formed in the conductive layer 220_2 in the step of forming the opening 290 but is formed in the step of forming the insulating layer 225.

[0280] 13A , the insulating layer 225 is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 240, and the top surface of the conductive layer 220_2 in the opening 290. The oxide semiconductor layer 230 is in contact with the bottom surface and side surface of the recess of the conductive layer 220_2.

[0281] When a recess is formed in the conductive layer 220_2 in at least one of the steps of forming the opening 290 and forming the insulating layer 225, the height of the bottom surface of the conductive layer 260 in the opening 290 can be reduced, making it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B.

[0282] When a recess is formed in the conductive layer 220_2 in the process of forming the insulating layer 225, the oxide semiconductor layer 230 can be in contact with the bottom and side surfaces of the recess of the conductive layer 220_2, the area of ​​contact between the oxide semiconductor layer 230 and the conductive layer 220_2 is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced, which is preferable.

[0283] For example, as shown in FIG. 13B, a transistor 200B may have a structure in which the insulating layer 225 does not cover the side surfaces of the conductive layer 240_2.

[0284] 13B is in contact with the bottom and side surfaces of the recess of the conductive layer 220, and is in contact with the side surface of the insulating layer 280 within the opening 290. The insulating layer 225 is in contact with part of the side surface of the conductive layer 240_1, but is not in contact with the side surface of the conductive layer 240_2. The insulating layer 225 may be in contact with one or more of the side surface of the insulating layer 280, the side surface of the conductive layer 240_1, and the side surface of the conductive layer 240_2 within the opening 290, or may cover part or all of each side surface.

[0285] When at least a part of the side surface of the conductive layer 240_2 is not covered with the insulating layer 225, the part is in contact with the oxide semiconductor layer 230. This increases the area where the oxide semiconductor layer 230 and the conductive layer 240 are in contact, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced. Similarly, when the insulating layer 225 does not cover the side surface of the conductive layer 240_2 and also does not cover at least a part of the side surface of the conductive layer 240_1, the part is in contact with the oxide semiconductor layer 230. This increases the area where the oxide semiconductor layer 230 and the conductive layer 240 are in contact, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0286] 12A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. For example, as shown in FIG. 14, the insulating layer 225 can have a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2.

[0287] 14 illustrates an example in which the insulating layer 225 has a two-layer structure including an insulating layer 225_1 in contact with the insulating layer 280 and an insulating layer 225_2 between the insulating layer 225_1 and the oxide semiconductor layer 230. The insulating layer 225 illustrated in FIG. 14 can be said to have a two-layer structure including the insulating layer 225_1 and the insulating layer 225_2 over the insulating layer 225_1.

[0288] The insulating layer 225_1 provided in contact with the side surface of the insulating layer 280 in the opening 290 can be a barrier insulating layer against hydrogen, and the insulating layer 225_2 provided in contact with the oxide semiconductor layer 230 can be an insulating layer having a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable to use silicon nitride for the insulating layer 225_1 and silicon oxide or silicon oxynitride for the insulating layer 225_2. The thicknesses of the insulating layers 225_1 and 225_2 are 2 nm and 2 nm, respectively.

[0289] As described above, by surrounding the oxide semiconductor layer 230 with a barrier insulating layer against hydrogen in a ring shape and providing an insulating layer having a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0290] Note that the insulating layer 225_1 can be made of a material applicable to the insulating layer 20a described in embodiment 1, and the insulating layer 225_2 can be made of a material applicable to the insulating layer 20b described in embodiment 1.

[0291] Here, another example of the configuration of the insulating layer 225 shown in FIG. 14 is shown in FIGS. 15A and 15B.

[0292] In the transistor 200B shown in Figure 15A, an example is shown in which the insulating layer 225_1 is provided in contact with a portion of the bottom surface and the side surface of the recess formed by the conductive layer 220_2, and the insulating layer 225_2 is located inside the insulating layer 225_1 in the opening 290 and is provided in contact with another portion of the bottom of the recess formed by the conductive layer 220_2.

[0293] 15B , the conductive layer 220_2 has a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, and the second recess is deeper than the third recess. The third recess is provided in the conductive layer 220_2 when the opening 290 is formed. Then, the second recess is provided in the conductive layer 220_2 when the insulating layer 225_1 is processed. Then, the first recess is provided in the conductive layer 220_2 when the insulating layer 225_2 is processed. Therefore, in FIG. 15B, the side surface of the third recess and the side surface of the insulating layer 280 in the opening 290 are aligned or approximately aligned, the side surface of the second recess and the surface of the insulating layer 225_1 on the insulating layer 225_2 side are aligned or approximately aligned, and the side surface of the first recess and the surface of the insulating layer 225_2 on the oxide semiconductor layer 230 side are aligned or approximately aligned.

[0294] In the transistor 200B shown in Figure 15B, the insulating layer 225_1 is provided in contact with the bottom and side surfaces of the third recess of the conductive layer 220_2, and the insulating layer 225_2 is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220_2.

[0295] 15A or 15B can be formed by providing the insulating layer 225_1 on the sidewall of the opening 290 and then forming and processing an insulating film to be the insulating layer 225_2. Compared to the transistor 200B shown in FIG. 14 , the region where the insulating layer 225_1 is in contact with the oxide semiconductor layer 230 is reduced, and a structure in which the insulating layer 225_2 is in contact with the oxide semiconductor layer 230 can be realized.

[0296] Note that a structure similar to that of at least one of the transistors 200 and 200A can also be applied to the transistor 200B. For example, as shown in FIG. 16A , in the semiconductor device shown in FIG. 12A , the insulating layer 280 can have a three-layer structure of insulating layers 280_1 to 280_3. An insulating layer 283 can be provided over the insulating layer 250 and the conductive layer 260. The conductive layer 220_1 can have a two-layer structure of conductive layers 220_11 and 220_12. An example in which the above structure is applied to the semiconductor device shown in FIG. 14 is shown in FIG. 16B.

[0297] [Transistor 200C] Fig. 17A1 is a plan view of a semiconductor device having a transistor 200C. Fig. 17A2 is a plan view showing an example of arranging a plurality of transistors 200C. Fig. 17B is a cross-sectional view taken along dashed line A1-A2 in Fig. 17A1. Fig. 17C is a cross-sectional view taken along dashed line A3-A4 in Fig. 17A1. Fig. 17D is a cross-sectional view taken along dashed line A5-A6 in Fig. 17C. Fig. 18A shows an enlarged view of Fig. 17C.

[0298] The semiconductor device shown in Figures 17A1 to 17D has an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210, an insulating layer 280 on the insulating layer 210, and an insulating layer 281 on the insulating layer 280.

[0299] The transistor 200C includes a conductive layer 220, a conductive layer 255 on the insulating layer 280, a conductive layer 240 on the insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0300] 17A1 to 17D differ from the semiconductor device shown in Figures 3A1 to 3D mainly in that the semiconductor device includes an insulating layer 225, a conductive layer 255, and an insulating layer 281. The transistor 200C shown in Figures 17A1 to 17D differs from the transistor 200B shown in Figures 11A1 to 11D mainly in that the transistor 200C includes a conductive layer 255.

[0301] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240_1 is located over the insulating layer 281.

[0302] As shown in FIG. 18A, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0303] In transistor 200C, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating layer.

[0304] The oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260 included in the transistor 200C correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 225, the insulating layer 250, and the conductive layer 260.

[0305] Alternatively, the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 225, and the conductive layer 255 included in the transistor 200C may correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. In this case, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, described in Embodiment 1, can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 225, and the conductive layer 255.

[0306] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 225 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200C.

[0307] Since the transistor 200C includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200C can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0308] In the transistor 200C, one of the conductive layer 255 and the conductive layer 260 may be used as a gate electrode and the other as a back gate electrode. The transistor 200C may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. When the conductive layer 260, which has a wider region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as the gate electrode, a gate electric field is applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. When the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer and the insulating layer 225 functions as a back gate insulating layer.

[0309] The conductive layer 255 can be made of a conductive material that can be used for the conductive layer 260 .

[0310] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0311] 18A shows an example in which the insulating layer 281 has a single-layer structure. Note that the insulating layer 281 can have a stacked structure of two or more layers. For example, as shown in FIG. 18B, the insulating layer 281 can have a three-layer structure including an insulating layer 281_1, an insulating layer 281_2 on the insulating layer 281_1, and an insulating layer 281_3 on the insulating layer 281_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 281_2, and to use barrier insulating layers against oxygen for the insulating layers 281_1 and 281_3. This can prevent the conductive layer 255 and the conductive layer 240 from being oxidized and prevent high resistance.

[0312] Note that the same structure as at least one of the transistors 200, 200A, and 200B can also be applied to the transistor 200C. For example, as shown in FIG. 18B, in the semiconductor device shown in FIG. 18A, the insulating layer 280 can have a three-layer structure of insulating layers 280_1 to 280_3. An insulating layer 283 can be provided over the insulating layer 250 and the conductive layer 260. The conductive layer 220_1 can have a two-layer structure of a conductive layer 220_11 and a conductive layer 220_12.

[0313] <Structural Example 2 of Semiconductor Device> Another structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 19A to 20B . FIG. 19A is a plan view of a semiconductor device including a transistor 200D. FIG. 19B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 19A , which is also a cross-sectional view of the transistor 200D in the channel length direction. FIG. 19C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 19A , which is also a cross-sectional view of the transistor 200D in the channel width direction. FIG. 19D is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 19A , which is also a cross-sectional view of the transistor 200D in the channel width direction. FIGS. 20A and 20B each show an enlarged cross-sectional view of the transistor 200D in the channel length direction.

[0314] The transistor 200D includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, an oxide semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the oxide semiconductor layer 230, an insulating layer 271a on the conductive layer 242a, an insulating layer 271b on the conductive layer 242b, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0315] In the transistor 200D, the oxide semiconductor layer 230 functions as a channel formation region, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0316] The oxide semiconductor layer 230, the insulating layer 224, the insulating layer 250, and the conductive layer 260 included in the transistor 200D correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 224, the insulating layer 250, and the conductive layer 260, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1 can be referred to.

[0317] Alternatively, the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 224, and the conductive layer 205 included in the transistor 200D may correspond to the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. In this case, the structures, materials, and the like of the oxide semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, described in Embodiment 1, can be referred to for the structures, materials, and the like of the oxide semiconductor layer 230, the insulating layer 250, the insulating layer 224, and the conductive layer 205.

[0318] An insulating layer 275 is provided over the insulating layer 271a and the insulating layer 271b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 reaching the insulating layer 222 and the oxide semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275, and the opening 289 overlaps with a region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surface of the insulating layer 280 in the opening 289 coincides or substantially coincides with the side surfaces of the conductive layer 242a and the conductive layer 242b. The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the upper end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided over the insulating layer 282. Further, an insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0319] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, 275, and 271a, and conductive layers 243a and 241a are provided in the openings. An insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, 275, and 271b, and conductive layers 243b and 241b are provided in the openings. An insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided over the transistor 200D to the source or drain of the transistor 200D.

[0320] The oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0321] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the oxide semiconductor layer 230. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged.

[0322] An insulating layer containing excess oxygen is provided near the oxide semiconductor layer, and heat treatment is performed to supply oxygen from the insulating layer to the oxide semiconductor layer, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200D may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if the amount of oxygen supplied from the insulating layer to the oxide semiconductor layer becomes excessively large, this may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and impairing their conductivity.

[0323] First, an insulating layer having a barrier property against hydrogen is formed near the oxide semiconductor layer 230, and V in the channel formation region of the oxide semiconductor layer 230 and its vicinity is formed. Ｏ It is preferable to reduce H.

[0324] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0325] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a higher hydrogen barrier property.

[0326] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222 that functions as the second gate insulating layer.

[0327] 20A , an insulating layer 212 having a function of suppressing hydrogen diffusion and an insulating layer 214 having a function of capturing or fixing hydrogen are preferably provided under the transistor 200D. By providing the insulating layer 212 under the transistor 200D, diffusion of hydrogen from layers below the transistor 200D can be suppressed. Furthermore, by providing the insulating layer 214 over the insulating layer 212, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This allows the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity to be reduced.

[0328] 20A , an insulating layer 221 having a function of suppressing hydrogen diffusion and an insulating layer 222 having a function of capturing or fixing hydrogen are preferably provided under the oxide semiconductor layer 230. By providing the insulating layer 221 under the oxide semiconductor layer 230, diffusion of hydrogen from below the oxide semiconductor layer 230 can be suppressed. Furthermore, by providing the insulating layer 222 over the insulating layer 221, hydrogen contained in the insulating layer 224 and the like can be captured or fixed by the insulating layer 222. This allows the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity to be reduced.

[0329] 20A , it is preferable to provide an insulating layer 275 to cover the oxide semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc. By providing the insulating layer 275, it is possible to suppress diffusion of hydrogen from the insulating layer 280 to the oxide semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0330] 20A , an insulating layer 282 having a function of capturing or fixing hydrogen and an insulating layer 283 having a function of suppressing diffusion of hydrogen are preferably provided over the transistor 200D. By providing the insulating layer 283 over the transistor 200D, diffusion of hydrogen from the upper layer of the transistor 200D can be suppressed. Furthermore, by providing the insulating layer 282 under the insulating layer 283, hydrogen contained in the insulating layer 280 or the like can be captured or fixed in the insulating layer 282. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity.

[0331] In this way, by using a structure in which the transistor 200D is surrounded by barrier insulating layers against hydrogen from above and below, diffusion of hydrogen into the oxide semiconductor is reduced, and the V Ｏ H can be reduced. This can improve the electrical characteristics and reliability of the transistor 200D.

[0332] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the oxide semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0333] As shown in FIG. 20A, the insulating layer 282 may have a stacked structure of an insulating layer 282_1 and an insulating layer 282_2 over the insulating layer 282_1.

[0334] In this case, oxygen can be added to the insulating layer 280 by forming the insulating layer 282_2 by a sputtering method in an atmosphere containing oxygen gas. At this time, by forming the insulating layer 282_2 after the insulating layer 282_1 has been formed, oxygen is added through the insulating layer 282_1, so that the amount of oxygen added to the insulating layer 280 can be controlled. If the insulating layer 282_1 is thick, the addition of oxygen is more likely to be hindered, and the amount of oxygen implanted into the insulating layer 280 decreases. If the insulating layer 282_1 is thin, the addition of oxygen is less likely to be hindered, and the amount of oxygen implanted into the insulating layer 280 increases. For example, by setting the thickness of the insulating layer 282_1 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, an appropriate amount of oxygen can be supplied to the insulating layer 280.

[0335] The insulating layer 282_1 is preferably formed by an ALD method to prevent oxygen from being added to the insulating layer 280. The insulating layer 282_1 is preferably formed by an ALD method to reduce the thickness of the insulating layer 282_1 as described above.

[0336] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the oxide semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283 having a barrier property against oxygen are formed over the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the oxide semiconductor layer 230 and the conductive layer 242a and 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the oxide semiconductor layer 230 can be adjusted.

[0337] Here, the insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the oxide semiconductor layer 230 and prevents the conductive layers 242a, 242b, and 260 from being oxidized.

[0338] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0339] Here, as shown in FIG. 20A, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the oxide semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, and an insulating layer 250c on the insulating layer 250b.

[0340] The insulating layer 250b is preferably formed using silicon oxide, silicon oxynitride, or the like, which has a high withstand voltage. To improve the withstand voltage, the insulating layer 250b may be thicker than the insulating layers 250a and 250c. By using such an oxide insulator, oxygen can be diffused in the insulating layer 250b by performing high-temperature heat treatment. Therefore, by performing heat treatment, oxygen contained in the insulating layer 280 can be supplied to the oxide semiconductor layer 230 through the insulating layer 250b.

[0341] The insulating layer 250a preferably has a function of capturing or fixing oxygen. The insulating layer 250a, which has a region in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has the function of capturing or fixing oxygen, thereby preventing the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200D. Furthermore, this structure can reduce the amount of oxygen in the insulating layer 250b absorbed by the conductive layer 242a and the conductive layer 242b. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250b to the oxide semiconductor layer 230, thereby reducing oxygen vacancies in the channel formation region of the oxide semiconductor layer 230.

[0342] Furthermore, by providing the insulating layer 250a between the insulating layer 280 and the insulating layer 250b and between the insulating layer 250b and the oxide semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the oxide semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the oxide semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, which can prevent the transistor 200D from becoming excessively normally off and improve reliability. In addition, excessive oxidation of the source and drain regions can be suppressed, which can cause a decrease in the on-state current or the field-effect mobility of the transistor 200D.

[0343] Therefore, the insulating layer 250a preferably has a thickness that does not excessively hinder the diffusion of oxygen from the insulating layer 280 to the insulating layer 250b and the diffusion of oxygen from the insulating layer 250b to the oxide semiconductor layer 230. For example, the thickness of the insulating layer 250a is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 0.5 nm to less than 3.0 nm, and still more preferably 0.5 nm to 2.0 nm.

[0344] As described above, it is preferable to appropriately diffuse oxygen from the insulating layer 280 to the insulating layer 250b and from the insulating layer 250b to the oxide semiconductor layer 230, and to suppress the diffusion of oxygen from the insulating layer 250b to the conductive layer 242a and the conductive layer 242b as much as possible. In the semiconductor device according to this embodiment, the contact area between the insulating layer 250a and the conductive layer 242a and the contact area between the insulating layer 250a and the conductive layer 242b are much smaller than the contact area between the insulating layer 250a and the oxide semiconductor layer 230. In other words, it is presumed that the amount of oxygen diffusing from the insulating layer 250b to the conductive layer 242a and the conductive layer 242b via the insulating layer 250a is smaller than the amount of oxygen diffusing from the insulating layer 250b to the oxide semiconductor layer 230 via the insulating layer 250a. Therefore, by controlling the amount of oxygen contained in the insulating layer 280 so that an appropriate amount of oxygen is supplied from the insulating layer 280 to the insulating layer 250b and the oxide semiconductor layer 230, oxidation of the conductive layer 242a and the conductive layer 242b can be suppressed.

[0345] The insulating layer 250a in contact with the channel formation region in the oxide semiconductor layer 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor layer 230. Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0346] Furthermore, it is preferable to use a high-k material for the insulating layer 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250a makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0347] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250a, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. It is even more preferable to use aluminum oxide having an amorphous structure, since an amorphous film of aluminum oxide can be formed relatively easily using the ALD method. In this embodiment, aluminum oxide is used as the insulating layer 250a. Aluminum oxide has the function of capturing or fixing oxygen and hydrogen, and is therefore suitable as the insulating layer 250a.

[0348] The insulating layer 250c preferably has a barrier property against oxygen. The insulating layer 250c is provided between the channel formation region of the oxide semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor layer 230 can be prevented from diffusing to the conductive layer 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor layer 230. Furthermore, oxygen contained in the oxide semiconductor layer 230 and oxygen contained in the insulating layer 280 can be prevented from diffusing to the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250c is preferably at least less permeable to oxygen than the insulating layer 250b. Furthermore, the insulating layer 250c preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing to the oxide semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250c.

[0349] 20B, a structure may be adopted in which an insulating layer 250d is provided on the insulating layer 250b. In this case, an insulating material applicable to the insulating layer 250a may be used as the insulating layer 250d. For example, hafnium oxide may be used as the insulating layer 250d. Here, by providing the insulating layer 250d between the insulating layer 250c and the insulating layer 250b, hydrogen contained in the insulating layer 250b and the like can be more effectively captured or fixed. Alternatively, a structure may be adopted in which the insulating layer 250a, the insulating layer 250b, and the insulating layer 250d are provided without providing the insulating layer 250c.

[0350] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200D can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0351] The insulating layers 250a to 250d are provided in the opening 289 together with the conductive layer 260. To miniaturize the transistor 200, the insulating layers 250a to 250d are preferably thin. The thicknesses of the insulating layers 250a to 250d are preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a to 250d may have a region with the above thickness at least in part.

[0352] In order to thin the insulating layers 250a to 250d as described above, it is preferable to form the insulating layers 250a to 250d by an ALD method. In addition, in order to form the insulating layers 250a to 250d in the opening 289 with good coverage, it is preferable to form the insulating layers 250a to 250d by an ALD method.

[0353] Although the above description has been given of a structure in which the insulating layer 250 has a three-layer structure of insulating layers 250a to 250c or a four-layer structure of insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can also have a structure including at least one of the insulating layers 250a to 250d. By configuring the insulating layer 250 as one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0354] The conductive layer 205 is disposed so as to overlap with the oxide semiconductor layer 230 and the conductive layer 260. The conductive material described in the later section [Conductive Layer] can be used for the conductive layer 205. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. Furthermore, the conductive layer 205 is preferably provided so as to extend in the channel width direction as shown in FIGS. 19A and 19C . With such a structure, the conductive layer 205 functions as a wiring when a plurality of transistors are provided.

[0355] 20A , the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205b is provided so as to fill a recess in the conductive layer 205a formed along the opening. Here, the height of the upper surface of the conductive layer 205 coincides with or approximately coincides with the height of the upper surface of the insulating layer 216.

[0356] Here, the conductive layer 205a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0357] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the oxide semiconductor layer 230 through the insulating layer 216 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 205a, it is possible to suppress a decrease in the conductivity of the conductive layer 205b due to oxidation. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0358] The conductive layer 205b is preferably made of a conductor having high conductivity. For example, the conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205b preferably contains tungsten.

[0359] The conductive layer 205 can function as a second gate electrode. In this case, the potential applied to the conductive layer 205 can be changed independently of the potential applied to the conductive layer 260, thereby controlling the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 205, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 205, the drain current when the potential applied to the conductive layer 260 is 0 V can be made smaller than when no negative potential is applied.

[0360] 20A shows a stacked structure of the conductive layer 205a and the conductive layer 205b, the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205a may have a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and the conductive layer 205b having a tungsten film may be provided on the conductive layer 205a. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200D can be prevented from diffusing into the conductive layer 205.

[0361] The insulating layer 224 functions as a second gate insulating layer together with the insulating layers 221 and 222 .

[0362] The insulating layer 224 in contact with the oxide semiconductor layer 230 can be formed using the insulating material applicable to the insulating layer 20 described in Embodiment 1. The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the oxide semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0363] The insulating layer 224 is preferably processed into an island shape, similar to the oxide semiconductor layer 230. Thus, when a plurality of transistors 200D are provided, each transistor 200D has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the oxide semiconductor layer 230 in each transistor 200D becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200D within the substrate surface can be suppressed.

[0364] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 21A to 21D, the insulating layer 224 may not be formed into an island shape, but may have a shape in which an opening is formed in a part of it. Figures 21A to 21D correspond to Figures 19A to 19D, respectively, and are the same as Figures 19A to 19D except that the shape of the insulating layer 224 is different.

[0365] 21A to 21D , the insulating layer 224 has a smaller thickness in a region that does not overlap with the oxide semiconductor layer 230 than in a region that overlaps with the oxide semiconductor layer 230. An opening is formed in a region that does not overlap with the oxide semiconductor layer 230 and overlaps with the insulating layer 250. When a plurality of transistors are provided over the same substrate, the insulating layer 224 is formed in this manner, so that the oxide semiconductor layer 230 of each transistor is formed over the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the oxide semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0366] Note that in the insulating layer 224 shown in FIGS. 21A to 21D, an opening is formed in a region that does not overlap with the oxide semiconductor layer 230 and overlaps with the insulating layer 250; however, a configuration without such an opening may be adopted.

[0367] The conductive layers 242a, 242b, and 260 can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a, 242b, and 260.

[0368] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen.

[0369] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the conductive material may be used for the lower layers of the conductive layers 242a and 242b, and a conductive material with higher conductivity may be used for the upper layers of the conductive layers 242a and 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer.

[0370] The insulating layers 271a and 271b are inorganic insulating layers that function as etching stoppers and protect the conductive layers 242a and 242b when processing the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, they are preferably inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. Therefore, as shown in FIG. 20A , it is preferable that the insulating layer 271a has a stacked structure of an insulating layer 271a1 and an insulating layer 271a2 on the insulating layer 271a1, and that the insulating layer 271b has a stacked structure of an insulating layer 271b1 and an insulating layer 271b2 on the insulating layer 271b1. Here, the insulating layers 271a1 and 271b1 are preferably made of a nitride insulator that can be used for the insulating layer 250c so as to prevent the conductive layers 242a and 242b from being oxidized, and the insulating layers 271a2 and 271b2 are preferably made of an oxide insulator that can be used for the insulating layer 250b so as to function as an etching stopper.

[0371] Here, the insulating layer 271a1 is in contact with the upper surface of the conductive layer 242a, and the insulating layer 271b1 is in contact with the upper surface of the conductive layer 242b. The insulating layer 271a2 is in contact with the upper surface of the insulating layer 271a1 and the lower surface of the insulating layer 275, and the insulating layer 271b2 is in contact with the upper surface of the insulating layer 271b1 and the lower surface of the insulating layer 275. For example, silicon nitride can be used for the insulating layers 271a1 and 271b1, and silicon oxide can be used for the insulating layers 271a2 and 271b2.

[0372] The insulating layers that form the insulating layers 271a and 271b function as masks for the conductive layers that form the conductive layers 242a and 242b. Therefore, as shown in FIG. 19D , the conductive layers 242a and 242b do not have curved surfaces between their side surfaces and top surfaces. As a result, the conductive layers 242a and 242b have angular edges where their side surfaces and top surfaces intersect. The angular edges where the side surfaces and top surfaces of the conductive layers 242a and 242b intersect increase the cross-sectional areas of the conductive layers 242a and 242b compared to when the edges have curved surfaces. Furthermore, using a nitride insulator that does not easily oxidize metal for the insulating layers 271a1 and 271b1 can prevent the conductive layers 242a and 242b from being excessively oxidized. As a result, the resistance of the conductive layers 242a and 242b is reduced, thereby increasing the on-state current of the transistor.

[0373] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side surface and upper surface of the oxide semiconductor layer 230 via the insulating layer 250. The height of the upper surface of the conductive layer 260 is equal to or approximately equal to the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0374] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as voids can be reduced.

[0375] 19A and 19C, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0376] 19C , in a cross-sectional view of the transistor 200D in the channel width direction, a curved surface may be formed between the side surface of the oxide semiconductor layer 230 and the top surface of the oxide semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0377] In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin structure. In this specification, a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0378] By forming the transistor 200D in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. By forming the transistor 200D in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor layer 230 and the gate insulator can be the entire bulk of the oxide semiconductor layer 230. Therefore, the density of current flowing through the transistor can be increased, thereby improving the on-state current or the field-effect mobility of the transistor.

[0379] In this embodiment, the insulating layer 224 is provided in an island shape. Therefore, as shown in FIG. 19C , at least a part of the bottom surface of the conductive layer 260 can be provided below the bottom surface of the oxide semiconductor layer 230. This allows the conductive layer 260 to be provided facing the top surface and side surface of the oxide semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the top surface and side surface of the oxide semiconductor layer 230. By providing the insulating layer 224 in an island shape in this manner, the transistor 200D can have an S-channel structure.

[0380] 19C illustrates an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0381] As shown in Fig. 20A, it is preferable that the conductive layer 260 has a two-layer structure. Here, it is preferable that the conductive layer 260 has a conductive layer 260a and a conductive layer 260b arranged on the conductive layer 260a. For example, it is preferable that the conductive layer 260a is arranged so as to surround the bottom and side surfaces of the conductive layer 260b. In this case, it is preferable that the conductive layer 260a is made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0382] The conductive layer 260a can be formed using a conductive material that can be used for the conductive layer 205a. For example, the conductive layer 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 260b caused by oxygen contained in the insulating layer 280 or the like.

[0383] The conductive layer 260b can be formed using a conductive material applicable to the conductive layer 205b. The conductive layer 260b may have a stacked structure, for example, a stacked structure of a titanium film or a titanium nitride film and a conductive material applicable to the conductive layer 205b.

[0384] In the transistor 200D, the conductive layer 260 is formed in a self-aligned manner to fill the opening 289. By forming the conductive layer 260 in this manner, the conductive layer 260 can be arranged to overlap the region between the conductive layer 242a and the conductive layer 242b without alignment.

[0385] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0386] For example, it is preferable that insulating layer 216, insulating layer 280, and insulating layer 285 each contain one or more of silicon oxide, silicon oxynitride, silicon oxide containing fluorine, silicon oxide containing carbon, silicon oxide containing carbon and nitrogen, and silicon oxide having vacancies.

[0387] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they allow for the easy formation of a region containing excess oxygen.

[0388] The upper surfaces of the insulating layer 216 and the insulating layer 280 may be planarized.

[0389] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0390] The conductive layers 243a and 243b can be formed using the conductive materials described in the section "Conductive Layer" below. The conductive layers 243a and 243b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example. The conductive layers 243a and 243b may have a stacked structure.

[0391] 20A , the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a includes a conductive layer 243a1 formed along the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b includes a conductive layer 243b1 formed along the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0392] For the conductive layers 243a1 and 243b1, similar to the conductive layer 205a, a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material having a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. Providing the conductive layers 243a1 and 243b1 can suppress impurities such as water and hydrogen from entering the oxide semiconductor layer 230 through the conductive layers 243a2 and 243b2. Note that the conductive layers 243a2 and 243b2 may be formed using a conductive material applicable to the conductive layers 243a and 243b.

[0393] 19B, the upper surfaces of the conductive layers 243a and 243b are flush or substantially flush with the upper surface of the insulating layer 285. As shown in Fig. 20A, the lower part of the conductive layer 243a may be formed so as to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 243b may be formed so as to be embedded in the conductive layer 242b.

[0394] The insulating layers 241a and 241b may be barrier insulating layers applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, 275, 271a, and 271b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the oxide semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0395] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with a sidewall of an opening such as the insulating layer 280 and a second insulating layer on the inner side thereof preferably use a combination of a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0396] 19B and other figures, insulating layer 250 is in contact with the side surface of insulating layer 280 in opening 289, but the present invention is not limited to this configuration. For example, an insulating layer may be provided between insulating layer 250 and insulating layer 280 in opening 289.

[0397] 22A to 23C will be used to describe modifications of the semiconductor device described with reference to FIGS. 19A to 19D. FIGS. 22A to 22D are plan views and cross-sectional views of a semiconductor device including a transistor 200D, and correspond to the plan views and cross-sectional views shown in FIGS. 19A to 19D, respectively. FIGS. 23A to 23C are enlarged cross-sectional views of the transistor 200D in the channel length direction, and correspond to the enlarged cross-sectional view shown in FIG. 20B, respectively.

[0398] 22A to 22D is a modified example of the transistor 200D shown in Figures 19A to 19D. Specifically, the transistor 200D shown in Figures 22A to 22D mainly differs from the transistor 200D shown in Figures 19A to 19D in that it includes an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0399] 22A to 22D, the conductive layers 242a and 242b are each shown as a two-layer structure. The conductive layer 242a has a laminated structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b has a laminated structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1. The conductive layers 242a1 and 242b1 correspond to the lower layers of the conductive layers 242a and 242b, respectively, and the conductive layers 242a2 and 242b2 correspond to the upper layers of the conductive layers 242a and 242b, respectively.

[0400] 22B and 22C , insulating layer 254 is disposed inside opening 289 and contacts the side surfaces of insulating layer 280, the side surfaces of conductive layer 242a2, the side surfaces of conductive layer 242b2, the top surfaces of conductive layer 242a1, the top surfaces of conductive layer 242b1, and the top surface of insulating layer 222 in opening 289. In other words, insulating layer 254 can also be said to be formed in the shape of a sidewall in contact with the side wall of opening 289. Here, the side wall of opening 289 corresponds to, for example, the side surface of insulating layer 280, etc. in opening 289.

[0401] The insulating layer 254 preferably has a barrier property against oxygen. The insulating layer 254 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a2 and 242b2 from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200D. An oxygen barrier insulating layer can be used as the insulating layer 254. For example, silicon nitride can be used as the insulating layer 254.

[0402] The opening 289 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a plan view, the side surfaces of the insulating layer 280 in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening 289. In other words, the portion of the conductive layer 242a1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, the portion of the conductive layer 242b1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 more than the conductive layer 242b2.

[0403] Here, part of the top surface of the conductive layer 242a1 is in contact with the conductive layer 242a2, and part of the top surface of the conductive layer 242b1 is in contact with the conductive layer 242b2. Therefore, the insulating layer 254 is in contact with another part of the top surface of the conductive layer 242a1, another part of the top surface of the conductive layer 242b1, a side surface of the conductive layer 242a2, and a side surface of the conductive layer 242b2 inside the opening 289. Furthermore, the insulating layer 250 is in contact with the top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a1, the side surface of the conductive layer 242b1, and the side surface of the insulating layer 254.

[0404] The insulating layer 254 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening 289. The insulating layer 254 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2 and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0405] 23A , in a cross-sectional view of the transistor 200D, the side edges of the insulating layer 254 coincide or substantially coincide with the side edges of the conductive layer 242a1 and the conductive layer 242b1.

[0406] Note that after separating the conductive layer 242a1 and the conductive layer 242b1, it is preferable to perform heat treatment in an atmosphere containing oxygen before forming the insulating layer 250. At this time, since the insulating layer 254 is formed in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be prevented. Furthermore, even when microwave plasma treatment is performed after separating the conductive layer 242a1 and the conductive layer 242b1, formation of an oxide film on the side surfaces of the conductive layer 242a and the conductive layer 242b can be suppressed.

[0407] The insulating layer 254, the insulating layer 250, and the conductive layer 260 are provided to reflect the shape of the opening 289. Therefore, the insulating layer 254 is provided so as to cover the sidewall of the opening 289, the insulating layer 250 is provided so as to cover the bottom of the opening 289 and the insulating layer 254, and the conductive layer 260 is provided so as to fill the recess of the insulating layer 250.

[0408] As described above, the insulating layer 250 may have a stacked structure. For example, as shown in Fig. 23A, the insulating layer 250 may have a three-layer structure of insulating layers 250a to 250c. Alternatively, as shown in Fig. 23B, the insulating layer 250 may have a four-layer structure of insulating layers 250a to 250d.

[0409] The thickness of the insulating layer 254 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and still more preferably 0.5 nm to 3 nm. By setting the insulating layer 254 to the above thickness, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be suppressed. Note that the insulating layer 254 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulating layer 254 is provided in contact with the sidewall of the opening 289, it is preferable to deposit the insulating layer 254 by an ALD method or the like, which has good coverage. If the insulating layer 254 is too thick, the deposition time of the insulating layer 254 by the ALD method increases, resulting in reduced productivity. Therefore, the thickness of the insulating layer 254 is preferably within the above range. The insulating layer 254 preferably has a thickness that does not excessively hinder the diffusion of excess oxygen from the insulating layer 280 to the insulating layer 250 b and from the insulating layer 250 b to the oxide semiconductor layer 230 .

[0410] As shown in FIG. 23A , in a cross-sectional view of the transistor 200D in the channel length direction, the distance L1 between the conductive layers 242a1 and 242b1 is smaller than the distance L2 between the conductive layers 242a2 and 242b2. Here, distance L1 refers to the shortest distance between the conductive layers 242a1 and 242b1, and distance L2 refers to the shortest distance between the conductive layers 242a2 and 242b2. This configuration allows for a shorter source-drain distance and a correspondingly shorter channel length. This improves the frequency characteristics of the transistor 200D. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0411] 23A , the difference between distance L2 and distance L1 is equal to twice the film thickness of insulating layer 254. In other words, distance L2 is equal to or approximately equal to distance L1 obtained by adding twice the film thickness of insulating layer 254. Here, the film thickness of insulating layer 254 refers to the width of at least a portion of insulating layer 254 in the A1-A2 direction.

[0412] The insulating layer 254 may also have a stacked structure of two or more layers. In this case, at least one layer can be the inorganic insulating layer that is resistant to oxidation. For example, the first insulating layer of the insulating layer 254 may be the inorganic insulating layer that is resistant to oxidation, and the second insulating layer on the first insulating layer of the insulating layer 254 may be made of an insulating material (e.g., silicon oxide) that is applicable to the insulating layer 250b. The second insulating layer of the insulating layer 254 preferably has a lower dielectric constant than the first insulating layer of the insulating layer 254. In this way, by forming the insulating layer 254 into a two-layer structure and increasing its thickness, the distance between the conductive layer 260 and the conductive layer 242a or 242b can be increased, thereby reducing parasitic capacitance.

[0413] Although the above describes an example in which the insulating layer 254 is formed into a sidewall shape by anisotropic etching, the present invention is not limited to this. As shown in Fig. 23C, the insulating layer 254 may have an opening inside the opening 289. In this case, the opening in the insulating layer 254 can be formed by removing a part of the insulating film that will become the insulating layer 254 by lithography. The opening in the insulating layer 254 preferably overlaps with the region between the conductive layer 242a1 and the conductive layer 242b1.

[0414] 23C, in a cross-sectional view, a protrusion is formed at the lower part of the insulating layer 254. The protrusion of the insulating layer 254 overlaps with the protrusion of the conductive layer 242a1 and the protrusion of the conductive layer 242b1.

[0415] In the first modification, the insulating layer 254 is provided in contact with the sidewall of the opening 289. However, the present invention is not limited to this configuration. For example, the insulating layer 254 may not be provided in the opening 289.

[0416] 24A to 25 will be used to describe a modification of the semiconductor device described in Modification 1. Figures 24A to 24D are plan views and cross-sectional views of a semiconductor device including a transistor 200D, and correspond to the plan views and cross-sectional views shown in Figures 22A to 22D, respectively. Figure 25 is an enlarged cross-sectional view of the transistor 200D in the channel length direction, and corresponds to the enlarged cross-sectional view shown in Figure 23C.

[0417] 24A to 24D is a modified example of the transistor 200D shown in Figures 22A to 22D. Specifically, the transistor 200D shown in Figures 24A to 24D differs from the transistor 200D shown in Figures 22A to 22D mainly in that the transistor 200D shown in Figures 24A to 24D does not have an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0418] 25 , in a configuration in which the insulating layer 254 is not provided, a portion of the insulating layer 250 is disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Also, a portion of the conductive layer 260 may be disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the conductive layer 242b1 contact the insulating layer 250. Furthermore, the side surface of the insulating layer 250 contacts the side surfaces of the insulating layer 280, the insulating layer 275, the insulating layer 271a, the insulating layer 271b, the conductive layer 242a2, and the conductive layer 242b2.

[0419] The insulating layer 250 is formed to reflect the shape of the opening 289. Therefore, the insulating layer 250 is formed to reflect the shapes of the conductive layers 242a1 and 242b1 protruding into the opening 289.

[0420] 25, in a cross-sectional view of the transistor 200D in the channel length direction, the distance L1 between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance L2 between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200D. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0421] 25, the width of the upper portion of the conductive layer 260 can be made larger than the distance L1, thereby reducing the wiring resistance of the conductive layer 260. As a result, the power consumption of the semiconductor device can be reduced.

[0422] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0423] [Oxide Semiconductor Layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0424] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0425] As described in the above embodiment, in an OS transistor, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0426] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0427] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0428] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Note that the lower limit of the hydrogen concentration in the channel formation region of the oxide semiconductor is not particularly limited, but is, for example, less than 1×10 １６ atoms / cm ３ It can be more than that.

[0429] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0430] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0431] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, the description in Embodiment 1 can be referred to.

[0432] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 254, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 284, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0433] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0434] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0435] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0436] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0437] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0438] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0439] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0440] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0441] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0442] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystalline structure, as this will result in the manifestation of ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0443] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0444] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0445] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0446] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0447] An insulating layer, such as a gate insulating layer, which is in contact with an oxide semiconductor layer or is provided near the oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For an insulating layer in which a region containing excess oxygen is easily formed, the description in Embodiment 1 can be referred to.

[0448] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0449] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0450] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0451] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0452] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0453] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0454] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0455] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0456] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0457] [Conductive Layer] For each of the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0458] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0459] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0460] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0461] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0462] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0463] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0464] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0465] 26A to 32. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0466] 26A to 26C , the structure of a memory device including a transistor and a capacitor will be described. Fig. 26A is a plan view of a memory device including a transistor 200 and a capacitor 100. Fig. 26B is a cross-sectional view taken along dashed line A1-A2 in Fig. 26A . Fig. 26C is a cross-sectional view taken along dashed line A3-A4 in Fig. 26A .

[0467] 26A to 26C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, and an insulating layer 280. The insulating layer 140 and the insulating layer 180 function as interlayer films. The conductive layer 110 functions as wiring.

[0468] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0469] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220_1 over the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. Note that the conductive layer 220_2 provided over the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0470] As shown in FIGS. 26B and 26C , an opening 190 reaching the conductive layer 110 is provided in the insulating layer 180. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. At least a portion of the insulating layer 130 is disposed so as to be located in the opening 190. At least a portion of the conductive layer 220_1 is disposed so as to be located in the opening 190. Note that, as shown in FIGS. 26B and 26C , the conductive layer 220_1 is preferably provided so as to fill the opening 190. Note that the films provided inside the openings 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed by an ALD method.

[0471] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0472] 26B and 26C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0473] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. In addition, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor 100 having such a configuration may be called a trench capacitor.

[0474] In addition, an insulating layer 280 is disposed over the capacitor 100. The insulating layer 280 has a portion located over the insulating layer 130 and a portion located over the conductive layer 220_2.

[0475] The transistor 200 includes a conductive layer 220 including a conductive layer 220_1 and a conductive layer 220_2, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0476] The detailed description of the transistor 200 will be omitted because the description in Embodiment 2 ( FIG. 4A ) can be referred to. The transistor included in the memory cell 150 is not limited to the transistor 200, and each of the transistors exemplified in Embodiment 2 can be applied.

[0477] As shown in FIGS. 26A to 26C , the transistor 200 is provided to overlap with the capacitor 100. Furthermore, an opening 290 where part of the structure of the transistor 200 is provided overlaps with an opening 190 where part of the structure of the capacitor 100 is provided. In particular, the conductive layer 220 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 26B and 26C show an example in which the width of the opening 190 is smaller than the width of the opening 290. The relationship between the width of the opening 190 and the width of the opening 290 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 be equal to or smaller than the width of the opening 290 .

[0478] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0479] 27A to 27C illustrate a memory device in which the transistor 200A described in Embodiment 2 is used as a transistor included in the memory cell 150. FIG. 27A is a plan view of a memory device including the transistor 200A and a capacitor 100. FIG. 27B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 27A. FIG. 27C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 27A.

[0480] 27B and 27C , a structure may be used in which the side edges of the insulating layer 130 and the conductive layer 220 coincide with each other. By using such a structure, the insulating layer 130 and the conductive layer 220 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.

[0481] 34A shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 34A, the configurations shown in FIGS. 26A to 26C function as memory cells. The memory cell 951 includes a transistor M1 and a capacitor CA. Here, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0482] One of the source and drain of the transistor M1 is connected to one of a pair of electrodes of the capacitor CA. The other of the source and drain of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor CA is connected to a wiring CAL.

[0483] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in FIGS. 26A to 26C , it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 240 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided intersecting each other. Also, in FIG. 26A , the wiring CAL (conductive layer 110) is provided parallel to the wiring WOL (conductive layer 260). However, the present invention is not limited to this. The wiring CAL may be provided parallel to the wiring BIL (conductive layer 240), for example.

[0484] The memory cells will be described in detail in a later embodiment.

[0485] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220_1. The conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0486] The conductive layer 110 functions as wiring CAL and can be provided in, for example, a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0487] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in [Conductive Layer] in Embodiment 2. For example, a conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0488] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is used in a single layer or a stacked layer. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 110. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 110.

[0489] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to be in contact with the top surface and side surfaces of the conductive layer 115. In other words, the insulating layer 130 preferably has a structure that covers the side end portions of the conductive layer 110. This can prevent a short circuit between the conductive layer 115 and the conductive layer 220_1.

[0490] Furthermore, a structure may be adopted in which the side edges of the insulating layer 130 and the conductive layer 115 coincide or substantially coincide with each other. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, which can simplify the manufacturing process of the memory device.

[0491] It is preferable to use a high-k material for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be sufficiently ensured.

[0492] The insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by stacking a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0493] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, see the description in the second embodiment.

[0494] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0495] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0496] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0497] The conductive layer 220_1 is provided in contact with a part of the upper surface of the insulating layer 130. The side end of the conductive layer 220_1 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction. Note that in a structure in which the insulating layer 130 covers the side end of the conductive layer 115, the side end of the conductive layer 220_1 may be located outside the side end of the conductive layer 115.

[0498] Since the insulating layer 180 functions as an interlayer film, it is preferable that the insulating layer 180 has a low relative dielectric constant. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low relative dielectric constant can be used as a single layer or a stacked layer.

[0499] 26B and 26C, the insulating layer 180 is shown as a single layer, but the present invention is not limited to this. The insulating layer 180 may have a stacked structure of two layers, or a stacked structure of three or more layers.

[0500] FIG. 28A shows an example in which the conductive layer 115 has a region 101 with rounded corners within a recess in the conductive layer 110. This allows for more suppression of electric field concentration in the insulating layer 130 near the region 101 than, for example, when the region 101 has a corner (right angle or acute angle) in cross-sectional view. Furthermore, the end 103 of the conductive layer 115 is located at a lower height from the reference plane than the top surface of the insulating layer 180. This allows for more suppression of electric field concentration in the insulating layer 130 near the end 103 than when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 prevents dielectric breakdown of the insulating layer 130, thereby providing a highly reliable memory device. The reference plane can be, for example, the top surface of the substrate or the top surface of the insulating layer 140.

[0501] 28B is a diagram showing an example in which end 103 shown in FIG. 28A is located on insulating layer 180. In the example shown in FIG. 28B, insulating layer 180 has a region 102 between the top surface and the side surface of opening 190, which has a curved portion. Also, in the example shown in FIG. 28B, end 103 has a tapered shape. By having region 102 have a curved portion and end 103 have a tapered shape, even when end 103 is located on insulating layer 180, electric field concentration in insulating layer 130 near region 102 and near end 103 can be suppressed. This suppresses dielectric breakdown of insulating layer 130, making it possible to provide a highly reliable memory device.

[0502] 28C is a diagram showing an example in which an insulating layer 187 is provided on the insulating layer 130 shown in FIG. 28B , for example, in a region of the insulating layer 130 that overlaps with the insulating layer 180. By providing the insulating layer 187, electric field concentration on the insulating layer 130 can be preferably suppressed in some cases.

[0503] <Structure Example 2 of Memory Device> FIGS. 29A and 29B are cross-sectional views of a memory device including a transistor 200a and a transistor 200b.

[0504] 29A and 29B includes an insulating layer 140 over a substrate (not shown), a memory cell 150 over the insulating layer 140, an insulating layer 280a over the insulating layer 140, and an insulating layer 280b above the insulating layer 280a. The insulating layer 140, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0505] The memory cell 150 includes a transistor 200a on the insulating layer 140 and a transistor 200b on the transistor 200a.

[0506] For the transistor 200a and the transistor 200b, the description of the transistor 200 ( FIG. 4A ) in Embodiment 2 can be referred to, and detailed description thereof will be omitted. For example, the configuration of the conductive layer 220a, the oxide semiconductor layer 230a, and the like can be referred to by replacing the conductive layer 220 with the conductive layer 220a and the oxide semiconductor layer 230 with the oxide semiconductor layer 230a, etc. Furthermore, for example, the configuration of the conductive layer 220b, the oxide semiconductor layer 230b, and the like can be referred to by replacing the conductive layer 220 with the conductive layer 220b and the oxide semiconductor layer 230 with the oxide semiconductor layer 230b, etc.

[0507] The insulating layer 280a and the insulating layer 280b can have the same structure as that used for the insulating layer 280.

[0508] The transistors included in the memory cell 150 are not limited to the combination of the transistor 200a and the transistor 200b, and one or more types of the transistors exemplified in Embodiment 2 can be used.

[0509] In the memory cell 150 shown in FIGS. 29A and 29B, capacitance generated between the conductive layer 220b and the conductive layer 240a can be used; therefore, data can be held without forming a separate capacitor.

[0510] The shortest distance from the top surface of the conductive layer 240a to the conductive layer 220b is preferably shorter than the shortest distance from the top surface of the conductive layer 240b to the gate wiring (conductive layer 260b in FIG. 29A ). This can increase the capacitance generated between the conductive layer 220b and the conductive layer 240a. Furthermore, the parasitic capacitance generated between the conductive layer 240b and the gate wiring can be reduced. For example, the structure of the transistor 200A described in Embodiment 2 can be applied to the transistor 200b.

[0511] As shown in FIGS. 29A and 29B , the transistor 200b is provided so as to overlap with the transistor 200a. Furthermore, an opening 290b in which part of the structure of the transistor 200b is provided overlaps with an opening 290a in which part of the structure of the transistor 200a is provided. In particular, the conductive layer 220b functions as one of the source electrode and drain electrode of the transistor 200b and as the gate electrode of the transistor 200a. Therefore, the transistors 200b and 200a share part of their structures. With this structure, the transistors 200b and 200a can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0512] 34E shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 34E, the configuration shown in FIGS. 29A and 29B functions as a memory cell. The memory cell 955 includes a transistor M2 and a transistor M3. Here, the transistor M2 corresponds to the transistor 200b, and the transistor M3 corresponds to the transistor 200a.

[0513] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M1 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.

[0514] Here, the wiring WBL corresponds to the conductive layer 240b, and the wiring WOL corresponds to the conductive layer 260b. As shown in Figures 29A and 29B, it is preferable that the conductive layer 260b is provided extending in the X direction, and the conductive layer 240b is provided extending in the Y direction. With this configuration, the wiring WBL and the wiring WOL are provided so as to intersect with each other.

[0515] The transistor M2 may have a back gate, and similarly, the transistor M3 may have a back gate.

[0516] <Configuration Example 3 of Memory Device> The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 has a low off-state current; therefore, by using the transistor 200 in a memory device, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 enable high-speed reading and writing of data from and to the memory device.

[0517] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.

[0518] 30A is a plan view of a memory device, showing an example in which 2×2 memory cells (memory cells 150a to 150d) are arranged in the X and Y directions.

[0519] Fig. 30B is a cross-sectional view taken along dashed line A3-A4 in Fig. 30A. In Fig. 30A and Fig. 30B, two memory cells (memory cell 150a and memory cell 150b in Fig. 30B) are connected to a common wiring (conductive layer 246).

[0520] A circuit diagram corresponding to two memory cells is shown in Figure 34B. As shown in Figure 34B, the memory device 952 has two memory cells, one of which has a transistor M1 and a capacitor CA1, and the other of which has a transistor M2 and a capacitor CA2. For example, when comparing Figure 34B with Figure 30B, the transistor M1 corresponds to the transistor 200a, the capacitor CA1 corresponds to the capacitor 100a, the transistor M2 corresponds to the transistor 200b, and the capacitor CA2 corresponds to the capacitor 100b.

[0521] One of the source and drain of transistor M1 is connected to one of a pair of electrodes of capacitor CA1. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL1. The other of the pair of electrodes of capacitor CA1 is connected to wiring CAL. One of the source and drain of transistor M2 is connected to one of a pair of electrodes of capacitor CA2. The other of the source and drain of transistor M2 is connected to wiring BIL. The gate of transistor M2 is connected to wiring WOL2. The other of the pair of electrodes of capacitor CA2 is connected to wiring CAL.

[0522] Here, the wiring BIL corresponds to the conductive layer 240 , the wiring WOL 1 corresponds to the conductive layer 260 , the wiring WOL 2 corresponds to another conductive layer 260 , and the wiring CAL corresponds to the conductive layer 110 .

[0523] Each of the memory cells 150a and 150b shown in Figures 30A and 30B has a configuration similar to that of the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. The memory cells 150c and 150d shown in Figure 30A also have a configuration similar to that of the memory cell 150. Therefore, in the memory device shown in Figures 30A and 30B, structures having the same functions as those of the structures constituting the memory device shown in Figures 26A to 26C are denoted by the same reference numerals. For details of the memory cells 150a to 150d, the description of the memory cell 150 in <Configuration Example 1 of Memory Device> can be referred to.

[0524] 30A and 30B , a conductive layer 260 functioning as a wiring WOL is provided in each of the memory cells 150a and 150b. As shown in FIG. 30A , one conductive layer 260 is provided in common to the memory cells 150a and 150c, and another conductive layer 260 is provided in common to the memory cells 150b and 150d. One conductive layer 240 functioning as part of the wiring BIL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the memory cell 150a and the oxide semiconductor layer 230 of the memory cell 150b. The other conductive layer 240 is provided in common to the memory cells 150c and 150d.

[0525] FIG. 30B shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1.

[0526] 30A and 30B includes conductive layers 245 and 246 which are connected to the memory cell 150a and the memory cell 150b and function as plugs (also referred to as connection electrodes). The conductive layer 245 is disposed in openings formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, and the insulating layer 280, and is in contact with the bottom surface of the conductive layer 240_1. The conductive layer 246 is disposed in openings formed in the insulating layer 286, the insulating layer 250, and the oxide semiconductor layer 230, and is in contact with the top surface of the conductive layer 240_2. Note that the conductive layers 245 and 246 can be formed using a conductive material that can be used for the conductive layer 240, or the like.

[0527] The conductive layer 246 can be in contact with the top surface of the conductive layer 240_1. Alternatively, the conductive layer 246 can be in contact with the top surface of the oxide semiconductor layer 230. That is, the conductive layer 240_2 may have an opening at a position overlapping with the conductive layer 246. The oxide semiconductor layer 230 does not necessarily have an opening at a position overlapping with the conductive layer 246. As a connection portion between the memory cell and the plug, a layer having low contact resistance with the conductive layer 246 among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 is preferably in contact with the conductive layer 246.

[0528] Similarly, the conductive layer 245 can be in contact with a bottom surface of the conductive layer 240_2 or a bottom surface of the oxide semiconductor layer 230. That is, the conductive layer 240_1 may have an opening at a position overlapping with the conductive layer 246. Of the layers constituting the conductive layer 240 and the oxide semiconductor layer 230, a layer having low contact resistance with the conductive layer 245 is preferably in contact with the conductive layer 245.

[0529] Of the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 , a layer having low wiring resistance is preferably in contact with the conductive layer 245 and the conductive layer 246 .

[0530] The conductive layers 245 and 246 function as plugs or wirings for connecting circuit elements, wirings, electrodes, or terminals, such as switches, transistors, capacitors, inductors, resistors, and diodes, to the memory cells 150a and 150b. For example, the conductive layer 245 can be connected to a sense amplifier (not shown) provided below the memory device shown in FIG. 30B, and the conductive layer 246 can be connected to a similar memory device (not shown) provided above the memory device shown in FIG. 30B. In this case, the conductive layers 245 and 246 function as part of the wiring BIL. In this way, by providing a memory device above or below the memory device shown in FIG. 30B, the memory capacity per unit area can be increased.

[0531] The memory cell 150a and the memory cell 150b are symmetrical with respect to the perpendicular bisector of the dashed-dotted line A3-A4. Therefore, the transistor 200a and the transistor 200b are also arranged symmetrically with the conductive layer 245 and the conductive layer 246 sandwiched therebetween. The conductive layer 240 functions as the other of the source and drain electrodes of the transistor 200a and the other of the source and drain electrodes of the transistor 200b. The transistor 200a and the transistor 200b share the conductive layer 245 and the conductive layer 246, which function as plugs. By configuring the connections between the two transistors and the plugs as described above, a memory device that can be miniaturized or highly integrated can be provided.

[0532] Note that the conductive layer 110 functioning as the wiring CAL may be provided in each of the memory cells 150 a and 150 b, or may be provided in common to the memory cells 150 a and 150 b. However, as shown in FIG. 30B , the conductive layer 110 is provided apart from the conductive layer 245 to prevent a short circuit between the conductive layer 110 and the conductive layer 245.

[0533] 27A to 27C may be used as the memory cell shown in Figures 30A and 30B. By configuring the side edge of the insulating layer 130 to coincide with the side edge of the conductive layer 220, the insulating layer 130 does not overlap with the conductive layer 245. This makes it relatively easy to process the opening in which the conductive layer 245 is to be provided.

[0534] 31 shows an example in which the four memory cells shown in FIG. 30A are stacked in n layers (n is an integer of 3 or more) in the Z direction. FIG. 31 is a cross-sectional view taken along dashed line A3-A4 shown in FIG. 30A.

[0535] The memory device shown in Figure 31 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided at the top. The number of memory cells included in one memory layer 160 is not particularly limited, and two or more memory cells may be included. The memory cells included in the n memory layers 160 are connected to a sense amplifier (not shown) provided below the n memory layers 160 by conductive layers 245, 246, 247, etc.

[0536] 31 shows an example in which the conductive layer 245 is in contact with the bottom surface of the conductive layer 240 and the conductive layer 246 is in contact with the top surface of the oxide semiconductor layer 230. As described above, various modes are possible for the connection points between the plugs such as the conductive layer 245 and the conductive layer 246 and each memory cell, and are not limited to the configuration in FIG.

[0537] 31, by stacking a plurality of memory cells, the cells can be integrated and arranged without increasing the area occupied by the memory cell array, that is, a 3D memory cell array can be configured.

[0538] FIG. 32 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0539] In FIG. 32, a memory cell 150 (a transistor 200 and a capacitor 100 ) is provided above a transistor 300 .

[0540] The transistor 300 is one of the transistors included in the sense amplifier.

[0541] For the memory cell 150 shown in FIG. 32, the description of the memory cell 150 in <Configuration example 1 of memory device> can be referred to.

[0542] 32, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cells 150. This reduces the bit line capacitance, enabling the memory device to be driven at high speed.

[0543] 32 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0544] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0545] Here, in the transistor 300 shown in FIG. 32 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0546] Note that the transistor 300 illustrated in FIG. 32 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0547] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0548] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0549] The insulating layer serving as an interlayer film may also serve as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0550] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 32, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0551] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0552] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0553] The conductive layer 240 of the transistor 200 is connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0554] The conductive layer 643 is buried in the insulating layer 280. The conductive layer 642 is provided over the insulating layer 130 and is buried in the insulating layer 280. The conductive layer 642 can be manufactured using the same material and in the same process as the conductive layer 220. The conductive layer 644 is buried in the insulating layer 180 and the insulating layer 130. The conductive layer 645 is buried in the insulating layer 180. The conductive layer 645 can be manufactured using the same material and in the same process as the conductive layer 110. The conductive layer 646 is buried in the insulating layer 648. The transistor 300 and the conductive layer 110 are insulated by the insulating layer 648.

[0555] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0556] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0557] Fig. 33 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 33 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 33 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0558] The memory cell 950 can be any of the memory devices described in Embodiment 3 (such as the memory cell 150 ).

[0559] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0560] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0561] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0562] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0563] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0564] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0565] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0566] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0567] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential).ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 33, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0568] 34A to 34G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0569] 34A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0570] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0571] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0572] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0573] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the ...

Claims

having a transistor, The transistor is a first insulating layer; a second insulating layer; an oxide semiconductor layer located between the first insulating layer and the second insulating layer, the oxide semiconductor layer having a portion in contact with the first insulating layer and a portion in contact with the second insulating layer; a conductive layer overlapping the oxide semiconductor layer with the second insulating layer interposed therebetween, the first insulating layer has a function of supplying oxygen to the oxide semiconductor layer, the oxide semiconductor layer includes an indium oxide film, the second insulating layer has a function of capturing either oxygen or hydrogen or both from the oxide semiconductor layer; a gallium concentration in a channel formation region of the oxide semiconductor layer is 0.1 atomic % or less. 　 having a transistor, The transistor is a first insulating layer; a second insulating layer; an oxide semiconductor layer located between the first insulating layer and the second insulating layer, the oxide semiconductor layer having a portion in contact with the first insulating layer and a portion in contact with the second insulating layer; a conductive layer overlapping the oxide semiconductor layer with the second insulating layer interposed therebetween, the first insulating layer includes a silicon oxide film; the oxide semiconductor layer includes an indium oxide film, the second insulating layer has an aluminum oxide film or a hafnium oxide film, a gallium concentration in a channel formation region of the oxide semiconductor layer is 0.1 atomic % or less. 　 In claim 1 or claim 2, The semiconductor device, wherein the concentration of gallium in the channel formation region of the oxide semiconductor layer is measured by analysis using secondary ion mass spectrometry, X-ray photoelectron spectroscopy, or inductively coupled plasma mass spectrometry. 　 In claim 1 or claim 2, the concentration of gallium in the first insulating layer is 0.1 atomic % or less; The semiconductor device, wherein the concentration of gallium in the second insulating layer is 0.1 atomic % or less. 　 In claim 1 or claim 2, The semiconductor device, wherein the oxide semiconductor layer has a region with a film thickness of 2.5 nm to 20 nm. 　 In claim 1 or claim 2, The semiconductor device, wherein the oxide semiconductor layer has a crystalline portion. 　 In claim 1 or claim 2, The semiconductor device, wherein the oxide semiconductor layer has a polycrystalline structure. 　 a first insulating layer; a second insulating layer; an oxide semiconductor layer located between the first insulating layer and the second insulating layer, the oxide semiconductor layer having a portion in contact with the first insulating layer and a portion in contact with the second insulating layer, forming the first insulating layer by atomic layer deposition using a first precursor containing silicon and a first oxidizing agent; forming the oxide semiconductor layer by atomic layer deposition using a second precursor containing indium and a second oxidizing agent; a third oxidizing agent and a third precursor containing aluminum or hafnium, and the second insulating layer is formed by atomic layer deposition. 　 In claim 8, a second insulating layer formed on the second insulating layer by thermal atomic layer deposition without exposure to the atmosphere; 　 In claim 8, The method for manufacturing a semiconductor device, wherein the purity of the source gas containing the second precursor is 5N or more. 　 In claim 8, The method for manufacturing a semiconductor device, wherein the second oxidizing agent includes ozone.

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