Semiconductor integrated circuit device

Abstract

A cell row (CR) includes an inverter cell (C1) having a logical function, and a termination cell (C3) disposed at least on one of both ends of the cell row (CR) and having no logical function. The inverter cell (C1) is provided with an active region (2P1) and power supply wiring (11) formed in a back surface wiring layer. The termination cell (C3) is provided with an active region (2P3). In a second direction, an end on a first side and an end on a second side of the active region (2P1) are disposed between an end on the first side and an end on the second side of the active region (2P3).

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter, also simply referred to as a cell, as appropriate) that includes a fork-sheet transistor.

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Standard cells include cells with logic functions such as NAND gates and NOR gates (hereinafter referred to as logic cells, as appropriate), as well as cells without logic functions. An example of a cell without logic functions is a "termination cell." A "termination cell" is a cell that does not contribute to the logic function of a circuit block and is used to terminate the circuit block. By placing a termination cell, it is possible to suppress variations in the finished shape of the layout pattern of cells located inside the termination cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0005] Patent Document 1 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a gate electrode in a fork shape, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 1 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0006] Japanese Patent Application Laid-Open No. 2003-144222 discloses a standard cell in which a backside wiring is provided on the backside immediately below a transistor in order to reduce the area of ​​the semiconductor integrated circuit device, and the source and drain of the transistor are connected to this wiring.

[0007] International Publication No. 2021 / 075434 U.S. Patent Application Publication No. 2022 / 0375761

[0008] However, no specific study has been done on termination cells using fork-sheet transistors and backside wiring.

[0009] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including a termination cell using a fork-sheet transistor and backside wiring.

[0010] In a first aspect of the present disclosure, there is provided a semiconductor device comprising a plurality of cell rows each including a plurality of standard cells arranged side by side in a first direction, wherein a first cell row being one of the plurality of cell rows comprises a first standard cell having a logic function and a second standard cell arranged at at least one end of the first cell row and not having a logic function, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, and the channel comprises a first active region including a first nanosheet extending in the first direction, a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction, a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage, and the first power supply wiring is formed in a region in the first active region where a region serving as a source of the first transistor overlaps with the first power supply wiring, and and a first via connecting the source of the first transistor and the first power supply wiring, the first nanosheet having a first side surface that is one side in the second direction exposed from the first gate wiring, the second standard cell constituting the channel, source, and drain of a first dummy transistor of a first conductivity type, the second active region including a second nanosheet extending in the first direction as the channel, a first dummy gate wiring that extends in the second direction and surrounds the periphery of the second nanosheet in the second direction and the third direction, and a second power supply wiring that is formed on the back side of the first dummy transistor, extends in the first direction, and supplies the first power supply voltage, the first side surface of the second nanosheet being exposed from the first dummy gate wiring, and the first side end and the second side end of the first active region are arranged between the first side end of the second active region and the second side end of the second active region that is the other side in the second direction.

[0011] According to the present disclosure, the first and second ends of the first active region of the first standard cell having a logic function are arranged between the first and second ends of the second active region of the second standard cell not having a logic function. By arranging the second standard cell at at least one of the two ends of the first cell row, the second active region of the second standard cell can be arranged along the entire side surface in the first direction of the first active region of the first standard cell. Therefore, the distance from the first active region of the first standard cell to the second active region of the second standard cell is set to a predetermined value. This improves the accuracy of estimating the transistor performance of standard cells having a logic function.

[0012] In a second aspect of the present disclosure, there is provided a semiconductor device including a plurality of standard cells arranged side by side in a first direction, and a plurality of cell rows arranged side by side in a second direction perpendicular to the first direction, the plurality of cell rows including a first cell row including first and third standard cells having a logic function, and a second cell row arranged at either end of the plurality of cell rows in the second direction and including a second standard cell having no logic function, the first standard cell constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in the first direction, a first gate wiring extending in the second direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction, a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage, and formed in a region where a region in the first active region that serves as a source of the first transistor and the first power supply wiring overlap, a first via connecting a source of a first transistor and the first power supply wiring, the first nanosheet having a first surface on one side in the second direction exposed from the first gate wiring; the second standard cell constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the second active region including a second nanosheet extending in the first direction as the channel; a first dummy gate wiring extending in the second direction and surrounding an outer periphery of the second nanosheet in the second direction and the third direction; and a second power supply wiring formed on a back surface side of the first dummy transistor, extending in the first direction, and supplying the first power supply voltage, the second nanosheet having a second surface on the other side in the second direction exposed from the first dummy gate wiring;a fifth power supply wiring formed on the back surface side of the third transistor, extending in the first direction, and supplying the first power supply voltage; and a third via formed in a region in the fifth active region where a region serving as a source of the third transistor and the fifth power supply wiring overlap, connecting the source of the third transistor in the fifth active region and the fifth power supply wiring, wherein the surface on the first side of the fifth nanosheet is exposed from the third gate wiring, and in a plan view, the width of the first active region in the second direction is the same as the width of the second active region in the second direction and is larger than the width of the fifth active region in the second direction.

[0013] According to the present disclosure, it is possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions in the layout of a semiconductor integrated circuit device including a termination cell using fork sheet transistors and backside wiring.

[0014] 10 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment. FIG. 11 is a plan view of portion A1 in FIG. 1 . FIG. 12 is a cross-sectional view of FIG. 2 . FIG. 2 is a circuit diagram of an inverter cell. FIG. 12 is a plan view of portion A2 in FIG. 1 . FIG. 13 is a plan view showing another example of the layout structure of a termination cell C3 according to a modified example of the first embodiment. FIG. 14 is a plan view of portion A3 in FIG. 1 . FIG. 15 is a plan view showing another example of the layout structure of a termination cell C4 according to a modified example of the first embodiment. FIG. 16 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the second embodiment. FIG. 17 is a plan view of portion A4 in FIG. 10 . FIG. 18 is a plan view of portion A5 in FIG. 10 . FIG. 19 is a plan view of portion A6 in FIG. 10 . FIG. 19 is a plan view showing another example of the layout structure of a termination cell C8 according to a modified example of the second embodiment.

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells, and at least some of the plurality of standard cells include fork sheet transistors, which are nanosheet FETs and have fork-shaped gate electrodes. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0017] 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a first embodiment. Note that in FIG. 1, only power supply wiring formed in a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed is shown, and other components are omitted.

[0018] 1 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a wiring layer (backside wiring layer) provided on the back side of the semiconductor chip on which the transistors are formed.

[0019] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0020] 1 and dashed lines surrounding cells in plan views such as Fig. 2 indicate the cell frame (outer edge of the standard cell) of the standard cell. A standard cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0021] 1, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The cells include standard cells with logic functions such as NAND gates and NOR gates, and termination cells with no logic functions.

[0022] Here, a "terminal cell" refers to a cell that does not contribute to the logical function of the circuit block and is arranged at the end of the circuit block. Here, the "end of the circuit block" refers to both ends of the cell row that constitutes the circuit block (here, both ends in the X direction), as well as the top and bottom rows of the circuit block (here, both end cell rows in the Y direction). In other words, a "terminal cell" is arranged at the end of the cell row, which is the end of the circuit block, such as both ends in the X direction or both end cell rows in the Y direction. By arranging the terminal cell, it is possible to suppress variation in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variation in semiconductor integrated circuit devices and improving yield and reliability.

[0023] In the layout of FIG. 1 , a rectangular logic unit LC, which includes logic cells having logic functions and realizes the circuit functions, is arranged in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C1 and C2 are arranged in the logic unit LC. Termination cells C3 and C4 are arranged in the termination cell unit. Specifically, termination cells C3 are arranged on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C4 are arranged in the cell rows CR arranged in the top and bottom rows of the circuit block in the Y direction.

[0024] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0025] (Configuration of inverter cell C1) Fig. 2 is a plan view of portion A1 in Fig. 1, Fig. 3 is a cross-sectional view in Fig. 2, and Fig. 4 is a circuit diagram configured in the inverter cell. Specifically, Fig. 3(a) is a cross-section taken along line X1-X1' in Fig. 2, Fig. 3(b) is a cross-section taken along line Y1-Y1' in Fig. 2, and Fig. 3(c) is a cross-section taken along line Y2-Y2' in Fig. 2.

[0026] In the following description, dashed lines running vertically and horizontally in plan views such as Figure 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0027] As shown in FIG. 4, the inverter cell C1 has transistors P1 and N1, and an inverter circuit with an input A and an output Y is configured.

[0028] As shown in FIGS. 1 and 2, the inverter cell C1 is arranged at the left end of the logic section LC in the drawing, and the termination cell C3 is arranged adjacent to it on the left side.

[0029] 2, a BM0 wiring layer, which is a wiring layer, is formed on the back surface of the semiconductor chip on which the transistors are formed. In the BM0 wiring layer, power supply wirings 11 and 12 extending in the X direction are formed at both ends of the cell in the Y direction in the drawing. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS. The power supply wirings 11 and 12 are shared with other cells in the cell string CR including the inverter cell C1, and serve as power supply wirings extending in the X direction.

[0030] An active region constituting the channel, source, and drain of the P-type transistor is formed in a P-type transistor region on an N-type well (NWell). Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0031] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2P1, the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in the region where the power supply wiring 11 and the active region 2P1 overlap in a planar view.

[0032] An active region constituting the channel, source, and drain of the N-type transistor is formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 overlaps with the power supply wiring 12 in a plan view.

[0033] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has a channel made of a nanosheet 22 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2N1, the source of the transistor N1 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in the region where the power supply wiring 12 and the active region 2N1 overlap in a planar view.

[0034] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0035] Gate wirings 31a and 31b extending in the Y direction are formed in the center of the cell in the X direction. The nanosheet 21 overlaps with the gate wiring 31a in a planar view. The nanosheet 22 overlaps with the gate wiring 31b in a planar view. The gate wiring 31a corresponds to the gate of transistor P1. The gate wiring 31b corresponds to the gate of transistor N1.

[0036] Similar to the dummy gate wirings 131a to 131a and 131b to 133b described below, the gate wirings 31a and 31b cover the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions, respectively, so as to expose a portion of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower surface of the nanosheet 21 in the Y direction is exposed from the gate wiring 31a, and the upper surface of the nanosheet 21 in the Y direction is covered by the gate wiring 31a. The upper surface of the nanosheet 22 in the Y direction is exposed from the gate wiring 31b, and the lower surface of the nanosheet 22 in the Y direction is covered by the gate wiring 31b.

[0037] The gate wirings 31a and 31b are connected via a bridge portion 31c extending in the Y direction.

[0038] Dummy gate wirings 32a and 32b are formed on the cell frame on the left side of the drawing in the X direction. Dummy gate wirings 33a and 33b are formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wirings 32a and 32b are shared with other cells arranged on the left side of the drawing. The dummy gate wirings 33a and 33b are shared with other cells arranged on the right side of the drawing. The dummy gate wirings 32a and 32b are connected via a bridge portion 32c extending in the Y direction. The dummy gate wirings 33a and 33b are connected via a bridge portion 33c extending in the Y direction.

[0039] The local interconnect layer has a local interconnect (LI) 41 extending in the Y direction. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1 and a portion of the active region 2N1 that serves as the drain of the transistor N1.

[0040] Wirings 51 and 52 extending in the X direction are formed in the M0 wiring layer, which is a metal wiring layer above the local wiring layer. Wiring 51 is connected to gate wiring 31b through a via. Wiring 52 is connected to local wiring 41 through a via. Wiring 51 corresponds to input A, and wiring 52 corresponds to output Y.

[0041] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0042] As shown in FIG. 2, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0043] (Configuration of Inverter Cell C2) FIG. 5 is a plan view of portion A2 in FIG.

[0044] As shown in FIGS. 1 and 5, the inverter cell C2 is arranged at the left end of the logic section LC in the drawing, and the termination cell C3 is arranged adjacent to it on the left side.

[0045] The inverter cell C2 has a configuration similar to that of the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C2 is a standard cell having a logic function.

[0046] As shown in FIG. 5, the inverter cell C2 is different from the inverter cell C1 shown in FIG. 2 in that active regions 2P2 and 2N2 having different widths in the Y direction are arranged in place of the active regions 2P1 and 2N1.

[0047] Specifically, the active regions 2P2 and 2N2 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0048] 2 and 5, the bottom end (top end) of the active region 2P2 (2N2) in the Y direction is located at the same position in the Y direction as the bottom end (top end) of the active region 2P1 (2N1) in the Y direction. That is, the bottom end (top end) of the active region 2P1 (2N1) in the Y direction of the inverter cell C1 and the bottom end (top end) of the active region 2P2 (2N2) in the Y direction of the inverter cell C2 are aligned in the Y direction.

[0049] In the inverter cell C1 of FIG. 2 (inverter cell C2 of FIG. 5), the nanosheet 21 has a lower surface in the Y direction exposed from the gate wiring 31a. The nanosheet 22 has an upper surface in the Y direction exposed from the gate wiring 31b. That is, the surfaces of the nanosheets 21 and 22 that face each other in the Y direction are exposed from the gate wiring 31a and 31b, respectively. This allows the distance d1 in the Y direction between the active regions 2P1 and 2N1 (2P2 and 2N2) in the inverter cell C1 (C2) to be reduced. This allows the area of ​​the semiconductor integrated circuit device to be reduced.

[0050] In the inverter cell C1 of FIG. 2 (inverter cell C2 of FIG. 5), the upper surface of the nanosheet 21 in the Y direction is covered by the gate wiring 31a. The lower surface of the nanosheet 22 in the Y direction is covered by the gate wiring 31b. Each cell row CR is arranged inverted in the Y direction, every other row. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their opposing surfaces not exposed from the gate wiring. Therefore, the distance in the Y direction between the active regions of cells adjacent to each other in the Y direction is greater than the distance d1 in the Y direction between the active regions 2P1, 2N1 (2P2, 2N2) in the inverter cell C1 (C2).

[0051] In addition, in the inverter cell C1 of FIG. 2 (inverter cell C2 of FIG. 5), the distance d2 in the Y direction between the power supply wiring 11 and 12 formed in the BM0 wiring layer is greater than the distance d1 in the Y direction between the active regions 2P1 and 2N1 (2P2 and 2N2). That is, in a plan view, the bottom end of the power supply wiring 11 in the Y direction is located above the bottom end of the active region 2P1 (2P2) in the Y direction. In a plan view, the top end of the power supply wiring 12 in the Y direction is located below the top end of the active region 2N1 (2N2) in the Y direction. In other words, in a plan view, the bottom end of the active region 2P1 (2P2) and the top end of the active region 2N1 (2N2) are located between the bottom end of the power supply wiring 11 and the top end of the power supply wiring 12 (i.e., inside the power supply wiring 11 and 12).

[0052] (Configuration of Terminating Cell C3) As shown in FIG. 1, the terminating cells C3 are arranged on both the left and right ends of the cell row CR in the X direction.

[0053] 2 and 5, power supply wirings 11 and 12 extending in the X direction are formed on both ends of the cell in the Y direction in the drawing in the BM0 wiring layer. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0054] An active region 2P3 is formed in the P-type transistor region. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0055] P-type dummy transistors DP1 to DP3 are formed in the active region 2P3. The dummy transistors DP1 to DP3 each have a channel made of three overlapping sheets in a plan view, and have nanosheets 121 to 123 extending in the X direction.

[0056] An active region 2N3 is formed in the N-type transistor region. The active region 2N3 overlaps with the power supply wiring 12 in plan view.

[0057] N-type dummy transistors DN1 to DN3 are formed in the active region 2N3. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0058] Dummy gate wirings 131a to 133a and 131b to 133b are formed extending in the Y and Z directions. The nanosheets 121 to 126 overlap the dummy gate wirings 131a to 133a and 131b to 133b, respectively, in a plan view. The dummy gate wirings 131a to 133a and 131b to 133b correspond to the gates of the dummy transistors DP1 to DP3 and DN1 to DN3, respectively.

[0059] As shown in FIG. 3C, dummy gate wirings 132a and 132b cover the outer peripheries of nanosheets 122 and 125 in the Y and Z directions, respectively, so that portions of the outer peripheries of nanosheets 122 and 125 are exposed. Specifically, the side surface of nanosheet 122 on the right side in the drawing is not covered by dummy gate wiring 132a. The side surface of nanosheet 125 on the left side in the drawing is not covered by dummy gate wiring 132b. In other words, the side surface of nanosheet 122 on the right side in the drawing is exposed from dummy gate wiring 132a. The side surface of nanosheet 125 on the left side in the drawing is exposed from dummy gate wiring 132b. Therefore, in FIG. 2, the side surface of nanosheet 122 on the lower side in the drawing is not covered by dummy gate wiring 132a. The side surface of nanosheet 125 on the upper side in the drawing is not covered by dummy gate wiring 132b. That is, the lower surface of nanosheet 122 in the Y direction is exposed from dummy gate wiring 132a, and the upper surface of nanosheet 125 in the Y direction is covered by dummy gate wiring 132a. The upper surface of nanosheet 125 in the Y direction is exposed from dummy gate wiring 132b, and the lower surface of nanosheet 125 in the Y direction is covered by dummy gate wiring 132b. Similarly, dummy gate wirings 131a, 133a, 131b, and 133b cover the outer peripheries of nanosheets 121, 123, 124, and 126 in the Y and Z directions, respectively, so that portions of the outer peripheries of nanosheets 121, 123, 124, and 126 are exposed, respectively. In FIG. 2, the lower surfaces of nanosheets 121 and 123 in the Y direction are exposed from dummy gate wirings 131a and 133a, respectively, and the upper surfaces of nanosheets 121 and 123 in the Y direction are covered by dummy gate wirings 131a and 133a, respectively. The upper surfaces of the nanosheets 124 and 126 in the Y direction are exposed from the dummy gate wirings 131b and 133b, respectively, and the lower surfaces of the nanosheets 124 and 126 in the Y direction are covered by the dummy gate wirings 131b and 133b, respectively.

[0060] The dummy gate wirings 131a and 131b are connected via a bridge portion 131c. The dummy gate wirings 132a and 132b are connected via a bridge portion 132c. The dummy gate wirings 133a and 133b are connected via a bridge portion 133c.

[0061] Dummy gate wirings 134a and 134b are formed on the cell frame on the left side of the drawing in the X direction. Dummy gate wirings 135a and 135b are formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wirings 135a and 135b are shared with other cells (inverter cell C1 in FIG. 2 and inverter cell C2 in FIG. 5) arranged on the right side of the drawing. The dummy gate wirings 134a and 134b are connected via a bridge portion 134c extending in the Y direction. The dummy gate wirings 135a and 135b are connected via a bridge portion 135c extending in the Y direction.

[0062] Local wirings 141 to 144 extending in the Y direction are formed in the local wiring layer. Local wiring 141 is connected to a portion that will become the source of dummy transistor DP1 in active region 2P3 and a portion that will become the source of dummy transistor DN1 in active region 2N3. Local wiring 142 is connected to a portion that will become the drain of dummy transistor DP1 and a portion that will become the source of dummy transistor DP2 in active region 2P3, and to a portion that will become the drain of dummy transistor DN1 and a portion that will become the source of dummy transistor DN2 in active region 2N3. Local wiring 143 is connected to a portion that will become the drain of dummy transistor DP2 and a portion that will become the source of dummy transistor DP3 in active region 2P3, and to a portion that will become the drain of dummy transistor DN2 and a portion that will become the source of dummy transistor DN3 in active region 2N3. The local wiring 144 is connected to a portion that serves as the drain of the dummy transistor DP3 in the active region 2P3 and a portion that serves as the drain of the dummy transistor DN3 in the active region 2N3.

[0063] 2 and 5, unlike the inverter cells C1 and C2, the dummy gate wirings 131a to 133a, 131b to 133b and the local wirings 141 to 144 are not connected to other wirings. In other words, the termination cell C3 is a standard cell that does not have a logic function.

[0064] Furthermore, nanosheets 121 to 126 are formed in the same layer as nanosheets 21 and 22. The bottom ends of nanosheets 121 to 123 in the drawing are aligned in the Y direction with the bottom end of nanosheet 21. The top ends of nanosheets 124 to 126 in the drawing are aligned in the Y direction with the top end of nanosheet 22 in the drawing.

[0065] Furthermore, the dummy gate wirings 131a to 134a and 131b to 134b are formed in the same layer as the gate wirings 31a and 31b and the dummy gate wirings 32a (135a), 33a, 32b (135b), and 33b. The dummy gate wirings 131a to 134a are formed at the same positions in the Y direction as the gate wiring 31a and the dummy gate wirings 32a (135a), and 33a, and are arranged at equal intervals in the X direction. The dummy gate wirings 131b to 134b are formed at the same positions in the Y direction as the gate wiring 31b and the dummy gate wirings 32b (135b), and 33b, and are arranged at equal intervals in the X direction.

[0066] The upper and lower ends of the dummy gate wirings 131a to 134a are aligned in the Y direction with the upper and lower ends of the gate wiring 31a and the dummy gate wirings 32a (135a) and 33a, respectively. The upper and lower ends of the dummy gate wirings 131b to 134b are aligned in the Y direction with the upper and lower ends of the gate wiring 31b and the dummy gate wirings 32b (135b) and 33b, respectively.

[0067] The local wirings 141 to 144 are formed in the same layer as the local wiring 41. The local wirings 141 to 144 are arranged at equal pitches in the X direction.

[0068] In the block layout of FIG. 1 , the terminal cell C3, which does not have a logic function, is arranged adjacent to the inverter cell C1, which has a logic function. The nanosheets 121-123 (124-126) of the terminal cell C3 are arranged in the same position in the Y direction as the nanosheet 21 (22) of the inverter cell C1. The nanosheets 21, 121-123 have their lower surfaces exposed from the gate wiring 31a and dummy gate wiring 131a-133a, respectively. The nanosheets 22, 124-126 have their upper surfaces exposed from the gate wiring 31b and dummy gate wiring 131b-133b, respectively. In other words, the nanosheets 21, 121-123 arranged in the same position in the Y direction have their surfaces on the same side in the Y direction exposed from the gate wiring 31a and dummy gate wiring 131a-133a, respectively. The nanosheets 22, 124 to 126 arranged at the same position in the Y direction have the same surfaces in the Y direction exposed from the gate wiring 31b and the dummy gate wirings 131b to 133b, respectively, which makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices, improve yields, and enhance reliability.

[0069] Furthermore, the opposing surfaces of the nanosheets 21 and 22 of the inverter cell C1 (C2) are exposed from the gate wirings 31a and 31b, respectively. The opposing surfaces of the nanosheets 121 and 124 of the terminal cell C3 are exposed from the dummy gate wirings 131a and 131b, respectively. The opposing surfaces of the nanosheets 122 and 125 of the terminal cell C3 are exposed from the dummy gate wirings 132a and 132b, respectively. The opposing surfaces of the nanosheets 123 and 126 of the terminal cell C3 are exposed from the dummy gate wirings 133a and 133b, respectively. This eliminates the need for overlapping gate wiring between the nanosheets 21 and 22, between the nanosheets 121 and 124, between the nanosheets 122 and 125, and between the nanosheets 123 and 126, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced.

[0070] Furthermore, the dummy gate wirings 131a-134a and 131b-134b of the terminal cell C3 are formed in the same layer as the gate wirings 31a and 31b and dummy gate wirings 32a (135a), 33a, 32b (135b), and 33b of the inverter cells C1 and C2. The local wirings 141-144 of the terminal cell C3 are formed in the same layer as the local wiring 41 of the inverter cells C1 and C2. That is, by forming the dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cells, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0071] Furthermore, the active regions 2P3 and 2N3 of the termination cell C3 are arranged close to the dummy gate wirings 32a (135a) and 32b (135b) that are arranged on the boundaries between the inverter cells C1 and C2 and the termination cell C3, respectively. That is, by providing the termination cell with an active region, the distance from the cell arranged at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0072] Furthermore, the lower end (upper end) in the Y direction of the active region 2P1 (2N1) of the inverter cell C1, the lower end (upper end) in the Y direction of the active region 2P2 (2N2) of the inverter cell C2, and the lower end (upper end) in the Y direction of the active region 2P3 (2N3) of the termination cell C3 are arranged at the same position in the Y direction. That is, the lower end (upper end) in the Y direction of the active region 2P1 (2N1) of the inverter cell C1, the lower end (upper end) in the Y direction of the active region 2P2 (2N2) of the inverter cell C2, and the lower end (upper end) in the Y direction of the active region 2P3 (2N3) of the termination cell C3 are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C1 and C2 and the nanosheets 121-123 (124-126) of the terminal cell C3 have their lower (upper) surfaces in the Y direction exposed from the gate wiring 31a (31b) and dummy gate wiring 131a-133a (131b-133b), respectively. That is, in the inverter cells C1, C2, and terminal cell C3, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. In a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row CR in which standard cells are arranged in the X direction, as in the configurations of Figures 2 and 5, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction, thereby making the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates the manufacture of semiconductor integrated circuit devices.

[0073] The Y-direction width of the active region 2P1 (2N1) in the inverter cell C1 and the Y-direction width of the active region 2P3 (2N3) in the termination cell C3 are w1. The Y-direction width of the active region 2P2 (2N2) in the inverter cell C2 is w2, which is smaller than w1. The Y-direction bottom end (top end) of the active region 2P1 (2N1) in the inverter cell C1, the Y-direction bottom end (top end) of the active region 2P2 (2N2) in the inverter cell C2, and the Y-direction bottom end (top end) of the active region 2P3 (2N3) in the termination cell C3 are aligned in the Y-direction. By arranging the termination cell C3 adjacent to the inverter cells C1 and C2, which have active regions with different Y-direction widths, the active region of the termination cell C3 can be positioned along the entire left side surface of the active region of the inverter cell C1 and the entire left side surface of the active region of the inverter cell C2. Therefore, the distances from the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2 to the active region 2P3 (2N3) of the termination cell C3 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0074] In this embodiment, the size of the terminal cell C3 in the X direction is set to four grids, but is not limited to this.

[0075] Furthermore, in this embodiment, the terminal cell C3 includes the local wirings 141 to 144, but it is not necessary to include some or all of these.

[0076] In this embodiment, some or all of the bridge portions 131c to 133c may be omitted in the terminal cell C3. That is, in the terminal cell C3, the gate wirings aligned in the Y direction may be separated rather than connected to each other.

[0077] (Modification of Termination Cell C3) FIGS. 6A and 6B are plan views showing another example of the layout structure of the termination cell C3 according to a modification of the first embodiment.

[0078] 2 and 5, the cell width (size in the X direction) of the terminal cell C3 in Fig. 6(a) is half (2 grids). In addition, the bridge portion connecting the dummy gate wirings arranged in the Y direction is omitted.

[0079] Specifically, the nanosheets 122 and 123, the dummy gate wirings 132a, 133a, 132b and 133b, and the local wirings 143 and 144 are omitted, and the width of the active regions 2P3 and 2N3 in the X direction is halved.

[0080] Furthermore, the bridge portion 131c is omitted, and the dummy gate wirings 131a and 131b are not connected.

[0081] The configuration of FIG. 6A can also provide the same effect as the termination cell C3 of FIGS.

[0082] 6B, compared with the terminal cell C3 in FIGS. 2 and 5, the local interconnects 141 to 144 are omitted.

[0083] The configuration of FIG. 6B also provides the same effect as the terminal cell C3 of FIGS.

[0084] (Configuration of Termination Cell C4) FIG. 7 is a plan view of portion A3 in FIG.

[0085] 1, the terminal cell C4 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C1 and C2 arranged at the top end of the logic unit LC in the drawing.

[0086] 7, power supply wirings 11 and 12 extending in the X direction are formed on both ends of the cell in the Y direction in the drawing in the BM0 wiring layer. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0087] An active region 2P4 is formed in the P-type transistor region. The active region 2P4 overlaps with the power supply wiring 11 in plan view.

[0088] P-type dummy transistors DP4 to DP6 are formed in the active region 2P4. The dummy transistors DP4 to DP6 have nanosheets 221 to 223 extending in the X direction.

[0089] An active region 2N4 is formed in the N-type transistor region. The active region 2N4 overlaps with the power supply wiring 12 in plan view.

[0090] N-type dummy transistors DN4 to DN6 are formed in the active region 2N4. The dummy transistors DN4 to DN6 have nanosheets 224 to 226 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0091] Dummy gate wirings 231a to 233a and 231b to 233b are formed extending in the Y and Z directions. The nanosheets 221 to 226 overlap the dummy gate wirings 231a to 233a and 231b to 233b, respectively, in a plan view. The dummy gate wirings 231a to 233a and 231b to 233b correspond to the gates of the dummy transistors DP4 to DP6 and DN4 to DN6, respectively.

[0092] Dummy gate wirings 231a to 233a and 231b to 233b cover the outer peripheries of nanosheets 221 to 226 in the Y and Z directions, respectively, so that a portion of the outer peripheries of nanosheets 221 to 226 is exposed, respectively. Specifically, the upper side surfaces of nanosheets 221 to 223 in the drawing are not covered by dummy gate wirings 231a to 233a, respectively. The lower side surfaces of nanosheets 224 to 226 in the drawing are not covered by dummy gate wirings 231b to 233b, respectively. In other words, the upper surfaces of nanosheets 221 to 223 in the Y direction are exposed from dummy gate wirings 231a to 233a, respectively, and the lower surfaces in the Y direction are covered by dummy gate wirings 231a to 233a, respectively. The surfaces of the nanosheets 224 to 226 on the lower side in the Y direction in the drawing are exposed from the dummy gate wirings 231b to 233b, respectively, and the surfaces on the upper side in the Y direction in the drawing are covered by the dummy gate wirings 231b to 233b, respectively.

[0093] The dummy gate wirings 231a and 231b are connected via a bridge portion 231c. The dummy gate wirings 232a and 232b are connected via a bridge portion 232c. The dummy gate wirings 233a and 233b are connected via a bridge portion 233c.

[0094] Dummy gate wirings 234a and 234b are formed on the cell frame on the left side of the drawing in the X direction. Dummy gate wirings 235a and 235b are formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wirings 234a and 234b are shared with other cells arranged on the left side of the drawing. The dummy gate wirings 235a and 235b are shared with other cells arranged on the right side of the drawing. The dummy gate wirings 234a and 234b are connected via a bridge portion 234c extending in the Y direction. The dummy gate wirings 235a and 235b are connected via a bridge portion 235c extending in the Y direction.

[0095] Local wirings 241 to 244 extending in the Y direction are formed in the local wiring layer. Local wiring 241 is connected to the portion that will become the source of dummy transistor DP4 in active region 2P4 and the portion that will become the source of dummy transistor DN4 in active region 2N4. Local wiring 242 is connected to the portion that will become the drain of dummy transistor DP4 and the portion that will become the source of dummy transistor DP5 in active region 2P4, and to the portion that will become the drain of dummy transistor DN4 and the portion that will become the source of dummy transistor DN5 in active region 2N4. Local wiring 243 is connected to the portion that will become the drain of dummy transistor DP5 and the portion that will become the source of dummy transistor DP6 in active region 2P4, and to the portion that will become the drain of dummy transistor DN5 and the portion that will become the source of dummy transistor DN6 in active region 2N4. The local wiring 244 is connected to a portion that serves as the drain of the dummy transistor DP6 in the active region 2P4 and a portion that serves as the drain of the dummy transistor DN6 in the active region 2N4.

[0096] 7, unlike the inverter cells C1 and C2, the dummy gate wirings 231a to 233a, 231b to 233b and the local wirings 241 to 244 are not connected to other wirings. In other words, the terminal cell C4 is a standard cell that does not have a logic function.

[0097] Furthermore, nanosheets 221 to 226 of terminal cell C4 are formed in the same layer as nanosheets 21 and 22 of inverter cells C1 and C2. Nanosheets 221 and 224 are formed in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C1. Nanosheets 223 and 226 are formed in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C2.

[0098] Furthermore, the dummy gate wirings 231a to 235a and 231b to 235b of the terminal cell C4 are formed in the same layer as the gate wirings 31a and 31b and dummy gate wirings 32a, 33a, 32b, and 33b of the inverter cells C1 and C2. The dummy gate wirings 231a to 235a of the terminal cell C4 are formed at the same position in the Y direction and at equal intervals in the X direction. The dummy gate wirings 231b to 235b of the terminal cell C4 are formed at the same position in the Y direction and at equal intervals in the X direction. The dummy gate wirings 231a and 231b of the terminal cell C4 are formed at the same position in the X direction as the gate wirings 31a and 31b of the inverter cell C1. The dummy gate wirings 233a and 233b of the terminal cell C4 are formed at the same position in the X direction as the gate wirings 31a and 31b of the inverter cell C2. The upper and lower ends of the dummy gate wirings 231a to 235a in the drawing are aligned in the Y direction. The upper and lower ends of the dummy gate wirings 231b to 235b in the drawing are aligned in the Y direction.

[0099] Furthermore, the local wirings 241 to 244 of the terminal cell C4 are formed in the same layer as the local wirings 41 of the inverter cells C1 and C2. The local wirings 241 to 244 of the terminal cell C4 are formed at the same position in the Y direction and are arranged at equal pitches in the X direction. The local wirings 242 and 244 of the terminal cell C4 are formed at the same position in the X direction as the local wirings 41 of the inverter cells C1 and C2.

[0100] In Figure 7, the terminal cell C4, which does not have a logic function, is arranged adjacent to the inverter cells C1 and C2, which have a logic function, in the cell row CR, which is the top row in the Y direction of the circuit block. The nanosheets 221 and 224 (223 and 226) of the terminal cell C4 are arranged in the same position in the X direction as the nanosheets 21 and 22 of the inverter cell C1 (C2). The nanosheet 21 of the inverter cell C1 (C2) and the nanosheets 224 and 226 of the terminal cell C4 have their lower surfaces exposed from the gate wiring 31a and dummy gate wiring 231b and 233b, respectively. The nanosheet 22 of the inverter cell C1 (C2) and the nanosheets 221 and 223 of the terminal cell C4 have their upper surfaces exposed from the gate wiring 31b and dummy gate wiring 231a and 233a, respectively. That is, the nanosheet 21 of the inverter cell C1 (C2) and the nanosheets 224 and 226 of the terminal cell C4, which are arranged at the same position in the X direction, have their surfaces on the same side in the Y direction exposed from the gate wiring 31a and the dummy gate wirings 231b and 233b, respectively. The nanosheet 22 of the inverter cell C1 (C2) and the nanosheets 221 and 223 of the terminal cell C4, which are arranged at the same position in the X direction, have their surfaces on the same side in the Y direction exposed from the gate wiring 31b and the dummy gate wirings 231a and 233a, respectively. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices, improve yields, and enhance reliability.

[0101] Furthermore, the opposing surfaces of the nanosheets 21 and 22 of the inverter cell C1 (C2) are exposed from the gate wirings 31a and 31b, respectively. The opposing surfaces of the nanosheets 221 and 224 of the terminal cell C4 are exposed from the dummy gate wirings 231a and 231b, respectively. The opposing surfaces of the nanosheets 222 and 225 of the terminal cell C4 are exposed from the dummy gate wirings 232a and 232b, respectively. The opposing surfaces of the nanosheets 223 and 226 of the terminal cell C4 are exposed from the dummy gate wirings 233a and 233b, respectively. This eliminates the need for overlapping gate wiring between the nanosheets 21 and 22, between the nanosheets 221 and 224, between the nanosheets 222 and 225, and between the nanosheets 223 and 226, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced.

[0102] Furthermore, dummy gate wirings 231a-235a and 231b-235b of the terminal cell C4 are formed in the same layer as the gate wirings 31a and 31b and dummy gate wirings 32a, 33a, 32b, and 33b of the inverter cells C1 and C2. Local wirings 241-244 of the terminal cell C4 are formed in the same layer as the local wiring 41 of the inverter cells C1 and C2. That is, by forming dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cells, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0103] In this embodiment, the size of the terminal cell C4 in the X direction is set to four grids, but is not limited to this.

[0104] Furthermore, in this embodiment, the terminal cell C4 includes the local wirings 241 to 244, but it is not necessary to include some or all of these.

[0105] In this embodiment, some or all of the bridge portions 231c to 233c may be omitted in the terminal cell C4, that is, the gate wirings aligned in the Y direction in the terminal cell C4 may be separated rather than connected to each other.

[0106] In this embodiment, the terminal cell C4 may have the same configuration as that shown in FIGS.

[0107] (Modification of Termination Cell C4) Figure 8 is a plan view showing an example of the layout structure of termination cell C4 according to a modification of the first embodiment. In termination cell C4 of Figure 8, the cell height (width of the cell in the Y direction) is half that of termination cell C4 of Figure 7, and the power supply wiring, active region, dummy gate wiring, etc., which were formed at the top of the drawing in the Y direction, are omitted. Specifically, in Figure 8, the power supply wiring 12, active region 2N4, and dummy gate wiring 231b to 235b are omitted. Furthermore, the lengths of local wirings 241 to 244 and bridge portions 231c to 235c in the Y direction are halved.

[0108] The configuration of FIG. 8 also provides the same effect as that of the termination cell C4 of FIG.

[0109] Furthermore, with the configuration of FIG. 8, the width of the terminal cell C4 in the Y direction is halved, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced.

[0110] In this modification, the surfaces of the nanosheets 221 to 223 on the upper side in the Y direction in the drawing may or may not be exposed from the dummy gate wirings 231a to 233a, respectively.

[0111] In addition, in this modified example, the power supply wiring 12, the active region 2P4, and the dummy gate wiring 231b to 235b are all omitted from the terminal cell C4, but the terminal cell C4 may also include some of the power supply wiring 12, the active region 2P4, and the dummy gate wiring 231b to 235b.

[0112] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0113] 9A shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in FIG. 9A is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0114] 9B shows a cross section of the terminal cell of FIG. 2 taken along line Y1-Y1' in this configuration example. As shown in FIG. 9B, a power supply wiring 11 that supplies VDD and a power supply wiring 12 that supplies VSS are formed in a wiring layer provided on the surface of chip B. Although not shown, in inverter cell C1 (C2), power supply wiring 11 is connected to active region 2P1 (2P2) of chip A via via 61. Power supply wiring 12 is connected to active region 2N1 (2N2) of chip A via via 62.

[0115] This configuration example also provides the same effects as the inverter cell described above.

[0116] Second Embodiment (Circuit Block Configuration) Fig. 10 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. Note that Fig. 10 shows only power supply wiring formed in a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed, and other components are omitted.

[0117] 10 is configured by arranging standard cells. In this embodiment, too, the power supply wiring is formed in the BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0118] 10, a plurality of cells arranged in the X direction constitute a cell row CR (six rows in this example). The plurality of cells includes standard cells having a logic function and termination cells having no logic function.

[0119] In the layout of Figure 10, a rectangular logic unit LC that includes logic cells having logic functions and realizes the circuit function is placed in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C5 and C6 are placed in the logic unit LC. Termination cells C7 and C8 are placed in the termination cell unit. Specifically, termination cells C7 are placed on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C8 are placed in the cell rows CR placed in the top and bottom rows of the circuit block in the Y direction.

[0120] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0121] (Configuration of Inverter Cell C5) Fig. 11 is a plan view of portion A4 in Fig. 10. As shown in Fig. 11, the inverter cell C5 has transistors P1 and N1, and an inverter circuit with input A and output Y is configured.

[0122] As shown in FIGS. 10 and 11, the inverter cell C5 is arranged at the left end of the logic section LC in the drawing, and the termination cell C7 is arranged adjacent to it on the left side.

[0123] 10 , power supply wiring 11 and 12 extending in the X direction are formed in the BM0 wiring layer at both ends of the cell in the Y direction in the drawing. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS. The power supply wiring 11 and 12 are shared with other cells in the cell string CR including the inverter cell C5, and serve as power supply wiring extending in the X direction.

[0124] An active region 2P5 is formed in the P-type transistor region. The active region 2P5 overlaps with the power supply wiring 11 in plan view.

[0125] A P-type transistor P1 is formed in the active region 2P5. The transistor P1 has a nanosheet 321 extending in the X direction as a channel. In the active region 2P5, a portion serving as the source of the transistor P1 is connected to the power supply wiring 11 via a via 361. The via 361 is formed in a region where the power supply wiring 11 and the active region 2P5 overlap in plan view.

[0126] An active region 2N5 is formed in the N-type transistor region. The active region 2N5 overlaps with the power supply wiring 12 in plan view.

[0127] An N-type transistor N1 is formed in the active region 2N5. The transistor N1 has a nanosheet 322 extending in the X direction as a channel. In the active region 2N5, a portion that serves as the source of the transistor N1 is connected to the power supply wiring 12 via a via 362. The via 362 is formed in a region where the power supply wiring 12 and the active region 2N5 overlap in a plan view.

[0128] A gate wiring 331 extending in the Y direction is formed in the center of the cell in the X direction. The nanosheets 321 and 322 overlap the gate wiring 331 in plan view. The gate wiring 331 corresponds to the gates of the transistors P1 and N1.

[0129] Gate wiring 331 covers the outer peripheries of nanosheets 321 and 322 in the Y and Z directions, respectively, so as to expose a portion of the outer peripheries of nanosheets 321 and 322. Specifically, the upper surface of nanosheet 321 in the Y direction in the drawing is exposed from gate wiring 331, and the lower surface of nanosheet 321 in the Y direction in the drawing is covered by gate wiring 331. The lower surface of nanosheet 322 in the Y direction in the drawing is exposed from gate wiring 331, and the upper surface of nanosheet 322 in the Y direction in the drawing is covered by gate wiring 331.

[0130] A dummy gate wiring 332 is formed on the cell frame on the left side of the drawing in the X direction. A dummy gate wiring 333 is formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wiring 332 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 333 is shared with other cells arranged on the right side of the drawing.

[0131] The local wiring layer is formed with a local wiring 341 extending in the Y direction. The local wiring 341 is connected to a portion in the active region 2P5 that serves as the drain of the transistor P1 and a portion in the active region 2N5 that serves as the drain of the transistor N1.

[0132] In the M0 wiring layer, wirings 351 and 352 extending in the X direction are formed. The wiring 351 is connected to the gate wiring 331 through a via. The wiring 352 is connected to the local wiring 341 through a via. The wiring 351 corresponds to the input A, and the wiring 352 corresponds to the output Y.

[0133] As described above, the inverter cell C5 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C5 is a standard cell having a logic function.

[0134] As shown in FIG. 11, the active regions 2P5 and 2N5 in the inverter cell C5 have a width w1 in the Y direction in plan view.

[0135] (Configuration of Inverter Cell C6) FIG. 12 is a plan view of portion A5 in FIG.

[0136] As shown in FIGS. 10 and 12, the inverter cell C6 is arranged at the left end of the logic section LC in the drawing, and the termination cell C7 is arranged adjacent to it on the left side.

[0137] The inverter cell C6 has a configuration similar to that of the inverter cell C5. Specifically, the inverter cell C6 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C6 is a standard cell having a logic function.

[0138] As shown in FIG. 12, the inverter cell C6 is different from the inverter cell C5 shown in FIG. 11 in that active regions 2P6 and 2N6 having different widths in the Y direction are arranged in place of the active regions 2P5 and 2N5.

[0139] Specifically, the active regions 2P6 and 2N6 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C5 is greater than the drive capability of the inverter cell C6.

[0140] 11 and 12, the upper end (lower end) of the active region 2P6 (2N6) in the Y direction is located at the same position in the Y direction as the upper end (lower end) of the active region 2P5 (2N5) in the Y direction. That is, the upper end (lower end) of the active region 2P5 (2N5) in the Y direction of the inverter cell C5 and the upper end (lower end) of the active region 2P6 (2N6) in the Y direction of the inverter cell C6 are aligned in the Y direction.

[0141] In inverter cell C5 of FIG. 11 (inverter cell C6 of FIG. 12), the upper surface of nanosheet 321 in the Y direction is exposed from gate wiring 331. The lower surface of nanosheet 322 in the Y direction is exposed from gate wiring 331. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring facing each other in the Y direction. This reduces the distance d13 from the upper end of active regions 2P5 and 2P6 in the Y direction to the upper end of the cell frame in the Y direction, and the distance d13 from the lower end of active regions 2N5 and 2N6 in the Y direction to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0142] 11 (inverter cell C6 in FIG. 12), the nanosheet 321 has a surface on the lower side in the Y direction covered by the gate wiring 331. The nanosheet 322 has a surface on the upper side in the Y direction covered by the gate wiring 331. That is, the surfaces of the nanosheets 321 and 322 that face each other in the Y direction are not exposed from the gate wiring 331. Therefore, the distance d11 (d12) in the Y direction between the active regions 2P5 and 2N5 (2P6 and 2N6) in the inverter cell C5 (C6) is greater than the distance (2×d13) in the Y direction between the active regions of cells adjacent in the Y direction.

[0143] (Configuration of Terminating Cell C7) As shown in FIG. 10, the terminating cells C7 are arranged on both the left and right ends of the cell row CR in the X direction.

[0144] 11 and 12, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer at both ends of the cell in the Y direction in the drawing. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0145] An active region 2P7 is formed in the P-type transistor region. The active region 2P7 overlaps with the power supply wiring 11 in plan view.

[0146] P-type dummy transistors DP1 to DP3 are formed in the active region 2P7. The dummy transistors DP1 to DP3 have nanosheets 421 to 423 extending in the X direction as channels.

[0147] An active region 2N7 is formed in the N-type transistor region. The active region 2N7 overlaps with the power supply wiring 12 in plan view.

[0148] N-type dummy transistors DN1 to DN3 are formed in the active region 2N7. The dummy transistors DN1 to DN3 have nanosheets 424 to 426 extending in the X direction as channels.

[0149] Dummy gate wirings 431 to 433 are formed extending in the Y and Z directions. Nanosheets 421 and 424 overlap with dummy gate wiring 431 in a planar view. Nanosheets 422 and 425 overlap with dummy gate wiring 432 in a planar view. Nanosheets 423 and 426 overlap with dummy gate wiring 433 in a planar view. Dummy gate wiring 431 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 432 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 433 corresponds to the gates of dummy transistors DP3 and DN3.

[0150] Dummy gate wiring 431 covers the outer peripheries of nanosheets 421 and 424 in the Y and Z directions so that part of the outer peripheries of nanosheets 421 and 424 are exposed. Dummy gate wiring 432 covers the outer peripheries of nanosheets 422 and 425 in the Y and Z directions so that part of the outer peripheries of nanosheets 422 and 425 are exposed. Dummy gate wiring 433 covers the outer peripheries of nanosheets 423 and 426 in the Y and Z directions so that part of the outer peripheries of nanosheets 423 and 426 are exposed. Specifically, the upper surfaces of nanosheets 421 to 423 in the Y direction in the drawing are exposed from dummy gate wirings 431 to 433, and the lower surfaces in the Y direction in the drawing are covered by dummy gate wirings 431 to 433. The surfaces of the nanosheets 424 to 426 on the lower side in the Y direction in the drawing are exposed from the dummy gate wirings 431 to 433, and the surfaces on the upper side in the Y direction in the drawing are covered by the dummy gate wirings 431 to 433.

[0151] A dummy gate wiring 434 is formed on the cell frame on the left side of the drawing in the X direction. A dummy gate wiring 435 is formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wiring 435 is shared with another cell (inverter cell C5 in FIG. 11 and inverter cell C6 in FIG. 12) arranged on the right side of the drawing.

[0152] Local wirings 441 to 444 extending in the Y direction are formed in the local wiring layer. Local wiring 441 is connected to the portion that will become the source of dummy transistor DP1 in active region 2P7 and the portion that will become the source of dummy transistor DN1 in active region 2N7. Local wiring 442 is connected to the portion that will become the drain of dummy transistor DP1 and the portion that will become the source of dummy transistor DP2 in active region 2P7, and to the portion that will become the drain of dummy transistor DN1 and the portion that will become the source of dummy transistor DN2 in active region 2N7. Local wiring 443 is connected to the portion that will become the drain of dummy transistor DP2 and the portion that will become the source of dummy transistor DP3 in active region 2P7, and to the portion that will become the drain of dummy transistor DN2 and the portion that will become the source of dummy transistor DN3 in active region 2N7. The local wiring 444 is connected to a portion that serves as the drain of the dummy transistor DP3 in the active region 2P7 and a portion that serves as the drain of the dummy transistor DN3 in the active region 2N7.

[0153] 11 and 12, unlike the inverter cells C5 and C6, the dummy gate wirings 431 to 433 and the local wirings 441 to 444 are not connected to other wirings. In other words, the termination cell C7 is a standard cell that does not have a logic function.

[0154] Furthermore, nanosheets 421 to 426 are formed in the same layer as nanosheets 321 and 322. The top ends of nanosheets 421 to 423 in the drawing are aligned in the Y direction with the top end of nanosheet 321. The bottom ends of nanosheets 424 to 426 in the drawing are aligned in the Y direction with the bottom end of nanosheet 322.

[0155] The dummy gate wirings 431 to 433 are formed in the same layer as the gate wiring 331 and the dummy gate wirings 332 (435), 333. The dummy gate wirings 431 to 434 are formed at the same positions in the Y direction as the gate wiring 331 and the dummy gate wirings 332 (335), 333, and are arranged at equal pitches in the X direction.

[0156] The upper and lower ends of the dummy gate wirings 431 to 434 are aligned in the Y direction with the upper and lower ends of the gate wiring 331 and the dummy gate wirings 332 (435) and 333, respectively.

[0157] The local wirings 441 to 444 are formed in the same layer as the local wiring 341. The local wirings 441 to 444 are arranged at equal pitches in the X direction.

[0158] In the block layout of Figure 10, the terminal cell C7, which does not have a logic function, is arranged adjacent to the inverter cell C5, which has a logic function. The nanosheets 421 to 423 (424 to 426) of the terminal cell C7 are arranged in the same position in the Y direction as the nanosheet 321 (322) of the inverter cell C5. The upper surfaces of the nanosheets 321, 421 to 423 in the drawing are exposed from the gate wiring 331 and the dummy gate wiring 431 to 433, respectively. The lower surfaces of the nanosheets 322, 424 to 426 in the drawing are exposed from the gate wiring 331 and the dummy gate wiring 431 to 433, respectively. In other words, the nanosheets 321, 421 to 423 arranged in the same position in the Y direction have the same surfaces in the Y direction exposed from the gate wiring 331 and the dummy gate wiring 431 to 433, respectively. Nanosheets 322, 424 to 426 arranged at the same position in the Y direction have the same surfaces in the Y direction exposed from gate wiring 331 and dummy gate wirings 431 to 433. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices, improve yields, and improve reliability.

[0159] Furthermore, dummy gate wirings 431 to 434 of the terminal cell C7 are formed in the same layer as the gate wiring 331 and dummy gate wirings 332 (435) and 333 of the inverter cells C5 and C6. Local wirings 441 to 444 of the terminal cell C7 are formed in the same layer as the local wiring 341 of the inverter cells C5 and C6. That is, by forming dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cells, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0160] Furthermore, the active regions 2P7 and 2N7 of the termination cell C7 are located close to the dummy gate wiring 332 (435) located at the boundary between the inverter cells C5 and C6 and the termination cell C7. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0161] Furthermore, the upper end (lower end) in the Y direction of the active region 2P5 (2N5) of the inverter cell C5, the upper end (lower end) in the Y direction of the active region 2P6 (2N6) of the inverter cell C6, and the upper end (lower end) in the Y direction of the active region 2P7 (2N7) of the termination cell C7 are arranged at the same position in the Y direction. That is, the upper end (lower end) in the Y direction of the active region 2P5 (2N5) of the inverter cell C5, the upper end (lower end) in the Y direction of the active region 2P6 (2N6) of the inverter cell C6, and the upper end (lower end) in the Y direction of the active region 2P7 (2N7) of the termination cell C7 are aligned in the Y direction. Furthermore, the nanosheets 321 (322) of the inverter cells C5 and C6 and the nanosheets 421 to 423 (424 to 426) of the terminal cell C7 have their surfaces on the upper side (lower side) of the drawing in the Y direction exposed from the gate wiring 331 and the dummy gate wiring 431 to 433, respectively. That is, in the inverter cells C5 and C6 and the terminal cell C7, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0162] The Y-direction width of the active region 2P5 (2N5) in the inverter cell C5 and the Y-direction width of the active region 2P7 (2N7) in the termination cell C7 are w1. The Y-direction width of the active region 2P6 (2N6) in the inverter cell C6 is w2, which is smaller than w1. The Y-direction top end (bottom end) of the active region 2P5 (2N5) in the inverter cell C5, the Y-direction top end (bottom end) of the active region 2P6 (2N6) in the inverter cell C6, and the Y-direction top end (bottom end) of the active region 2P7 (2N7) in the termination cell C7 are aligned in the Y-direction. By arranging the termination cell C7 adjacent to the inverter cells C5 and C6, which have active regions with different Y-direction widths, the active region of the termination cell C7 can be positioned along the entire left side of the active region of the inverter cell C5 and the entire left side of the active region of the inverter cell C6. Therefore, the distances from the active region 2P5 (2N5) of the inverter cell C5 and the active region 2P6 (2N6) of the inverter cell C6 to the active region 2P7 (2N7) of the termination cell C7 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0163] In this embodiment, the size of the terminal cell C7 in the X direction is set to four grids, but is not limited to this.

[0164] Furthermore, in this embodiment, the terminal cell C7 includes the local wirings 441 to 444, but it is not necessary to include some or all of these.

[0165] In this embodiment, in the terminal cell C7, some or all of the dummy gate wirings 431 to 433 may be omitted. Also, in some or all of the dummy gate wirings 431 to 433 of the terminal cell C7, the intermediate portions thereof may be separated.

[0166] In this embodiment, the terminal cell C7 may have the same configuration as that shown in FIGS.

[0167] (Configuration of Termination Cell C8) FIG. 13 is a plan view of portion A6 in FIG.

[0168] 10, the terminal cell C8 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C5 and C6 arranged at the top end of the logic unit LC in the drawing.

[0169] 13, power supply wirings 11 and 12 extending in the X direction are formed on both ends of the cell in the Y direction in the drawing in the BM0 wiring layer. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0170] An active region 2P8 is formed in the P-type transistor region. The active region 2P8 overlaps with the power supply wiring 11 in plan view.

[0171] P-type dummy transistors DP4 to DP6 are formed in the active region 2P8. The dummy transistors DP4 to DP6 have nanosheets 521 to 523 extending in the X direction.

[0172] An active region 2N8 is formed in the N-type transistor region. The active region 2N8 overlaps with the power supply wiring 12 in plan view.

[0173] N-type dummy transistors DN4 to DN6 are formed in the active region 2N8. The dummy transistors DN4 to DN6 have nanosheets 524 to 526 extending in the X direction as channels.

[0174] Dummy gate wirings 531 to 533 are formed extending in the Y and Z directions. Nanosheets 521 to 523 (524 to 526) overlap the dummy gate wirings 531 to 533, respectively, in a plan view. The dummy gate wiring 531 corresponds to the gates of dummy transistors DP4 and DN4. The dummy gate wiring 532 corresponds to the gates of dummy transistors DP5 and DN5. The dummy gate wiring 533 corresponds to the gates of dummy transistors DP6 and DN6.

[0175] The dummy gate wiring 531 covers the outer peripheries of the nanosheets 521 and 524 in the Y and Z directions so that part of the outer peripheries of the nanosheets 521 and 524 are exposed. The dummy gate wiring 532 covers the outer peripheries of the nanosheets 522 and 525 in the Y and Z directions so that part of the outer peripheries of the nanosheets 522 and 525 are exposed. The dummy gate wiring 533 covers the outer peripheries of the nanosheets 523 and 526 in the Y and Z directions so that part of the outer peripheries of the nanosheets 523 and 526 are exposed. Specifically, the lower surfaces of the nanosheets 521 to 523 in the Y direction in the drawing are exposed from the dummy gate wirings 531 to 533, and the upper surfaces in the Y direction in the drawing are covered by the dummy gate wirings 531 to 533. The upper surfaces of the nanosheets 524 to 526 in the Y direction are exposed from the dummy gate wirings 531 to 533, and the lower surfaces in the Y direction are covered by the dummy gate wirings 531 to 533.

[0176] A dummy gate wiring 534 is formed on the cell frame on the left side of the drawing in the X direction. A dummy gate wiring 535 is formed on the cell frame on the right side of the drawing in the X direction. The dummy gate wiring 534 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 535 is shared with other cells arranged on the right side of the drawing.

[0177] Local wirings 541 to 544 extending in the Y direction are formed in the local wiring layer. Local wiring 541 is connected to the portion that will become the source of dummy transistor DP4 in active region 2P8 and the portion that will become the source of dummy transistor DN4 in active region 2N8. Local wiring 542 is connected to the portion that will become the drain of dummy transistor DP4 and the portion that will become the source of dummy transistor DP5 in active region 2P8, and to the portion that will become the drain of dummy transistor DN4 and the portion that will become the source of dummy transistor DN5 in active region 2N8. Local wiring 543 is connected to the portion that will become the drain of dummy transistor DP5 and the portion that will become the source of dummy transistor DP6 in active region 2P8, and to the portion that will become the drain of dummy transistor DN5 and the portion that will become the source of dummy transistor DN6 in active region 2N8. The local wiring 544 is connected to a portion that serves as the drain of the dummy transistor DP6 in the active region 2P8 and a portion that serves as the drain of the dummy transistor DN6 in the active region 2N8.

[0178] 13, unlike the inverter cells C5 and C6, the dummy gate wirings 531 to 533 and the local wirings 541 to 544 are not connected to any other wirings. In other words, the terminal cell C8 is a standard cell that does not have a logic function.

[0179] Furthermore, nanosheets 521 to 526 of terminal cell C8 are formed in the same layer as nanosheets 321 and 322 of inverter cells C5 and C6. Nanosheets 521 and 524 are formed in the same positions in the X direction as nanosheets 321 and 322 of inverter cell C5. Nanosheets 523 and 526 are formed in the same positions in the X direction as nanosheets 321 and 322 of inverter cell C6.

[0180] Furthermore, the dummy gate wirings 531 to 535 of the terminal cell C8 are formed in the same layer as the gate wiring 331 and dummy gate wirings 332 and 333 of the inverter cells C5 and C6. The dummy gate wirings 531 to 535 of the terminal cell C8 are formed at the same position in the Y direction and are arranged at equal pitches in the X direction. The dummy gate wirings 531 and 533 of the terminal cell C8 are formed at the same position in the X direction as the gate wiring 331 of the inverter cell C5 and the gate wiring 331 of the inverter cell C6. The top and bottom ends of the dummy gate wirings 531 to 535 in the drawing are aligned in the Y direction.

[0181] Furthermore, local wirings 541 to 544 of the terminal cell C8 are formed in the same layer as the local wirings 341 of the inverter cells C5 and C6. The local wirings 541 to 544 of the terminal cell C8 are formed at the same position in the Y direction and are arranged at equal pitches in the X direction. The local wirings 542 and 544 of the terminal cell C8 are formed at the same position in the X direction as the local wirings 341 of the inverter cells C5 and C6.

[0182] 13, the terminal cell C8, which does not have a logic function, is arranged adjacent to the inverter cells C5 and C6, which have a logic function, in the cell row CR, which is the top row in the Y direction of the circuit block. The nanosheets 521 and 524 (523 and 526) of the terminal cell C8 are arranged in the same position in the X direction as the nanosheets 321 and 322 of the inverter cell C5 (C6). The nanosheet 321 of the inverter cell C5 (C6) and the nanosheets 524 and 526 of the terminal cell C8 have their upper surfaces exposed from the gate wiring 331 and the dummy gate wiring 531 and 533, respectively. The nanosheet 322 of the inverter cell C5 (C6) and the nanosheets 521 and 523 of the terminal cell C8 have their lower surfaces exposed from the gate wiring 331 and the dummy gate wiring 531 and 533, respectively. That is, the nanosheet 321 of the inverter cell C5 (C6) and the nanosheets 524 and 526 of the terminal cell C8, which are arranged at the same position in the X direction, have their surfaces on the same side in the Y direction exposed from the gate wiring 331 and the dummy gate wirings 531 and 533, respectively. The nanosheet 322 of the inverter cell C5 (C6) and the nanosheets 521 and 523 of the terminal cell C8, which are arranged at the same position in the X direction, have their surfaces on the same side in the Y direction exposed from the gate wiring 331 and the dummy gate wirings 531 and 533, respectively. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices, improve yields, and enhance reliability.

[0183] Furthermore, dummy gate wirings 531-535 of the terminal cell C8 are formed in the same layer as the gate wiring 331 and dummy gate wirings 332-333 of the inverter cells C5-C6. Local wirings 541-544 of the terminal cell C8 are formed in the same layer as the local wiring 341 of the inverter cells C5-C6. That is, by forming dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cells, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0184] In this embodiment, the size of the terminal cell C8 in the X direction is set to four grids, but is not limited to this.

[0185] Furthermore, in this embodiment, the terminal cell C8 includes the local wirings 541 to 544, but it is not necessary to include some or all of these.

[0186] In this embodiment, in the terminal cell C8, some or all of the dummy gate wirings 531 to 533 may be omitted. Also, in some or all of the dummy gate wirings 531 to 533 of the terminal cell C8, the intermediate portions thereof may be separated.

[0187] In this embodiment, the terminal cell C8 may have the same configuration as that shown in FIGS.

[0188] (Modification of Termination Cell C8) FIG. 14 is a plan view showing an example of the layout structure of termination cell C8 according to a modification of the second embodiment. In termination cell C8 of FIG. 14, the cell height (width of the cell in the Y direction) is half that of termination cell C8 of FIG. 13, and the power supply wiring, active region, dummy gate wiring, and the like that were formed at the top of the drawing in the Y direction are omitted. Specifically, power supply wiring 12 and active region 2N8 are omitted in FIG. 8. Furthermore, the lengths of local wirings 541-544 and dummy gate wirings 531-535 in the Y direction are halved.

[0189] The configuration of FIG. 14 also provides the same effect as that of the termination cell C8 of FIG.

[0190] Furthermore, with the configuration of FIG. 14, the width of the terminal cell C8 in the Y direction is halved, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced.

[0191] In addition, in this modification, the power supply wiring 12 and the active region 2N8 are entirely omitted from the terminal cell C8, but the terminal cell C4 may include the power supply wiring 12 and part of the active region 2N8.

[0192] In the above-described embodiments and modifications, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0193] In the above-described embodiment and modified examples, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0194] Furthermore, in the above-described embodiments and modifications, the standard cells having logic functions are described as inverter cells, but the standard cells having logic functions may be other cells (NAND, NOR, flip-flops, etc.).

[0195] In the above-described embodiment and modifications, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same wiring width, but the power supply wirings 11 and 12 may have different wiring widths.

[0196] The present disclosure makes it possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions in the layout of a semiconductor integrated circuit device including termination cells using fork-sheet transistors and backside wiring.

[0197] 11, 12 Power supply wiring 21, 22, 121 to 126, 221 to 226, 321, 421 to 424, 521 to 526 Nanosheet 31a, 31b, 331 Gate wiring 32a, 33a, 32b, 33b, 131a to 135a, 131b to 135b, 231a to 235a, 231b to 235b, 332, 333, 431 to 435, 531 to 535 Dummy gate wiring 31c to 33c, 131c to 135c, 231c to 235c Bridge section 41, 141 to 144, 241 to 244, 341, 441 to 444, 541 to 545 Local wiring 61, 62, 261, 262 Via 2P1 to 2P8, 2N1 to 2N8 Active area P1, N1 Transistor DP1 to DP6, DN1 to DN6 Dummy transistor C1, C2, C5, C6 Inverter cell C3, C4, C7, C8 Termination cell

Claims

1. A semiconductor device comprising a plurality of cell rows, each of which comprises a plurality of standard cells arranged side by side in a first direction, wherein a first cell row, which is one of the plurality of cell rows, comprises a first standard cell having a logic function, and a second standard cell, which is arranged on at least one end of the first cell row and does not have a logic function, wherein the first standard cell comprises: a first active region constituting the channel, source, and drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding the periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; and a first via formed in a region in the first active region where the region serving as the source of the first transistor overlaps with the first power supply wiring, the first via connecting the source of the first transistor in the first active region to the first power supply wiring; a first side surface of the first nanosheet, which is one side in the second direction, exposed from the first gate wiring; and the second standard cell comprises: a second active region that forms the channel, source, and drain of a first dummy transistor of the first conductivity type and includes a second nanosheet extending in the first direction as the channel; a first dummy gate wiring that extends in the second direction and surrounds the outer periphery of the second nanosheet in the second and third directions; and a second power supply wiring that is formed on the back side of the first dummy transistor, extends in the first direction, and supplies the first power supply voltage; and the first side surface of the second nanosheet is exposed from the first dummy gate wiring.

2. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell further comprises: a third active region including a third nanosheet extending in the first direction, constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the channel; a second gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions; a third power supply wiring formed on the back side of the second transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the third active region where the region serving as the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the third active region to the third power supply wiring, wherein the second side surface of the third nanosheet is exposed from the second gate wiring; and the second standard cell further comprises: a fourth active region that constitutes the channel, source, and drain of the second conductivity type second dummy transistor and includes a fourth nanosheet extending in the first direction as the channel; a second dummy gate wiring that extends in the second direction and surrounds the outer periphery of the fourth nanosheet in the second direction and the third direction; and a fourth power supply wiring that is formed on the back side of the second dummy transistor, extends in the first direction, and supplies the second power supply voltage, wherein the second side surface of the fourth nanosheet is exposed from the second dummy gate wiring, and the first side end and the second side end of the third active region are arranged between the first side end and the second side end of the fourth active region in the second direction.

3. A semiconductor integrated circuit device according to claim 2, wherein, in a plan view, the first side end of the first active region and the second side end of the third active region are disposed between the first side end of the first power supply wiring and the second side end of the second power supply wiring.

4. A semiconductor integrated circuit device according to claim 3, wherein the third nanosheet is arranged on the first side of the first nanosheet, and the fourth nanosheet is arranged on the first side of the second nanosheet.

5. A semiconductor integrated circuit device according to claim 2, wherein the third nanosheet is arranged on the second side of the first nanosheet, and the fourth nanosheet is arranged on the second side of the second nanosheet.

6. A semiconductor integrated circuit device according to claim 1, wherein, in a plan view, the first side end of the first nanosheet and the first side end of the second nanosheet are arranged at the same position in the second direction.

7. A semiconductor integrated circuit device according to claim 1, wherein a second cell row, which is one of the plurality of cell rows, comprises a third standard cell having a logic function, and the second standard cell arranged on at least one of both ends of the second cell row, the third standard cell comprising: a fifth active region constituting the channel, source, and drain of the third transistor of the first conductivity type, the channel including a fifth nanosheet extending in the first direction; a third gate wiring surrounding the periphery in the second and third directions; a fifth power supply wiring formed on the back side of the third transistor, extending in the first direction, and supplying the first power supply voltage; and a third via formed in a region in the fifth active region where the region serving as the source of the third transistor overlaps with the fifth power supply wiring, connecting the source of the third transistor in the fifth active region to the fifth power supply wiring, the first side of the fifth nanosheet being exposed from the third gate wiring, a width of the fifth active region in the second direction in a plan view that is smaller than a width of the first active region in the second direction; 8. A semiconductor integrated circuit device according to claim 7, wherein the first standard cell further comprises: a third active region including a third nanosheet extending in the first direction as the channel, constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type; a second gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions; a third power supply wiring formed on the back side of the second transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the third active region where a region serving as the source of the second transistor in the third active region overlaps with the third power supply wiring, connecting the source of the second transistor in the third active region with the third power supply wiring, wherein the second side surface of the third nanosheet is exposed from the second gate wiring; and the third standard cell further comprises: a sixth active region including a sixth nanosheet extending in the first direction as the channel, constituting the channel, source, and drain of a fourth transistor of the second conductivity type; a fourth gate wiring extending in the second direction and surrounding the periphery of the sixth nanosheet in the second direction and the third direction; a sixth power supply wiring formed on the back side of the fourth transistor, extending in the first direction, and supplying the second power supply voltage; and a fourth via formed in a region in the sixth active region where a region serving as a source of the fourth transistor and the sixth power supply wiring overlap, connecting the source of the fourth transistor in the sixth active region and the sixth power supply wiring, wherein the second side surface of the sixth nanosheet is exposed from the fourth gate wiring, and in a planar view, the width of the sixth active region in the second direction is smaller than the width of the third active region in the second direction.

9. A semiconductor integrated circuit device according to claim 7, wherein in the first cell row, in a planar view, the first side end of the first active region and the first side end of the second active region are arranged at the same position in the second direction; and in the second cell row, in a planar view, the first side end of the second active region and the first side end of the fifth active region are arranged at the same position in the second direction.

10. A semiconductor integrated circuit device according to claim 1, wherein a third dummy gate wiring extending in the second direction and the third direction is provided at the boundary between the first standard cell and the second standard cell, and the first gate wiring, the first dummy gate wiring and the third dummy gate wiring are arranged at the same pitch in the first direction.

11. A semiconductor device comprising a plurality of standard cells arranged side by side in a first direction and a plurality of cell rows arranged side by side in a second direction perpendicular to the first direction, wherein the plurality of cell rows include a first cell row including first and third standard cells having a logic function, and a second cell row arranged at either end of the plurality of cell rows in the second direction and including a second standard cell not having a logic function, wherein the first standard cell comprises: a first active region constituting the channel, source, and drain of a first transistor of a first conductivity type, the first active region including a first nanosheet extending in the first direction as the channel; a first gate wiring extending in the second direction and surrounding the periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; and a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage. the first nanosheet has a first side surface, which is one side in the second direction, exposed from the first gate wiring; the second standard cell has: a second active region including a second nanosheet, which forms a channel, source, and drain of a first dummy transistor of the first conductivity type, and which extends in the first direction as the channel; a first dummy gate wiring, which extends in the second direction and surrounds the periphery of the second nanosheet in the second direction and the third direction; and a second power supply wiring, which is formed on the back side of the first dummy transistor, extends in the first direction, and supplies the first power supply voltage; the second nanosheet has a second side surface, which is the other side in the second direction, exposed from the first dummy gate wiring; and the third standard cell has: a fifth active region that constitutes a channel, a source, and a drain of the third transistor of the first conductivity type, and that includes a fifth nanosheet extending in the first direction as the channel;a third gate wiring surrounding the periphery in the second direction and the third direction; a fifth power supply wiring formed on the back side of the third transistor, extending in the first direction, and supplying the first power supply voltage; and a third via formed in a region in the fifth active region where a region serving as a source of the third transistor overlaps with the fifth power supply wiring, and connecting the source of the third transistor in the fifth active region to the fifth power supply wiring, wherein the surface on the first side of the fifth nanosheet is exposed from the third gate wiring, and in a planar view, the width of the first active region in the second direction is the same as the width of the second active region in the second direction and is larger than the width of the fifth active region in the second direction.

12. A semiconductor integrated circuit device according to claim 11, wherein the first standard cell further comprises: a third active region including a third nanosheet extending in the first direction, constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the channel; a second gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions; a third power supply wiring formed on the back side of the second transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a second via formed in a region in the third active region where the region serving as the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the third active region to the third power supply wiring, wherein the second side surface of the third nanosheet is exposed from the second gate wiring; and the second standard cell further comprises: the third standard cell further comprises: a fourth active region constituting the channel, source, and drain of the second dummy transistor of the second conductivity type and including a fourth nanosheet extending in the first direction as the channel; a second dummy gate wiring extending in the second direction and surrounding the periphery of the fourth nanosheet in the second direction and the third direction; and a fourth power supply wiring formed on the back surface side of the second dummy transistor, extending in the first direction, and supplying the second power supply voltage, wherein the first side surface of the fourth nanosheet is exposed from the second dummy gate wiring; and the third standard cell further comprises: a sixth active region constituting the channel, source, and drain of the fourth transistor of the second conductivity type and including a sixth nanosheet extending in the first direction as the channel; a fourth gate wiring extending in the second direction and surrounding the periphery of the sixth nanosheet in the second direction and the third direction; and a sixth power supply wiring formed on the back surface side of the fourth transistor, extending in the first direction, and supplying the second power supply voltage.a fourth via formed in a region in the sixth active region where a region serving as a source of the fourth transistor overlaps with the sixth power wiring, the fourth via connecting the source of the fourth transistor in the sixth active region to the sixth power wiring; the sixth nanosheet has the second side surface exposed from the fourth gate wiring; and in a planar view, the width of the third active region in the second direction is the same as the width of the fourth active region in the second direction and is larger than the width of the sixth active region in the second direction.

13. A semiconductor integrated circuit device according to claim 11, wherein the second nanosheet is disposed on the second side of the first and second nanosheets.

14. A semiconductor integrated circuit device according to claim 11, wherein the second nanosheet is disposed on the first side of the first and second nanosheets.

15. A semiconductor integrated circuit device according to claim 11, wherein the width of the second standard cell in the second direction is half the width of the first standard cell in the second direction.

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