Display substrate, driving method thereof, display panel, and display apparatus

Abstract

A display substrate, a driving method thereof, a display panel and a display apparatus, relating to the technical field of display. The display substrate comprises: a base substrate, and a display region and a non-display region which are located on one side of the base substrate; the non-display region comprises a plurality of cascaded gate driving units; the display region comprises a plurality of gate lines, a plurality of bias signal lines and a plurality of data lines, the gate lines and the data lines intersecting with each other to form a plurality of sub-pixel regions; the sub-pixel regions comprise sub-pixels, each sub-pixel comprising a switching transistor and a pixel electrode; the switching transistor comprises a first gate, a first source, a first drain and a first bias electrode, the first gate being electrically connected to a gate line, the first source being electrically connected to a data line, the first drain being electrically connected to the pixel electrode, the first bias electrode being electrically connected to a bias signal line, and the first bias electrode and the first gate being arranged in a stacked manner on two sides of an active layer of the switching transistor. In a same row of sub-pixels, a bias signal line and a gate line are separately and directly connected to a same gate driving unit.

Description

Display substrate and driving method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a driving method thereof, a display panel, and a display device. Background Art

[0002] With the continuous advancement of display technology, liquid crystal displays have been successfully applied to display devices such as notebook computers, monitors, and televisions.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising: a base substrate, and a display area and a non-display area located on one side of the base substrate, wherein the non-display area comprises a plurality of gate driving units cascaded to each other;

[0005] The display area includes a plurality of gate lines extending in a row direction, a plurality of bias signal lines extending in a row direction, and a plurality of data lines extending in a column direction, wherein the orthographic projections of the gate lines and the data lines on the substrate intersect with each other to form a plurality of sub-pixel areas;

[0006] The sub-pixel region includes a sub-pixel, the sub-pixel includes a switching transistor and a pixel electrode, the switching transistor includes a first gate, a first source, a first drain, and a first bias electrode, the first gate is electrically connected to the gate line, the first source is electrically connected to the data line, the first drain is electrically connected to the pixel electrode, and the first bias electrode is electrically connected to the bias signal line, and the first bias electrode and the first gate are stacked on both sides of the active layer of the switching transistor;

[0007] In the same row of sub-pixels, the bias signal line and the gate line are directly connected to the same gate driving unit respectively.

[0008] In some embodiments, the first gate and the first bias electrode are both provided in different layers from the first source, and the first source and the first drain are provided in the same layer.

[0009] In some embodiments, the first bias electrode and the first gate have different signals.

[0010] In some embodiments, the gate line and the bias signal line are electrically connected to the same output terminal of the same gate driving unit.

[0011] In some embodiments, the gate line and the bias signal line are electrically connected to different output terminals of the same gate driving unit;

[0012] The gate driving unit includes:

[0013] a first output circuit, electrically connected to the first node, the first voltage signal terminal, the second voltage signal terminal, and the first output terminal, respectively, and configured to write a first voltage signal provided by the first voltage signal terminal to the first output terminal in a first phase, and to write a second voltage signal provided by the second voltage signal terminal to the first output terminal in a second phase, based on the potential of the first node;

[0014] a second output circuit, electrically connected to the second node, the third node, the third voltage signal terminal, the fourth voltage signal terminal, and the second output terminal, respectively, and configured to write a third voltage signal provided by the third voltage signal terminal to the second output terminal in a first phase according to the potential of the second node, and to write a fourth voltage signal provided by the fourth voltage signal terminal to the second output terminal in a second phase according to the potential of the third node;

[0015] The first output end and the second output end are different output ends, and the first output end is electrically connected to the gate line, and the second output end is electrically connected to the bias signal line.

[0016] In some embodiments, the first output circuit includes:

[0017] a first pull-up sub-circuit, electrically connected to the first node, the first voltage signal terminal, and the first output terminal, respectively, and configured to write the first voltage signal to the first output terminal in a first phase according to the potential of the first node;

[0018] a first pull-down sub-circuit, electrically connected to the first node, the second voltage signal terminal, and the first output terminal, respectively, and configured to write the second voltage signal to the first output terminal in a second phase according to the potential of the first node;

[0019] The second output circuit includes:

[0020] a second pull-up sub-circuit, electrically connected to the second node, the third voltage signal terminal, and the second output terminal, respectively, and configured to write the third voltage signal into the second output terminal in a first phase according to the potential of the second node;

[0021] The second pull-down sub-circuit is electrically connected to the third node, the fourth voltage signal terminal and the second output terminal respectively, and is configured to write the fourth voltage signal into the second output terminal in the second stage according to the potential of the third node.

[0022] In some implementations, the first node, the second node, and the third node are the same node.

[0023] In some implementations, the first node and the second node are different nodes, and the third node and the first node are the same node.

[0024] In some implementations, the first node and the second node are different nodes, and the third node and the second node are the same node.

[0025] In some embodiments, the second node is electrically connected to the first voltage signal terminal.

[0026] In some embodiments, the first pull-up sub-circuit includes: a first pull-up transistor, having a gate electrically connected to the first node, a source electrically connected to the first voltage signal terminal, and a drain electrically connected to the first output terminal;

[0027] The first pull-down sub-circuit includes: a first pull-down transistor, a gate electrically connected to the first node, a source electrically connected to the second voltage signal terminal, and a drain electrically connected to the first output terminal;

[0028] The second pull-up sub-circuit includes: a second pull-up transistor, a gate electrically connected to the second node, a source electrically connected to the third voltage signal terminal, and a drain electrically connected to the second output terminal;

[0029] The second pull-down sub-circuit includes: a second pull-down transistor, a gate electrically connected to the third node, a source electrically connected to the fourth voltage signal terminal, and a drain electrically connected to the second output terminal.

[0030] In some embodiments, when the first node and the second node are different nodes, the third node and the second node are both electrically connected to the first voltage signal terminal, and the third voltage signal terminal and the fourth voltage signal terminal are the same input terminal, one of the second pull-up transistor and the second pull-down transistor is a P-type transistor, and the other is an N-type transistor.

[0031] In some embodiments, the non-display area further includes a plurality of binding terminals and one or more detection transistors, the plurality of detection transistors are spaced apart from each other, the detection transistors are disposed in the same layer as the switch transistor, and the structures located in the same film layer are made of the same material and / or have the same thickness;

[0032] The detection transistor includes a second gate, a second source, a second drain and a second bias electrode. The second gate and the second bias electrode are directly connected to the same gate driving unit respectively. The second source and the second drain are electrically connected to different binding terminals.

[0033] In some embodiments, the bias signal line includes a first line segment and a second line segment, the first line segment does not overlap with the orthographic projection of the data line on the base substrate, the second line segment overlaps with the orthographic projection of the data line on the base substrate, and the width of the second line segment along the column direction is less than or equal to the width of the first line segment along the column direction.

[0034] In some embodiments, an orthographic projection of the bias signal line on the base substrate is located within an orthographic projection region of the gate line on the base substrate.

[0035] In some embodiments, the bias signal line and the gate line have no overlap in their orthographic projections on the substrate.

[0036] In some embodiments, the bias signal line and the orthographic projection of the pixel electrode on the base substrate do not overlap.

[0037] In some embodiments, the gate line is electrically connected to the gate driving unit via a first lead, the bias signal line is electrically connected to the gate driving unit via a second lead, and the orthographic projections of the first lead and the second lead on the substrate are at least partially non-overlapping.

[0038] In some embodiments, the gate line, the first lead, and the first gate are located in a first conductive layer, and the bias signal line, the second lead, and the first bias electrode are located in a second conductive layer;

[0039] The non-display area further includes a common electrode lead, and the common electrode lead and the data line are located in the third conductive layer;

[0040] The common electrode lead includes a hollow hole. In an orthographic projection on the base substrate, the hollow hole overlaps with the first lead and the second lead respectively, and the hollow hole covers the first lead and the second lead in the column direction.

[0041] In some embodiments, when the gate line and the bias signal line are electrically connected to the same output end of the same gate driving unit, the first lead is electrically connected to a first transfer pattern, the second lead is electrically connected to a second transfer pattern, the first transfer pattern is located in the first conductive layer, the second transfer pattern is located in the second conductive layer, and the second transfer pattern is electrically connected to the first transfer pattern through a first via hole, the second transfer pattern is electrically connected to a common output pattern through a second via hole, and the common output pattern is located in the third conductive layer and electrically connected to the same output end.

[0042] The present disclosure provides a display panel including the display substrate as described in any one of the embodiments.

[0043] The present disclosure provides a display device, comprising:

[0044] The display panel according to any one of the embodiments; and

[0045] The driving circuit is electrically connected to the display substrate and is used to provide a driving signal to the display substrate.

[0046] The present disclosure provides a method for driving a display substrate, which is applied to the display substrate according to any embodiment. The method includes:

[0047] The gate driving unit is controlled to provide a scanning signal to the gate line and a bias signal to the bias signal line, wherein the scanning signal can turn on the first source and the first drain in the first stage and disconnect the first source and the first drain in the second stage, and the bias signal and the scanning signal have the same phase at the same time.

[0048] In some embodiments, the scan signal includes a first voltage signal and a second voltage signal, and the bias signal includes a third voltage signal and a fourth voltage signal;

[0049] The gate driving unit includes: a first pull-up sub-circuit, a first pull-down sub-circuit, a second pull-up sub-circuit and a second pull-down sub-circuit, the first pull-up sub-circuit is electrically connected to the first node, the first voltage signal terminal and the first output terminal respectively, the first pull-down sub-circuit is electrically connected to the first node, the second voltage signal terminal and the first output terminal respectively, the second pull-up sub-circuit is electrically connected to the second node, the third voltage signal terminal and the second output terminal respectively, the second pull-down sub-circuit is electrically connected to the third node, the fourth voltage signal terminal and the second output terminal respectively, the first output terminal and the second output terminal are different output terminals, and the first output terminal is electrically connected to the gate line, and the second output terminal is electrically connected to the bias signal line;

[0050] The step of controlling the gate driving unit to provide a scanning signal to the gate line and a bias signal to the bias signal line comprises:

[0051] In a first stage, a first voltage signal is provided to the first voltage signal terminal so that the first pull-up sub-circuit writes the first voltage signal to the first output terminal, and a third voltage signal is provided to the third voltage signal terminal so that the second pull-up sub-circuit writes the third voltage signal to the second output terminal;

[0052] In the second stage, a second voltage signal is provided to the second voltage signal terminal so that the first pull-down sub-circuit writes the second voltage signal to the first output terminal, and a fourth voltage signal is provided to the fourth voltage signal terminal so that the second pull-down sub-circuit writes the fourth voltage signal to the second output terminal;

[0053] When the first node and the second node are different nodes, the third node and the first node are the same node, and the second node is electrically connected to the first voltage signal end, the first voltage signal is a clock signal, and the third voltage signal is a DC signal.

[0054] In some embodiments, the non-display area further includes a detection transistor, which is formed using the same process as the switching transistor. Before the step of controlling the gate driving unit to provide a scan signal to the gate line and a bias signal to the bias signal line, the driving method further includes:

[0055] obtaining characteristics of the detection transistor;

[0056] predicting the characteristics of the switching transistor based on the characteristics of the detection transistor;

[0057] The step of controlling the gate driving unit to provide a scanning signal to the gate line and a bias signal to the bias signal line comprises:

[0058] According to the predicted characteristics of the switching transistor, the gate driving unit is controlled to provide a scanning signal to the gate line and a bias signal to the bias signal line.

[0059] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0060] BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0062] FIG1 exemplarily shows a schematic diagram of a planar structure of a display substrate;

[0063] FIG2 exemplarily shows a schematic cross-sectional structure diagram of a switching transistor;

[0064] FIG3 exemplarily shows a circuit structure diagram of a first gate driving unit;

[0065] FIG4 exemplarily shows a timing diagram of input and output signals of a first gate driving unit;

[0066] FIG5 exemplarily shows a circuit structure diagram of a second gate driving unit;

[0067] FIG6 exemplarily shows a timing diagram of input and output signals of a second gate driving unit;

[0068] FIG7 exemplarily shows a circuit structure diagram of a third gate driving unit;

[0069] FIG8 exemplarily shows a timing diagram of input and output signals of a third gate driving unit;

[0070] FIG9 exemplarily shows a circuit structure diagram of a fourth gate driving unit;

[0071] FIG10 exemplarily shows a timing diagram of input and output signals of a fourth gate driving unit;

[0072] FIG11 exemplarily shows the position and connection structure diagram of the detection transistor;

[0073] FIG12 exemplarily shows a schematic diagram of the position of a detection transistor in a display substrate;

[0074] FIG13 exemplarily shows a schematic diagram of a planar structure of a first display area;

[0075] FIG14 exemplarily shows a schematic diagram of a planar structure of a second display area;

[0076] FIG15 exemplarily shows a schematic diagram of a planar structure of a third display area;

[0077] FIG16 exemplarily shows a circuit layout diagram of a fourth display area;

[0078] FIG17 exemplarily shows a circuit layout diagram of a fifth display area;

[0079] FIG. 18 exemplarily shows a circuit layout diagram at the junction of the display area and the non-display area.

[0080] Detailed description

[0081] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0082] The present disclosure provides a display substrate, as shown in FIG1 , which includes: a base substrate 10 (not shown in FIG1 ), and a display area AA and a non-display area NA located on one side of the base substrate 10 . The non-display area NA may be located on at least one side of the display area AA.

[0083] As shown in FIG1 , the non-display area NA includes a plurality of gate driving units GOA connected in cascade, such as a first-stage gate driving unit GOA1 and a second-stage gate driving unit GOA2 .

[0084] Exemplarily, the gate driving unit GOA can be located on one side of the display area AA (such as the left side) to achieve unilateral driving of the gate line GL. The gate driving unit GOA can also be located on two opposite sides of the display area AA (such as the left and right sides) to achieve bilateral driving of the gate line GL.

[0085] As shown in FIG1 , the display area AA includes a plurality of gate lines GL extending along a row direction f1, a plurality of bias signal lines BL extending along the row direction f1, and a plurality of data lines DL extending along a column direction f2. The orthographic projections of the gate lines GL and the data lines DL on the base substrate 10 intersect with each other to form a plurality of sub-pixel areas.

[0086] For example, a sub-pixel region includes a sub-pixel PX. As shown in Figures 1 and 2, sub-pixel PX includes a switching transistor T1 and a pixel electrode PE. Switching transistor T1 includes a first gate G1, a first source S1, a first drain D1, and a first bias electrode B1. The first gate G1 is electrically connected to the gate line GL, the first source S1 is electrically connected to the data line DL, the first drain D1 is electrically connected to the pixel electrode PE, and the first bias electrode B1 is electrically connected to the bias signal line BL. The first bias electrode B1 and the first gate G1 are stacked on both sides of the active layer ACT1 of the switching transistor T1.

[0087] As shown in Figure 1, the gate line GL is electrically connected between the first gate G1 and the gate driving unit GOA, the bias signal line BL is electrically connected between the first bias electrode B1 and the gate driving unit GOA, and in the same row of sub-pixels PX, the bias signal line BL and the gate line GL are directly connected to the same gate driving unit GOA.

[0088] The bias signal line BL and the gate line GL are directly connected to the same gate driving unit GOA, which means that no other signal processing unit, such as an inverter, is provided between the gate driving unit GOA and the bias signal line BL, and between the gate driving unit GOA and the gate line GL.

[0089] In the present disclosure, the threshold voltage V th is related to the bias voltage Vb of the first bias electrode B1 and satisfies the following formula: Among them, γ is the body effect coefficient, and is the Fermi potential, Vsb is the voltage difference between the first source voltage Vs of the switching transistor T1 and the bias voltage Vb of the first bias electrode B1, when Vsb is equal to zero, the threshold voltage V th V th0 Taking the switching transistor T1 as an N-type transistor as an example, when the bias voltage Vb drops to a negative potential less than zero, more positively charged holes will be attracted to the vicinity of the first bias electrode B1, leaving a large amount of immovable negative charges, which will cause the width of the depletion layer to increase. As the bias voltage Vb decreases, the total amount of charge in the depletion layer increases, resulting in a threshold voltage V th Increase. When the bias voltage Vb increases to a positive potential greater than zero, as the bias voltage Vb increases, the threshold voltage V th Decrease.

[0090] That is, when the bias voltage Vb is positive, Vsb<0, and as the bias voltage Vb increases, the threshold voltage V th When the bias voltage Vb is negative, Vsb>0, as the bias voltage Vb decreases, the threshold voltage V th This effect is called the body effect of the transistor.

[0091] According to the body effect of the transistor, the threshold voltage of the switching transistor T1 can be adjusted by controlling the bias voltage Vb of the first bias electrode B1, thereby controlling the on-current, leakage current, subthreshold current, etc. of the switching transistor T1.

[0092] Taking the switching transistor T1 as an N-type transistor as an example, when the switching transistor T1 is in the on state, a bias voltage Vb greater than zero can be applied to the first bias electrode B1 to make Vsb < 0 (i.e., Vs < Vb), thereby lowering the threshold voltage of the switching transistor T1, thereby lowering the turn-on voltage, increasing the on-current, improving the subthreshold swing coefficient, and improving the turn-on capability of the switching transistor T1. When the switching transistor T1 is in the off state, a bias voltage Vb less than or equal to zero (or a positive bias voltage Vb less than the threshold voltage) can be applied to the first bias electrode B1 to make Vsb > 0 (i.e., Vs > Vb), thereby increasing the threshold voltage of the switching transistor T1, thereby reducing leakage current, reducing power consumption, and improving voltage holding ratio. In other words, in different operating states of the switching transistor T1, by applying different bias voltages Vb to the first bias electrode B1, the threshold voltage of the switching transistor T1 can be changed. In specific implementations, the magnitude of the bias voltage Vb can be adjusted according to actual needs, and this disclosure is not limited to this.

[0093] In the present disclosure, the scan signal gate on the first gate G1 and the bias signal bias on the first bias electrode B1 are provided by the same gate driver unit GOA. The gate driver unit GOA transmits the scan signal gate directly to the first gate G1 via the gate line GL and transmits the bias signal bias directly to the first bias electrode B1 via the bias signal line BL, thereby realizing signal supply between the first gate G1 and the first bias electrode B1. The scan signal gate can turn on the first source S1 and the first drain D1 in the first phase t1 and disconnect the first source S1 and the first drain D1 in the second phase t2.

[0094] Exemplarily, as shown in FIG. 4 , FIG. 6 , FIG. 8 or FIG. 10 , the bias signal bias and the scanning signal gate have the same phase at the same moment.

[0095] As shown in Figure 1 , the first gate electrodes G1 of sub-pixels PX in the same row are electrically connected to the same gate line GL, while the first gate electrodes G1 of sub-pixels PX in different rows are electrically connected to different gate lines GL. Similarly, the first bias electrodes B1 of sub-pixels PX in the same row are electrically connected to the same bias signal line BL, while the first bias electrodes B1 of sub-pixels PX in different rows are electrically connected to different bias signal lines BL.

[0096] For example, as shown in FIG2 , the first gate G1 is located on a side of the active layer ACT1 of the switching transistor T1 that is close to the base substrate 10, and the first bias electrode B1 is located on a side of the active layer ACT1 of the switching transistor T1 that is away from the base substrate 10. Of course, the first bias electrode B1 may also be located on a side of the active layer ACT1 of the switching transistor T1 that is close to the base substrate 10, and the first gate G1 may be located on a side of the active layer ACT1 of the switching transistor T1 that is away from the base substrate 10, and this disclosure is not limited thereto.

[0097] In some embodiments, as shown in FIG. 2 , the first gate G1 and the first bias electrode B1 are disposed in different layers from the first source S1 , and the first source S1 and the first drain D1 are disposed in the same layer.

[0098] In the present disclosure, "same-layer arrangement" refers to a structure in which two (or more) structures are formed by the same patterning process. "Different-layer arrangement" refers to a structure in which two (or more) structures are formed by different patterning processes.

[0099] Exemplarily, the first source S1 and the first drain D1 are provided in the same layer and made of the same material.

[0100] Since the first gate G1 and the first source S1 are arranged in different layers, and the first bias electrode B1 and the first source S1 are arranged in different layers, the display substrate provided in this embodiment is compatible with amorphous silicon processes and LTPS processes, thereby reducing process complexity.

[0101] Exemplarily, as shown in FIG. 2 , the first source electrode S1 (and the first drain electrode D1 ) are stacked between the active layer ACT1 of the switching transistor T1 and the first bias electrode B1 .

[0102] Exemplarily, the first gate G1 is provided on the same layer and made of the same material as the gate line GL, the first bias electrode B1 is provided on the same layer and made of the same material as the bias signal line BL, and the data line DL, the first source electrode S1, and the first drain electrode D1 are provided on the same layer and made of the same material. For example, as shown in FIG2 , the first gate G1 and the gate line GL are located in the first conductive layer LA1, the first bias electrode B1 and the bias signal line BL are located in the second conductive layer LA2, and the data line DL, the first source electrode S1, and the first drain electrode D1 are located in the third conductive layer LA3. The first conductive layer LA1, the active layer ACT1 of the switching transistor T1, the third conductive layer LA3, and the second conductive layer LA2 are sequentially stacked on one side of the base substrate 10.

[0103] For example, as shown in FIG2 , a gate insulating layer GI may be further provided between the first conductive layer LA1 and the active layer ACT1 , and a passivation layer PVX may be further provided between the third conductive layer LA3 and the second conductive layer LA2 .

[0104] Illustratively, the first bias electrode B1 may be made of a transparent conductive material, such as metal oxides such as ITO, IZO, IGZO, IGO, and ZTO, or metal materials such as Cu, Mo, Al, Ag, and Mg.

[0105] Exemplarily, the signals on the first bias electrode B1 and the first gate G1 are different.

[0106] For example, the signal on the first bias electrode B1 and the signal on the first gate G1 have the same phase at the same time, but different amplitudes. For example, at the same time, the amplitude of the signal on the first bias electrode B1 is greater than the amplitude of the signal on the first gate G1, which can better optimize the characteristics of the switching transistor. Of course, the amplitude of the signal on the first bias electrode B1 can also be smaller than the amplitude of the signal on the first gate G1, and this is not limited in this disclosure.

[0107] Since the signal on the first bias electrode B1 and the signal on the bias signal line BL are both bias signals, and the signal on the first gate G1 and the signal on the gate line GL are both scan signals gate, the signals on the gate line GL and the bias signal line BL are different.

[0108] Exemplarily, the scanning signal gate and the bias signal bias have the same phase at the same time, but different amplitudes. For example, at the same time, the amplitude of the bias signal bias is greater than the amplitude of the scanning signal gate, which can better optimize the characteristics of the switching transistor. Of course, the amplitude of the bias signal bias can also be smaller than the amplitude of the scanning signal gate, and this disclosure is not limited to this.

[0109] In some embodiments, as shown in FIG. 3 , the gate line GL and the bias signal line BL are electrically connected to the same output terminal of the same gate driving unit GOA, such as the first output terminal OP1 .

[0110] 3 , the gate line GL and the bias signal line BL are both electrically connected to the first output terminal OP1 of the gate driving unit GOA. This eliminates the need to change the design of the gate driving unit GOA, avoids adding wiring in the non-display area NA, and avoids increasing circuit costs.

[0111] A timing diagram of the first voltage signal V1, the scanning signal gate, and the bias signal bias is shown in FIG4 . As shown in FIG4 , the scanning signal gate provided by the gate driving unit GOA shown in FIG3 to the gate line GL and the bias signal bias provided to the bias signal line BL have the same phase and amplitude at the same time.

[0112] This embodiment does not require drilling holes in the display area AA to electrically connect the first gate G1 and the first bias electrode B1 , and can provide the same scan signal gate and bias signal bias to the first gate G1 and the first bias electrode B1 , thereby reducing process complexity and improving yield.

[0113] Taking the switching transistor T1 as an N-type transistor as an example, as shown in Figure 4, in the first stage t1, the scanning signal gate is at a high potential, the switching transistor T1 is turned on, and the bias signal bias is at a high potential, thereby reducing the threshold voltage of the switching transistor T1; in the second stage t2, the scanning signal gate is at a low potential, the switching transistor T1 is turned off, and the bias signal bias is at a low potential, thereby increasing the threshold voltage of the switching transistor T1.

[0114] Exemplarily, as shown in Figure 3, the gate driving unit GOA includes: a first output circuit 31, which is electrically connected to the first node N1, the first voltage signal terminal CLK, the second voltage signal terminal VGL and the first output terminal OP1, respectively, and is configured to write the first voltage signal V1 provided by the first voltage signal terminal CLK into the first output terminal OP1 in the first stage t1, and write the second voltage signal V2 provided by the second voltage signal terminal VGL into the first output terminal OP1 in the second stage t2 according to the potential of the first node N1.

[0115] In this example, the scan signal gate and the bias signal bias are output by the same output circuit, namely the first output circuit 31. There is no need to set up an additional output circuit for the bias signal bias in the gate driving unit GOA, thereby saving wiring space in the non-display area NA and reducing circuit costs.

[0116] Among them, the first output circuit 31 is controlled by the first node N1, and the first voltage signal terminal CLK provides the scanning signal gate and the bias signal bias (i.e., the first voltage signal V1) of the first stage t1 to the first output terminal OP1, and the second voltage signal terminal VGL provides the scanning signal gate and the bias signal bias (i.e., the second voltage signal V2) of the second stage t2 to the first output terminal OP1.

[0117] Exemplarily, as shown in Figure 3, the first output circuit 31 includes: a first pull-up sub-circuit 311, which is electrically connected to the first node N1, the first voltage signal terminal CLK and the first output terminal OP1, respectively, and is configured to write the first voltage signal V1 to the first output terminal OP1 in the first stage t1 according to the potential of the first node N1; and a first pull-down sub-circuit 312, which is electrically connected to the first node N1, the second voltage signal terminal VGL and the first output terminal OP1, respectively, and is configured to write the second voltage signal V2 to the first output terminal OP1 in the second stage t2 according to the potential of the first node N1.

[0118] Exemplarily, the first pull-up sub-circuit 311 includes: a first pull-up transistor M3 , a gate electrically connected to the first node N1 , a source electrically connected to the first voltage signal terminal CLK, and a drain electrically connected to the first output terminal OP1 .

[0119] Exemplarily, the first pull-down sub-circuit 312 includes: a first pull-down transistor M4 , a gate electrically connected to the first node N1 , a source electrically connected to the second voltage signal terminal VGL, and a drain electrically connected to the first output terminal OP1 .

[0120] In other embodiments, as shown in FIG. 5 , FIG. 7 or FIG. 9 , the gate line GL and the bias signal line BL are electrically connected to different output terminals of the same gate driving unit GOA.

[0121] 5, 7 or 9, the first output end OP1 and the second output end OP2 are different output ends of the same gate driving unit GOA, and the first output end OP1 is electrically connected to the gate line GL, and the second output end OP2 is electrically connected to the bias signal line BL.

[0122] Exemplarily, as shown in Figures 5, 7 or 9, the gate driving unit GOA includes: a first output circuit 31, which is electrically connected to the first node N1, the first voltage signal terminal CLK, the second voltage signal terminal VGL and the first output terminal OP1, respectively, and is configured to write the first voltage signal V1 provided by the first voltage signal terminal CLK into the first output terminal OP1 in the first stage t1 according to the potential of the first node N1, and write the second voltage signal V2 provided by the second voltage signal terminal VGL into the first output terminal OP1 in the second stage t2; and a second output circuit 51, which is electrically connected to the second node N2, the third node N3, the third voltage signal terminal BIASH, the fourth voltage signal terminal BIASL and the second output terminal OP2, respectively, and is configured to write the third voltage signal V3 provided by the third voltage signal terminal BIASH into the second output terminal OP2 in the first stage t1 according to the potential of the second node N2, and write the fourth voltage signal V4 provided by the fourth voltage signal terminal BIASL into the second output terminal OP2 in the second stage t2 according to the potential of the third node N3.

[0123] In this example, the scan signal gate and the bias signal bias are output by two different output circuits, namely, a first output circuit 31 and a second output circuit 51. The first output circuit 31 is controlled by the first node N1 and provides the scan signal gate (i.e., the first voltage signal V1) of the first phase t1 to the first output terminal OP1 via the first voltage signal terminal CLK, and provides the scan signal gate (i.e., the second voltage signal V2) of the second phase t2 to the first output terminal OP1 via the second voltage signal terminal VGL. The second output circuit 51 is controlled by the second node N2 and the third node N3 and provides the bias signal bias of the first phase t1 (i.e., the third voltage signal V3) to the second output terminal OP2 via the third voltage signal terminal BIASH, and provides the bias signal bias of the second phase t2 (i.e., the fourth voltage signal V4) to the second output terminal OP2 via the fourth voltage signal terminal BIASL.

[0124] In this way, by separately setting the output circuits of the scan signal gate and the bias signal bias, the adjustment freedom of the bias signal bias can be increased, and the magnitude of the bias voltage Vb can be adjusted according to actual needs.

[0125] Exemplarily, as shown in Figures 5, 7 or 9, the first output circuit 31 includes: a first pull-up sub-circuit 311, which is electrically connected to the first node N1, the first voltage signal terminal CLK and the first output terminal OP1, respectively, and is configured to write the first voltage signal V1 to the first output terminal OP1 in the first stage t1 according to the potential of the first node N1; and a first pull-down sub-circuit 312, which is electrically connected to the first node N1, the second voltage signal terminal VGL and the first output terminal OP1, respectively, and is configured to write the second voltage signal V2 to the first output terminal OP1 in the second stage t2 according to the potential of the first node N1.

[0126] Exemplarily, as shown in Figures 5, 7 or 9, the second output circuit 51 includes: a second pull-up sub-circuit 511, which is electrically connected to the second node N2, the third voltage signal terminal BIASH and the second output terminal OP2, respectively, and is configured to write the third voltage signal V3 to the second output terminal OP2 in the first stage t1 according to the potential of the second node N2; and a second pull-down sub-circuit 512, which is electrically connected to the third node N3, the fourth voltage signal terminal BIASL and the second output terminal OP2, respectively, and is configured to write the fourth voltage signal V4 to the second output terminal OP2 in the second stage t2 according to the potential of the third node N3.

[0127] 5 , 7 or 9 , the first pull-up sub-circuit 311 includes a first pull-up transistor M3 having a gate electrically connected to the first node N1 , a source electrically connected to the first voltage signal terminal CLK, and a drain electrically connected to the first output terminal OP1 .

[0128] 5 , 7 or 9 , the first pull-down sub-circuit 312 includes a first pull-down transistor M4 having a gate electrically connected to the first node N1 , a source electrically connected to the second voltage signal terminal VGL, and a drain electrically connected to the first output terminal OP1 .

[0129] 5 , 7 or 9 , the second pull-up sub-circuit 511 includes a second pull-up transistor M8 having a gate electrically connected to the second node N2 , a source electrically connected to the third voltage signal terminal BIASH , and a drain electrically connected to the second output terminal OP2 .

[0130] Exemplarily, the second pull-down sub-circuit 512 includes: a second pull-down transistor M9 , a gate electrically connected to the third node N3 , a source electrically connected to the fourth voltage signal terminal BIASL, and a drain electrically connected to the second output terminal OP2 .

[0131] The electrical connection relationship among the first node N1 , the second node N2 , and the third node N3 is exemplarily described below.

[0132] In the first example, the first node N1 , the second node N2 , and the third node N3 are the same node.

[0133] As shown in FIG5 , the first node N1 , the second node N2 and the third node N3 are all nodes PU, that is, the output of the first output circuit 31 and the second output circuit 51 are both controlled by the potential of the node PU.

[0134] In the first example, the first voltage signal terminal CLK, the second voltage signal terminal VGL, the third voltage signal terminal BIASH, and the fourth voltage signal terminal BIASL are different signal terminals that can independently provide signals to the gate drive unit GOA. In this way, by adjusting the voltages input to the gate drive unit GOA from the third voltage signal terminal BIASH and the fourth voltage signal terminal BIASL, the bias signal bias in the first stage t1 and the second stage t2 can be adjusted, making the bias signal bias adjustable. Therefore, a more ideal threshold voltage can be obtained by adjusting the bias signal bias according to actual circuit requirements, process or environmental differences.

[0135] To ensure that the scan signal gate and the bias signal bias are in phase at the same time, illustratively, the first voltage signal V1 and the third voltage signal V3 are in phase at the first stage t1, and the second voltage signal V2 and the fourth voltage signal V4 are in phase at least at the second stage t2. For example, the second voltage signal V2 and the fourth voltage signal V4 are both high-level or low-level DC signals.

[0136] Since the outputs of the first output circuit 31 and the second output circuit 51 are both controlled by the potential of the node PU, in order to ensure that the scanning signal gate and the bias signal bias are in the same phase at the same time, and to avoid the node PU jumping to a high potential before the first stage t1, causing the second pull-up sub-circuit 511 to output, the third voltage signal V3 is also in the same phase as the first voltage signal V1 in the second stage t2, and is opposite to the phase in the first stage t1. Therefore, the third voltage signal V3 and the first voltage signal V1 are timing-synchronized pulse signals, and the two have the same phase at the same time, and the amplitudes can be the same or different.

[0137] 6 shows a timing diagram of a first voltage signal V1, a third voltage signal V3, a fourth voltage signal V4, a scanning signal gate, and a bias signal bias. As shown in FIG6, the first voltage signal V1 is a clock signal, the second voltage signal V2 is, for example, a low-voltage DC signal (not shown in FIG6), the third voltage signal V3 is a pulse signal, and the fourth voltage signal V4 is, for example, a low-voltage DC signal. As shown in FIG5, the scanning signal gate provided by the gate drive unit GOA to the gate line GL and the bias signal bias provided to the bias signal line BL have the same phase at the same time, and the amplitudes can be the same or different.

[0138] Taking the switching transistor T1 as an N-type transistor as an example, as shown in FIG6 , in the first phase t1, the first voltage signal V1 is at a high level, the scanning signal gate is at a high level during the first phase t1, and the switching transistor T1 is turned on. Simultaneously, the third voltage signal V3 is at a high level, and the bias signal bias during the first phase t1 is at a high level, thereby lowering the threshold voltage of the switching transistor T1. In the second phase t2, the second voltage signal V2 is at a low level, the scanning signal gate during the second phase t2 is at a low level, and the switching transistor T1 is turned off. Simultaneously, the fourth voltage signal V4 is at a low level, and the bias signal bias during the second phase t2 is at a low level, thereby increasing the threshold voltage of the switching transistor T1.

[0139] In the second example, the first node N1 and the second node N2 are different nodes, and the third node N3 and the first node N1 are the same node.

[0140] As shown in FIG7 , the first node N1 and the third node N3 are both nodes PU, and the second node N2 is the first voltage signal terminal CLK. That is, the output of the first output circuit 31 is controlled by the potential of the node PU, and the second output circuit 51 is controlled by the potential of the node PU and the potential of the first voltage signal terminal CLK.

[0141] In the second example, because the second node N2 is the first voltage signal terminal CLK, and the first voltage signal V1 input to the first voltage signal terminal CLK is a clock signal, the third voltage signal V3 at the third voltage signal terminal BIASH can be a DC signal. Under the control of the clock signal, the second output circuit 51 can still synchronize the bias signal bias with the scan signal gate. By setting the third voltage signal V3 at the third voltage signal terminal BIASH to a DC signal, efficiency can be improved and costs can be reduced.

[0142] In the second example, the first voltage signal terminal CLK, the second voltage signal terminal VGL, the third voltage signal terminal BIASH, and the fourth voltage signal terminal BIASL are different signal terminals that can independently provide signals to the gate drive unit GOA. In this way, by adjusting the voltages input to the gate drive unit GOA from the third voltage signal terminal BIASH and the fourth voltage signal terminal BIASL, the bias signal bias in the first stage t1 and the second stage t2 can be adjusted, making the bias signal bias adjustable. Therefore, a more ideal threshold voltage can be obtained by adjusting the bias signal bias according to actual circuit requirements, process or environmental differences.

[0143] To ensure that the scan signal gate and the bias signal bias are in phase at the same time, illustratively, the first voltage signal V1 and the third voltage signal V3 are in phase during the first phase t1, and the second voltage signal V2 and the fourth voltage signal V4 are in phase at least during the second phase t2. For example, the second voltage signal V2 and the fourth voltage signal V4 are both high-level or low-level DC signals. The first voltage signal V1 is a clock signal, and the third voltage signal V3 is a high-level or low-level DC signal.

[0144] 8 shows a timing diagram of a first voltage signal V1, a third voltage signal V3, a fourth voltage signal V4, a scanning signal gate, and a bias signal bias. As shown in FIG8, the first voltage signal V1 is a clock signal, the second voltage signal V2 is, for example, a low-voltage DC signal (not shown in FIG8), the third voltage signal V3 is, for example, a high-voltage DC signal, and the fourth voltage signal V4 is, for example, a low-voltage DC signal. As shown in FIG7, the scanning signal gate provided by the gate drive unit GOA to the gate line GL and the bias signal bias provided to the bias signal line BL have the same phase at the same time, and the amplitudes may be the same or different.

[0145] Taking the switching transistor T1 as an N-type transistor as an example, as shown in FIG8 , in the first phase t1, the first voltage signal V1 is at a high level, the scanning signal gate is at a high level during the first phase t1, and the switching transistor T1 is turned on. Simultaneously, the third voltage signal V3 is at a high level, and the bias signal bias during the first phase t1 is at a high level, thereby lowering the threshold voltage of the switching transistor T1. In the second phase t2, the second voltage signal V2 is at a low level, the scanning signal gate during the second phase t2 is at a low level, and the switching transistor T1 is turned off. Simultaneously, the fourth voltage signal V4 is at a low level, and the bias signal bias during the second phase t2 is at a low level, thereby increasing the threshold voltage of the switching transistor T1.

[0146] In the third example, the first node N1 and the second node N2 are different nodes, and the third node N3 and the second node N2 are the same node.

[0147] As shown in FIG9 , the first node N1 is the node PU, and the second node N2 and the third node N3 are both the first voltage signal terminal CLK. That is, the output of the first output circuit 31 is controlled by the potential of the node PU, and the second output circuit 51 is controlled by the potential inputted by the first voltage signal terminal CLK.

[0148] In the third example, the first voltage signal terminal CLK, the second voltage signal terminal VGL, and the third voltage signal terminal BIASH are different signal terminals, which can independently provide signals to the gate drive unit GOA. Among them, the third voltage signal terminal BIASH and the fourth voltage signal terminal BIASL can be the same input terminal, and the third voltage signal V3 and the fourth voltage signal V4 are the same signal. In this case, the third voltage signal V3 (or the fourth voltage signal V4) is a pulse signal. By adjusting the size of the third voltage signal V3 (or the fourth voltage signal V4), the bias signal bias of the first stage t1 and the second stage t2 can be adjusted, so that the size of the bias signal bias is adjustable, so that a more ideal threshold voltage can be obtained by adjusting the size of the bias signal bias according to the actual needs of the circuit, process or environmental differences.

[0149] To ensure that the scanning signal gate and the bias signal bias are in phase at the same time, illustratively, the first voltage signal V1 and the third voltage signal V3 are in phase at the first stage t1, and the second voltage signal V2 and the fourth voltage signal V4 are in phase at least at the second stage t2. For example, the second voltage signal V2 is a high-level or low-level DC signal. The first voltage signal V1 is a clock signal, and the third voltage signal V3 (or the fourth voltage signal V4) is a pulse signal that is synchronized with the first voltage signal V1. The two are in phase at the same time, and the amplitudes can be the same or different.

[0150] 10 shows a timing diagram of a first voltage signal V1, a third voltage signal V3, a fourth voltage signal V4, a scan signal gate, and a bias signal bias. As shown in FIG10 , the first voltage signal V1 is a clock signal, the second voltage signal V2 is, for example, a low-voltage DC signal (not shown in FIG10 ), the third voltage signal V3 and the fourth voltage signal V4 are pulse signals, and the scan signal gate provided by the gate drive unit GOA to the gate line GL and the bias signal bias provided to the bias signal line BL shown in FIG9 have the same phase at the same time, and may have the same or different amplitudes.

[0151] Taking the switching transistor T1 as an N-type transistor as an example, as shown in FIG10 , in the first phase t1, the first voltage signal V1 is at a high level, the scanning signal gate is at a high level during the first phase t1, and the switching transistor T1 is turned on. Simultaneously, the third voltage signal V3 is at a high level, and the bias signal bias during the first phase t1 is at a high level, thereby lowering the threshold voltage of the switching transistor T1. In the second phase t2, the second voltage signal V2 is at a low level, the scanning signal gate during the second phase t2 is at a low level, and the switching transistor T1 is turned off. Simultaneously, the fourth voltage signal V4 is at a low level, and the bias signal bias during the second phase t2 is at a low level, thereby increasing the threshold voltage of the switching transistor T1.

[0152] Exemplarily, when the third node N3 and the second node N2 are both electrically connected to the first voltage signal terminal CLK, and the third voltage signal terminal BIASH and the fourth voltage signal terminal BIASL are the same input terminal, one of the second pull-up transistor M8 and the second pull-down transistor M9 is a P-type transistor, and the other is an N-type transistor.

[0153] For example, the second pull-up transistor M8 is a P-type transistor and the second pull-down transistor M9 is an N-type transistor, or the second pull-up transistor M8 is an N-type transistor and the second pull-down transistor M9 is a P-type transistor.

[0154] Exemplarily, the second pull-up transistor M8 is an N-type transistor, and the second pull-down transistor M9 is a P-type transistor. In the first stage t1, the first voltage signal V1 is at a high level, the second pull-up transistor M8 is turned on, and the second pull-down transistor M9 is turned off, providing a high-level third voltage signal V3 to the second output terminal OP2. In the second stage t2, the first voltage signal V1 is at a low level, the second pull-up transistor M8 is turned off, and the second pull-down transistor M9 is turned on, providing a low-level fourth voltage signal V4 to the second output terminal OP2.

[0155] In this disclosure, "node A and node B are the same node" means that they are located at the same location, or that they are electrically connected via a wire but do not have any electronic components. "Node A and node B are different nodes" means that an electronic component is provided between them. Examples of electronic components include resistors, capacitors, transistors, and amplifiers.

[0156] Exemplarily, as shown in FIG3 , FIG5 , FIG7 or FIG9 , the gate driving unit GOA may further include: a first transistor M1 , a gate electrically connected to the first input terminal Input, a source electrically connected to the first input terminal Input, and a drain electrically connected to the PU node.

[0157] 3, 5, 7 or 9, the gate driving unit GOA may further include: a second transistor M2, a gate electrically connected to the reset control terminal Reset, a source electrically connected to the second voltage signal terminal VGL, and a drain electrically connected to the PU node.

[0158] Exemplarily, as shown in FIG3, FIG5, FIG7 or FIG9, the gate driving unit GOA may further include: a seventh transistor M7, a gate electrically connected to the PU node, a source electrically connected to the second voltage signal terminal VGL, and a drain electrically connected to the PU node.

[0159] Exemplarily, as shown in FIG3 , FIG5 , FIG7 or FIG9 , the gate driving unit GOA may further include: a fifth transistor M5 , a gate and a source both electrically connected to the second input terminal VGH, and a drain electrically connected to the PU node.

[0160] Exemplarily, as shown in FIG3 , FIG5 , FIG7 or FIG9 , the gate driving unit GOA may further include: a sixth transistor M6 , a gate and a drain both electrically connected to the PU node, and a source electrically connected to the second voltage signal terminal VGL.

[0161] In some embodiments, as shown in FIG11 , the non-display area NA further includes a plurality of binding terminals PIN and one or more detection transistors T2 . The plurality of detection transistors T2 are separated from each other. The detection transistors T2 are arranged in the same layer as the switching transistor T1 , and the structures located in the same film layer have the same material and / or the same thickness.

[0162] The detection transistor T2 includes a second gate G2, a second source S2, a second drain D2 and a second bias electrode B2, and the second gate G2 and the second bias electrode B2 are directly connected to the same gate driving unit GOA, and the second source S2 and the second drain D2 are electrically connected to different binding terminals PIN.

[0163] Among them, the second gate G2 and the second bias electrode B2 are directly connected to the same gate driving unit GOA, which means that no other signal processing units, such as inverters, are set between the gate driving unit GOA and the second gate G2, and between the gate driving unit GOA and the second bias electrode B2.

[0164] Exemplarily, the detection transistor T2 and the switching transistor T1 can be formed using the same process. Thus, the detection transistor T2 and the switching transistor T1 have the same stacked structure, and the film layers disposed on the same layer are made of the same material and have the same thickness. For example, the second gate G2 is disposed on the same layer and made of the same material as the first gate G1, the second bias electrode B2 is disposed on the same layer and made of the same material as the first bias electrode B1, the active layer ACT2 of the detection transistor T2 is disposed on the same layer and made of the same material as the active layer ACT1 of the switching transistor T1, and the second source S2, the second drain D2, the first source S1, and the first drain D1 are disposed on the same layer and made of the same material.

[0165] Due to process uniformity limitations and transistor aging, the characteristics of the detection transistor T2 in the non-display area NA are generally slightly worse than or comparable to those of the switching transistor T1 in the display area AA. Therefore, the characteristics of the switching transistor T1 can be predicted based on the characteristics of the detection transistor T2. The bias signal can then be adjusted based on the predicted characteristics of the switching transistor T1, thereby improving the performance of the switching transistor T1.

[0166] The binding terminal PIN is electrically connected to a driver circuit IC (not shown in FIG11 ). The driver circuit IC can obtain the characteristics of the detection transistor T2 through the binding terminal PIN. Based on the characteristics of the detection transistor T2, the characteristics of the switching transistor T1 can be predicted. The bias signal is then adjusted based on the predicted characteristics of the switching transistor T1. Thus, by providing the detection transistor T2, the bias signal adjustment for the display substrate has an adaptive function. That is, the bias signal can be adjusted based on the actual state of the display substrate, thereby improving the performance of the switching transistor T1.

[0167] Exemplarily, as shown in FIG12 , the display substrate is a quadrilateral, the non-display area NA is arranged around the display area AA, the detection transistors T2 are arranged near the four inner corners of the quadrilateral, and the four detection transistors T2 are respectively located at the upper left corner, upper right corner, lower left corner and lower right corner of the display panel.

[0168] As shown in Figure 11, the binding terminal UD is electrically connected to the drains of the detection transistors T2 located in the upper left and upper right corners, and the binding terminal DD is electrically connected to the drains of the detection transistors T2 located in the lower left and lower right corners. The binding terminal LUS is electrically connected to the source of the detection transistor T2 located in the upper left corner, the binding terminal RUS is electrically connected to the source of the detection transistor T2 located in the upper right corner, the binding terminal LDS is electrically connected to the source of the detection transistor T2 located in the lower left corner, and the binding terminal RDS is electrically connected to the source of the detection transistor T2 located in the lower right corner. The binding terminal LGS provides a control signal to the gate drive unit GOA electrically connected to the detection transistors T2 in the upper left and lower left corners, and the binding terminal RGS provides a control signal to the gate drive unit GOA electrically connected to the detection transistors T2 in the upper right and lower right corners.

[0169] Exemplarily, the driving circuit IC first obtains the characteristics of the four detection transistors T2, compares the characteristics of the four detection transistors T2, selects the worst one (or the average value) as the characteristic prediction result of the switching transistor T1, and adjusts the bias signal bias according to the prediction result to obtain better characteristics of the switching transistor T1.

[0170] Illustratively, the gate driving unit GOA electrically connected to the detection transistor T2 and the gate driving unit GOA electrically connected to the switching transistor T1 may be shared or independently provided, which is not limited in the present disclosure.

[0171] In some embodiments, as shown in FIG13 , the bias signal line BL includes a first line segment XD1 and a second line segment XD2, the first line segment XD1 does not overlap with the orthographic projection of the data line DL on the base substrate 10, the second line segment XD2 overlaps with the orthographic projection of the data line DL on the base substrate 10, and the width of the second line segment XD2 along the column direction f2 is less than or equal to the width of the first line segment XD1 along the column direction f2.

[0172] As shown in FIG13 , since the second line segment XD2 overlaps with the data line DL, and the width of the second line segment XD2 along the column direction f2 is smaller than the width of the first line segment XD1 along the column direction f2, by reducing the width of the second line segment XD2 along the column direction f2, the coupling capacitance between the bias signal line BL and the data line DL can be reduced, thereby reducing signal crosstalk.

[0173] 14 and 17 , the orthographic projection of the bias signal line BL on the base substrate 10 is located within the orthographic projection region of the gate line GL on the base substrate 10. Overlapping the gate line GL and the bias signal line BL can improve the aperture ratio of the display substrate.

[0174] In some embodiments, as shown in FIG13 and FIG15 , the orthographic projections of the gate lines GL and the bias signal lines BL on the base substrate 10 do not overlap, and the gate lines GL and the bias signal lines BL are arranged along the column direction f2. This can reduce the coupling capacitance between the gate lines GL and the bias signal lines BL and reduce signal crosstalk.

[0175] Exemplarily, for the switching transistor T1 electrically connected to the gate line GL and the bias signal line BL, the gate line GL and the bias signal line BL are located on the same side of the switching transistor T1, the gate line GL is located between the switching transistor T1 and the bias signal line BL (as shown in FIG13 ), or the gate line GL is located on the side of the bias signal line BL away from the switching transistor T1 (as shown in FIG15 ).

[0176] In some embodiments, as shown in Figures 16 and 17 , the bias signal line BL and the pixel electrode PE have no overlap in their orthographic projections on the base substrate 10. This can reduce the overlapping capacitance between the bias signal line BL and the pixel electrode PE and reduce signal crosstalk.

[0177] As shown in Figures 16 and 17, the gate line GL and the bias signal line BL are located between two adjacent rows of sub-pixels PX. Of course, the orthographic projections of the bias signal line BL and the pixel electrodes PE of adjacent rows on the base substrate 10 may also overlap to save wiring space, which is not limited in this disclosure.

[0178] In order to reduce the coupling capacitance between the gate line GL and the data line DL, as shown in FIG16 , the width of the overlapping region of the gate line GL and the data line DL along the column direction f2 is shrunk, thereby reducing signal crosstalk.

[0179] In some embodiments, as shown in FIG18 , the gate line GL is electrically connected to the gate driver unit GOA via a first lead Y1, and the bias signal line BL is electrically connected to the gate driver unit GOA via a second lead Y2. The orthographic projections of the first lead Y1 and the second lead Y2 on the base substrate 10 at least partially do not overlap. This reduces the coupling capacitance between the first lead Y1 and the second lead Y2, thereby reducing signal crosstalk.

[0180] Exemplarily, the gate line GL, first lead line Y1, and first gate electrode G1 are located in the first conductive layer LA1, while the bias signal line BL, second lead line Y2, and first bias electrode B1 are located in the second conductive layer LA2. The non-display area NA also includes a common electrode lead line COM, which is located in the third conductive layer LA3 along with the data line DL.

[0181] Exemplarily, as shown in FIG18 , the common electrode lead COM includes a hollow hole HL. In the orthographic projection on the base substrate 10 , the hollow hole HL overlaps with the first lead Y1 and the second lead Y2 , respectively, and the hollow hole HL covers the first lead Y1 and the second lead Y2 in the column direction f2 .

[0182] As shown in FIG18 , the width of the hollow hole HL along the column direction f2 is greater than the width of the first lead Y1 and the second lead Y2 along the column direction f2, and the orthographic projections of the first lead Y1 and the second lead Y2 on the base substrate 10 are located within the region of the hollow hole HL at least in the column direction f2.

[0183] In some embodiments, as shown in FIG18 , when the gate line GL and the bias signal line BL are electrically connected to the same output terminal (e.g., the first output terminal OP1) of the same gate drive unit GOA, the first lead Y1 is electrically connected to the first transfer pattern ZJ1, and the second lead Y2 is electrically connected to the second transfer pattern ZJ2. The first transfer pattern ZJ1 is located on the first conductive layer LA1, and the second transfer pattern ZJ2 is located on the second conductive layer LA2. The second transfer pattern ZJ2 is electrically connected to the first transfer pattern ZJ1 through a first via VIA1, and the second transfer pattern ZJ2 is electrically connected to the common output pattern PT through a second via VIA2. The common output pattern PT is located on the third conductive layer LA3 and is electrically connected to the same output terminal (e.g., the first output terminal OP1).

[0184] In order to reduce the contact resistance, illustratively, the plurality of first via holes VIA1 are arranged along the column direction f2 , and the plurality of second via holes VIA2 are arranged along the column direction f2 .

[0185] Exemplarily, the ratio of the width of the first switching pattern ZJ1 along the row direction f1 to the width of the sub-pixel PX along the row direction f1 may be greater than or equal to 1 / 15 and less than or equal to 2 / 15. For example, if the width of the sub-pixel PX along the row direction f1 is 150 microns, the width of the first switching pattern ZJ1 along the row direction f1 may be greater than or equal to 10 microns and less than or equal to 20 microns.

[0186] For example, the non-display area NA further includes a functional transistor with a single-gate structure, which can be formed simultaneously with the switch transistor T1, but does not include the first bias electrode B1. This helps save wiring space in the non-display area NA and reduce coupling capacitance.

[0187] Exemplarily, the transistors in the gate driving unit are all functional transistors, the gate of the functional transistor is set on the same layer and the same material as the first gate G1, the active layer of the functional transistor is set on the same layer and the same material as the active layer ACT1 of the switching transistor T1, and the source (and drain) of the functional transistor is set on the same layer and the same material as the first source S1 (and the first drain D1).

[0188] In the present disclosure, the active layer includes a channel region, a first electrical connection portion and a second electrical connection portion, wherein the channel region is an area in the active layer that overlaps with the positive projection of the gate on the base substrate 10, the first electrical connection portion is an area in the active layer that is electrically connected to the source, and the second electrical connection portion is an area in the active layer that is electrically connected to the drain.

[0189] In order to better control the channel region, illustratively, the orthographic projection of the first bias electrode B1 on the substrate 10 completely covers the orthographic projection of the channel region of the switching transistor T1 on the substrate 10 .

[0190] In order to better control the channel region, illustratively, the orthographic projection of the second bias electrode B2 on the base substrate 10 completely covers the orthographic projection of the channel region of the detection transistor T2 on the base substrate 10 .

[0191] The present disclosure provides a display panel, including the display substrate provided in any embodiment.

[0192] Those skilled in the art will appreciate that the display panel provided by the present disclosure has the advantages of the above-mentioned display substrate.

[0193] Exemplarily, the display panel is a liquid crystal display panel.

[0194] Illustratively, the display panel may further include an opposing substrate disposed opposite to the display substrate, and may further include a liquid crystal layer located between the opposing substrate and the display substrate, which is not limited in the present disclosure.

[0195] The present disclosure provides a display device, including: a display panel as provided in any embodiment; and a driving circuit electrically connected to a display substrate and configured to provide a driving signal to the display substrate.

[0196] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display panel.

[0197] For example, the display device disclosed herein may include, but is not limited to, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function.

[0198] The present disclosure provides a method for driving a display substrate, which is applied to a display substrate provided in any embodiment. The driving method includes:

[0199] Step S01: Control the gate drive unit GOA to provide a scan signal gate to the gate line GL and a bias signal bias to the bias signal line BL. The scan signal gate can turn on the first source S1 and the first drain D1 in the first stage t1, and disconnect the first source S1 and the first drain D1 in the second stage t2. The bias signal bias and the scan signal gate have the same phase at the same time.

[0200] In some embodiments, the scan signal gate includes a first voltage signal V1 and a second voltage signal V2, and the bias signal bias includes a third voltage signal V3 and a fourth voltage signal V4. The gate driving unit GOA includes: a first pull-up sub-circuit 311, a first pull-down sub-circuit 312, a second pull-up sub-circuit 511, and a second pull-down sub-circuit 512. The first pull-up sub-circuit 311 is electrically connected to the first node N1, the first voltage signal terminal CLK, and the first output terminal OP1, respectively. The first pull-down sub-circuit 312 is electrically connected to the first node N1, the second voltage signal terminal VGL, and the first output terminal OP1, respectively. The second pull-up sub-circuit 511 is electrically connected to the second node N2, the third voltage signal terminal BIASH, and the second output terminal OP2, respectively. The second pull-down sub-circuit 512 is electrically connected to the third node N3, the fourth voltage signal terminal BIASL, and the second output terminal OP2, respectively. The first output terminal OP1 and the second output terminal OP2 are different output terminals, and the first output terminal OP1 is electrically connected to the gate line GL, and the second output terminal OP2 is electrically connected to the bias signal line BL.

[0201] In this embodiment, step S01 may specifically include:

[0202] Step S11: In the first phase t1, a first voltage signal V1 is provided to the first voltage signal terminal CLK, so that the first pull-up sub-circuit 311 writes the first voltage signal V1 into the first output terminal OP1, and a third voltage signal V3 is provided to the third voltage signal terminal BIASH, so that the second pull-up sub-circuit 511 writes the third voltage signal V3 into the second output terminal OP2.

[0203] Step S12: In the second phase t2, a second voltage signal V2 is provided to the second voltage signal terminal VGL so that the first pull-down sub-circuit 312 writes the second voltage signal V2 into the first output terminal OP1, and a fourth voltage signal V4 is provided to the fourth voltage signal terminal BIASL so that the second pull-down sub-circuit 512 writes the fourth voltage signal V4 into the second output terminal OP2.

[0204] Exemplarily, when the first node N1 , the second node N2 , and the third node N3 are the same node, the first voltage signal V1 is a clock signal, and the third voltage signal V3 is a pulse signal.

[0205] Exemplarily, when the first node N1 and the second node N2 are different nodes, the third node N3 and the first node N1 are the same node, and the second node N2 is electrically connected to the first voltage signal terminal CLK, the first voltage signal V1 is a clock signal, and the third voltage signal V3 is a DC signal.

[0206] Exemplarily, when the first node N1 and the second node N2 are different nodes, the third node N3 and the second node N2 are both electrically connected to the first voltage signal terminal CLK, and the third voltage signal terminal BIASH and the fourth voltage signal terminal BIASL are the same input terminal, the first voltage signal V1 is a clock signal, and the third voltage signal V3 (or the fourth voltage signal V4) is a pulse signal.

[0207] In some embodiments, the non-display area NA further includes a detection transistor T2, which is formed in the same process as the switch transistor T1. Before step S01, the driving method further includes:

[0208] Step S21: Acquire the characteristics of the detection transistor T2.

[0209] Step S22: predicting the characteristics of the switching transistor T1 based on the characteristics of the detection transistor T2.

[0210] Accordingly, step S01 may specifically include: controlling the gate driving unit GOA to provide a scanning signal gate to the gate line GL and a bias signal bias to the bias signal line BL according to the predicted characteristics of the switching transistor T1 .

[0211] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0212] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0213] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0214] References in this disclosure to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0215] In this disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0216] When describing some embodiments, the expressions "coupled" and "electrically connected" may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this disclosure.

[0217] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0218] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0219] As used in this disclosure, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0220] The use of "for" or "configured to" in this disclosure is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0221] The use of "based on" or "according to" in this disclosure is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0222] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0223] As used in this disclosure, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0224] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0225] The present disclosure describes exemplary embodiments with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this disclosure, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0226] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate, comprising: A base substrate, and a display area and a non-display area located on one side of the base substrate, wherein the non-display area includes a plurality of gate driving units cascaded to each other; The display area includes a plurality of gate lines extending in a row direction, a plurality of bias signal lines extending in a row direction, and a plurality of data lines extending in a column direction, wherein the orthographic projections of the gate lines and the data lines on the substrate intersect with each other to form a plurality of sub-pixel areas; The sub-pixel region includes a sub-pixel, the sub-pixel includes a switching transistor and a pixel electrode, the switching transistor includes a first gate, a first source, a first drain, and a first bias electrode, the first gate is electrically connected to the gate line, the first source is electrically connected to the data line, the first drain is electrically connected to the pixel electrode, and the first bias electrode is electrically connected to the bias signal line, and the first bias electrode and the first gate are stacked on both sides of the active layer of the switching transistor; In the same row of sub-pixels, the bias signal line and the gate line are directly connected to the same gate driving unit respectively.

2. The display substrate according to claim 1, wherein The first gate and the first bias electrode are both arranged in a different layer from the first source, and the first source and the first drain are arranged in the same layer.

3. The display substrate according to claim 1, wherein The first bias electrode and the first gate have different signals.

4. The display substrate according to claim 1, wherein The gate line and the bias signal line are electrically connected to the same output terminal of the same gate driving unit.

5. The display substrate according to claim 1, wherein The gate line and the bias signal line are electrically connected to different output terminals of the same gate driving unit; The gate driving unit includes: a first output circuit, electrically connected to the first node, the first voltage signal terminal, the second voltage signal terminal, and the first output terminal, respectively, and configured to write a first voltage signal provided by the first voltage signal terminal to the first output terminal in a first phase, and to write a second voltage signal provided by the second voltage signal terminal to the first output terminal in a second phase, based on the potential of the first node; a second output circuit, electrically connected to the second node, the third node, the third voltage signal terminal, the fourth voltage signal terminal, and the second output terminal, respectively, and configured to write a third voltage signal provided by the third voltage signal terminal to the second output terminal in a first phase according to the potential of the second node, and to write a fourth voltage signal provided by the fourth voltage signal terminal to the second output terminal in a second phase according to the potential of the third node; The first output end and the second output end are different output ends, and the first output end is electrically connected to the gate line, and the second output end is electrically connected to the bias signal line.

6. The display substrate according to claim 5, wherein: The first output circuit includes: a first pull-up sub-circuit, electrically connected to the first node, the first voltage signal terminal, and the first output terminal, respectively, and configured to write the first voltage signal to the first output terminal in a first phase according to the potential of the first node; a first pull-down sub-circuit, electrically connected to the first node, the second voltage signal terminal, and the first output terminal, respectively, and configured to write the second voltage signal to the first output terminal in a second phase according to the potential of the first node; The second output circuit includes: a second pull-up sub-circuit, electrically connected to the second node, the third voltage signal terminal, and the second output terminal, respectively, and configured to write the third voltage signal into the second output terminal in a first phase according to the potential of the second node; The second pull-down sub-circuit is electrically connected to the third node, the fourth voltage signal terminal and the second output terminal respectively, and is configured to write the fourth voltage signal into the second output terminal in the second stage according to the potential of the third node.

7. The display substrate according to claim 6, wherein: The first node, the second node, and the third node are the same node.

8. The display substrate according to claim 6, wherein: The first node and the second node are different nodes, and the third node and the first node are the same node.

9. The display substrate according to claim 6, wherein: The first node and the second node are different nodes, and the third node and the second node are the same node.

10. The display substrate according to claim 8 or 9, wherein: The second node is electrically connected to the first voltage signal terminal.

11. The display substrate according to claim 6, wherein: The first pull-up sub-circuit includes: a first pull-up transistor, a gate electrically connected to the first node, a source electrically connected to the first voltage signal terminal, and a drain electrically connected to the first output terminal; The first pull-down sub-circuit includes: a first pull-down transistor, a gate electrically connected to the first node, a source electrically connected to the second voltage signal terminal, and a drain electrically connected to the first output terminal; The second pull-up sub-circuit includes: a second pull-up transistor, a gate electrically connected to the second node, a source electrically connected to the third voltage signal terminal, and a drain electrically connected to the second output terminal; The second pull-down sub-circuit includes: a second pull-down transistor, a gate electrically connected to the third node, a source electrically connected to the fourth voltage signal terminal, and a drain electrically connected to the second output terminal.

12. The display substrate according to claim 11, wherein: When the first node and the second node are different nodes, the third node and the second node are both electrically connected to the first voltage signal terminal, and the third voltage signal terminal and the fourth voltage signal terminal are the same input terminal, one of the second pull-up transistor and the second pull-down transistor is a P-type transistor, and the other is an N-type transistor.

13. The display substrate according to claim 1, wherein The non-display area further includes a plurality of binding terminals and one or more detection transistors, wherein the plurality of detection transistors are arranged separately from each other, and the detection transistors are arranged in the same layer as the switch transistor, and the structures located in the same film layer are made of the same material and / or have the same thickness; The detection transistor includes a second gate, a second source, a second drain and a second bias electrode. The second gate and the second bias electrode are directly connected to the same gate driving unit respectively. The second source and the second drain are electrically connected to different binding terminals.

14. The display substrate according to claim 1, wherein The bias signal line includes a first line segment and a second line segment, the first line segment does not overlap with the orthographic projection of the data line on the base substrate, the second line segment overlaps with the orthographic projection of the data line on the base substrate, and the width of the second line segment along the column direction is less than or equal to the width of the first line segment along the column direction.

15. The display substrate according to claim 1, wherein The orthographic projection of the bias signal line on the base substrate is located within the orthographic projection region of the gate line on the base substrate.

16. The display substrate according to claim 1, wherein The orthographic projections of the bias signal line and the gate line on the base substrate do not overlap.

17. The display substrate according to claim 1, wherein The bias signal line and the orthographic projection of the pixel electrode on the base substrate do not overlap.

18. The display substrate according to claim 1, wherein The gate line is electrically connected to the gate driving unit via a first lead, the bias signal line is electrically connected to the gate driving unit via a second lead, and the orthographic projections of the first lead and the second lead on the base substrate at least partially do not overlap.

19. The display substrate according to claim 18, wherein: The gate line, the first lead and the first gate are located in a first conductive layer, and the bias signal line, the second lead and the first bias electrode are located in a second conductive layer; The non-display area further includes a common electrode lead, and the common electrode lead and the data line are located in the third conductive layer; The common electrode lead includes a hollow hole. In an orthographic projection on the base substrate, the hollow hole overlaps with the first lead and the second lead respectively, and the hollow hole covers the first lead and the second lead in the column direction.

20. The display substrate according to claim 19, wherein In the case where the gate line and the bias signal line are electrically connected to the same output end of the same gate drive unit, the first lead is electrically connected to a first transfer pattern, the second lead is electrically connected to a second transfer pattern, the first transfer pattern is located in the first conductive layer, the second transfer pattern is located in the second conductive layer, and the second transfer pattern is electrically connected to the first transfer pattern through a first via hole, the second transfer pattern is electrically connected to a common output pattern through a second via hole, and the common output pattern is located in the third conductive layer and electrically connected to the same output end.

21. A display panel comprising the display substrate according to any one of claims 1 to 20.

22. A display device comprising: The display panel according to claim 22; as well as The driving circuit is electrically connected to the display substrate and is used to provide a driving signal to the display substrate.

23. A method for driving a display substrate, applied to the display substrate according to any one of claims 1 to 20, the method comprising: Control the gate drive unit to provide a scan signal to the gate line and a bias signal to the bias signal line, wherein the scan signal can turn on the first source and the first drain in the first stage. The first source and the first drain are disconnected in the second stage, and the bias signal and the scan signal have the same phase at the same time.

24. The driving method according to claim 23, wherein: The scanning signal includes a first voltage signal and a second voltage signal, and the bias signal includes a third voltage signal and a fourth voltage signal; The gate driving unit includes: a first pull-up sub-circuit, a first pull-down sub-circuit, a second pull-up sub-circuit and a second pull-down sub-circuit, the first pull-up sub-circuit is electrically connected to the first node, the first voltage signal terminal and the first output terminal respectively, the first pull-down sub-circuit is electrically connected to the first node, the second voltage signal terminal and the first output terminal respectively, the second pull-up sub-circuit is electrically connected to the second node, the third voltage signal terminal and the second output terminal respectively, the second pull-down sub-circuit is electrically connected to the third node, the fourth voltage signal terminal and the second output terminal respectively, the first output terminal and the second output terminal are different output terminals, and the first output terminal is electrically connected to the gate line, and the second output terminal is electrically connected to the bias signal line; The step of controlling the gate driving unit to provide a scanning signal to the gate line and a bias signal to the bias signal line comprises: In a first stage, a first voltage signal is provided to the first voltage signal terminal so that the first pull-up sub-circuit writes the first voltage signal to the first output terminal, and a third voltage signal is provided to the third voltage signal terminal so that the second pull-up sub-circuit writes the third voltage signal to the second output terminal; In the second stage, a second voltage signal is provided to the second voltage signal terminal so that the first pull-down sub-circuit writes the second voltage signal to the first output terminal, and a fourth voltage signal is provided to the fourth voltage signal terminal so that the second pull-down sub-circuit writes the fourth voltage signal to the second output terminal; When the first node and the second node are different nodes, the third node and the first node are the same node, and the second node is electrically connected to the first voltage signal end, the first voltage signal is a clock signal, and the third voltage signal is a DC signal.

25. The driving method according to claim 1, wherein: The non-display area further includes a detection transistor, which is formed in the same process as the switch transistor. Before the step of controlling the gate driving unit to provide a scan signal to the gate line and a bias signal to the bias signal line, the driving method further includes: obtaining characteristics of the detection transistor; predicting the characteristics of the switching transistor based on the characteristics of the detection transistor; The step of controlling the gate driving unit to provide a scanning signal to the gate line and a bias signal to the bias signal line comprises: According to the predicted characteristics of the switching transistor, the gate driving unit is controlled to provide a scanning signal to the gate line and a bias signal to the bias signal line.

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