Vertical-cavity surface-emitting laser and preparation method therefor

Abstract

The present application relates to the technical field of semiconductor devices, and provides a vertical-cavity surface-emitting laser and a preparation method therefor. The preparation method comprises: growing an N-GaAs buffer layer, an N-type DBR structure, an N-AlGaAs spacer layer, a periodic GaAs / InGaAs multiple quantum well layer, a P-AlGaAs spacer layer, and a P-type DBR structure on an N-GaAs substrate to obtain a wafer structure; forming hole-shaped structures by etching and annular cavities by corrosion; filling the hole-shaped structures and the annular cavities with a SiO2 filler; and preparing metal electrodes to obtain the vertical-cavity surface-emitting laser. This preparation method replaces a wet oxidation-based current confinement structure preparation method, and allows for rapid and uniform preparation of annular confinement structures, thereby improving the production rate. The reliance on stringent process parameters is reduced and the process threshold is lowered, and a tape-out process for large-size wafer structures can be achieved, thereby effectively improving the preparation efficiency and reducing the preparation cost.

Description

A vertical cavity surface emitting laser and its preparation method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 29, 2024, with application number 202410223666.7 and invention name “A vertical cavity surface emitting laser and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of semiconductor devices, and in particular to a vertical cavity surface emitting laser and a preparation method thereof. Background Art

[0003] With the advancement of the Internet of Things (IoT), artificial intelligence (AI), and fifth-generation mobile communication technology (5G), three-dimensional imaging (3D) and sensing technologies are experiencing rapid growth. This is driving the development of smartphones, augmented reality (AR) / virtual reality (VR), smart cars, and other fields, accelerating the advent of the Internet of Everything (IoE). Vertical cavity surface emitting lasers (VCSELs), as core components in 3D imaging and sensing systems, are at the pinnacle of the intelligent interconnected industry. Currently, short-wave infrared VCSELs based on gallium arsenide substrates, such as those with wavelengths of 850nm and 980nm, have seen significant development and are widely used. However, VCSEL fabrication and development remain hindered by numerous factors, such as the difficulty in achieving current limiting. The currently adopted international process is mostly based on wet oxidation, which is extremely complex, carries the risk of cracking, affects yield, and places high demands on equipment.

[0004] Therefore, a new preparation method is urgently needed to solve the problems of high production cost and low production efficiency.

[0005] Summary of the Invention

[0006] The present application provides a vertical cavity surface emitting laser and a preparation method thereof, so as to solve the technical problems of high production cost and low production efficiency of the existing vertical cavity surface emitting laser.

[0007] The first aspect of the present application provides a method for preparing a vertical cavity surface emitting laser, comprising: providing an N-GaAs substrate; sequentially growing an N-GaAs buffer layer, an N-type DBR structure, an N-AlGaAs space layer, a periodic GaAs / InGaAs multi-quantum well layer, a P-AlGaAs space layer, and a P-type DBR structure on the N-GaAs substrate to obtain a wafer structure; wherein the N-type DBR structure is an N-type AlGaAs / GaAs DBR structure, and the P-type DBR structure is a P-type AlGaAs / GaAs DBR structure; sequentially cleaning the wafer structure with acetone, alcohol, and deionized water; and using inductively coupled plasma assisted laser (ICP) to clean the wafer structure. The daughter body etching technology etches multiple hole structures in the P-type DBR structure, wherein the extension direction of the hole structure is the same as the height direction of the P-type DBR structure, and the height of the hole structure is the same as the height of the P-type DBR structure; the etched wafer structure is immersed in HF solution, and the HF solution is allowed to corrode the AlGaAs in the P-type DBR structure through the hole structure to form multiple spaced annular cavities in the axial direction of each hole structure; SiO2 filler is filled in the hole structure and the annular cavity using plasma enhanced chemical vapor deposition technology; metal electrodes are prepared on the N-GaAs substrate and the P-type DBR structure respectively to obtain a vertical cavity surface emitting laser.

[0008] In some feasible implementations, the N-GaAs buffer layer, N-type DBR structure, N-AlGaAs space layer, periodic GaAs / InGaAs multi-quantum well layer, P-AlGaAs space layer and P-type DBR structure are all grown using molecular beam epitaxy technology, and the growth temperature is 720-780°C; among them, the number of periods of the N-type DBR structure is greater than that of the P-type DBR structure.

[0009] In some feasible implementations, the period number of the N-type DBR structure is 30-34, the period number of the P-type DBR structure is 28-32, and the period number of the periodic GaAs / InGaAs multi-quantum well layer is 3-6.

[0010] In some feasible implementations, the number of periods of the N-type DBR structure is 32, wherein the thickness of AlGaAs in each period of the N-type DBR structure is 20 nm, and the thickness of GaAs in each period of the N-type DBR structure is 48 nm; the number of periods of the P-type DBR structure is 30, wherein the thickness of AlGaAs in each period of the P-type DBR structure is 20 nm; the thickness of GaAs in each period of the P-type DBR structure is 48 nm; the number of periods of the periodic GaAs / InGaAs multi-quantum well layer is 3, wherein the thickness of GaAs in each period of the periodic GaAs / InGaAs multi-quantum well layer is 8 nm, and the thickness of InGaAs in each period of the periodic GaAs / InGaAs multi-quantum well layer is 5 nm.

[0011] In some feasible implementations, the thickness of the N-GaAs substrate is 300 μm, the thickness of the N-GaAs buffer layer is 500 nm, the thickness of the N-AlGaAs space layer is 90 nm, and the thickness of the P-AlGaAs space layer is 140 nm.

[0012] The fabrication method for vertical cavity surface emitting lasers provided in this application replaces the traditional wet oxidation method for fabricating current limiting structures. It enables the rapid and uniform fabrication of annular limiting structures, increasing production rates while mitigating the risk of cracking during the fabrication process, thereby improving product yield. This reduces reliance on stringent process parameters, lowers the process threshold, and enables the tape-out of large-scale wafer structures, effectively improving fabrication efficiency and reducing fabrication costs.

[0013] The vertical cavity surface emitting laser provided in the second aspect of the present application comprises: an N-GaAs substrate; an N-GaAs buffer layer, an N-type DBR structure, an N-AlGaAs space layer, a periodic GaAs / InGaAs multi-quantum well layer, a P-AlGaAs space layer and a P-type DBR structure sequentially grown on the N-GaAs substrate; wherein the N-type DBR structure is an N-type AlGaAs / GaAs DBR structure, and the P-type DBR structure is a P-type AlGaAs / GaAs DBR structure; a plurality of hole-like structures are arranged on the P-type DBR structure, and the hole-like structures are electrically connected. The inductively coupled plasma etching technology is used to etch the P-type DBR structure, wherein the extension direction of the porous structure is the same as the height direction of the P-type DBR structure, and the height of the porous structure is the same as the height of the P-type DBR structure; multiple annular cavities, each porous structure is provided with multiple spaced annular cavities in the axial direction, wherein the annular cavities are formed by using HF solution to etch AlGaAs in the P-type DBR structure through the porous structure; SiO2 filler, SiO2 filler is arranged in the porous structure and the annular cavity; two metal electrodes are respectively arranged on the N-GaAs substrate and the P-type DBR structure.

[0014] In some feasible implementations, the N-GaAs buffer layer, N-type DBR structure, N-AlGaAs space layer, periodic GaAs / InGaAs multi-quantum well layer, P-AlGaAs space layer and P-type DBR structure are all grown using molecular beam epitaxy technology, and the growth temperature is 720-780°C; among them, the number of periods of the N-type DBR structure is greater than that of the P-type DBR structure.

[0015] In some feasible implementations, the period number of the N-type DBR structure is 30-34, the period number of the P-type DBR structure is 28-32, and the period number of the periodic GaAs / InGaAs multi-quantum well layer is 3-6.

[0016] In some feasible implementations, the number of periods of the N-type DBR structure is 32, wherein the thickness of AlGaAs in each period of the N-type DBR structure is 20 nm, and the thickness of GaAs in each period of the N-type DBR structure is 48 nm; the number of periods of the P-type DBR structure is 30, wherein the thickness of AlGaAs in each period of the P-type DBR structure is 20 nm; the thickness of GaAs in each period of the P-type DBR structure is 48 nm; the number of periods of the periodic GaAs / InGaAs multi-quantum well layer is 3, wherein the thickness of GaAs in each period of the periodic GaAs / InGaAs multi-quantum well layer is 8 nm, and the thickness of InGaAs in each period of the periodic GaAs / InGaAs multi-quantum well layer is 5 nm.

[0017] In some feasible implementations, the thickness of the N-GaAs substrate is 300 μm, the thickness of the N-GaAs buffer layer is 500 nm, the thickness of the N-AlGaAs space layer is 90 nm, and the thickness of the P-AlGaAs space layer is 140 nm.

[0018] It can be understood that the vertical cavity surface emitting laser provided in the second aspect is prepared by the preparation method provided in the first aspect. Therefore, the beneficial effects that can be achieved can refer to the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] FIG1 is a schematic flow chart of a method for preparing a vertical cavity surface emitting laser according to an embodiment of the present application;

[0021] FIG2 is a schematic structural diagram of a wafer structure provided in an embodiment of the present application;

[0022] FIG3 is a schematic diagram of a structure in which a hole structure is formed by etching on a wafer structure according to an embodiment of the present application;

[0023] FIG4 is a schematic diagram of a structure in which an annular cavity is formed by etching on a wafer structure according to an embodiment of the present application;

[0024] FIG5 is a schematic structural diagram of a vertical cavity surface emitting laser provided in an embodiment of the present application.

[0025] Graphic markings: 100-vertical cavity surface emitting laser; 10-N-GaAs substrate; 20-N-GaAs buffer layer; 30-N-type DBR structure; 40-N-AlGaAs space layer; 50-periodic GaAs / InGaAs multiple quantum well layer; 60-P-AlGaAs space layer; 70-P-type DBR structure; 71-AlGaAs; 72-GaAs; 73-pore structure; 74-annular cavity; 80-SiO2 filler; 90-metal electrode. DETAILED DESCRIPTION

[0026] The following will clearly describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0027] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] In addition, in this application, directional terms such as "upper", "lower", "inner" and "outer" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0029] A vertical cavity surface emitting laser (VCSEL) is a semiconductor laser diode, developed based on semiconductor materials such as gallium arsenide. It differs from other light sources such as light emitting diodes (LEDs) and laser diodes (LDs). Unlike traditional edge-emitting lasers, VCSELs emit a high-power optical laser beam vertically from the top surface. They offer advantages such as small size, a circular output spot, natural 2D structured light, single longitudinal mode output, low threshold current, a wide operating temperature range, low cost, and ease of integration into large-area arrays. They are widely used in optical communications, optical interconnects, and optical storage.

[0030] With the development of the Internet of Things, AI, and 5G, 3D and sensing technologies are experiencing rapid growth, driving the development of smartphones, AR / VR, smart cars, and other fields, accelerating the arrival of the Internet of Everything (IoE). VCSELs, as core components in 3D imaging and sensing systems, are at the pinnacle of the intelligent interconnected industry. Currently, short-wave infrared VCSELs based on gallium arsenide substrates, such as those with wavelengths of 850nm and 980nm, have seen significant development and are finding widespread application.

[0031] However, the production and development of VCSELs still face numerous constraints, such as the difficulty in achieving current limits. Currently, the internationally adopted process mostly relies on wet oxidation, which involves high temperatures and requires precise control of airflow, placing high demands on the process and a long production time. Consequently, production efficiency and yield are relatively low. Furthermore, this process is extremely complex, carries the risk of chipping, and places high demands on equipment.

[0032] To address the aforementioned technical issues, the present invention provides a method for fabricating a vertical cavity surface emitting laser (VCSEL). This method replaces the traditional wet oxidation method for fabricating current confinement, enabling rapid and uniform fabrication of an annular confinement structure and increasing production rates. This method reduces the fabrication method's dependence on the growth process and fabrication equipment, lowering the process threshold and reducing production costs.

[0033] FIG1 is a schematic flow chart of a method for preparing a vertical cavity surface emitting laser provided in an embodiment of the present application.

[0034] FIG2 is a schematic structural diagram of a wafer structure provided in an embodiment of the present application.

[0035] 1 and 2 , the method for manufacturing a vertical cavity surface emitting laser provided in an embodiment of the present application can be implemented by the following steps S100 to S700 .

[0036] Step S100: providing an N-GaAs substrate 10.

[0037] Step S200: sequentially growing an N-GaAs buffer layer 20, an N-type DBR structure 30, an N-AlGaAs space layer 40, a periodic GaAs / InGaAs multi-quantum well layer 50, a P-AlGaAs space layer 60 and a P-type DBR structure 70 on an N-GaAs substrate 10 to obtain a wafer structure.

[0038] Step S200 can be implemented by the following steps S201 to S206 .

[0039] Step S201 : growing an N-GaAs buffer layer 20 on an N-GaAs substrate 10 .

[0040] Specifically, the N-GaAs buffer layer 20 may be grown on the N-GaAs substrate 10 using molecular beam epitaxy (MBE) technology. The function of the N-GaAs buffer layer 20 is to improve the growth quality of subsequent structures.

[0041] In some feasible implementations, the growth temperature of the N-GaAs buffer layer 20 may be 720-780°C.

[0042] Step S202 : growing an N-type DBR structure 30 on the N-GaAs buffer layer 20 .

[0043] In step S202, the N-type DBR structure 30 may be an N-type AlGaAs / GaAs DBR structure. The AlGaAs / GaAs DBR structure is a periodic structure. Each period of AlGaAs / GaAs consists of a layer of AlGaAs and a layer of GaAs. In other words, a layer of AlGaAs and a layer of GaAs are grown on the N-GaAs buffer layer 20, and then a layer of AlGaAs and a layer of GaAs are grown sequentially until the desired period is achieved.

[0044] Step S203 : growing an N-AlGaAs spacer layer 40 on the N-type DBR structure 30 .

[0045] Step S204 : growing a periodic GaAs / InGaAs multi-quantum well layer 50 on the N-AlGaAs spacer layer 40 .

[0046] The periodic GaAs / InGaAs multi-quantum well layer 50 is GaAs and InGaAs grown sequentially, and each period of GaAs / InGaAs consists of a layer of GaAs and a layer of InGaAs.

[0047] Step S205 : growing a P-AlGaAs spacer layer 60 on the periodic GaAs / InGaAs multi-quantum well layer 50 .

[0048] Step S206 : growing a P-type DBR structure 70 on the P-AlGaAs space layer 60 to obtain a wafer structure.

[0049] The P-type DBR structure 70 is a P-type AlGaAs / GaAs DBR structure.

[0050] Specifically, steps S201 to S206 can all be grown using molecular beam outer edge technology.

[0051] Specifically, the N-type DBR structure 30, the periodic GaAs / InGaAs multi-quantum well layer 50, and the P-type DBR structure 70 are all periodic structures, and the three have different period numbers. The period number of the N-type DBR structure 30 is greater than that of the P-type DBR structure 70, and the period number of the P-type DBR structure 70 is greater than that of the periodic GaAs / InGaAs multi-quantum well layer 50.

[0052] In some specific implementations, the number of periods of the N-type DBR structure 30 is 30-34, the number of periods of the P-type DBR structure 70 is 28-32, and the number of periods of the periodic GaAs / InGaAs multi-quantum well layer 50 is 3-6.

[0053] For example, the period number of the N-type DBR structure 30 can be one of 30, 32 or 34; the period number of the P-type DBR structure 70 can be one of 28, 30 or 32; the period number of the periodic GaAs / InGaAs multi-quantum well layer 50 can be one of 3, 4, 5 or 6.

[0054] In a specific implementation, the number of periods of the N-type DBR structure 30 is 32; the number of periods of the P-type DBR structure 70 is 30; and the number of periods of the periodic GaAs / InGaAs multi-quantum well layer 50 is 3.

[0055] Specifically, in the N-type DBR structure 30 with a period number of 32, the thickness of AlGaAs in each period of the N-type DBR structure 30 is 20 nm, and the thickness of GaAs in each period of the N-type DBR structure 30 is 48 nm; in the P-type DBR structure 70 with a period number of 30, the thickness of AlGaAs in each period of the P-type DBR structure 70 is 20 nm; the thickness of GaAs in each period of the P-type DBR structure 70 is 48 nm; in the periodic GaAs / InGaAs multi-quantum well layer 50 with a period number of 3, the thickness of GaAs in each period of the GaAs / InGaAs multi-quantum well layer is 8 nm, and the thickness of InGaAs in each period of the GaAs / InGaAs multi-quantum well layer is 5 nm; the thickness of the N-GaAs substrate 10 is 300 μm, and the thickness of the N-GaAs buffer layer 20 is 500 nm; the thickness of the N-AlGaAs space layer 40 is 90 nm, and the thickness of the P-AlGaAs space layer 60 is 140 nm.

[0056] In some feasible implementations, the growth temperatures of the N-GaAs buffer layer 20, the N-type DBR structure 30, the N-AlGaAs space layer 40, the periodic GaAs / InGaAs multi-quantum well layer 50, the P-AlGaAs space layer 60 and the P-type DBR structure 70 can all be 720-780°C.

[0057] The growth temperatures of the N-GaAs buffer layer 20 , the N-type DBR structure 30 , the N-AlGaAs space layer 40 , the periodic GaAs / InGaAs multi-quantum well layer 50 , the P-AlGaAs space layer 60 and the P-type DBR structure 70 may be the same.

[0058] For example, the growth temperatures of the N-GaAs buffer layer 20, the N-type DBR structure 30, the N-AlGaAs space layer 40, the periodic GaAs / InGaAs multi-quantum well layer 50, the P-AlGaAs space layer 60 and the P-type DBR structure 70 can all be one of 720°C, 750°C or 780°C.

[0059] In a specific implementation, the growth temperatures of the N-GaAs buffer layer 20, the N-type DBR structure 30, the N-AlGaAs space layer 40, the periodic GaAs / InGaAs multi-quantum well layer 50, the P-AlGaAs space layer 60 and the P-type DBR structure 70 may all be 750°C.

[0060] Referring to FIG. 2 , after step S200 , a wafer structure as shown in FIG. 2 can be obtained.

[0061] Step S300: Cleaning the wafer structure with acetone, alcohol and deionized water in sequence.

[0062] In step S300 , acetone may be used to perform a first cleaning operation on the wafer structure, alcohol may be used to perform a second cleaning operation on the wafer structure, and deionized water may be used to perform a third cleaning operation on the wafer structure.

[0063] Acetone and alcohol can be of analytical grade. The cleaning operation can be performed at room temperature.

[0064] In some feasible implementations, step S301 may be further performed after step S300.

[0065] Step S301: using photolithography technology to define the size of the wafer structure.

[0066] Specifically, if the required wafer structure is significantly different from the prepared wafer structure, a wafer structure of the required size can be etched using photolithography technology.

[0067] Of course, in other feasible implementations, the specific growth size can also be defined during the preparation process, and in this case, the photolithography technology does not need to be used to define the size of the wafer structure.

[0068] In other words, the preparation method provided in the embodiment of the present application can not only prepare small-sized wafer structures, but also prepare large-sized wafer structures.

[0069] Step S400 : etching a plurality of hole structures 73 in the P-type DBR structure 70 using inductively coupled plasma etching technology.

[0070] The extending direction of the hole structure 73 is the same as the height direction of the P-type DBR structure 70 , and the height of the hole structure 73 is the same as the height of the P-type DBR structure 70 .

[0071] In step S400, inductively coupled plasma etching (ICP) is used to etch the P-type DBR structure 70 from the surface away from the P-AlGaAs space layer 60 until the surface of the P-AlGaAs space layer 60 is reached, thereby forming a plurality of spaced-apart hole structures 73, each of which extends along the growth direction of the P-type DBR structure 70.

[0072] FIG3 is a schematic diagram of a structure in which a hole-shaped structure is formed by etching on a wafer structure according to an embodiment of the present application.

[0073] FIG4 is a schematic structural diagram of an annular cavity formed by etching on a wafer structure provided in an embodiment of the present application.

[0074] 2 , 3 and 4 , based on the wafer structure prepared in FIG. 2 , step S400 is performed to etch the wafer structure to form a hole-shaped structure 73 . As shown in FIG. 3 , the hole-shaped structure 73 has a diameter of R1 and a height of L1 , where L1 is the height of the P-type DBR structure 70 .

[0075] Step S500 : immersing the etched wafer structure in HF solution, so that the HF solution corrodes the AlGaAs 71 in the P-type DBR structure 70 through the hole structure 73 , thereby forming a plurality of annular cavities 74 spaced apart in the axial direction of each hole structure 73 .

[0076] In step S500, the HF solution has a corrosive property. Specifically, the HF solution can corrode the AlGaAs 71 in the P-type DBR structure 70, but does not corrode the GaAs 72 in the P-type DBR structure 70. Thus, the prepared wafer structure is immersed in the HF solution. The HF solution enters the porous structure 73 to corrode the AlGaAs 71 spaced apart on the inner wall of the porous structure 73, thereby forming a plurality of annular cavities 74.

[0077] A pure HF solution can be used to control the degree of corrosion based on the desired size of the annular cavity 74, the corrosion rate based on the degree of corrosion, and the corrosion time based on the corrosion rate. It is worth noting that the diameters of the pore structures 73 and the annular cavities 74 are not limited in this embodiment of the present application. The diameters of the pore structures 73 and the annular cavities 74, as well as the number of pore structures 73, can be adjusted adaptively based on usage requirements.

[0078] 3 and 4 , after the porous structure 73 is prepared, step S500 is executed to perform etching on the wafer structure to form an annular cavity 74. The diameter of the annular cavity 74 is R2 and the height is L2, where L2 is the height of the AlGaAs 71 in the P-type DBR structure 70. The value of R2 can be adjusted by the degree of etching. For example, the greater the degree of etching, the greater the value of R2.

[0079] It is worth noting that the number of periods of the P-type DBR structure 70 shown in FIG3 is 3, which is only for example and not a specific limitation. At the same time, the number of the hole structure 73 in FIG3 and FIG4 is one, which is also for example and not a specific limitation.

[0080] Step S600: using plasma enhanced chemical vapor deposition technology to fill the porous structure 73 and the annular cavity 74 with SiO 2 filler 80 .

[0081] 3 , after the annular cavity 74 is formed, damage is repaired and passivation is performed by plasma enhanced chemical vapor deposition, and SiO 2 fillers 80 are filled in the porous structure 73 and the annular cavity 74 .

[0082] Specifically, after filling the SiO 2 filler 80 , a ring-shaped current limiting layer structure can be formed inside the wafer structure.

[0083] Step S700: metal electrodes are prepared on the N-GaAs substrate 10 and the P-type DBR structure 70 respectively to obtain a vertical cavity surface emitting laser.

[0084] Specifically, metal electrodes are prepared on two opposite surfaces of the filled wafer structure, thereby completing the preparation of the vertical cavity surface emitting laser.

[0085] The method for fabricating a vertical cavity surface emitting laser (VCSEL) provided in the embodiments of this application replaces the traditional wet oxidation method for fabricating current limiting structures. It enables rapid and uniform fabrication of annular limiting structures, increases production rates, mitigates the risk of cracking during the fabrication process, and improves product yield. This method reduces reliance on stringent process parameters, lowers the process threshold, and enables tape-out of large-scale wafer structures, effectively improving fabrication efficiency and reducing fabrication costs.

[0086] Corresponding to the embodiment of the method for preparing a vertical cavity surface emitting laser described above, the present application also provides an embodiment of a vertical cavity surface emitting laser.

[0087] FIG5 is a schematic structural diagram of a vertical cavity surface emitting laser provided in an embodiment of the present application.

[0088] 4 and 5 , the vertical cavity surface emitting laser 100 includes an N-GaAs substrate 10, an N-GaAs buffer layer 20, an N-type DBR structure 30, an N-AlGaAs space layer 40, a periodic GaAs / InGaAs multi-quantum well layer 50, a P-AlGaAs space layer 60, a P-type DBR structure 70, a plurality of hole-like structures 73, a plurality of annular cavities 74, a SiO2 filler 80, and two metal electrodes 90.

[0089] Specifically, an N-GaAs buffer layer 20, an N-type DBR structure 30, an N-AlGaAs spacer layer 40, a periodic GaAs / InGaAs multi-quantum well layer 50, a P-AlGaAs spacer layer 60, and a P-type DBR structure 70 are sequentially grown on an N-GaAs substrate 10. The N-type DBR structure 30 is an N-type AlGaAs / GaAs DBR structure, and the P-type DBR structure 70 is a P-type AlGaAs / GaAs DBR structure.

[0090] The porous structure 73 is arranged on the P-type DBR structure 70. The porous structure 73 is formed by etching in the P-type DBR structure 70 using inductively coupled plasma etching technology, wherein the extension direction of the porous structure 73 is the same as the height direction of the P-type DBR structure 70, and the height of the porous structure 73 is the same as the height of the P-type DBR structure 70; and each porous structure 73 is provided with a plurality of spaced annular cavities 74 in the axial direction, wherein the annular cavities 74 are formed by etching AlGaAs 71 in the P-type DBR structure 70 through the porous structure 73 using HF solution.

[0091] The SiO 2 filler 80 is filled in the porous structure 73 and the annular cavity 74 .

[0092] Two metal electrodes 90 are respectively disposed on the N-GaAs substrate 10 and the P-type DBR structure 70 .

[0093] In some feasible implementations, the N-GaAs buffer layer 20, the N-type DBR structure 30, the N-AlGaAs space layer 40, the periodic GaAs / InGaAs multi-quantum well layer 50, the P-AlGaAs space layer 60 and the P-type DBR structure 70 are all grown using molecular beam epitaxy technology, and the growth temperature is 720-780°C; among them, the period number of the N-type DBR structure 30 is greater than the period number of the P-type DBR structure 70, and the period number of the P-type DBR structure 70 is greater than the period number of the periodic GaAs / InGaAs multi-quantum well layer 50.

[0094] Specifically, the period number of the N-type DBR structure 30 is 30-34, the period number of the P-type DBR structure 70 is 28-32, and the period number of the periodic GaAs / InGaAs multi-quantum well layer 50 is 3-6.

[0095] In a specific implementation, the number of periods of the N-type DBR structure 30 is 32, wherein the thickness of AlGaAs in each period of the N-type DBR structure 30 is 20 nm, and the thickness of GaAs in each period of the N-type DBR structure 30 is 48 nm.

[0096] The periodic GaAs / InGaAs multi-quantum well layer 50 has a period number of 3, wherein the thickness of GaAs in each period of the periodic GaAs / InGaAs multi-quantum well layer 50 is 8 nm, and the thickness of InGaAs in each period of the periodic GaAs / InGaAs multi-quantum well layer 50 is 5 nm. The periodic P-type DBR structure 70 has a period number of 30, wherein the thickness of AlGaAs in each period of the P-type DBR structure 70 is 20 nm, and the thickness of GaAs in each period of the P-type DBR structure 70 is 48 nm. The thickness of the N-GaAs substrate 10 is 300 μm, and the thickness of the N-GaAs buffer layer 20 is 500 nm. The thickness of the N-AlGaAs spacer layer 40 is 90 nm, and the thickness of the P-AlGaAs spacer layer 60 is 140 nm.

[0097] The VCSEL 100 provided in the embodiments of the present application replaces the traditional wet oxidation method for current confinement, enabling the rapid and uniform fabrication of annular confinement structures. This increases production rates while mitigating the risk of cracking during the fabrication process, thereby improving product yield. This reduces reliance on stringent process parameters, lowers the process threshold, and enables tape-out of large-scale wafer structures, effectively improving fabrication efficiency and reducing fabrication costs.

[0098] It should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope of this application is indicated by the claims.

[0099] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for preparing a vertical cavity surface emitting laser, characterized in that: include: Providing an N-GaAs substrate; An N-GaAs buffer layer, an N-type DBR structure, an N-AlGaAs space layer, a periodic GaAs / InGaAs multi-quantum well layer, a P-AlGaAs space layer, and a P-type DBR structure are sequentially grown on the N-GaAs substrate to obtain a wafer structure; wherein the N-type DBR structure is an N-type AlGaAs / GaAs DBR structure, and the P-type DBR structure is a P-type AlGaAs / GaAs DBR structure; Cleaning the wafer structure with acetone, alcohol, and deionized water in sequence; Etching a plurality of hole-like structures in the P-type DBR structure using an inductively coupled plasma etching technique, wherein an extension direction of the hole-like structures is the same as a height direction of the P-type DBR structure, and a height of the hole-like structures is the same as a height of the P-type DBR structure; Immersing the etched wafer structure in an HF solution, allowing the HF solution to corrode the AlGaAs in the P-type DBR structure through the porous structure, so as to form a plurality of annular cavities spaced apart in the axial direction of each of the porous structures; Filling the porous structure and the annular cavity with SiO2 filler using plasma enhanced chemical vapor deposition technology; Metal electrodes are prepared on the N-GaAs substrate and the P-type DBR structure respectively to obtain a vertical cavity surface emitting laser.

2. The method for preparing a vertical cavity surface emitting laser according to claim 1, wherein: The N-GaAs buffer layer, the N-type DBR structure, the N-AlGaAs space layer, the periodic GaAs / InGaAs multi-quantum well layer, the P-AlGaAs space layer and the P-type DBR structure are all grown using molecular beam epitaxy technology, and the growth temperature is 720-780° C.; The number of periods of the N-type DBR structure is greater than the number of periods of the P-type DBR structure.

3. The method for preparing a vertical cavity surface emitting laser according to claim 2, wherein: The period number of the N-type DBR structure is 30-34, the period number of the P-type DBR structure is 28-32, and the period number of the periodic GaAs / InGaAs multi-quantum well layer is 3-6.

4. The method for preparing a vertical cavity surface emitting laser according to claim 3, wherein: The number of periods of the N-type DBR structure is 32, wherein the thickness of AlGaAs in the N-type DBR structure in each period is 20 nm, and the thickness of GaAs in the N-type DBR structure in each period is 48 nm; The number of periods of the P-type DBR structure is 30, wherein the thickness of AlGaAs in the P-type DBR structure in each period is 20 nm; the thickness of GaAs in the P-type DBR structure in each period is 48 nm; The number of periods of the periodic GaAs / InGaAs multi-quantum well layer is 3, wherein the thickness of GaAs in the periodic GaAs / InGaAs multi-quantum well layer in each period is 8 nm, and the thickness of InGaAs in the periodic GaAs / InGaAs multi-quantum well layer in each period is 5 nm.

5. The method for preparing a vertical cavity surface emitting laser according to claim 4, wherein: The thickness of the N-GaAs substrate is 300 μm, and the thickness of the N-GaAs buffer layer is 500 nm; The thickness of the N-AlGaAs space layer is 90 nm, and the thickness of the P-AlGaAs space layer is 140 nm.

6. A vertical cavity surface emitting laser, characterized in that include: N-GaAs substrate; An N-GaAs buffer layer, an N-type DBR structure, an N-AlGaAs space layer, a periodic GaAs / InGaAs multi-quantum well layer, a P-AlGaAs space layer and a P-type DBR structure are sequentially grown on the N-GaAs substrate; wherein the N-type DBR structure is an N-type AlGaAs / GaAs DBR structure, and the P-type DBR structure is a P-type AlGaAs / GaAs DBR structure; A plurality of pore structures are provided on the P-type DBR structure, wherein the pore structures are formed by etching in the P-type DBR structure using an inductively coupled plasma etching technique, wherein an extension direction of the pore structures is the same as a height direction of the P-type DBR structure, and a height of the pore structures is the same as a height of the P-type DBR structure; A plurality of annular cavities, wherein each of the hole-like structures is provided with a plurality of annular cavities spaced apart in the axial direction thereof, wherein the annular cavities are formed by etching AlGaAs in the P-type DBR structure through the hole-like structure using an HF solution; SiO2 filler, the SiO2 filler is arranged in the porous structure and the annular cavity; Two metal electrodes are respectively arranged on the N-GaAs substrate and the P-type DBR structure.

7. The vertical cavity surface emitting laser according to claim 6, characterized in that The N-GaAs buffer layer, the N-type DBR structure, the N-AlGaAs space layer, the periodic GaAs / InGaAs multi-quantum well layer, the P-AlGaAs space layer and the P-type DBR structure are all grown by molecular beam epitaxy technology, and the growth temperature is 720-780° C. The number of periods of the N-type DBR structure is greater than the number of periods of the P-type DBR structure.

8. The vertical cavity surface emitting laser according to claim 7, wherein: The period number of the N-type DBR structure is 30-34, the period number of the P-type DBR structure is 28-32, and the period number of the periodic GaAs / InGaAs multi-quantum well layer is 3-6.

9. The vertical cavity surface emitting laser according to claim 8, characterized in that The number of periods of the N-type DBR structure is 32, wherein the thickness of AlGaAs in the N-type DBR structure in each period is 20 nm, and the thickness of GaAs in the N-type DBR structure in each period is 48 nm; The number of periods of the P-type DBR structure is 30, wherein the thickness of AlGaAs in the P-type DBR structure in each period is 20 nm; the thickness of GaAs in the P-type DBR structure in each period is 48 nm; The number of periods of the periodic GaAs / InGaAs multi-quantum well layer is 3, wherein the thickness of GaAs in the periodic GaAs / InGaAs multi-quantum well layer in each period is 8 nm, and the thickness of InGaAs in the periodic GaAs / InGaAs multi-quantum well layer in each period is 5 nm.

10. The vertical cavity surface emitting laser according to claim 9, characterized in that The thickness of the N-GaAs substrate is 300 μm, and the thickness of the N-GaAs buffer layer is 500 nm; The thickness of the N-AlGaAs space layer is 90 nm, and the thickness of the P-AlGaAs space layer is 140 nm.

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