Memory allocation method and computing device

Abstract

Disclosed in the embodiments of the present application are a memory allocation method and a computing device. The memory allocation method is applied to a computing device having an ARM architecture. The method comprises: configuring the page size of a first virtual page in a first virtual address space and the page size of a second virtual page in a second virtual address space, wherein the page size of the first virtual page is greater than the page size of the second virtual page; determining whether a task to which a memory is to be allocated belongs to a preset control group; and when the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task on the basis of the control group to which the task belongs. By configuring the first virtual address space and the second virtual address space that have different page size granularities, and allocating the first virtual page or the second virtual page to different tasks on the basis of preset control groups, memory allocation for different page size granularities can be realized under a server having an ARM architecture, thereby meeting more diversified and flexible memory allocation requirements of the server having an ARM architecture.

Description

Memory allocation method and computing device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 29, 2024, with application number 202410232194.1 and application name “A memory allocation method and computing device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of memory management technology, and in particular to a memory allocation method and computing device. Background Art

[0003] In the Advanced RISC Machine (ARM) architecture, memory in a computing device is managed as physical pages. When the central processing unit (CPU) of a computing device executes a task, the CPU can read and write the corresponding physical pages in memory by accessing the virtual pages in the virtual address space of the task.

[0004] A page table entry (PTE) is a data structure used to organize and manage the mapping between virtual addresses and physical addresses. Each PTE is used to associate a virtual page with a physical page. In this way, when a task needs to access a physical page, the CPU can query the corresponding PTE based on the virtual page and then access the corresponding physical page.

[0005] Currently, the ARM architecture supports mapping physical and virtual pages at a granularity of 4KB, 16KB, or 64KB. It's understandable that using large pages for memory allocation improves the hit rate of the translation lookaside buffer (TLB), while using small pages for memory allocation is more flexible. Therefore, using a single page size for memory allocation makes it difficult to accommodate diverse memory allocation requirements.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a memory allocation method and a computing device, which can implement memory allocation of different page size granularities under the ARM architecture to meet more diverse and flexible memory allocation needs.

[0008] A first aspect of an embodiment of the present application provides a memory allocation method, which is applied to a computing device of an ARM architecture, and includes:

[0009] Configure the page size of the first virtual page of the first virtual address space and the page size of the second virtual page of the second virtual address space; determine whether the task to which memory is to be allocated belongs to a preset control group; if the task belongs to the preset control group, allocate the first virtual page or the second virtual page to the task based on the control group to which the task belongs.

[0010] The page size of the first virtual page is larger than the page size of the second virtual page.

[0011] The preset control group includes a first control group and a second control group; the first control group is used to control allocation of the first virtual page for the preset kernel mode task; the second control group is used to control allocation of the first virtual page or the second virtual page for the preset user mode task.

[0012] In an embodiment of the present application, by configuring two intervals with different page size granularities in the virtual address space and allocating the first virtual page or the second virtual page to different tasks based on a preset control group, memory allocation with different page size granularities can be achieved to meet more memory allocation requirements.

[0013] In one possible implementation, the first virtual address space includes a first sub-virtual address space and a second sub-virtual address space; wherein, the first sub-virtual address space is a kernel mode address space; the second sub-virtual address space is a user mode address space; and when the task belongs to the preset control group, the first virtual page or the second virtual page is allocated to the task based on the control group to which the task belongs, including: when the task belongs to the first control group, the first virtual page located in the first sub-virtual address space is allocated to the task; when the task belongs to the second control group, the first virtual page located in the second sub-virtual address space is allocated to the task.

[0014] In an embodiment of the present application, by dividing the first virtual address space to include a first sub-virtual address space and a second sub-virtual address space, and using the first sub-virtual address space as the kernel mode address space and the second sub-virtual address space as the user mode address space, both user mode tasks and kernel mode tasks can use the large pages in the first virtual address space, thereby improving the hit rate of the TLB.

[0015] In one possible implementation, the first virtual address space includes a first sub-virtual address space, and the second virtual address space includes a third sub-virtual address space; wherein, the first sub-virtual address space is a kernel mode address space; the third sub-virtual address space is a user mode address space; and when the task belongs to the preset control group, the first virtual page or the second virtual page is allocated to the task based on the control group to which the task belongs, including: when the task belongs to the first control group, the first virtual page located in the first sub-virtual address space is allocated to the task; when the task belongs to the second control group, the second virtual page located in the third sub-virtual address space is allocated to the task.

[0016] In an embodiment of the present application, by using the third sub-virtual address space in the second virtual address space as the user state address space and allocating memory for user state tasks based on the smaller second virtual page, memory utilization efficiency can be improved; the kernel state address space and the user state address space can be further isolated to improve the security of memory access.

[0017] In a possible implementation, the method further includes: allocating the second virtual page to the task when the task does not belong to the preset control group.

[0018] In the embodiment of the present application, for tasks that are not managed by a preset control group, a second virtual page is uniformly allocated, which can reduce the workload of the staff in pre-setting the control group and improve work efficiency.

[0019] In one possible implementation, the second virtual address space includes a fourth sub-virtual address space, which is a kernel mode address space; when the task does not belong to the preset control group, the second virtual page is allocated to the task, including: when the task does not belong to the preset control group, determining whether the task is a kernel mode task; when the task is the kernel mode task, allocating the second virtual page located in the fourth sub-virtual address space to the task.

[0020] In the embodiment of the present application, by dividing the fourth sub-virtual space in the second virtual space and allocating the second virtual page to the kernel-mode task, the memory allocation demand of the kernel-mode task for small pages can be met.

[0021] In a possible implementation, before determining whether the task to which memory is to be allocated belongs to a preset control group, the method further includes: determining whether the task is a target task, and determining whether the task to which memory is to be allocated belongs to the preset control group, including: if the task is the target task, determining whether the task belongs to the second control group; if the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs, including: if the task belongs to the second control group, determining whether the offset in the MMAP request corresponding to the task matches the page size of the first virtual page; if the offset matches the page size of the first virtual page, determining whether the MMAP request is a fixed mapping and whether the mapping address range of the MMAP request is located in the third sub-virtual address space; if the MMAP request is not a fixed mapping, or the mapping address range is located in the second sub-virtual address space, allocating the first virtual page located in the second sub-virtual address space to the task.

[0022] Wherein, when the MMAP request is a fixed mapping and the mapping address range is located in the third sub-virtual address space, the first virtual page located in the second sub-virtual address space is allocated to the task.

[0023] The second control group is specifically used to control allocation of the first virtual page to the preset user mode task; the first virtual address space includes a second sub-virtual address space; and the second virtual address space includes a third sub-virtual address space.

[0024] The second sub-virtual address space and the third sub-virtual address space are user-mode address spaces.

[0025] The target task is to execute the memory mapping MMAP task.

[0026] In an embodiment of the present application, the memory mapping behavior requested by the task can be authenticated through the control group to which the task belongs and the mapping address range indicated by the MMAP request, and a virtual page of corresponding size can be allocated, which can meet different memory mapping requirements while ensuring the security of memory mapping.

[0027] In one possible implementation, after the control group to which the task belongs allocates the first virtual page or the second virtual page to the task, the method further includes: determining the first physical page accessed by the task based on the target virtual page and the page table; in response to the first physical page being missing, determining whether the page size of the target virtual page matches the page size of the first virtual page; in the case where the page size of the target virtual page matches the page size of the first virtual page, determining whether the virtual address corresponding to the target virtual page is located in the second sub-virtual address space; in the case where the virtual address corresponding to the target virtual page is located in the second sub-virtual address space, allocating a second physical page to the task; and adding the mapping relationship between the second physical page and the target virtual page to the page table.

[0028] The target virtual page is the virtual page indicated by the virtual address in the access request of the task.

[0029] The second physical page has the same page size as the first virtual page.

[0030] In an embodiment of the present application, when a page fault is detected, the access behavior is authenticated, and when it is determined that the access target is the user space, the corresponding physical page allocation is performed, which can improve the security of the access behavior.

[0031] In one possible implementation, the first virtual address space includes a second sub-virtual address space; the second virtual address space includes a fourth sub-virtual address space; the method also includes: in response to creating a first task, adding a first page table entry in the task_struct data structure of the first task and adding the second page table entry in the second page table base address register of the current task to the task_struct data structure of the first task.

[0032] The second page table base address register is used to store the page table base address of the second virtual address space.

[0033] The first page table entry is used to indicate the page table base address of the second sub-virtual address space; and the second page table entry is used to indicate the page table base address of the fourth sub-virtual address space.

[0034] In an embodiment of the present application, by adding its own first page table entry and the second page table entry of the current task in the task_struct data structure of the first task when creating the first task, the correctness of the user-mode address space and the kernel-mode address space can be guaranteed, avoiding exceptions or failures when the processor accesses memory.

[0035] In one possible implementation, after adding the second page table entry of the current task in the second page table base address register to the task_struct data structure of the first task, the method further includes: in response to switching the first task to the second task, updating the corresponding page table entry in the first page table base address register according to the first page table entry in the task_struct data structure of the second task; updating the task_struct data structure of the second task according to the second page table entry in the second page table base address register of the first task; and then loading the PGD in the task_struct data structure of the second task into the second page table base address register.

[0036] The first page table base address register is used to store the page table base address of the first virtual address space.

[0037] In an embodiment of the present application, by updating the page table entries in the first page table base address register and the second page table base address register when switching the first task to the second task, the page table base address of the user space of the second task is loaded accordingly, and the page table base address of the kernel space remains unchanged, thereby ensuring the correctness of the user state address space and the kernel state address space, and avoiding exceptions or failures when the processor accesses memory.

[0038] A second aspect of an embodiment of the present application provides a computing device, comprising: a memory and a processor; wherein the processor is an ARM architecture; the processor is coupled to the memory; computer program instructions are stored in the memory; the computer program instructions are loaded and executed by the processor, so that the computing device implements any possible implementation method described in the first aspect.

[0039] A third aspect of an embodiment of the present application provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a computing device to implement any possible implementation method described in the first aspect.

[0040] A fourth aspect of an embodiment of the present application further provides a computer program product, which includes computer execution instructions, which are stored in a computer-readable storage medium; at least one processor of the device can read the computer execution instructions from the computer-readable storage medium, and at least one processor executes the computer execution instructions so that the device executes any possible method implemented in the first aspect.

[0041] It should be understood that the beneficial effects of the above aspects can be referenced to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram of the distribution of a virtual address space;

[0043] FIG2 is a schematic diagram of an application scenario of an embodiment of the present application;

[0044] FIG3 is a flow chart of a memory allocation method provided in an embodiment of the present application;

[0045] FIG4 is a schematic diagram of a distribution of a virtual address space provided in an embodiment of the present application;

[0046] FIG5 is a schematic diagram of a memory mapping process provided in an embodiment of the present application;

[0047] FIG6 is a schematic diagram of a page error processing process provided by an embodiment of the present application;

[0048] FIG7 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present application, rather than all the embodiments. Those skilled in the art will appreciate that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0050] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0051] The following is an explanation of some terminology concepts involved in the embodiments of this application.

[0052] (1) Advanced RISC Machine (ARM) Architecture

[0053] The ARM architecture, also known as the ARM system architecture, is a hardware specification that primarily defines the instruction set and internal chip architecture. Computing devices using the ARM architecture, previously known as advanced reduced instruction set machines (RISC) central processing unit architecture, are widely used in many embedded system designs.

[0054] (2) Operating system

[0055] An operating system is the system software that manages computer hardware and software resources and is the cornerstone of a computer system. It handles basic tasks such as managing and allocating memory, prioritizing the supply and demand of system resources, controlling input and output devices, operating the network, and managing the file system. The operating system also provides an interface for users to interact with the system.

[0056] (3) Kernel

[0057] The kernel is a program used to manage data input and output requests from software, translating these requests into data processing instructions and handing them over to the central processing unit (CPU) and other electronic components in the computer for processing. It is the most basic part of a modern operating system.

[0058] (4) Memory

[0059] Memory, also known as internal or main memory, is a crucial component of computing devices. It temporarily stores computational data from the CPU and exchanges data with external storage devices like hard drives. Memory bridges the gap between external storage and the CPU. All computer programs run in memory, and its performance impacts the overall performance of the computer.

[0060] (5) Tasks

[0061] A program is a description of instructions, data, and their organization, while a process is the running entity of a program. A process can contain multiple threads concurrently. A thread is the actual operating unit of a process, and can also be called a lightweight process. In the ARM architecture, processes and threads are not distinguished and are managed uniformly by the task_struct data structure. In the embodiments of this application, tasks are used to uniformly describe processes and threads.

[0062] (6) Virtual Address Space

[0063] The virtual address space is a collection of virtual addresses. A virtual address is a logical address used by the CPU when executing a task. The CPU accesses the corresponding physical address in the physical memory through the virtual address. The virtual address space can also be called the process address space. The virtual address space includes the user space that each task owns independently, which can avoid access conflicts and access errors caused by tasks accessing each other. The virtual address space also includes the kernel space shared by all tasks.

[0064] (7) Physical page, virtual page, page table

[0065] The operating system divides the memory space into partitions of equal size, which are called physical blocks. A physical page is a collection of one or more physical blocks, which is also called a page frame.

[0066] The operating system divides the virtual address space into areas of the same size as physical pages. These areas are called virtual pages.

[0067] The page mapping table created by the operating system for each process is called a page table. For all virtual pages in the virtual address space of a process, there is a page table entry in the page table of the process. The page table entry records the mapping relationship between the virtual page and the corresponding physical page in the memory.

[0068] In memory management, to conserve memory space and facilitate discrete storage, a multi-level page table approach is often used to manage page table entries. In this multi-level page table memory management model, a four-level page table is used as an example. The four levels of page tables are the page global directory (PGD), the page upper directory (PUD), the page middle directory (PMD), and the page table.

[0069] (8) Kernel mode tasks and user mode tasks

[0070] The operating system divides its virtual address space into kernel space and user space. Kernel space is used to map kernel code, while user space is used to map the application code for the corresponding task. When a task executes within the application code, it is called a user-mode task, or simply a user-mode task. When a task executes a system call and falls into kernel code, it is called a kernel-mode task, or simply a kernel-mode task.

[0071] (9) Control group (Cgroup)

[0072] The members of a control group are tasks. A control group can be used to limit the resource usage objects, resource usage quantities, and resource usage priorities of its members.

[0073] (10) Memory map (MMAP)

[0074] Memory mapping is a method of mapping files or other objects into the virtual address space of a process.

[0075] (11) Page fault

[0076] A page fault, also known as a page miss, occurs when the CPU discovers that the target virtual page being accessed has no corresponding physical page in memory while executing a task, leading to an interruption. In practice, when the CPU executes a newly created task, page faults will occur repeatedly while accessing the task's virtual address space. The page fault handler then allocates the actual physical page for the task and writes the mapping between the physical page and the target virtual page into the corresponding page table.

[0077] (12) Translation table base register (TTBR)

[0078] In the ARM architecture, TTBR0 and TTBR1 store the base addresses of the first-level page tables (PGDs) for user and kernel space, respectively. Because all tasks share the same kernel space, the contents of TTBR1 are immutable. However, since each task's user space is independent, TTBR0 contains the PGD from the task_struct data structure of the task currently being executed by the CPU.

[0079] After understanding the basic meanings of the above terms, the application scenarios of the embodiments of the present application are introduced below.

[0080] First, refer to Figure 1, which shows a diagram of the virtual address space distribution. In the current ARMv8 architecture, ARM processors support a 64-bit virtual address space. However, current application memory requirements do not require the full 64-bit virtual address space. Therefore, the ARMv8 architecture typically uses a 48-bit address line width, dividing the 64-bit virtual address space into 48-bit user space and 48-bit kernel space.

[0081] As shown in Figure 1, the kernel space is at the top of the virtual address space, with the upper 16 bits all 1, and the address range is [0xFFFF 0000 0000 0000, 0xFFFF FFFF FFFF FFFF]; the user space is at the bottom of the virtual address space, with the upper 16 bits all 0, and the address range is [0x0000 0000 0000 0000, 0x0000 FFFF FFFF FFFF]; the address with the upper 16 bits all 1 or all 0 is called a standard address, and the addresses in between are non-standard addresses and are not allowed to be used.

[0082] Then, please refer to Figure 2, which is a schematic diagram of an application scenario of an embodiment of the present application. As shown in Figure 2, the computing device 10 includes a processor 110, a memory 120, a first page table base address register TTBR1, and a second page table base address register TTBR0. The processor 110 includes a memory management unit (MMU) 111 and a page table cache (TLB) 112. The memory 120 stores a page table 121. The processor 110, TTBR0, and TTBR1 can be integrated into the same chip. Exemplarily, the processor 110 is an ARM architecture processor.

[0083] When the processor 110 needs to access the memory 120 during the execution of a task, it generates a memory access request, which includes a virtual address in the virtual address space of the task; the processor 110 queries the TLB 112 through the MMU 111 whether there is a page table entry corresponding to the virtual address; if so, the processor 110 can allocate the corresponding memory resources to the task according to the page table entry; if not, the processor 110 can further search the page table 121 for the page table entry corresponding to the virtual address through the MMU 111.

[0084] If there is no page table entry corresponding to the virtual address in both TLB 112 and page table 121, a page fault is triggered. At this time, the processor 110 can execute the page fault handler, allocate an actual physical page for the task, and then write the mapping relationship between the physical address of the physical page and the virtual address into the corresponding page table.

[0085] During the above-mentioned page table search 121, if the highest bit of the virtual address in the memory allocation request is 0, the processor 110 can obtain the user space PGD from TTBR0 and query the page table corresponding to the virtual address based on the PGD. If the highest bit of the virtual address is 1, the processor 110 can obtain the kernel space page table base address from TTBR1 and then query the page table corresponding to the virtual address based on the page table base address.

[0086] For example, [38:30] of the virtual address can be used to place the index of the PGD, [29:21] can be used to place the index of the PMD, [20:12] can be used to place the index of the PTE, and [11:0] can be used to place the page offset. After obtaining the physical page base address from TTBR0 or TTBR1, the processor 110 can perform the following steps:

[0087] The first step is to use the PGD index in [38:30] of the virtual address as the offset of the PGD, then add the starting address in TTBR0 or TTBR1 to the PGD offset to obtain an item in the PGD, and determine the PMD pointed to by the item in the PGD. The second step is to use the PMD index in [29:21] of the virtual address as the offset of the PMD, and add the starting address of the PMD determined in the first step to the offset of the PMD to obtain an item in the PMD, and determine the PTE pointed to by the item in the PMD. The third step is to use the PTE index in [20:12] of the virtual address as the offset of the PTE, and add the starting address of the PTE determined in the second step to the offset of the PTE to obtain an item in the PTE, determine the page table entry corresponding to the item in the PTE, and determine the address of the physical page corresponding to the virtual address based on the page table entry. After determining the address of the physical page, the offset of the physical address placed in [11:0] of the virtual address can be added to the address of the physical page to obtain the physical address.

[0088] In the application scenario shown in FIG2 , if the MMU 111 can find the corresponding page table entry when querying the TLB 112, that is, a direct access hit, the processor 110 does not need to query the page table 121, which can save a lot of computing resources. Therefore, by using pages with a larger page size granularity for mapping between physical pages and virtual pages, the same number of page table entries in the TLB 112 can indicate a larger memory range, thereby improving the hit rate of the TLB 112.

[0089] Using pages with smaller page table size granularity to map between physical pages and virtual pages can improve memory utilization, reduce internal fragmentation, and avoid the situation where the memory required by a task is much smaller than a memory page, resulting in most of the memory of the memory page being wasted.

[0090] However, the current ARM architecture supports mapping between physical pages and virtual pages at one of the page size granularities of 4KB, 16KB, or 64KB, and cannot use two or more page size granularities for memory allocation at the same time, making it difficult to meet different memory allocation requirements.

[0091] Based on this, the embodiments of the present application provide a memory allocation method and related equipment, which can realize memory allocation of different page size granularities under the ARM architecture to meet more memory allocation requirements.

[0092] Please refer to Figure 3, which is a flow chart of a memory allocation method provided in an embodiment of the present application. The method is applied to the computing device shown in Figure 2, which includes an ARM architecture processor (hereinafter referred to as the processor), so the computing device can also be called an ARM architecture computing device; the method specifically includes steps 301 to 304.

[0093] Step 301: Configure the page size of a first virtual page of a first virtual address space and the page size of a second virtual page of a second virtual address space.

[0094] Among them, in the startup phase after the computing device is powered on, the processor can configure the TG1 field in the TCR_EL1 register in the computing device, so that the first virtual address space in the virtual address space is divided according to the preset page size (page length), thereby configuring the page size of the first virtual page in the first virtual address space; and then configure the page table base address in TTBR1 according to the page size of the first virtual page.

[0095] Exemplarily, when the TG1 field is set to 0b10, the page size of the first virtual page is 4KB; when the TG1 field is set to 0b01, the page size of the first virtual page is 16KB; when the TG1 field is set to 0b11, the page size of the first virtual page is 64KB.

[0096] The processor can configure the TG0 field in the TCR_EL1 register so that the second virtual address space of the virtual address space is divided according to the preset page size, thereby configuring the page size of the second virtual page in the second virtual address space; and then configure the virtual address part in TTBR0 according to the page size of the second virtual page.

[0097] Exemplarily, when the TG0 field is set to 0b00, the page size of the first virtual page is 4KB; when the TG1 field is set to 0b10, the page size of the first virtual page is 16KB; when the TG1 field is set to 0b01, the page size of the first virtual page is 64KB.

[0098] The page size of the first virtual page is larger than the page size of the second virtual page. For example, the page size of the first virtual page is 64 KB, and the page size of the second virtual page is 4 KB.

[0099] Among them, after configuring the virtual page size in the first virtual address space and the second virtual address space, the processor can configure the access rights of the first virtual address space and the second virtual address space to control the access behavior of different tasks to the virtual address space to avoid access conflicts or access errors.

[0100] Specifically, each page table entry in the page table includes a mapping relationship between a virtual page and a physical page, as well as the access rights to the virtual page corresponding to the page table entry. The processor can perform authentication after finding the corresponding page table entry, and perform subsequent access actions after determining that the currently executed task has the corresponding permissions.

[0101] The first virtual address space configured by the TG1 field belongs to the high-order space of the virtual address space, where the first n bits of the address in the high-order space are 1, and n is an integer greater than 0 and less than 64. The second virtual address space configured by the TG0 field belongs to the low-order space of the virtual address space, where the first n bits of the address in the low-order space are 0. For example, n can be 16.

[0102] Among them, the first virtual address space may include a first sub-virtual address space and a second sub-virtual address space; the processor can configure the access rights of the first sub-virtual address space to be accessible to kernel-mode tasks, and the access rights of the second sub-virtual address space to be accessible to both kernel-mode tasks and user-mode tasks.

[0103] In one possible implementation, as shown in FIG4 , the second virtual address space includes a third sub-virtual address space and a fourth sub-virtual address space; the access rights of the third sub-virtual address space are accessible to both kernel mode tasks and user mode tasks, and the access rights of the fourth sub-virtual address space are accessible to kernel mode tasks.

[0104] Therefore, in the specific example of Figure 4, the first sub-virtual address space and the fourth sub-virtual address space serve as kernel mode address space (hereinafter referred to as kernel space), and the second sub-virtual address space and the third sub-virtual address space serve as user mode address space (hereinafter referred to as user space).

[0105] Optionally, the processor may further configure the access rights of the second sub-virtual address space to be accessible only to user-mode tasks, thereby preventing the second sub-virtual address space reserved for user-mode tasks from being occupied by kernel-mode tasks.

[0106] The embodiment of the present application further divides the high-order first virtual address space and the low-order second virtual address space, and uses part of the high-order space and part of the low-order space together as kernel space, and another part of the high-order space and another part of the low-order space together as user space; thereby being able to flexibly allocate physical pages of different sizes according to the needs of kernel-mode tasks and user-mode tasks.

[0107] It can be understood that the interval distribution shown in Figure 4 is only an example and not a limitation. In a specific implementation, the second sub-virtual address space can also be located before the first sub-virtual address space, or the first sub-virtual address space can be divided into two parts; the position of the fourth sub-virtual address space is the same.

[0108] Specifically, the processor can configure the access rights of the page table entries corresponding to one or more page table base addresses in TTBR0 to be accessible to kernel mode tasks, so that the address interval corresponding to the one or more page table base addresses serves as the fourth sub-virtual address space in the second virtual address space. In this way, when the driver module or other functional module in the kernel needs to use a smaller physical page (such as 4KB), the processor can allocate a second virtual page of the corresponding size to the corresponding task.

[0109] Similarly, the processor can configure the access rights of the page table entries corresponding to one or more page table base addresses in TTBR1 to be accessible to user-mode tasks, so that the address interval corresponding to the one or more page table base addresses is the second sub-virtual address space in the first virtual address space. In this way, the processor can allocate the first virtual page to the application, thereby improving the TLB hit rate.

[0110] Optionally, the size of the first sub-virtual address space is larger than the size of the second sub-virtual address space, and the size of the third sub-virtual address space is larger than the size of the fourth sub-virtual address space. This ensures that kernel-mode tasks are allocated more large-page memory, thereby improving kernel performance.

[0111] As you can understand, the virtual address space is typically divided into two areas: kernel space and user space. The high-order space is reserved for the operating system and hardware, while the low-order space is available to applications. Specifically, hardware registers are typically mapped to the high-address region of the physical address space. Therefore, using the high-order space in the virtual address space as kernel space allows the kernel to access the hardware more quickly. Furthermore, for programming convenience, it is more reasonable for applications to start allocating from the low-order addresses. This separation of kernel and user space prevents conflicts between user programs and the kernel, providing better protection for the kernel.

[0112] In an embodiment of the present application, using a first virtual address space with more high bits as kernel space and a second virtual address space with more low bits as user space can better be compatible with existing applications, operating systems and hardware; after the first virtual page of the first virtual address space is configured, the processor can map the first virtual page to the memory and the input / output (IO) space of various hardware respectively, so that the operating system can call the kernel code stored in the memory and various hardware resources based on the first virtual address space.

[0113] At the same time, kernel-mode tasks can use more first virtual pages with larger page size granularity, which can reduce the number of memory allocations and improve kernel performance.

[0114] Step 302: Determine whether the task to which memory is to be allocated belongs to a preset control group.

[0115] After completing the page configuration of the first virtual address space and the second virtual address space, if the processor detects that virtual memory needs to be allocated to a task, step 302 may be executed. The task to be allocated memory refers to the task to which virtual memory is allocated. Exemplarily, when the processor maps the associated file of the task in the external memory of the computing device, such as a hard disk, to the virtual address space, the processor allocates a virtual page in the virtual address space to the task and maps the virtual page to the associated file.

[0116] The preset control group is used to control memory allocation for tasks. Specifically, the preset control group includes a first control group and a second control group; the first control group is used to control allocation of a first virtual page for a preset kernel-mode task; and the second control group is used to control allocation of a first virtual page or a second virtual page for a preset user-mode task.

[0117] Specifically, the processor may first determine whether the task is a kernel mode task or a user mode task; and then determine whether the task belongs to a control group in the preset control group for controlling kernel mode tasks, or whether the task belongs to a control group in the preset control group for controlling user mode tasks.

[0118] Optionally, the second control group includes a first sub-control group and a second sub-control group; the first sub-control group is used to control allocation of a first virtual page for a preset user mode task, and the second sub-control group is used to control allocation of a second virtual page for a preset user mode task.

[0119] Optionally, the second control group is used to control the priority allocation of one of the first virtual page or the second virtual page to the preset user mode task, and when the priority allocated virtual page is insufficient, allocate the other of the first virtual page or the second virtual page to the preset user mode task.

[0120] Among them, the members of the control group are tasks. When the processor calls kernel code or application code to execute a task, the operating system running on the processor can obtain the identifier of the currently executed task, and then determine the control group to which the task belongs based on the identifier. Specifically, the operating system can obtain the first identifier of the task to be allocated memory, and then traverse the second identifiers of the members in the preset control group to determine whether the first identifier matches the second identifier, thereby determining whether the task belongs to the preset control group. Exemplarily, the first identifier and / or the second identifier can be information in the task_struct data structure of the corresponding task, which is used to uniquely identify the task.

[0121] Step 303 : When the task belongs to a preset control group, allocate the first virtual page or the second virtual page based on the control group to which the task belongs.

[0122] When it is determined that the task belongs to the preset control group, the processor may allocate virtual pages to the task based on the memory usage permission or memory usage priority set for the corresponding control group.

[0123] Specifically, the processor may first obtain the virtual memory size required by the task, and then allocate a corresponding number of first virtual pages or second virtual pages to the task based on the memory usage permission or memory usage priority set by the corresponding control group.

[0124] In one possible implementation, when the task belongs to the first control group, that is, when the task is a preset kernel-mode task, the processor can allocate a first virtual page to the task; when the task belongs to the second control group, that is, when the task is a preset user-mode task, the processor can allocate a first virtual page or a second virtual page to the task.

[0125] In a case where the task belongs to the first control group, the processor may allocate a first virtual page in the first sub-virtual address space to the task.

[0126] Optionally, when the task belongs to the second control group, the processor may allocate a first virtual page in the second sub-virtual address space to the task.

[0127] Optionally, the second virtual address space includes a third sub-virtual address space, and the third sub-virtual address space is a user space; when the task belongs to the second control group, the processor allocates a second virtual page in the third sub-virtual address space to the task.

[0128] In one possible implementation, the second control group includes a first sub-control group and a second sub-control group; when the task belongs to the first sub-control group, the processor can allocate a first virtual page located in the second sub-virtual address space to the task; when the task belongs to the second sub-control group, the processor can allocate a second virtual page located in the third sub-virtual address space to the task.

[0129] In another possible implementation, when the task belongs to the second control group, the processor prioritizes allocating the first virtual page located in the second sub-virtual address space to the task; when the first virtual page in the second sub-virtual address space is insufficient, the second virtual page located in the third sub-virtual address space is allocated to the task.

[0130] Step 304: If the task does not belong to the preset control group, allocate a second virtual page to the task.

[0131] Among them, by using the preset control group, it is possible to allocate virtual pages of preset page sizes to different tasks, and to allocate virtual pages of corresponding sizes based on the actual needs of different tasks, so that these tasks can use physical pages of corresponding sizes, making memory usage more efficient. It is understandable that during the operation of a computing device, the processor needs to perform a huge number of tasks, and it is difficult and unnecessary to divide and control these tasks one by one through the preset control group; therefore, the staff can divide tasks with high importance, high operating requirements, or high memory read and write requirements into the preset control group; for tasks that do not belong to the preset control group, the processor can uniformly allocate a second virtual page with a smaller granularity to them, to avoid these tasks with lower importance, lower operating requirements, or lower memory read and write requirements occupying the first virtual page.

[0132] In one possible implementation, the second virtual address space includes a third sub-virtual address space and a fourth sub-virtual address space, the third sub-virtual address space serves as a user space, and the fourth sub-virtual address space serves as a kernel space; when the task does not belong to a preset control group, the processor can first determine whether the task is a kernel mode task; when the task is a kernel mode task, the second virtual page located in the fourth sub-virtual address space is allocated to the task; when the task is a user mode task, the second virtual page located in the third sub-virtual address space is allocated to the task.

[0133] In an embodiment of the present application, by configuring two intervals with different page size granularities in the virtual address space, and allocating the first virtual page or the second virtual page to the preset different tasks based on the preset control group, memory allocation with different page size granularities can be achieved to meet more memory allocation requirements.

[0134] It can be understood that the user space of the task is described and managed through the task_struct data structure of the task. Therefore, in the embodiment shown in Figure 3, when the virtual address space is divided as shown in Figure 4, and both the user space and the kernel space include high addresses and low addresses, the processor needs to adjust and update the task_struct data structure of the corresponding task when creating or switching tasks to avoid access conflicts under the new access permission settings.

[0135] Specifically, after completing the configuration of the access rights of the virtual address space, the processor can update the task_struct data structure of the corresponding task and the page table entries in TTBR0 and TTBR1 when creating a task or switching tasks.

[0136] There are five basic states of tasks: new state, which is the state when a new task is created by the processor; ready state, which means that the task has been allocated all necessary resources except processor resources, and is waiting for the system to allocate processor resources to run; running state, which is the state in which the task is being run by the processor; waiting state, also called blocking state or sleeping state, which is the state in which the task does not have the running conditions and is suspended, waiting for a certain event to occur; terminated state, which is the state in which the task ends normally after completion, or terminates abnormally due to an insurmountable error, or is terminated by the operating system and a process with termination authority.

[0137] Specifically, after creating a task, the processor may configure the task_struct data structure of the task.

[0138] In one possible implementation, after configuring the page sizes of the first virtual address space and the second virtual address space, as well as the access permissions of each sub-virtual address space, the processor can add a first page table entry to the task_struct data structure of the first task in response to creating the first task; and then add the second page table entry in the second page table base address register of the current task to the task_struct data structure of the first task.

[0139] The current task is the task that the processor is executing.

[0140] The first page table entry is used to indicate the page table base address of the second sub-virtual address space; the second page table entry is used to indicate the page table base address of the fourth sub-virtual address space.

[0141] The computing device includes a first page table base address register, corresponding to TTBR1 in the embodiment shown in FIG2 , and a second page table base address register, corresponding to TTBR0 in the embodiment shown in FIG2 . For ease of description, TTBR1 will be used to refer to the first page table base address register, and TTBR0 will be used to refer to the second page table base address register.

[0142] Specifically, TTBR1 is used to store the page table base address of the first virtual address space, and TTBR0 is used to store the page table base address of the second virtual address space.

[0143] Each task has its own user space. When creating a task, the processor divides the second virtual address space according to the TG0 field in the TCR_EL1 register to obtain the PGD of the second virtual address space of the task. It then allocates a physical page to store the PGD and maps the physical address of the physical page to the first address of the PGD. Finally, when configuring the management information of the task, the PGD is written into the task_struct data structure of the task. In this way, when executing the task, the processor can obtain the PGD from the task_struct data structure of the task and load the PGD into TTBR0, so that the MMU can find the page table corresponding to the task through the page table base address in TTBR0.

[0144] Since in this embodiment, the processor configures the access rights of the second sub-virtual address space in the first virtual address space and regards the second sub-virtual address space as part of the user space, the processor can add a first page table entry for indicating the page table base address of the second sub-virtual address space of the task in the task_struct data structure of the newly created task, so that the processor can synchronize the corresponding first page table entry to TTBR1 when executing the task, so that the processor can access the second sub-virtual address space of the currently executing task through TTBR1 to avoid access errors.

[0145] Specifically, the processor can obtain the PGD of the first virtual address space of the first task, and then obtain the first address of the second sub-virtual address space from it; then allocate a physical page for the first task and map it to the first address of the second sub-virtual address space; finally, write the mapping relationship and the page table base address of the second sub-virtual address space, that is, the first page table entry, into the task_struct data structure of the first task.

[0146] In addition, since the processor in this embodiment configures the access rights of the fourth sub-virtual address space of the second virtual address space and uses the fourth sub-virtual address space as the kernel space, and each task shares the same kernel space but has an independent user space, it is necessary to keep the third sub-virtual address space of each task independent of each other and the page table base address of the fourth sub-virtual address space consistent. Furthermore, since the PGD in the task_struct data structure of each task is used to manage the second virtual address space of the corresponding task, the processor can update the second page table entry of the currently executing task in TTBR0 to the PGD in the task_struct data structure of the newly created first task, thereby maintaining the consistency of the kernel space when the processor executes different tasks and avoiding exceptions or failures when the processor accesses the kernel space.

[0147] Specifically, the processor may write the second page table entry into the PGD, overwriting the page table entry with the same virtual address portion in the PGD.

[0148] After completing the configuration of the task_struct data structure of the task, the task is converted from the new state to the ready state; when the task switches from the ready state or the waiting state to the running state, the processor needs to switch the relevant context to ensure the normal operation of the task.

[0149] The context is a static description of the entire task execution process. The contents of previously executed task instructions and data in related registers and on the stack are called the context; the contents of currently executing instructions and data in related registers and on the stack are called the body; and the contents of pending instructions and data in related registers and on the stack are called the context. Context switching involves switching virtual address spaces to ensure that when executing a task, the CPU accesses instructions and data in the address space in memory that belongs to the task.

[0150] In one possible implementation, the processor creates a first task and a second task, and executes the first task; in response to switching the first task to the second task, the processor can update the corresponding page table entry in TTBR1 according to the first page table entry in the task_struct data structure of the second task; and then update the task_struct data structure of the second task according to the second page table entry of the first task in TTBR0.

[0151] In the process of switching the first task to the second task, the processor may switch the context of the first task to the context of the second task.

[0152] Among them, the page table entry in TTBR1 is used to indicate the page table base address of the first virtual address space, that is, TTBR1 includes the first page table entry for indicating the page table base address of the second sub-virtual address space of the current task; therefore, when switching the first task to the second task, it is necessary to update the first page table entry corresponding to the first task in TTBR1 to the first page table entry corresponding to the second task, so that the processor can access its own user space through TTBR1.

[0153] Specifically, the processor may write the page table entry value of the first page table entry corresponding to the second task into TTBR1, overwriting the first page table entry corresponding to the first task.

[0154] Among them, the processor can obtain the second page table entry of the first task in TTBR0, that is, the page table base address of the fourth sub-virtual address space of the first task; and copy and write the PGD corresponding to the second task according to the second page table entry corresponding to the first task, and update the second page table entry corresponding to the second task; then, write the PGD of the second task into TTBR0 to keep the page table base address of the kernel space unchanged.

[0155] It is understandable that the processor may first update the page table entries in TTBR1 and then update the page table entries in TTBR0; or the processor may first update the page table entries in TTBR0 and then update the page table entries in TTBR1. This embodiment of the present application does not specifically limit this.

[0156] In another possible implementation, the processor can obtain the third page table entry in PGD in the task_struct data structure of the second task, where the third page table entry is the page table base address used to indicate the third sub-virtual address space of the second task; and then update the page table entry corresponding to the third sub-virtual address space in TTBR0 according to the third page table entry.

[0157] Among them, the processor can keep the page table entry of the fourth sub-virtual address space in TTBR0 unchanged, and then update the third page table entry corresponding to the third sub-virtual address space as the user space to TTBR0.

[0158] Specifically, the processor may write the page table entry value of the third page table entry corresponding to the second task into TTBR0, overwriting the third page table entry corresponding to the first task in TTBR0.

[0159] In another possible implementation, the processor may first obtain the second page table entry of the first task in TTBR0, then write the PGD in the task_struct data structure of the second task into TTBR0, and then update the second page table entry of the second task in TTBR0 according to the second page table entry corresponding to the first task.

[0160] Through the above configuration and update actions when creating and switching tasks, access conflicts can be avoided and the security of the kernel space can be improved when both the user space and the kernel space include high addresses and low addresses.

[0161] The memory allocation process in the embodiment of the present application will be further described below in combination with two application scenarios.

[0162] Please refer to Figure 5, which is a schematic diagram of a memory mapping process in an embodiment of the present application. The process is executed by a computing device, which includes an ARM architecture processor; as shown in Figure 5, the memory mapping process includes steps 501 to 506.

[0163] Step 501: Determine that the task to be allocated memory is a target task.

[0164] The virtual address space distribution in this embodiment is shown in FIG4 .

[0165] The target task is a task that performs a memory map (MMAP) operation. After a task is created, the processor allocates virtual pages in the virtual address space to the task, mapping the task's associated files into the task's virtual address space. At this point, the processor determines that the task to which memory is to be allocated is the target task. Specifically, when the task performs MMAP, it sends an MMAP request to the operating system.

[0166] The MMAP request includes the starting address of the file in the memory, the mapping length, and the offset of the mapping starting address in the file.

[0167] When the processor is executing a task, if the task requires allocation of virtual memory, the processor may first determine whether the task is a target task; if the task is a target task, the processor may obtain the MMAP request and execute step 502.

[0168] In the case that the task is not the target task, steps 302 to 304 in the embodiment shown in FIG3 may be executed to allocate virtual memory for the task.

[0169] Step 502: Determine whether the task belongs to the second control group.

[0170] After receiving the MMAP request, the processor may first determine whether the task is in a second control group, wherein the second control group is a preset control group used to control allocation of the first virtual page to the preset user mode task.

[0171] It can be understood that, in the memory mapping scenario of this embodiment, the processor will preferentially allocate the first virtual page to the user-mode tasks belonging to the second control group.

[0172] In some other possible implementations, the first control group is used to control its group members to use only the first virtual page.

[0173] In this embodiment, when the first virtual page of the second sub-virtual address space has been allocated, or the first virtual page cannot be allocated temporarily, the processor may execute step 506 .

[0174] If the task is in the second control group, step 503 is executed; if the task is not in the second control group, step 506 is executed.

[0175] Step 503: If the task belongs to the second control group, determine whether the offset of the MMAP request corresponding to the task matches the page size of the first virtual page.

[0176] After determining that the task is in the second control group, the processor may further determine whether the offset in the MMAP request matches the page size of the first virtual page.

[0177] Specifically, the processor may determine whether the offset is an integer multiple of the page size of the first virtual page. If so, the processor may determine that the MMAP request meets the requirement of using the first virtual page for memory mapping and execute step 504; if not, the processor may determine that the MMAP request does not meet the requirement and execute step 506.

[0178] Step 504: When the offset matches the page size of the first virtual page, determine whether the MMAP request is a fixed mapping and the mapping address range is located in the third sub-virtual address space.

[0179] Among them, after determining that the task belongs to the second control group, the processor needs to allocate a first virtual page for the task, and determine that the offset of the MMAP request matches the page size of the first virtual page, and meets the requirements of using the first virtual page for memory mapping. The processor can also further determine whether the current memory mapping of the task specifically specifies the use of the second virtual page for mapping.

[0180] At this time, the processor may determine whether the MMAP request is a fixed mapping and the mapping address range is located in the third sub-virtual address space.

[0181] The processor may obtain a mapping function of the memory mapping request. If the mapping function is a fixed mapping function map_fixed, the memory mapping request may be determined to be a fixed mapping; otherwise, the memory mapping request may be determined not to be a fixed mapping.

[0182] If the memory mapping request is a fixed mapping, the fixed mapping function specifies the first address of the mapping in the virtual address space; and the mapping address range can be obtained according to the first address and the mapping length.

[0183] If the MMAP request is a fixed mapping and the mapping address range is within the third sub-virtual address space, it means that the current memory mapping of the task specifically specifies the use of the second virtual page for mapping and the mapping request is legal. At this time, the processor can execute step 506.

[0184] If the MMAP request is a fixed mapping and the mapping address range is not located in the second sub-virtual address space and the third sub-virtual address space, that is, the mapping address range is located in the kernel space (the first sub-virtual address space or the fourth sub-virtual address space), the processor can return a message to the task that the memory mapping failed or that the mapping is not authorized.

[0185] If the MMAP request is not a fixed mapping, or the mapping address range of the fixed mapping is within the second sub-virtual address space, it indicates that the task's request to use the first virtual page for memory mapping is legal, and the processor may execute step 505 .

[0186] Step 505: When the MMAP request is not a fixed mapping, or the mapping address range is located in the second sub-virtual address space, allocate a first virtual page in the second sub-virtual address space to the task.

[0187] Among them, if the MMAP request is not a fixed mapping, the processor can obtain the second first address of the mapping, which is determined by the operating system based on the current idle status of the second sub-virtual address space; and then allocate the first virtual page in the second sub-virtual address space to the task starting from the first address.

[0188] If the MMAP request is a fixed mapping and the mapping address range is located in the second sub-virtual address space, the processor may allocate the first virtual page in the second sub-virtual address space for the task starting from the first first address specified in the MMAP request.

[0189] Thereafter, the processor may map the related files of the task to the first virtual page allocated to the task.

[0190] Step 506: Allocate a second virtual page in the third sub-virtual address space to the task.

[0191] Among them, if the task is not in the second control group, or the offset in the MMAP request does not match the page size of the first virtual page, the processor can obtain the mapped third first address, which is determined by the operating system based on the current idle status of the third sub-virtual address space, and then allocate the second virtual page to the task starting from this first address.

[0192] Among them, if the memory mapping request is a fixed mapping and the mapping address range is located in the third sub-virtual address space, the processor can allocate the second virtual page in the third sub-virtual address space to the task based on the first first address specified in the fixed mapping function.

[0193] Thereafter, the processor may map the related file of the task to the second virtual page allocated to the task.

[0194] In an embodiment of the present application, the memory mapping behavior requested by the task can be authenticated through the control group to which the task belongs and the mapping address range indicated by the MMAP request, and a virtual page of corresponding size can be allocated, which can meet different memory mapping requirements while ensuring the security of memory mapping.

[0195] Please refer to Figure 6, which is a schematic diagram of a page fault handling process in an embodiment of the present application. The process is executed by a computing device including an ARM architecture processor. As shown in Figure 6, the page fault handling process includes steps 601 to 608. The virtual address space distribution in this embodiment is shown in Figure 4.

[0196] Step 601: Determine the first physical page accessed by the task based on the target virtual page and the page table.

[0197] The target virtual page is the virtual page indicated by the virtual address in the access request of the task.

[0198] When the processor executes a task, it needs to access the corresponding physical page containing the task's related file data through the virtual page in the user space of the task. At this time, the processor can obtain the virtual address of the target virtual page in the memory access request and then determine the corresponding first physical page based on the page table entry in the page table.

[0199] It is understandable that after establishing a mapping between a virtual page and the relevant files or data of a corresponding task, the processor may not immediately allocate a physical page corresponding to the virtual page to the task, but instead allocates a physical page to the task by triggering a page fault handler when the task accesses the virtual page.

[0200] Therefore, in the case of determining that the first physical page is missing, the processor may execute step 602 .

[0201] Step 602: In response to a first physical page miss, determine whether the page size of the target virtual page matches the page size of the first virtual page.

[0202] A page fault typically occurs during user space access. This embodiment uses a page fault that occurs when a processor accesses user space as an example. When the processor executes a user-mode task and accesses memory through the second or third sub-virtual address space, if the target virtual page being accessed cannot find the corresponding first physical page in either the TLB or the memory page table, the processor determines that the first physical page is missing and a page fault occurs.

[0203] After determining that a page fault occurs, the processor may first determine whether the page size of the target virtual page matches the page size of the first virtual page, and then determine the page size of the first physical page.

[0204] Exemplarily, the page size of the first virtual page is 64KB, and the page size of the second virtual page is 4KB; if the page size of the target virtual page is 64KB, the processor can determine that the page size of the target virtual page matches the page size of the first virtual page; if the page size of the target virtual page is 4KB, the processor can determine that the page size of the target virtual page matches the page size of the second virtual page.

[0205] If the page size of the target virtual page matches the page size of the first virtual page, the processor executes step 603 ; if the page size of the target virtual page matches the page size of the second virtual page, the processor executes step 605 .

[0206] It can be understood that in this embodiment, the virtual pages of the entire virtual address space include the first virtual page and the second virtual page. That is, when the page size of the target virtual page does not match the page size of the first virtual page, the page size of the target virtual page matches the page size of the second virtual page.

[0207] In some other embodiments, when the virtual address space includes virtual pages of greater granularity, embodiments with the same effect can be obtained based on the adaptation and adjustment of this embodiment, and these embodiments should be within the protection scope of the embodiments of the present application.

[0208] Step 603: When the page size of the target virtual page matches the page size of the first virtual page, determine whether the virtual address corresponding to the target virtual page is located in the second sub-virtual address space.

[0209] After determining the page size of the target virtual page, the processor may further determine the sub-virtual address space where the target virtual page is located to determine whether the access by the task is legal.

[0210] Specifically, when the page size of the target virtual page matches the page size of the first virtual page, the processor may further determine whether the target virtual page is in the second sub-virtual address space.

[0211] If the target virtual page is in the second sub-virtual address space, it means that the access target of the task is the first virtual page in the user space. The processor has the corresponding access rights when executing the task, so step 604 can be executed.

[0212] If the target virtual page is not in the second sub-virtual address space, that is, in the first sub-virtual address space, it means that the access target of the task is the kernel space, and the processor does not have the corresponding access rights when executing the task. At this time, the processor can execute step 608.

[0213] Step 604: When the virtual address is located in the second sub-virtual address space, allocate a second physical page to the task.

[0214] The second physical page has the same page size as the first virtual page.

[0215] When it is determined that a page miss occurs and the access behavior of the task is legal, the processor may allocate a second physical page having the same page size as the first virtual page to the task, so as to map the second physical page to the target virtual page.

[0216] In a possible implementation, if the page fault is a soft page fault, that is, the data content corresponding to the target virtual page has been loaded into the second physical page of the memory, the processor may allocate the second physical page to the task and then execute step 607.

[0217] In another possible implementation, when the page miss is a hard page miss, that is, the data content corresponding to the target virtual page is not loaded into the second physical page of the memory, the processor can determine an idle physical page with the same page size as the first virtual page as the second physical page, and load the data content of the task corresponding to the target virtual page into the second physical page, and then allocate the second physical page to the task, and then execute step 607.

[0218] Step 605: If the page size of the target virtual page does not match the page size of the first virtual page, determine whether the virtual address corresponding to the target virtual page is located in the third sub-virtual address space.

[0219] If the target virtual page is not the first virtual page, but the second virtual page, the processor may determine whether the target virtual page is in the third sub-virtual address space to determine whether the access behavior is legal.

[0220] If the target virtual page is in the third sub-virtual address space, it means that the access target of the task is the second virtual page corresponding to the user space, and the processor has the corresponding access rights when executing the task, so step 606 can be executed; if the target virtual page is not in the third sub-virtual address space, that is, it is in the fourth sub-virtual address space, it means that the access target of the user-state task is the kernel space, and the processor does not have the corresponding access rights when executing the user-state task, and the processor can execute step 608 at this time.

[0221] Step 606: When the virtual address is located in the third sub-virtual address space, allocate a third physical page to the task.

[0222] The third physical page has the same page size as the second virtual page.

[0223] It is understandable that the specific implementation of step 606 is similar to that of step 604 , and the third physical page is equivalent to the second physical page of step 604 , which will not be described in detail here.

[0224] Step 607: Add the mapping relationship between the physical page allocated to the task and the target virtual page to the page table.

[0225] After allocating the physical page to the task, the processor may write the mapping relationship between the physical page and the target virtual page into a corresponding page table so that the task can access it again later.

[0226] Step 608: Return access failure information.

[0227] When the processor determines that the access target of the current user-mode task is the kernel space, it may return an access failure message or an insufficient access permission message to the task.

[0228] In an embodiment of the present application, when a page fault is detected, the access behavior is authenticated, and when it is determined that the access target is the user space, the corresponding physical page allocation is performed, which can improve the security of the access behavior.

[0229] Please refer to Figure 7, which is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. As shown in Figure 7, the computing device 700 provided in an embodiment of the present application includes a processor 710 and a memory 720. Among them, the processor 710 is an ARM architecture processor.

[0230] Among them, the processor 710 may include one or more processing cores. The processor 710 uses various interfaces and lines to connect the various parts within the computing device 700, and executes the methods provided by any one or more of the above embodiments by running or executing instructions, programs, code sets or instruction sets stored in the memory 720, and calling data stored in the memory 720. Optionally, the processor 710 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 710 can integrate one or more of a CPU, a graphics processing unit (GPU), and a modem. It is understandable that the above-mentioned modem may not be integrated into the processor 710, but may be implemented separately through a communication chip.

[0231] The memory 720 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 720 includes a non-transitory computer-readable storage medium. The memory 720 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 720 may include a program storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the method of the embodiment of the present application, etc.

[0232] The processor 710 and the memory 720 are communicatively connected via a bus within the computing device 700. This bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG7 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0233] In another embodiment of the present application, a computer-readable storage medium is also provided, in which computer-executable instructions are stored. When at least one processor of the device executes the computer-executable instructions, the device executes the method flow described in any of the above embodiments of Figures 3, 5 or 6.

[0234] In another embodiment of the present application, a computer program product is also provided, which includes computer execution instructions, which are stored in a computer-readable storage medium; at least one processor of the device can read the computer execution instructions from the computer-readable storage medium, and at least one processor executes the computer execution instructions so that the device executes the method flow described in any of the embodiments of Figures 3, 5 or 6 above.

[0235] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0236] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0237] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0238] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0239] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0240] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. A memory allocation method, characterized in that: The memory allocation method is applied to a computing device of an ARM architecture; the method comprises: Configuring a page size of a first virtual page of a first virtual address space and a page size of a second virtual page of a second virtual address space; wherein the page size of the first virtual page is larger than the page size of the second virtual page; Determining whether the task to which memory is to be allocated belongs to a preset control group; the preset control group includes a first control group and a second control group; wherein the first control group is used to control allocation of the first virtual page to a preset kernel mode task; and the second control group is used to control allocation of the first virtual page or the second virtual page to a preset user mode task; In a case where the task belongs to the preset control group, the first virtual page or the second virtual page is allocated to the task based on the control group to which the task belongs.

2. The method according to claim 1, characterized in that The first virtual address space includes a first sub-virtual address space and a second sub-virtual address space; wherein the first sub-virtual address space is a kernel state address space; the second sub-virtual address space is a user state address space; When the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs includes: In a case where the task belongs to the first control group, allocating a first virtual page in the first sub-virtual address space to the task; In a case where the task belongs to the second control group, a first virtual page located in the second sub-virtual address space is allocated to the task.

3. The method according to claim 1, characterized in that The first virtual address space includes a first sub-virtual address space, and the second virtual address space includes a third sub-virtual address space; wherein the first sub-virtual address space is a kernel state address space; and the third sub-virtual address space is a user state address space; When the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs includes: In a case where the task belongs to the first control group, allocating a first virtual page in the first sub-virtual address space to the task; In a case where the task belongs to the second control group, a second virtual page located in the third sub-virtual address space is allocated to the task.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: In a case where the task does not belong to the preset control group, the second virtual page is allocated to the task.

5. The method according to claim 4, characterized in that The second virtual address space includes a fourth sub-virtual address space, and the fourth sub-virtual address space is a kernel mode address space; When the task does not belong to the preset control group, allocating the second virtual page to the task includes: If the task does not belong to the preset control group, determining whether the task is a kernel-mode task; In a case where the task is the kernel mode task, a second virtual page located in the fourth sub-virtual address space is allocated to the task.

6. The method according to claim 1, characterized in that The second control group is used to control the allocation of the first virtual page to the preset user mode task; the first virtual address space includes a second sub-virtual address space; the second virtual address space includes a third sub-virtual address space; wherein the second sub-virtual address space and the third sub-virtual address space are user mode address spaces; Before determining whether the task to be allocated memory belongs to a preset control group, the method further includes: Determine whether the task is a target task, wherein the target task is a task that performs memory mapping MMAP; Determining whether the task to be allocated memory belongs to a preset control group includes: If the task is the target task, determining whether the task belongs to the second control group; When the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs includes: If the task belongs to the second control group, determining whether an offset in the MMAP request corresponding to the task matches a page size of the first virtual page; If the offset matches the page size of the first virtual page, determining whether the MMAP request is a fixed mapping and the mapping address range of the MMAP request is located in the third sub-virtual address space; In a case where the MMAP request is not a fixed mapping, or the mapping address range is located in the second sub-virtual address space, the first virtual page located in the second sub-virtual address space is allocated to the task.

7. The method according to claim 2, characterized in that After allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs, the method further includes: Determining a first physical page accessed by the task based on a target virtual page and a page table, wherein the target virtual page is a virtual page indicated by a virtual address in an access request of the task; In response to the first physical page being missing, determining whether a page size of the target virtual page matches a page size of the first virtual page; In a case where the page size of the target virtual page matches the page size of the first virtual page, determining whether the virtual address corresponding to the target virtual page is located in the second sub-virtual address space; When the virtual address corresponding to the target virtual page is located in the second sub-virtual address space, allocating a second physical page to the task, wherein the second physical page has the same page size as the first virtual page; A mapping relationship between the second physical page and the target virtual page is added to the page table.

8. The method according to any one of claims 1 to 7, characterized in that The first virtual address space includes a second sub-virtual address space; the second virtual address space includes a fourth sub-virtual address space; The method further comprises: In response to creating the first task, adding a first page table entry in the task_struct data structure of the first task; the first page table entry is used to indicate a page table base address of the second sub-virtual address space; Add the second page table entry of the current task in the second page table base address register to the task_struct data structure of the first task; wherein, the second page table base address register is used to store the page table base address of the second virtual address space; and the second page table entry is used to indicate the page table base address of the fourth sub-virtual address space.

9. The method according to claim 8, characterized in that After adding the second page table entry of the current task in the second page table base address register to the task_struct data structure of the first task, the method further includes: In response to switching the first task to a second task, updating a corresponding page table entry in a first page table base address register according to a first page table entry in a task_struct data structure of the second task; wherein the first page table base address register is used to store a page table base address of the first virtual address space; Update the task_struct data structure of the second task according to the second page table entry of the first task in the second page table base address register.

10. A computing device, characterized in that The computing device includes a memory and a processor; wherein the processor is an ARM architecture; The memory is coupled to the processor; The memory is used to store computer program instructions; The processor is configured to call the computer program instructions to execute the memory allocation method according to any one of claims 1 to 9.

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