Creating a layout of a printed circuit board (PCB) including electrical components using a model for assigning the electrical components onto positions of a PCB array

Abstract

The invention relates to a method for creating a layout of a PCB including a plurality of electrically connected, electrical components. To facilitate creating the PCB layout, the method includes: providing an array of a board canvas of the PCB; providing a list of components and electrical connections of the components; providing feature information of the respective component and of the respective connection; providing a model incorporating the array, the list, and the feature information, where the model describes a sequence of consecutive actions of assigning one of the components of the list onto a respective position of the array; determining a respective probability distribution for assigning one of the components onto a respective position of the array using the model; composing the layout of the components on the array using the respective assigning action with the highest respective probability in the respective probability distribution; and outputting the composed layout.

Description

202400525 1 CREATING A LAYOUT OF A PRINTED CIRCUIT BOARD (PCB) INCLUDING ELECTRICAL COMPONENTS USING A MODEL FOR ASSIGNING THE ELECTRICAL COMPONENTS ONTO POSITIONS OF A PCB ARRAY TECHNICAL FIELD

[0001] The present disclosure is directed, in general, to electronic design automation (EDA) and, more specifically, to create a layout of a printed circuit board (PCB) including electrical components using a model for assigning the components onto positions of the PCB array. Such electronic design automation systems and PCB layout systems are collectively referred to herein as product systems. BACKGROUND ART

[0002] The development of electronic devices with printed circuit boards typically involves many steps known as a design flow. This design flow typically starts with a specification for a new electronic device to be implemented with a printed circuit board. The specification of the electronic device may be transformed into an electronic device design, such as a netlist (e.g., by a schematic capture tool or by synthesizing a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic device). The netlist may be specified in an Electronic Design Interchange Format (EDIF) or the like, which may describe nets or connectivity between various components or parts in the electronic device design.

[0003] The design flow may continue by verifying functionality of the electronic device design, for example, by simulating, emulating, or prototyping the electronic device design and verifying that the results of the simulation or emulation correspond with an expected output from the electronic device design. The functionality may also be verified by formally verifying with one or more solvers or statically checking the electronic device design for various attributes that may be problematic during operation of the electronic device built utilizing the electronic device design.

[0004] Once the electronic device design has been functionally verified, the design flow may utilize the logical design to generate a layout design for the electronic device. This procedure may be implemented in different ways, but typically, through the use of a layout tool, which may place and interconnect various components or parts into a representation of a printed circuit board. For example, the layout tool implemented in a computing system may present a graphical view of the printed circuit board and allow a designer to utilize the layout tool to place parts from a library onto the printed circuit board in the graphical view.202400525 2

[0005] In this context, the task of creating a layout of a PCB may sometimes be roughly divided into three parts: Component selection (e.g., choosing the hardware components having interplay that fulfils the functional requirements associated with the PCB, and connecting the chosen components to one another accordingly); Component placement (e.g., PCB floor-planning), such as choosing the physical locations for each of the selected components on the PCB; and component wiring (e.g., outlining how exactly the copper traces meant for connecting the components will be applied onto the PCB).

[0006] In some respects, the present patent disclosure primarily focusses on the second task in the PCB layout process (e.g., component placement). Given a list of components and their connections (e.g., netlist), the engineers are to decide on the board layout (e.g., the placement of the physical components on the PCB).

[0007] Currently, there exist product systems and solutions that support creating a layout of a PCB including electrical components. Such product systems may benefit from improvements. SUMMARY AND DESCRIPTION

[0008] Variously disclosed embodiments include methods and computer systems that may be used to facilitate creating a layout of a PCB including electrical components.

[0009] According to a first aspect of the present invention, a computer-implemented method for creating a layout of a PCB including a plurality of electrically connected, electrical components may include: providing an array of a board canvas of the PCB; providing a list of the components and of the electrical connections of the components; providing feature information of the respective component and of the respective connection; providing a model incorporating the array, the list, and the feature information, where the model describes a sequence of consecutive actions of assigning one of the components of the list onto a respective position of the array; determining a respective probability distribution for assigning one of the components onto a respective position of the array using the model; composing the layout of the components on the array using the respective assigning action with the highest respective probability in the respective probability distribution; and outputting the composed layout.

[0010] According to a second aspect of the invention, a computer system may be arranged and configured to execute the steps of this computer-implemented method according to the first aspect.

[0011] According to a third aspect, a computer program product may include computer program code that, when executed by the computer system according to the second aspect,202400525 3 causes the computer system to carry out the method according to the first aspect.

[0012] According to a fourth aspect, a computer-readable medium (e.g., a non-transitory computer-readable storage medium) may include the computer program product according to the third aspect. By way of example, the described computer-readable medium may be non- transitory and may further be a software component on a storage device.

[0013] The foregoing has outlined rather broadly the technical features of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure will be described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that the conception and the specific embodiments disclosed may readily be used as a basis for modifying or creating a layout of other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0014] Also, before undertaking the detailed description below, it should be understood that various definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.

[0015] Embodiments will be described below in greater detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 depicts a functional block diagram of a first example system that facilitates creating a layout of a PCB comprising electrical components in a product system.

[0017] Figures 2-4 depict a flow diagram of a first to third aspect of an example PCB layout process that may be performed by the first example system, respectively.

[0018] Figure 5 depicts a functional block diagram of a second example system that facilitates creating a layout of a PCB including electrical components in a product system.

[0019] Figure 6 depicts a flow diagram of a training procedure relating to the example PCB layout process that may be performed by the first example system or the second example system.

[0020] Figure 7 depicts a flow diagram of an example methodology that facilitates creating a layout of a PCB comprising electrical components in a product system.202400525 4

[0021] Figure 8 depicts a block diagram of a data processing system in which an embodiment can be implemented. DETAILED DESCRIPTION

[0022] Various technologies that pertain to systems and methods for creating a layout of a printed circuit board (PCB) including electrical components in a product system are described with reference to the drawings, where like reference numerals represent like elements throughout. The drawings discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document, are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged apparatus. Functionality that is described as being carried out by certain system elements may be performed by multiple elements. Similarly, for example, an element may be configured to perform functionality that is described as being carried out by multiple elements. The numerous innovative teachings of the present patent document will be described with reference to exemplary non-limiting embodiments.

[0023] With reference to Figure 1, a functional block diagram of an example computer system or data processing system 100 is depicted. The example computer system or data processing system 100 facilitates creating a layout 140 of a PCB 120 including electrical components 122. The processing system 100 may include a PCB layout system 118 that may, in some examples, include at least one processor 102 (e.g., a processor) that is configured to execute at least one application software component 106 from a memory 104 accessed by the processor 102. The application software component 106 may be configured (e.g., programmed) to cause the processor 102 to carry out various acts and functions described herein. For example, the described application software component 106 may include and / or correspond to one or more components of an application for creating a layout 140 of a PCB 120 including electrical components 122. The application software component 106 may, for example, be configured to generate and store product data in a data store 108 such as a database.

[0024] By way of example, the PCB layout system 118 may be cloud-based, internet-based, and / or be operated by a provider providing support for creating a layout 140 of PCBs 120. In some examples, the user may be located close to the PCB layout system 118 or remote from the PCB layout system 118 (e.g., anywhere else, such as using a mobile device for connecting to the PCB layout system 118, such as via the internet; the mobile device may include an202400525 5 input device 110 and a display device 112). In some examples, the PCB layout system 118 may be installed and run on a user device, such as a computer, laptop, pad, on-premises computing facility, or the like.

[0025] Creating the layout 140 of PCBs 120 may be a challenging and time-consuming process that may require highly skilled engineers with many years of training. For example, advanced knowledge in electronics, physics, and other scientific domains may be required, or selections of many options need to be made consciously, each involving many manual steps, which is a long and inefficient process.

[0026] To enable the enhanced creation of a layout 140 of PCBs 120, the described product system or processing system 100 may include at least one input device 110 and at least one display device 112 (e.g., a display screen). The described processor 102 may be configured to generate a graphical user interface (GUI) 114 through the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, scroll bars usable by a user to provide inputs through the input device 110 that cause creating the layout 140 of a PCB 120. By way of example, the GUI 114 may include a PCB layout user interface (UI) 116 provided to a user.

[0027] In an example embodiment, for creating a layout 140 of a PCB 120 including a plurality of electrically connected, electrical components 122, the application software component 106 and / or the processor 102 may be configured to provide an array 124 of a board canvas of the PCB 120.

[0028] Herein, the creation of the layout 140 may be understood as a determination or derivation of the layout 140 using input data, which is explained in more detail below. Further, a PCB 120 (e.g., printed wiring board (PWB)) is a medium used to connect or "wire" components to one another in an electric circuit. In some examples, the components 122 may include electrical resistances, electrical capacitors, and transistors, batteries, and the like. The components 122 may further include net nodes of the types: ground, power (e.g., 24 volts), etc., where a net may be understood as the electrically interconnected components 122 and their connections 128. In some examples, a net may correspond to the electric wire or connection 128 between two components 122 (e.g., direct pins of the connected components 122 or the conductor path between the connected components 122) and optionally further components 122 electrically arranged between the connected components 122.

[0029] In some examples, the PCB 120 and the components 122 arranged on the PCB 120 may also be understood as an integrated circuit (IC) (e.g., a microchip). An IC is a small electronic device made up of multiple interconnected electronic components such as202400525 6 transistors, resistors, and capacitors. These components may be etched onto a small piece of semiconductor material (e.g., silicon).

[0030] Further, an area of the PCB 120 on which the components 122 may be arranged and electrically connected may be described by the board canvas, which may in turn be described by the array 124. Herein, the array 124 may, for example, be two-dimensional and be subdivided in specific positions 136 that may be arranged in columns and rows. Further, the array 124 may be understood as a geometrical construct that may be used for the described purposes of determining the layout 140 of the PCB 120. In some examples, also a three- dimensional array 124 may be possible, for example, by staggering two or more two- dimensional arrays 124. Such three-dimensional arrays 124 may be useful for more complex PCBs 120 that provide two or more layers in which the components 122 may be arranged or through which the components 122 may be connected.

[0031] In some examples, providing the array 124 may involve that the area of the PCB 120 on which the components 122 may be arranged and electrically connected may be determined by a user or engineer. The array 124 may be provided and stored in the data store 108 of the PCB layout system 118 (e.g., by the user using the PCB layout UI 116 and / or the input device 110). In some examples, the array 124 may be received, for example, via an application programming interface (API) from another data source 108’. Similar approaches may also be used for the provision of the other input information, which is explained in more detail below.

[0032] In some examples, the plurality of electrically connected, electrical components 122 includes millions or even billions of such components 122.

[0033] In some examples, the application software component 106 and / or the processor 102 may further be configured to provide a list 126 of the components 122 and of the electrical connections 128 of the components 122.

[0034] The list 124 may, for example, be determined or be provided after the above- mentioned component selection task, which may be part of the above-mentioned design flow. The list 124 includes the PCB’s 120 components 122 and the connections 128 connecting the components 122. In the EDA or design flow context, the list 124 may also be referred to as netlist.

[0035] By way of example, the application software component 106 and / or the processor 102 may further be configured to provide feature information 130 of the respective component 122 and of the respective connection 128.

[0036] The feature information 130 may include information on the type, the shape, or other202400525 7 characteristics of the respective component 122 or of the respective connection 128. For example, with respect to the components 122, the feature information 130 may, for example, indicate whether the respective component 122 is a resistance, a capacitor, a transistor, or a battery, but also a ground potential or an electrical potential of a certain voltage (e.g., 24 volts). With respect to the connections 128, the feature information 130 may, for example, indicate whether the respective connection 128 is a signal connection or a power connection that is suitable for larger electric currents or electric voltages than a signal connection. Optionally, in some examples, the feature information 130 may further include information on the placement if the component 122 is already placed (e.g., the feature information 130 may include a position 136 to which a certain component 122 or connection 128 has already been assigned beforehand).

[0037] In further examples, the application software component 106 and / or the processor 102 may further be configured to provide a model 132 incorporating the array 124, the list 126, and the feature information 130. The model 132 describes a sequence of consecutive actions 134 of assigning one of the components 122 of the list 126 onto a respective position 136 of the array 124.

[0038] The PCB 120 may be produced by placing the individual components 122 on the PCB 120 (e.g., on a surface of the PCB 120). Similarly, the layout 140 of the PCB 120 may be composed by “placing” or assigning the components 122 onto a respective position 136 of the array 124. The positions 136 may, for example, be given in x, y, and optionally z coordinates, where other coordinate systems may also be used. Herein, the components 122 may be positioned individually (e.g., one after the other in a sequence of consecutive assignment actions 134 during which one after the other of the components 122 are “placed” or assigned onto a respective position 136 of the array 124 until all the components 122 are assigned to the array 124). The sequence of consecutive assignment actions 134 may be described or characterized by the model 132, which incorporates the above-mentioned and provided array 124, list 126, and respective feature information 130. The model 132 may, for example, be understood as a policy network modelling the action of placing a component 122 from the list 126 onto the array 124.

[0039] In some examples, the model 132 may be rather simple and may, for example, involve clustering components 122 by starting to assign the components 122 that are electrically interconnected (e.g., directly) in the vicinity of these electrically interconnected (e.g., directly) components 122, before positioning the connections 128 of these electrically interconnected (e.g., directly) components 122. By way of example, the model 132 may take202400525 8 into account electrically interconnected components 122 by assigning a certain preference value to proximately positioned, electrically interconnected components 122. Since, in many examples, competing requirements are to be complied with, the model 132 may help to make a selection using the preference values and satisfy, for example, the most important of the competing requirements when creating the layout 140. More advanced models 132 and how the more advanced models 132 may be obtained are explained in more detail below.

[0040] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine a respective probability distribution 138 for assigning one of the components 122 onto a respective position 136 of the array 124 using the model 132.

[0041] The model 132 may then be used to determine a respective probability distribution 138 for assigning one of the components 122 onto a respective position 136 of the array 124. Herein, the probability distribution 138 may, in some examples, be understood to achieve a normalization to values between 0 and 1. Hence, for an individual assigning action 134 of assigning one of the components 122 onto a respective position 136 of the array 124, a respective assigning probability may be determined for each position 136 of the array 124. Thus, a probability distribution 138 may be determined for each assigning action 134 covering the complete array 124, such that the probability of assigning the respective component 122 is determined for each position 136 of the array 124.

[0042] Herein, in some examples, the respective probability distribution 138 may be expressed using the above-mentioned board canvas: the sequence of consecutively assigned components 122 on the array 124 may be expressed with a corresponding sequence of step canvases, where for each assigning action 134 (and the previously already assigned components 122), a corresponding step canvas may be provided. The respective canvas has the array 124, where a probability from the respective probability distribution 138 is assigned to each position of the array 124 of the respective canvas. Hence, for each assigning action 134, there may be an individual board canvas with an individual array 124. The probability distribution 138 for this assigning action 134 is mapped to the positions 136 of this array 124.

[0043] By way of example, there may be positions 136 of the array 124 with a comparably small assigning probability (e.g., since the component 122 to be assigned is remote from electrically interconnected components 122), and there may be positions 136 of the array 124 with a comparably high assigning probability (e.g., since the component 122 to be assigned is in the vicinity of electrically interconnected components 122). The probability distribution 138 may, for example, be understood as a sort of heat map, where “hot” areas of the array202400525 9 124 indicate positions 136 with a comparably high assigning probability with respect to the respective component 122, whereas “cold” areas of the array 124 indicate positions 136 with a comparably low assigning probability with respect to the respective component 122. In this context, the respective heat map for the individual assigning action 134 or component 122 may be expressed using the above-explained respective canvas and the corresponding array 124.

[0044] In some examples, the application software component 106 and / or the processor 102 may further be configured to compose the layout 140 of the components 122 on the array 124 using the respective assigning action 134 with the highest respective probability in the respective probability distribution 138.

[0045] The layout 140 of the components 122 may be obtained by carrying out the sequence of consecutive assigning actions 134 until all the components 122 are assigned to a respective position 136 of the array 124. To determine the respective, individual assigning action 134, the determined respective probability distribution 138 may be used as follows: for each action 134 of assigning one of the components 122 onto a respective position 136 of the array 124, the respective assigning action 134 with the highest respective probability in the respective probability distribution 138 may be used. Hence, each component 122 may, for example, be assigned to one of the positions 136 of the array 124 according to the respective assigning action 134 with the highest respective probability. This may, for example, be understood as composing the layout 140 of the PCB 120 step-by-step or from one layout state to the next layout state, where for each step, only the most likely next state of the layout 140 is considered.

[0046] Herein, in some examples, this procedure may be done consecutively for each of the components 122 to determine the respective, suitable position 136 of the array 124 to which the respective component 122 is to be assigned. In other examples, this procedure may be done consecutively for each of the positions 136 of the array 124 to determine the respective, suitable component 122 that is to be assigned to the respective position 136.

[0047] After the sequence of consecutive assigning actions 134 has been determined and the components 122 have been assigned to a respective position 136 of the array 124, the layout 140 of the PCB 120 is complete. Since only the highest respective probability is considered for assigning the respective component 122 onto a respective position 136 of the array 124, only one layout 140 is obtained. If, in some examples, for one specific assigning action 134 there are two positions 136 with the highest respective probability in the respective probability distribution 138, one of these two positions 136 may be selected randomly or202400525 10 according to pre-configurable assignment rules (e.g., the physical properties explained below).

[0048] In some examples, the layout 140 of both the components 122 and the connections 128 on the array 124 may be determined using the respective assigning action 134 with the highest respective probability in the respective probability distribution 138.

[0049] By way of example, the application software component 106 and / or the processor 102 may further be configured to output the composed layout 140.

[0050] The composed layout 140 may then, for example, be output to a user or an engineer (e.g., via the PCB layout UI 116 that may be displayed to the user on the display device 112). In further examples, the composed layout 140 may additionally or alternatively be output to another device that is communicatively connected with the PCB layout system 118. Such further examples are explained in more detail below.

[0051] In further examples, the application software component 106 and / or the processor 102 may further be configured to: use the provided array 124 as a step canvas with a height H and a width W, on which the components 122 may be arranged; and to update the step canvas after the respective assigning action 134 of one of the components 122.

[0052] As already mentioned above, the sequence of consecutively assigned components 122 on the array 124 may be expressed with a corresponding sequence of step canvases, where for each assigning action 134 (and the previously already assigned components 122), a corresponding step canvas may be provided. The array 124 and accordingly the step canvas may have the height H and the width W that are available for positioning or assigning the components 122. In some examples, other geometries (e.g., other than a rectangular shape) may be reflected by the step canvas. In further examples, three-dimensional arrays 124 may be used further including a thickness besides the height H and the width W.

[0053] After each action 134 of assigning one of the components 122 onto a respective position 136 of the array 124 or the step canvas (e.g., according to the highest respective probability in the respective probability distribution 138), the step canvas may be updated so that the assigned component 122 is properly reflected by the updated step canvas.

[0054] In more mathematical terms, the array 124 and accordingly the step canvas may be atwo-dimensional array ^^ ∈ ℕுஸ^ൈ^of height H and width W, with ℕஸ^ ൌ ^^^ | ^^ ∈ ℕ, ^^ ^ ^^^,representing the boardevery step. Here, ^^ indicatesof components 122. A cell ^^^,^stores the type identification (ID) number of the occupying component 122, or 0 ifno component 122 is placed at coordinate ^^^, ^^^, which corresponds to the position 136. A202400525 11 corresponding expression of the array 124 may be used for three-dimensional arrays 124.

[0055] By way of example, the application software component 106 and / or the processor 102 may further be configured to provide the list 126 as a graph representing the respective component 122 and the respective connection 128 of the respective component 122.

[0056] Herein, a graph may be understood to be a structure amounting to a set of objects in which some pairs of the objects are in some sense "related". The objects correspond to mathematical abstractions referred to as vertices (e.g., nodes or points), and each of the related pairs of vertices is referred to as an edge (e.g., link or line). A graph may be depicted in diagrammatic form as a set of dots or circles for the vertices, joined by lines or curves for the edges.

[0057] In the context of the present embodiments, the nodes of the graph may correspond to the components 122 or optionally to the nets or net nodes. As already mentioned above, net nodes may be of the types: ground, power (e.g., 24 volts), etc., where a net may be understood as the electrically interconnected components 122 and their connections 128. Further, the edges of the graph may correspond to the connections 128 that electrically connect the components 122 and optionally the nets or net nodes. Hence, the elements of the list 126 may be represented by the mentioned graph.

[0058] As already mentioned above, the list 126 may be known in an EDA context as netlist, which may, for example, include the design schematic of all electrical component connections via nets. Hereby, the mentioned schematic is not to be confused with the layout 140 of the PCB 120. The list 126 or the netlist may be represented as an undirected GraphG ൌ ^V, E^, where V is a set of all required components 122 and nets, and E is a set ofconnections 128 between the components and nets. While a netlist may naturally correspond to a hypergraph, the netlist may, in many examples, be transformed into a bipartite graph between component nodes and net nodes.

[0059] In some examples, the feature information 130 may include respective information on the type, the shape, or the characteristics of the respective component 122 and / or of the respective connection 128, respectively.

[0060] The mentioned type may, for example, indicate whether the respective component 122 is a resistance, a capacitor, a transistor, a battery, a net node, a ground potential, or an electrical potential of a certain voltage (e.g., 24 volts), as already mentioned above. Further, the mentioned type may, for example, indicate whether the respective connection 128 is signal connection or a power connection that is suitable for larger electric currents or electric voltages than a signal connection. The respective shape may indicate the size of the202400525 12 respective component 122 or the respective connection 128, for example, in terms of geometric dimensions. The mentioned characteristics may, for example, include electric, thermal, physical, or chemical properties of the respective component 122 or the respective connection 128, such as generated dissipation heat or electromagnetic radiation or interference during the operation of the respective component 122 or the respective connection 128. Herein, in some examples, net nodes may have types, such as ground, power 24 volt, etc., but no placement or shape.

[0061] Further, as already mentioned above, the feature information 130 may optionally further include, in some examples, information on the placement if the component 122 is already placed (e.g., the feature information 130 may include a position 136 to which a certain component 122 or connection 128 has already been assigned beforehand).

[0062] The application software component 106 and / or the processor 102 may, for example, further be configured to provide the feature information 130 as a two-dimensional feature array, where a respective vector of the feature array is assigned to the respective node of the graph and where the respective vector includes the respective information on the type, the shape, or the characteristics of the respective component 122.

[0063] The two-dimensional feature array may, for example, have the form ^^ ∈ ℝ^ൈ^, withN ൌ |V|, where V is the above-mentioned set of all required components 122 and nets. Forevery node in the graph G, a d-dimensional vector of values further characterizing the components and nets (e.g., its shape (such as height and width) and its (appropriately encoded) type (such as resistor, capacitor, battery, etc.), an optional placement (the position 136 if the component 122 is already placed), and other characteristics) is provided. Herein, d may be one if the feature information 130 is directly assigned to the respective node of the graph G, or d may be, for example, three if the feature information 130 is sub-divided in its potential contributions type, shape, and other characteristics.

[0064] In further examples, the application software component 106 and / or the processor 102 may further be configured to transform the model 132 into a factored probability distribution 138, where the factored probability distribution 138 includes for each assigning action 134: a factor for the respective component 122; a factor for a x-coordinate in the array 124; and a factor for a y-coordinate in the array 124. The application software component 106 and / or the processor 102 may further be configured to identify the factored probability distribution 138 to be the respective probability distribution 138 for assigning one of the components 122 onto a respective position 136 of the array 124.202400525 13

[0065] In some examples, the model 132 may be expressed by a policy network modelling the assigning action 134 of placing a component 122 from the list 126 onto the array 124. If the policy with which the model 132 is expressed is denoted with π, the assigning action 134 is denoted with ^^௧, and the state of the canvas or the array 124 at a given step t is denoted with ^^௧, then the policy π^^^௧|^^௧^ may first be expressed as a respective probabilitydistribution 138 denoted with P at state or step ^^௧ as follows: π ^^^௧; ^^௧^ ൌ ^^^^^^^^^^^௧, ^^௧,^^௧^.Then, the policy may be simplified to a factored (e.g., auto-regressive) probability distribution 138: ^^^^^௧; ^^௧^ ൌ ^^^^^^^^^^^௧, ^^௧,^^௧^ ൌ ^^^^^^^^^^^௧^ ^^^^^௧^ ^^^^^௧^.

[0066] Herein, ^^^^^^^^^^^௧^ denotes the factor for the respective component 122 (or node, as explained above), ^^^^^௧^ denotes the factor for an x-coordinate in the array 124, and ^^^^^௧^ denotes the factor for a y-coordinate in the array 124, for the assigning action 134 or the state ^^௧.of the canvas or the array 124 at a given step t. If three-dimensional arrays 124 are used, the policy may, for example, be simplified to a factored (e.g., auto-regressive) probability distribution 138 including an additional factor ^^^^^௧^for a z-coordinate in the array 124: ^^^^^௧; ^^௧^ ൌ ^^^^^^^^^^^௧ , ^^௧ ,^^௧ , ^^௧^ ൌ ^^^^^^^^^^^௧^ ^^^^^௧^ ^^^^^௧^^^^^^௧^.

[0067] The factorization of the respective probability distribution 138 may, in some examples, allow for a considerable reduction of the dimensions of the involved space and thus contributes to boost efficiency when creating the layout 140 of a PCB 120 including electrical components 122. Herein, the mentioned factorization of the respective probability distribution 138 may, for example, be possible thanks to sequencing the assignment of the components 122 and the connections 128 to the array 124 instead of assigning all of the plurality of the components 122 and the connections 128 to the array 124 in one step. However, the mentioned sequencing of the assignments does not necessarily involve drawbacks since the sequencing is in practice (e.g., when producing the PCB) not required or actually carried out. Rather, the mentioned sequencing of the assignments is a tool to allow the mentioned factorization and to benefit from the reduction of the dimensions of the involved space. Further, by way of example, the mentioned factorization may make the incorporation of action masking possible. This increased efficiency may be achieved, for202400525 14 example, since considerably less computational and memory resources are required for the processor 102 to carry out the suggested method. In some examples, especially for large arrays with many components 122 or complex connections 128, the layout 140 may, for the first time ever, be created, for example, without human expert engineers.

[0068] By way of example, each factor may depend on the array 124, the graph, and the feature array, respectively.

[0069] Hence, the policy (e.g., with which the model 132 is expressed), the respective probability distribution 138, and the factored (e.g., auto-regressive) probability distribution 138 may be expressed as follows: ^^^^^௧|^^௧^ ൌ ^^^^^^^^^^^௧ , ^^௧ , ^^௧ |^^௧ ,^^ ,^^௧^ൌ ^^^^^^^^^^^௧ |^^௧ ,^^ ,^^௧^ ^^^^^௧ |^^^^^^^^,^^௧ ,^^ ,^^௧^ ^^^^^௧ |^^,^^^^^^^^,^^௧ ,^^ ,^^௧^

[0070] Herein, C denotes the above-mentioned two-dimensional array 124, G denotes the graph, and X denotes the two-dimensional feature array. Accordingly, thanks to the factorization of the respective probability distribution 138, the size of the action space is dramatically reduced from N×H×W to N+H+W. Herein, as mentioned above, N=|V|, where V is the above-mentioned set of all required components 122 and nets, and H and W are the height H and a width W of the array 124 or step canvas, on which the components 122 may be arranged. This dramatic reduction of the space size allows for a tremendous efficiency boost when creating the layout 140 of a PCB 120 including electrical components 122. If three-dimensional arrays 124 are used, the factorization of the respective probability distribution 138, may, for example, reduce the size of the action space N×H×W×T to N+H+W+T, where T denotes the above-mentioned thickness of the array 124.

[0071] In some examples, if artificial intelligence (AI) models are used in this context, and if θ denotes the number of parameters to be trained of the respective AI model, the policy (e.g., with which the model 132 is expressed), the respective probability distribution 138, and the factored (e.g., auto-regressive) probability distribution 138 may be expressed as follows: ^^ఏ^^^௧|^^௧^ ൌ ^^^^^^^^^^^௧ , ^^௧ ,^^௧ |^^௧ ,^^ ,^^௧;^^^ൌ ^^^^^^^^^^^௧ |^^௧,^^ ,^^௧;^^^ ^^^^^௧ |^^^^^^^^,^^௧,^^ ,^^௧;^^^ ^^^^^௧ |^^, ^^^^^^^^,^^௧,^^ ,^^௧;^^^202400525 15

[0072] By way of example, the architecture may include a number of neural networks that may partly be depicted in Figures 2 to 4. For the input graph G and 2-dimensional array X, a GNN Encoder (e.g., a graph neural network (GNN) to encode the netlist and component (node) features into a latent space) is provided. This may involve a transformation from the graph space to a vector space that is a reduced state space with adequately adjusted weights of the GNN. For the input 2-dimensional array 124 “C”, “Conv” (e.g., a convolutional neural network (CNN) to encode the spatial information of placed components into latent space) is provided. This may involve a transformation of the two-dimensional input into a vector space that is a reduced state space with adequately adjusted weights of the CNN. For “De-conv”, a CNN is also provided but with transposed (e.g., De-convolutions) to restore the original canvas shape in latent space. This may involve a corresponding back transformation or inverse transformation. For Node action layer, this may be a simple feed-forward multi-layer perceptron (MLP) or dot-product between node embeddings and the pooled canvas representation. A node mask assigns 0-probability to already placed components or other non-placeable components. For X Action layer, feed-forward MLP or a dot-product between the sampled node embedding and the y-pooled canvas representation is provided. The X mask assigns 0-probability to X coordinates that may never fit the sampled node (e.g., component), regardless of y location. For Y Action layer, feed-forward MLP or dot-product of sampled node embeddings is provided, with the sampled x canvas embedding and the X- pooled canvas representation as inputs. The Y mask assigns 0-probability to Y coordinates, which cannot fit the sampled node (e.g., component) and sampled x.

[0073] If three-dimensional arrays 124 are used in some examples, a corresponding Z Action layer may be added.

[0074] In some examples, the application software component 106 and / or the processor 102 may further be configured to: provide a training layout 144 including a training array 124 of a training board canvas, a training list 126 of the components 122 and of the electrical connections 128 of the components 122 of the training layout 144, and training feature information 130 of the respective component 122 and of the respective connection 128 of the training layout 144; determine a respective training probability distribution 138 for assigning one of the components 122 onto a respective position 136 of the training array 124 using the model 132; compose a testing layout 140 of the components 122 on the training array 124 using the respective assigning action 134 with the highest respective probability in the respective training probability distribution 138; assign a reward 142 to the determined,202400525 16 respective assigning action 134, if the determined, respective assigning action 134 complies with pre-configurable boundary conditions; and update the model 132 using the assigned reward 142.

[0075] The suggested update of the model 132 may, for example, be understood as a training procedure of the model 132. To this end, a training layout 144 (e.g., a layout 140 of an already developed or produced PCB 120) may be provided. The training layout 144 may, for example, be developed by an experienced engineer with or without other EDA tools. The training layout 144 may include, explicitly or implicitly, the training array 124, the training list 126, and the training feature information 130. If the training layout 144 does not include this information explicitly, an analysis may be done to derive this information from the provided training layout 144.

[0076] To carry out the training procedure, the training array 124, the training list 126, and the training feature information 130 may be used along with the model 132 to be trained, where a respective training probability distribution 138 may be determined, and a testing layout 140 may be composed analogously to the above-described method steps of the suggested creation of the layout 140 of the PCB 120.

[0077] The composed testing layout 140 may then be compared with the training layout 144, where a reward 142 may be assigned to a respective assigning action 134 that has been determined during the training procedure if the respective assigning action 134 complies with pre-configurable boundary conditions. Herein, the pre-configurable boundary conditions may, for example, incentivize favorable assigning actions 134 or a favorable testing layout 140 that has been determined or composed during the training procedure. Hence, the reward 142 may be assigned to either the individual assignment actions 134 or the overall placement (e.g., the resulting testing layout 140) to further guide the policy of the agents.

[0078] The respective reward may then be used to improve and update the model 132 so that the updated model 132, for example, makes the respective, rewarded assigning action 134 more likely (e.g., by attributing an increased probability to this assigning action 134).

[0079] In some examples, the provided training layout 144 may include only the final training layout 144, whereas in other examples, the provided training layout 144 may further include the sequence of assignment actions 134 that leads to the provided training layout 144. In the latter example, the training data may include of a set of observed sequences (e.g., episodes) where each sequence may correspond to a chain of component placements over time. Then, each episode in terms of a Markov decision process may be modelled starting from the initial observation with an empty step canvas (e.g., Step 0) and a given netlist and202400525 17 the component features (e.g., the feature information 130). At each step, an action may be sampled from the policy until either a maximum number of steps is reached or no more components 122 may be placed.

[0080] The mentioned training procedure may focus on learning of expert behavior from existing layouts 144 (e.g., PCB layout designs (placements)), but may be extended without modifications of the policy to other forms of feedback, such as simulation key performance indices (KPIs).

[0081] By way of example, the pre-configurable boundary conditions may relate to physical properties of the respective assigned component 122 and / or the plurality of assigned components 122, and / or the pre-configurable boundary conditions may relate to the agreement of the composed testing layout 140 with the training layout 144.

[0082] Herein, the physical properties may include electric, thermal, or other physical properties of the respective component 122 or the plurality of assigned components 122, so that the physical properties of the complete, composed layout 140 may also be, in some examples, relevant to the decision of assigning the mentioned reward 142. By way of example, favorable thermal properties, a reduced heat dissipation during the operation, or reduced electromagnetic radiation or interference during the operation may be included in the mentioned physical properties so that the model 132 may be trained and improved in this respect. Hence, for example, a reward 142 may be computed based on the electrical and thermal conductivity of the placements.

[0083] In some examples, the model 132 may be trained and improved to achieve best agreement of the testing layout 140 that has been composed during the training procedure with the provided training layout 144. Herein, the training layout 144 may, for example, be understood as (e.g., human) ground-truth designs or layouts 144 of the PCB 120.

[0084] In further example, the plurality of components 122 may include at least one net node, where the pre-configurable boundary conditions may relate to a distance of the components 122 connected to the same net node.

[0085] According to this aspect of the present embodiments, a simple surrogate reward for an optimal placement is suggested. For example, the Euclidean distance of all components 122 that are connected to the same net is suggested. In an optimal placement, this may beminimized. Given the list of all net nodes ^^ே^௧, for every ^^^^௧^ ∈ ^^ே^௧, first, a fullyconnected graph ^^^^௧^between all components connected to ^^^^^^^may be created. Each edge in this graph may be weighted with the Euclidean distance of the component placements.202400525 18 Then ^^^^௧^may be used to find its minimum spanning tree (MST) ^^^^^^^^௧^. The reward 142 may then be the sum of all edge weights of the MST. For example, the reward 142 for ^^^^^^^would be calculated as: ^^^^^^^^^^^^^^௧^ ൌ ^ ‖^^^^^^^^^^^^^^^^^^^^^^ െ ^^^^^^^^^^^^^^^^^^^^^^‖ଶ ^௨,௩^ ∈ ெௌ

[0086] The(e.g., trust- region policy optimization (TRPO) or proximal policy optimization (PPO)).

[0087] In some examples, the application software component 106 and / or the processor 102 may further be configured to transmit the composed layout 140 to a PCB manufacturing machine 150 (e.g., for manufacturing one or more PCBs 120 according to the transmitted, composed layout 140 or for preparing such a manufacture).

[0088] In further examples, the application software component 106 and / or the processor 102 may further be configured to cause the PCB manufacturing machine 150 to manufacture one or more PCBs 120 according to the transmitted, composed layout 140.

[0089] The described application software component 106 and / or the processor 102 may carry out an analogous method of creating a layout 140 of a PCB 120 including electrical components 122. Further, a computer-readable medium 160 that may include a computer program product 162 is shown in Figure 1, where the computer program product 162 may be encoded with executable instructions that, when executed, cause the computer system 100 and / or the app development platform 118 to carry out the described method.

[0090] In the present patent document, a reinforcement learning-based PCB component placement system may be suggested that may both be trained to imitate human expert placement, as well as additional reward signals that indicate the quality of the placement (e.g., KPIs derived from thermal or electrical properties listed above). The system may include a novel policy network architecture and training procedure.

[0091] The main aspects may, for example, include: a trainable policy that encodes the PCB Netlist, Board Canvas, and Component Features; an efficient policy learning via factored action space, reducing the exploration and making it possible to scale to large board sizes and number of components; and an efficient policy learning via action masking (e.g., unavailable or constrained placements may be easily incorporated; and a possibility to learn from expert placements, where the approach may also be extensible to other forms of feedback / reward202400525 19 (e.g., temperature, wiring KPIs, etc.).

[0092] These aspects may, for example, lead to: a more efficient PCB layout and design process; an increased efficiency in disseminating product engineering knowledge across an organization (e.g., thanks to the usage of design examples created by experienced engineers as training data); and a potential decrease in costs associated with a trial-and-error approach to PCB design, where an iteration of a design needs to be physically manufacturer for testing purposes.

[0093] In further examples, the architecture (e.g., the model 132) is also open for further incorporation of constraints (e.g., minimum distance between certain types of components 122).

[0094] Figures 2 to 4 depict a flow diagram of a first to third aspect of an example PCB layout process that may, for example, be performed by the first example system 100.

[0095] The list 126 of the components 122 and of the electrical connections 128 of the components 122, and the feature information 130 of the respective component 122 and of the respective connection 128 are provided. Further, a suitable array 124 or step canvas (e.g., depicted in Figures 2 to 4 as “Step Canvas”) is provided.

[0096] This information may be input into the policy network or model 132, which includes a GNN Encoder, Conv, and De-Conv, as depicted in Figures 2 to 4. Herein, as already mentioned above, the architecture may include a number of neural networks that may partly be depicted in Figures 2 to 4. For the input graph G and 2-dimensional array X, a GNN Encoder (e.g., a graph neural network (GNN) to encode the netlist and component (node) features into a latent space) may be provided. This may involve a transformation from the graph space to a vector space that is a reduced state space with adequately adjusted weights of the GNN. For the input 2-dimensional array 124 “C”, “Conv” (e.g., a convolutional neural network (CNN) to encode the spatial information of placed components into latent space) may be provided. This may involve a transformation of the two-dimensional input into a vector space that is a reduced state space with adequately adjusted weights of the CNN. For “De-conv”, a CNN may also be provided but with transposed (e.g., De-convolutions) to restore the original canvas shape in latent space. This may involve a corresponding back transformation or inverse transformation.

[0097] The model may then be transformed into a factored probability distribution 138, where the factored probability distribution 138 includes, for each assigning action 134, a factor for the respective component 122 or node, depicted in Figure 2 as “Node Action Layer” making a first contribution to the assigning action 134. The Node action layer may,202400525 20 for example, be a simple feed-forward multi-layer perceptron (MLP) or dot-product between node embeddings and the pooled canvas representation. A node mask assigns 0-probability to already placed components 122 or other non-placeable components 122. A factor for an x- coordinate in the array 124 is depicted in Figure 3 as “X Action Layer” making a second contribution to the assigning action 134.

[0098] The X Action layer may, for example, be a feed-forward MLP or a dot-product between the sampled node embedding and the y-pooled canvas representation. The X mask assigns 0-probability to X coordinates that may never fit the sampled node (e.g., component 122), regardless of y location. A factor for a y-coordinate in the array 124 is depicted in Figure 4 as “Y Action Layer” making a third contribution to the assigning action 134. The Y Action layer may, for example, be a feed-forward MLP or dot-product of sampled node embeddings, the sampled x canvas embedding, and the X-pooled canvas representation as inputs. The Y mask assigns 0-probability to Y coordinates that cannot fit the sampled node (e.g., component 122) and sampled x.

[0099] If three-dimensional arrays 124 are used in some examples, a corresponding Z Action layer may be added.

[0100] Figure 5 depicts a functional block diagram of a second example system 100 that facilitates creating a layout 140 of a PCB 120 including electrical components 122 in a product system 100.

[0101] In the second example system 100, the model 132 may be trained with a training layout 144, where a reward 142 may be assigned to the determined, respective assigning action 134 if the determined, respective assigning action 134 complies with pre-configurable boundary conditions. The model 132 may then be updated using the assigned reward 142, as explained in more detail above and explained in another example in the context of Figure 6.

[0102] Figure 6 depicts a flow diagram of a training procedure relating to the example PCB layout process that may, for example, be performed by the first example system 100 or the second example system 100.

[0103] For the training procedure, a training layout 144 including a training list 126 of the components 122 and of the electrical connections 128 of the components 122 of the training layout 144, and training feature information 130 of the respective component 122 and of the respective connection 128 of the training layout 144 are provided. Further, a suitable training array 124 or step canvas (e.g., depicted in Figure 6 as “Step 0 Canvas”) are provided.

[0104] In step 1, this information may be input into the policy network or model 132 that may then determine a training probability distribution 138 for assigning one of the202400525 21 components 122 onto a respective position 136 of the training array 124 using the model 132. The assigning action 134 with the highest probability in the probability distribution 138 is selected, and the canvas or array 124 is updated accordingly by assigning the respective component 122 to the determined position 136 to obtain the “Step 1 Canvas” or array 124’ as depicted in Figure 6.

[0105] Further, a comparison may be done with the training layout 144 (e.g., depicted in Figure 6 as “Ground-truth Placement”) to deduce a reward 142, where “IOU” in Figure 6 stands for “intersection over union”. The reward 142 may be used to update the model 132.

[0106] In step 2 and the following steps until the final canvas (e.g., in step T) has been composed, the previous step canvas or array (e.g., for step 2: 124’) is used as input into the policy network or model 132 that may then determine a training probability distribution (e.g., for step 2: 138’) for assigning one of the components 122 onto a respective position (e.g., in step 2: 136’) of the training array 124 using the model 132. Again, the assigning action 134 with the highest respective probability in the probability distribution 138 is selected, and the canvas or array (e.g., for step 2: 124’) may be updated accordingly by assigning the respective component 122 to the determined position (e.g., in step 2: 136’) to obtain (e.g., for step 2) the “Step 2 Canvas” or array 124’’ as depicted in Figure 6.

[0107] Referring now to Figure 6, a methodology M that facilitates creating a layout of a PCB including electrical components in a product system is provided. The method may start at M02, and the methodology may include a number of acts carried out through operation of at least one processor.

[0108] These acts may include: an act M04 of providing an array of a board canvas of the PCB; an act M06 of providing a list of the components and of the electrical connections of the components; an act M08 of providing feature information of the respective component and of the respective connection; an act M10 of providing a model incorporating the array, the list, and the feature information, where the model describes a sequence of consecutive actions of assigning one of the components of the list onto a respective position of the array; an act M12 of determining a respective probability distribution for assigning one of the components onto a respective position of the array using the model; an act M14 of composing the layout of the components on the array using the respective assigning action with the highest respective probability in the respective probability distribution; and an act M16 of outputting the composed layout. At M18, the methodology may end.

[0109] The methodology M may include other acts and features discussed previously with respect to the computer-implemented method of creating a layout of a PCB including202400525 22 electrical components.

[0110] Figure 8 depicts a block diagram of a data processing system 1000 (e.g., also referred to as a computer system) in which an embodiment may be implemented, for example, as a portion of a product system, and / or other system operatively configured by software or otherwise to perform the processes as described herein. The data processing system 1000 may include, for example, the computer or IT system or data processing system 100 mentioned above. The data processing system depicted includes at least one processor 1002 (e.g., a CPU) that may be connected to one or more bridges / controllers / buses 1004 (e.g., a north bridge, a south bridge). One of the buses 1004, for example, may include one or more I / O buses such as a PCI Express bus. Also connected to various buses in the depicted example may include a main memory 1006 (RAM) and a graphics controller 1008. The graphics controller 1008 may be connected to one or more display devices 1010. In some embodiments, one or more controllers (e.g., graphics, south bridge) may be integrated with the CPU (on the same chip or die). Examples of CPU architectures include IA-32, x86-64, and ARM processor architectures.

[0111] Other peripherals connected to one or more buses may include communication controllers 1012 (e.g., Ethernet controllers, WiFi controllers, cellular controllers) operative to connect to a local area network (LAN), Wide Area Network (WAN), a cellular network, and / or other wired or wireless networks 1014 or communication equipment.

[0112] Further components connected to various busses may include one or more I / O controllers 1016 such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (e.g., connected to speakers and / or microphones). Various peripherals may be connected to the I / O controller(s) (e.g., via various ports and connections) including input devices 1018 (e.g., keyboard, mouse, pointer, touch screen, touch pad, drawing tablet, trackball, buttons, keypad, game controller, gamepad, camera, microphone, scanners, motion sensing devices that capture motion gestures), output devices 1020 (e.g., printers, speakers), or any other type of device that is operative to provide inputs to or receive outputs from the data processing system. Many devices referred to as input devices or output devices may both provide inputs and receive outputs of communications with the data processing system. For example, the processor 1002 may be integrated into a housing (e.g., a tablet) that includes a touch screen that serves as both an input and display device. Further, some input devices (e.g., a laptop) may include a plurality of different types of input devices (e.g., touch screen, touch pad, keyboard). Other peripheral hardware 1022 connected to the I / O controllers 1016 may include any type of device, machine, or component that is configured to communicate202400525 23 with a data processing system.

[0113] Additional components connected to various busses may include one or more storage controllers 1024 (e.g., SATA). A storage controller may be connected to a storage device 1026 such as one or more storage drives and / or any associated removable media, which may be any suitable non-transitory machine usable or machine-readable storage medium. Examples include nonvolatile devices, volatile devices, read only devices, writable devices, ROMs, EPROMs, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disk drives (CDs, DVDs, Blu-ray), and other known optical, electrical, or magnetic storage devices drives and / or computer media. Also, in some examples, a storage device such as an SSD may be connected directly to an I / O bus 1004 such as a PCI Express bus.

[0114] A data processing system in accordance with an embodiment of the present disclosure may include an operating system 1028, software / firmware 1030, and data stores 1032 (e.g., that may be stored on a storage device 1026 and / or the memory 1006). Such an operating system may employ a command line interface (CLI) shell and / or a graphical user interface (GUI) shell. The GUI shell permits multiple display windows to be presented in the graphical user interface simultaneously, with each display window providing an interface to a different application or to a different instance of the same application. A cursor or pointer in the graphical user interface may be manipulated by a user through a pointing device such as a mouse or touch screen. The position of the cursor / pointer may be changed, and / or an event, such as clicking a mouse button or touching a touch screen, may be generated to actuate a desired response. Examples of operating systems that may be used in a data processing system may include Microsoft Windows, Linux, UNIX, iOS, and Android operating systems. Also, examples of data stores include data files, data tables, relational database (e.g., Oracle, Microsoft SQL Server), database servers, or any other structure and / or device that is capable of storing data that is retrievable by a processor.

[0115] The communication controllers 1012 may be connected to the network 1014 (not a part of data processing system 1000) that may be any public or private data processing system network or combination of networks, as known to those of skill in the art, including the Internet. Data processing system 1000 may communicate over the network 1014 with one or more other data processing systems such as a server 1034 (e.g., also not part of the data processing system 1000). However, an alternative data processing system may correspond to a plurality of data processing systems implemented as part of a distributed system in which processors associated with a number of data processing systems may be in communication202400525 24 via one or more network connections, and may collectively perform tasks described as being performed by a single data processing system. Thus, when referring to a data processing system, such a system may be implemented across a number of data processing systems organized in a distributed system in communication with each other via a network.

[0116] Further, the term “controller” may be any device, system, or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software, or some combination of at least two of the same. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

[0117] In addition, data processing systems may be implemented as virtual machines in a virtual machine architecture or cloud environment. For example, the processor 1002 and associated components may correspond to a virtual machine executing in a virtual machine environment of one or more servers. Examples of virtual machine architectures include VMware ESCi, Microsoft Hyper-V, Xen, and KVM.

[0118] Those of ordinary skill in the art will appreciate that the hardware depicted for the data processing system may vary for particular implementations. For example, the data processing system 1000 in this example may correspond to a computer, workstation, server, PC, notebook computer, tablet, mobile phone, and / or any other type of apparatus / system that is operative to process data and carry out functionality and features described herein associated with the operation of a data processing system, computer, processor, and / or a controller discussed herein. The depicted example is provided for the purpose of explanation only and is not meant to imply architectural limitations with respect to the present disclosure.

[0119] Also, the processor described herein may be located in a server that is remote from the display and input devices described herein. In such an example, the described display device and input device may be included in a client device that communicates with the server and / or a virtual machine executing on the server through a wired or wireless network (e.g., which may include the Internet). In some embodiments, such a client device, for example, may execute a remote desktop application or may correspond to a portal device that carries out a remote desktop protocol with the server in order to send inputs from an input device to the server and receive visual information from the server to display through a display device. Examples of such remote desktop protocols include Teradici's PCoIP, Microsoft's RDP, and the RFB protocol. In such examples, the processor described herein may correspond to a virtual processor of a virtual machine executing in a physical processor of the server.

[0120] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system202400525 25 or component may be a process, a process executing on a processor, or a processor. Additionally, a component or system may be localized on a single device or distributed across several devices.

[0121] Also, as used herein, a processor corresponds to any electronic device that is configured via hardware circuits, software, and / or firmware to process data. For example, processors described herein may correspond to one or more (or a combination) of a microprocessor, CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit that is capable of processing data in a data processing system, which may have the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device.

[0122] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of data processing system 1000 may conform to any of the various current implementations and practices known in the art.

[0123] Also, the words or phrases used herein should be construed broadly, unless expressly limited in some examples. For example, the terms “comprise” and “comprise,” as well as derivatives thereof, provide inclusion without limitation. The singular forms “a”, “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term “or” is inclusive, providing and / or, unless the context clearly indicates otherwise. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may be to comprise, be comprised within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.

[0124] Also, although the terms “first,” “second,” “third,” and so forth may be used herein to describe various elements, functions, or acts, these elements, functions, or acts should not be limited by these terms. Rather, these numeral adjectives are used to distinguish different elements, functions, or acts from each other. For example, a first element, function, or act may be termed a second element, function, or act, and, similarly, a second element, function, or act may be termed a first element, function, or act, without departing from the scope of the202400525 26 present disclosure.

[0125] In addition, phrases such as “processor is configured to” carry out one or more functions or processes, may provide that the processor is operatively configured to or operably configured to carry out the functions or processes via software, firmware, and / or wired circuits. For example, a processor that is configured to carry out a function / process may correspond to a processor that is executing the software / firmware, which is programmed to cause the processor to carry out the function / process, and / or may correspond to a processor that has the software / firmware in a memory or storage device that is available to be executed by the processor to carry out the function / process. A processor that is “configured to” carry out one or more functions or processes, may also correspond to a processor circuit particularly fabricated or “wired” to carry out the functions or processes (e.g., an ASIC or FPGA design). Further, the phrase “at least one” before an element (e.g., a processor) that is configured to carry out more than one function may correspond to one or more elements (e.g., processors) that each carry out the functions, and may also correspond to two or more of the elements (e.g., processors) that respectively carry out different ones of the one or more different functions.

[0126] In addition, the term “adjacent to” may provide that an element is relatively near to but not in contact with a further element, or that the element is in contact with the further portion, unless the context clearly indicates otherwise.

[0127] Although example embodiments of the present disclosure have been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0128] None of the description in the present patent document should be read as implying that any particular element, step, act, or function is an essential element that must be included in the claim scope; the scope of patented subject matter is defined only by the allowed claims.

[0129] The elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present invention. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent. Such new combinations are to be understood as forming a part of the present specification.

[0130] While the present invention has been described above by reference to various202400525 27 embodiments, it should be understood that many changes and modifications can be made to the described embodiments. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and / or combinations of embodiments are intended to be included in this description.202400525 28 Reference Signs List 100 processing system 102 processor 104 memory 106 application software component 108 internal data store 110 input device 112 display device 114 graphical user interface (GUI) 116 PCB layout UI 118 PCB layout system 120 PCB 122 electrical components 124 array 126 list 128 electrical connections 130 feature information 132 model 134 assigning action 136 position 138 probability distribution 140 layout 142 reward 144 ground-truth 150 PCB manufacturing machine 160 computer-readable medium 162 computer program product

Claims

202400525 29 Claims 1. A computer-implemented method for creating a layout of a printed circuit board (PCB) comprising a plurality of electrical components, the plurality of electrical components being electrically connected, the computer-implemented method comprising: providing an array of a board canvas of the PCB; providing a list of components and electrical connections of the components; providing feature information of a respective component of the components and of a respective electrical connection of the electrical connections; providing a model incorporating the array, the list, and the feature information, wherein the model describes a sequence of consecutive actions of assigning one of the components of the list onto a respective position of the array; determining a respective probability distribution for assigning one of the components onto a respective position of the array using the model; composing the layout of the components on the array using the respective assigning action with a highest respective probability in the respective probability distribution; and outputting the composed layout.

2. The computer-implemented method of claim 1, further comprising: using the provided array as a step canvas with a height H and a width W, on which the components may be arranged; and updating the step canvas after the respective assigning action of one of the components.

3. The computer-implemented method of any of the preceding claims, further comprising: providing the list as a graph representing the respective component and the respective electrical connection of the respective component.

4. The computer-implemented method of any of the preceding claims, wherein the feature information includes respective information on a type, a shape, or characteristics of the respective component, the respective connection, or the respective component and the respective connection.202400525 30 5. The computer-implemented method of claims 3 and 4, further comprising: providing the feature information as a two-dimensional feature array, wherein a respective vector of the two-dimensional feature array is assigned to a respective node of the graph, and wherein the respective vector includes the respective information on the type, the shape, or the characteristics of the respective component.

6. The computer-implemented method of any of the preceding claims, further comprising: transforming the model into a factored probability distribution, wherein the factored probability distribution includes, for each assigning action: a factor for the respective component; a factor for a x-coordinate in the array; and a factor for a y-coordinate in the array; and identifying the factored probability distribution to be the respective probability distribution for assigning one of the components onto a respective position of the array.

7. The computer-implemented method of claim 6, wherein each factor depends on the array, the graph, and the feature array, respectively.

8. The computer-implemented method of any of the preceding claims, further comprising: providing a training layout including a training array of a training board canvas, a training list of the components and the electrical connections of the components of the training layout, and training feature information of the respective component and of the respective connection of the training layout; determining a respective training probability distribution for assigning one of the components onto a respective position of the training array using the model; composing a testing layout of the components on the training array using the respective assigning action with the highest respective probability in the respective training probability distribution;202400525 31 assigning a reward to the determined, respective assigning action, when the determined, respective assigning action complies with pre-configurable boundary conditions; and updating the model using the assigned reward.

9. The computer-implemented method of claim 8, wherein the pre-configurable boundary conditions relate to physical properties of the respective assigned component, the assigned components, or the respective assigned component and the assigned components, and / or the pre-configurable boundary conditions relate to agreement of the composed testing layout with the training layout.

10. The computer-implemented method of claim 8 or 9, wherein the components include at least one net node, and wherein the pre-configurable boundary conditions relate to a distance of the components connected to a same net node of the at least one net node.

11. The computer-implemented method of any of the preceding claims, further comprising: transmitting the composed layout to a PCB manufacturing machine.

12. The computer-implemented method of claim 11, further comprising: causing the PCB manufacturing machine to manufacture one or more PCBs according to the transmitted, composed layout.

13. A computer system arranged and configured to execute the steps of the computer- implemented method of any one of the preceding claims.

14. A computer program product, including computer program code that, when executed by a computer system, cause the computer system to carry out the method of one of the claims 1 to 12.

15. A computer-readable medium including a computer program product including computer program code that, when executed by a computer system, cause the computer system to carry out the method of one of the claims 1 to 12.

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