Pixel circuit, driving method, and display apparatus

Abstract

A pixel circuit, a driving method, and a display apparatus. The pixel circuit comprises a light-emitting element (E1), a driving circuit (10), a compensation control circuit (11), a first energy storage circuit (12), a second energy storage circuit (13) and a control circuit (14), wherein the control circuit (14) controls, under the control of a first control signal (CS1), a third node (N3) to connect to a control voltage end; the control voltage end is electrically connected to a fourth node (N4), or the control voltage end is a first reference voltage end (REF1); and the compensation control circuit (11) controls, under the control of a second control signal (CS2), a first node (N1) to connect to a second node (N2). During operation of the pixel circuit, a diode-connected mode can be used to perform threshold voltage compensation, so as to compensate for a threshold voltage of a driving transistor (TD).

Description

Pixel circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, and a display device. Background Art

[0002] Oxide TFTs (thin-film transistors) are increasingly being adopted in medium- and large-sized low-frequency products due to their lower leakage current and improved hysteresis resistance compared to LTPS (low-temperature polysilicon) TFTs. However, pixel circuits using n-type transistors for threshold voltage compensation via diode connections are particularly sensitive to parasitic capacitance, as data is written via capacitive coupling, making them prone to crosstalk.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a compensation control circuit, a first energy storage circuit, a second energy storage circuit, and a control circuit;

[0005] A first terminal of the driving circuit is electrically connected to a first node, a control terminal of the driving circuit is electrically connected to a second node, a first terminal of the first energy storage circuit is electrically connected to a third node, and a second terminal of the driving circuit is electrically connected to the light-emitting element via a fourth node, wherein the driving circuit is configured to drive the light-emitting element under control of a potential of the second node;

[0006] The second end of the first energy storage circuit is electrically connected to the second node, and the first energy storage circuit is used to store electrical energy;

[0007] A first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to the fourth node, and the second energy storage circuit is used to store electrical energy;

[0008] The control circuit is electrically connected to the first control terminal, the third node, and the control voltage terminal, respectively, and is configured to control the communication between the third node and the control voltage terminal under the control of a first control signal provided by the first control terminal; the control voltage terminal is electrically connected to the fourth node, or the control voltage terminal is a first reference voltage terminal;

[0009] The compensation control circuit is electrically connected to the second control terminal, the first node and the second node respectively, and is used to control the connection between the first node and the second node under the control of a second control signal provided by the second control terminal.

[0010] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0011] The first initialization circuit is electrically connected to the third control terminal, the first reference voltage terminal and the fourth node respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the fourth node under the control of a third control signal provided by the third control terminal.

[0012] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit;

[0013] The data writing circuit is electrically connected to the scan end, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scan signal provided by the scan end.

[0014] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0015] The second initialization circuit is electrically connected to the reset control terminal, the second reference voltage terminal and the second node respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the second node under the control of the reset control signal provided by the reset control terminal.

[0016] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit;

[0017] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0018] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit;

[0019] The second light emitting control circuit is electrically connected to the light emitting control terminal, the fourth node, and the first electrode of the light emitting element, respectively, and is used to control the fourth node to be connected to the first electrode of the light emitting element under the control of the light emitting control signal;

[0020] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0021] Optionally, the driving circuit includes a driving transistor;

[0022] A gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the fourth node.

[0023] Optionally, the driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor;

[0024] The first gate of the driving transistor is electrically connected to the second node, and the second gate of the driving transistor is electrically connected to the second electrode of the driving transistor, the first gate of the driving transistor or the DC voltage terminal;

[0025] A first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the fourth node.

[0026] Optionally, the driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; the pixel circuit further includes a third energy storage circuit and a third initialization circuit;

[0027] The first gate of the driving transistor is electrically connected to the second node; the first electrode of the driving transistor is electrically connected to the first node; and the second electrode of the driving transistor is electrically connected to the fourth node.

[0028] A first end of the third energy storage circuit is electrically connected to the second gate of the driving transistor, a second end of the third energy storage circuit is electrically connected to the fourth node, and the third energy storage circuit is used to store electrical energy;

[0029] The third initialization circuit is electrically connected to the fourth control terminal, the third reference voltage terminal and the second gate of the driving transistor respectively, and is used to write the third reference voltage provided by the third reference voltage terminal into the second gate of the driving transistor under the control of the fourth control signal provided by the fourth control terminal.

[0030] Optionally, the first control end and the fourth control end are the same control end.

[0031] Optionally, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the control circuit includes a first transistor, and the compensation control circuit includes a second transistor;

[0032] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the second node;

[0033] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node;

[0034] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the third node, and the second electrode of the first transistor is electrically connected to the control voltage terminal;

[0035] A gate of the second transistor is electrically connected to the second control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node.

[0036] Optionally, the first initialization circuit includes a third transistor;

[0037] The gate of the third transistor is electrically connected to the third control terminal, the first electrode of the third transistor is electrically connected to the first reference voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node.

[0038] Optionally, the data writing circuit includes a fourth transistor;

[0039] A gate of the fourth transistor is electrically connected to the scan end, a first electrode of the fourth transistor is electrically connected to the data line, and a second electrode of the fourth transistor is electrically connected to the third node.

[0040] Optionally, the second initialization circuit includes a fifth transistor;

[0041] A gate of the fifth transistor is electrically connected to the reset control terminal, a first electrode of the fifth transistor is electrically connected to the second reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

[0042] Optionally, the first light emitting control circuit includes a sixth transistor;

[0043] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node.

[0044] Optionally, the second light emitting control circuit includes a seventh transistor;

[0045] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0046] Optionally, the third energy storage circuit includes a third capacitor, and the third initialization circuit includes an eighth transistor;

[0047] A first end of the third capacitor is electrically connected to the second gate of the driving transistor, and a second end of the third capacitor is electrically connected to the fourth node;

[0048] The gate of the eighth transistor is electrically connected to the fourth control terminal, the first electrode of the eighth transistor is electrically connected to the third reference voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second gate of the driving transistor.

[0049] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit. The driving method includes:

[0050] The driving circuit drives the light emitting element under the control of the potential of the second node;

[0051] The control circuit controls the third node to be connected to the control voltage terminal under the control of the first control signal;

[0052] The compensation control circuit controls the connection between the first node and the second node under the control of the second control signal;

[0053] The pixel circuit further includes a first initialization circuit and a data writing circuit;

[0054] The display cycle includes a compensation phase and a data writing phase which are arranged in sequence; the driving method includes:

[0055] During the compensation phase, the compensation control circuit controls the first node and the second node to be connected under the control of the second control signal, the first initialization circuit writes the first reference voltage to the fourth node under the control of the third control signal, and the control circuit controls the third node to be connected to the control voltage terminal under the control of the first control signal;

[0056] In the data writing phase, the first initialization circuit writes the first reference voltage into the fourth node under the control of the third control signal, and the data writing circuit writes the data voltage into the third node under the control of the scan signal;

[0057] The display cycle further includes an initialization phase before the compensation phase, and the pixel circuit further includes a first initialization circuit and a second initialization circuit; the driving method further includes:

[0058] During the initialization stage, the first initialization circuit writes the first reference voltage into the fourth node under the control of the third control signal, and the control circuit controls the connection between the third node and the control voltage terminal under the control of the first control signal; the second initialization circuit writes the second reference voltage into the second node under the control of the reset control signal.

[0059] Optionally, the display cycle further includes a light emitting phase arranged after the data writing phase, and the pixel circuit further includes a first light emitting control circuit; and the driving method further includes:

[0060] In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first node under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

[0061] Optionally, the driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; the pixel circuit further includes a third energy storage circuit and a third initialization circuit;

[0062] The driving method may further include:

[0063] During the initialization phase and the compensation phase, the third initialization circuit writes a third reference voltage into the second gate of the driving transistor under the control of a fourth control signal.

[0064] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG14 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG13 ;

[0079] FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG. 21 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 20 . DETAILED DESCRIPTION

[0086] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0087] The pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a driving circuit, a compensation control circuit, a first energy storage circuit, a second energy storage circuit and a control circuit;

[0088] A first terminal of the driving circuit is electrically connected to a first node, a control terminal of the driving circuit is electrically connected to a second node, a first terminal of the first energy storage circuit is electrically connected to a third node, and a second terminal of the driving circuit is electrically connected to the light-emitting element via a fourth node, wherein the driving circuit is configured to drive the light-emitting element under control of a potential of the second node;

[0089] The second end of the first energy storage circuit is electrically connected to the second node, and the first energy storage circuit is used to store electrical energy;

[0090] A first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to the fourth node, and the second energy storage circuit is used to store electrical energy;

[0091] The control circuit is electrically connected to the first control terminal, the third node, and the control voltage terminal, respectively, and is configured to control the communication between the third node and the control voltage terminal under the control of a first control signal provided by the first control terminal; the control voltage terminal is electrically connected to the fourth node, or the control voltage terminal is a first reference voltage terminal;

[0092] The compensation control circuit is electrically connected to the second control terminal, the first node and the second node respectively, and is used to control the connection between the first node and the second node under the control of a second control signal provided by the second control terminal.

[0093] When the pixel circuit described in the embodiment of the present disclosure is in operation, threshold voltage compensation can be performed in a diode connection manner to achieve compensation of the threshold voltage of the driving transistor.

[0094] When the pixel circuit described in the embodiment of the present disclosure is in operation, by adjusting the ratio of the capacitance value of the capacitor included in the first energy storage circuit to the total capacitance at the second node, and adjusting the ratio of the capacitance value of the capacitor included in the second energy storage circuit to the total capacitance at the fourth node, when △VN3 is generated at the third node due to a jump in the voltage on the data line, due to the capacitive coupling effect, △VN4 can be made equal to △VN2, thereby keeping the gate-source voltage of the driving transistor unchanged and suppressing the current change of the light-emitting element, thereby effectively reducing crosstalk.

[0095] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1, a driving circuit 10, a compensation control circuit 11, a first energy storage circuit 12, a second energy storage circuit 13, and a control circuit 14;

[0096] A first terminal of the driving circuit 10 is electrically connected to a first node N1, a control terminal of the driving circuit 10 is electrically connected to a second node N2, a first terminal of the first energy storage circuit 12 is electrically connected to a third node N3, and a second terminal of the driving circuit 10 is electrically connected to the light-emitting element E1 via a fourth node N4. The driving circuit 10 is configured to drive the light-emitting element E1 under the control of the potential of the second node N2.

[0097] The second end of the first energy storage circuit 12 is electrically connected to the second node N2, and the first energy storage circuit 12 is used to store electrical energy;

[0098] A first end of the second energy storage circuit 13 is electrically connected to the third node N3, a second end of the second energy storage circuit 13 is electrically connected to the fourth node N4, and the second energy storage circuit 13 is used to store electrical energy;

[0099] The control circuit 14 is electrically connected to the first control terminal CS1, the third node N3, and a control voltage terminal, respectively. The control voltage terminal is electrically connected to the fourth node N4. The control circuit 14 is configured to control the communication between the third node N3 and the fourth node N4 under the control of a first control signal provided by the first control terminal CS1.

[0100] The compensation control circuit 11 is electrically connected to the second control terminal CS2, the first node N1 and the second node N2 respectively, and is used to control the connection between the first node N1 and the second node N2 under the control of a second control signal provided by the second control terminal CS2.

[0101] In at least one embodiment shown in FIG. 1 , the control voltage terminal is electrically connected to the fourth node N4 .

[0102] As shown in FIG2 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1, a driving circuit 10, a compensation control circuit 11, a first energy storage circuit 12, a second energy storage circuit 13 and a control circuit 14;

[0103] A first end of the driving circuit 10 is electrically connected to a first node N1, a control end of the driving circuit 10 is electrically connected to a second node N2, a first end of the first energy storage circuit 12 is electrically connected to a third node N3, and a second end of the driving circuit 10 is electrically connected to the light-emitting element E1 via a fourth node N4. The driving circuit 10 is configured to drive the light-emitting element E1 under the control of the potential of the second node N2.

[0104] The second end of the first energy storage circuit 12 is electrically connected to the second node N2, and the first energy storage circuit 12 is used to store electrical energy;

[0105] A first end of the second energy storage circuit 13 is electrically connected to the third node N3, a second end of the second energy storage circuit 13 is electrically connected to the fourth node N4, and the second energy storage circuit 13 is used to store electrical energy;

[0106] The control circuit 14 is electrically connected to the first control terminal CS1, the third node N3, and the first reference voltage terminal REF1, respectively. The control circuit 14 is configured to control the connection between the third node N3 and the first reference voltage terminal REF1 under the control of a first control signal provided by the first control terminal CS1. The first reference voltage terminal REF1 is configured to provide a first reference voltage Vref1.

[0107] The compensation control circuit 11 is electrically connected to the second control terminal CS2, the first node N1 and the second node N2 respectively, and is used to control the connection between the first node N1 and the second node N2 under the control of a second control signal provided by the second control terminal CS2.

[0108] In at least one embodiment shown in FIG. 2 , the control voltage terminal is a first reference voltage terminal.

[0109] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0110] The first initialization circuit is electrically connected to the third control terminal, the first reference voltage terminal and the fourth node respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the fourth node under the control of a third control signal provided by the third control terminal.

[0111] In a specific implementation, the pixel circuit may further include a first initialization circuit, which, under the control of a third control signal, writes the first reference voltage provided by the first reference voltage terminal into the fourth node, and the first electrode of the light-emitting element may be electrically connected to the fourth node to be able to clear the residual charge in the first electrode of the light-emitting element.

[0112] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 31 ;

[0113] The first initialization circuit 31 is electrically connected to the third control terminal CS3, the first reference voltage terminal REF1 and the fourth node N4 respectively, and is used to write the first reference voltage Vref1 provided by the first reference voltage terminal REF1 into the fourth node N4 under the control of the third control signal provided by the third control terminal CS3.

[0114] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 31 ;

[0115] The first initialization circuit 31 is electrically connected to the third control terminal CS3, the first reference voltage terminal REF1 and the fourth node N4 respectively, and is used to write the first reference voltage Vref1 provided by the first reference voltage terminal REF1 into the fourth node N4 under the control of the third control signal provided by the third control terminal CS3.

[0116] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit;

[0117] The data writing circuit is electrically connected to the scan end, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scan signal provided by the scan end.

[0118] In a specific implementation, the pixel circuit may further include a data writing circuit, and the data writing circuit writes the data voltage into the third node under the control of the scanning signal to perform data voltage writing.

[0119] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, the data voltage writing process and the threshold voltage compensation process can be separated to increase the duration of the threshold voltage compensation process, improve the threshold voltage compensation effect, and better adapt to the requirements of higher resolution and higher refresh rate.

[0120] Optionally, the duration of the threshold voltage compensation process may be set to be greater than 1H (1H is a row scan time), for example, 40H or 80H, but not limited thereto.

[0121] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 51 ;

[0122] The data writing circuit 51 is electrically connected to the scan terminal GT, the data line DT and the third node N3 respectively, and is used to write the data voltage Vdata provided by the data line DT into the third node N3 under the control of the scan signal provided by the scan terminal GT.

[0123] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG4 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 51 ;

[0124] The data writing circuit 51 is electrically connected to the scan terminal GT, the data line DT and the third node N3 respectively, and is used to write the data voltage Vdata provided by the data line DT into the third node N3 under the control of the scan signal provided by the scan terminal GT.

[0125] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0126] The second initialization circuit is electrically connected to the reset control terminal, the second reference voltage terminal and the second node respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the second node under the control of the reset control signal provided by the reset control terminal.

[0127] In a specific implementation, the pixel circuit may further include a second initialization circuit. Under the control of the reset control signal, the second initialization circuit writes a second reference voltage into the second node to initialize the potential of the second node.

[0128] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 71 ;

[0129] The second initialization circuit 71 is electrically connected to the reset control terminal R1, the second reference voltage terminal REF2 and the second node N2 respectively, and is used to write the second reference voltage Vref2 provided by the second reference voltage terminal REF2 into the second node N2 under the control of the reset control signal provided by the reset control terminal R1.

[0130] As shown in FIG8 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 71 ;

[0131] The second initialization circuit 71 is electrically connected to the reset control terminal R1, the second reference voltage terminal REF2 and the second node N2 respectively, and is used to write the second reference voltage Vref2 provided by the second reference voltage terminal REF2 into the second node N2 under the control of the reset control signal provided by the reset control terminal R1.

[0132] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit;

[0133] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0134] In a specific implementation, the pixel circuit may further include a first light emitting control circuit. Under the control of the light emitting control signal, the first light emitting control circuit controls the connection between the power supply voltage terminal and the first node to perform light emitting control.

[0135] As shown in FIG9 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 91 ;

[0136] The first light emitting control circuit 91 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal VDD and the first node N1 respectively, and is used to control the connection between the power supply voltage terminal VDD and the first node N1 under the control of the light emitting control signal provided by the light emitting control terminal EM.

[0137] As shown in FIG10 , based on at least one embodiment of the pixel circuit shown in FIG8 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 91 ;

[0138] The first light emitting control circuit 91 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal VDD and the first node N1 respectively, and is used to control the connection between the power supply voltage terminal VDD and the first node N1 under the control of the light emitting control signal provided by the light emitting control terminal EM.

[0139] In at least one embodiment of the present disclosure, the pixel circuit further includes a second light emitting control circuit;

[0140] The second light emitting control circuit is electrically connected to the light emitting control terminal, the fourth node, and the first electrode of the light emitting element, respectively, and is used to control the fourth node to be connected to the first electrode of the light emitting element under the control of the light emitting control signal;

[0141] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0142] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0143] In a specific implementation, the pixel circuit may further include a second light emitting control circuit, which controls the connection between the fourth node and the first electrode of the light emitting element under the control of the light emitting control signal to perform light emitting control.

[0144] As shown in FIG11 , based on at least one embodiment of the pixel circuit shown in FIG9 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit 111 ;

[0145] The second light emitting control circuit 111 is electrically connected to the light emitting control terminal EM, the fourth node N4, and the first electrode of the light emitting element E1, respectively, and is configured to control the fourth node N4 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal;

[0146] The second electrode of the light emitting element E2 is electrically connected to the first voltage terminal V1.

[0147] As shown in FIG12 , based on at least one embodiment of the pixel circuit shown in FIG10 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emitting control circuit 111 ;

[0148] The second light emitting control circuit 111 is electrically connected to the light emitting control terminal EM, the fourth node N4, and the first electrode of the light emitting element E1, respectively, and is configured to control the fourth node N4 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal;

[0149] The second electrode of the light emitting element E2 is electrically connected to the first voltage terminal V1.

[0150] Optionally, the driving circuit includes a driving transistor;

[0151] A gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the fourth node.

[0152] Optionally, the driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor;

[0153] The first gate of the driving transistor is electrically connected to the second node, and the second gate of the driving transistor is electrically connected to the second electrode of the driving transistor, the first gate of the driving transistor or the DC voltage terminal;

[0154] A first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the fourth node.

[0155] In at least one embodiment of the present disclosure, the driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; the pixel circuit further includes a third energy storage circuit and a third initialization circuit;

[0156] The first gate of the driving transistor is electrically connected to the second node; the first electrode of the driving transistor is electrically connected to the first node; and the second electrode of the driving transistor is electrically connected to the fourth node.

[0157] A first end of the third energy storage circuit is electrically connected to the second gate of the driving transistor, a second end of the third energy storage circuit is electrically connected to the fourth node, and the third energy storage circuit is used to store electrical energy;

[0158] The third initialization circuit is electrically connected to the fourth control terminal, the third reference voltage terminal and the second gate of the driving transistor respectively, and is used to write the third reference voltage provided by the third reference voltage terminal into the second gate of the driving transistor under the control of the fourth control signal provided by the fourth control terminal.

[0159] In at least one embodiment of the present disclosure, the first control terminal and the fourth control terminal can be the same control terminal, so as to reduce the number of control terminals used in the pixel circuit and the number of GOA (Gate On Array, a gate driving circuit provided on an array substrate) circuits for generating control signals, thereby facilitating the realization of a narrow frame.

[0160] Optionally, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the control circuit includes a first transistor, and the compensation control circuit includes a second transistor;

[0161] The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the second node;

[0162] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node;

[0163] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the third node, and the second electrode of the first transistor is electrically connected to the control voltage terminal;

[0164] A gate of the second transistor is electrically connected to the second control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node.

[0165] Optionally, the first initialization circuit includes a third transistor;

[0166] The gate of the third transistor is electrically connected to the third control terminal, the first electrode of the third transistor is electrically connected to the first reference voltage terminal, and the second electrode of the third transistor is electrically connected to the fourth node.

[0167] Optionally, the data writing circuit includes a fourth transistor;

[0168] A gate of the fourth transistor is electrically connected to the scan end, a first electrode of the fourth transistor is electrically connected to the data line, and a second electrode of the fourth transistor is electrically connected to the third node.

[0169] Optionally, the second initialization circuit includes a fifth transistor;

[0170] A gate of the fifth transistor is electrically connected to the reset control terminal, a first electrode of the fifth transistor is electrically connected to the second reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

[0171] Optionally, the first light emitting control circuit includes a sixth transistor;

[0172] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node.

[0173] Optionally, the second light emitting control circuit includes a seventh transistor;

[0174] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0175] Optionally, the third energy storage circuit includes a third capacitor, and the third initialization circuit includes an eighth transistor;

[0176] A first end of the third capacitor is electrically connected to the second gate of the driving transistor, and a second end of the third capacitor is electrically connected to the fourth node;

[0177] The gate of the eighth transistor is electrically connected to the fourth control terminal, the first electrode of the eighth transistor is electrically connected to the third reference voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second gate of the driving transistor.

[0178] As shown in FIG13 , based on at least one embodiment of the pixel circuit shown in FIG8 , the driving circuit includes a driving transistor TD; the light emitting element is an organic light emitting diode O1;

[0179] The gate of the driving transistor TD is electrically connected to the second node N2, the drain of the driving transistor TD is electrically connected to the first node N1, and the source of the driving transistor TD is electrically connected to the fourth node N4;

[0180] The first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, the control circuit includes a first transistor T1, and the compensation control circuit includes a second transistor T2;

[0181] A first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the second node N2;

[0182] The first end of the second capacitor C2 is electrically connected to the third node N3, and the second end of the second capacitor C2 is electrically connected to the fourth node N4; the fourth node N4 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0183] The gate of the first transistor T1 is electrically connected to the first control terminal CS1, the drain of the first transistor T1 is electrically connected to the third node N3, and the source of the first transistor T1 is electrically connected to the fourth node N4;

[0184] The gate of the second transistor T2 is electrically connected to the second control terminal CS2, the drain of the second transistor T2 is electrically connected to the first node N1, and the source of the second transistor T2 is electrically connected to the second node N2;

[0185] The first initialization circuit includes a third transistor T3;

[0186] The gate of the third transistor T3 is electrically connected to the third control terminal CS3, the drain of the third transistor T3 is electrically connected to the first reference voltage terminal REF1, and the source of the third transistor T3 is electrically connected to the fourth node N4; the first reference voltage terminal REF1 is used to provide a first reference voltage Vref1;

[0187] The data writing circuit includes a fourth transistor T4;

[0188] The gate of the fourth transistor T4 is electrically connected to the scanning terminal GT, the drain of the fourth transistor T4 is electrically connected to the data line DT, and the source of the fourth transistor T4 is electrically connected to the third node N3;

[0189] The second initialization circuit includes a fifth transistor T5;

[0190] The gate of the fifth transistor T5 is electrically connected to the reset control terminal R1, the drain of the fifth transistor T5 is electrically connected to the second reference voltage terminal REF2, and the source of the fifth transistor T5 is electrically connected to the second node N2; the second reference voltage terminal REF2 is used to provide a second reference voltage Vref2;

[0191] The first light emitting control circuit includes a sixth transistor T6;

[0192] A gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, a drain of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and a source of the sixth transistor T6 is electrically connected to the first node N1.

[0193] In at least one embodiment of the pixel circuit shown in FIG13 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto. In a specific implementation, the transistors may also be LTPS (low temperature polysilicon) n-type TFTs.

[0194] In at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure, the ratio of the capacitance value of C1 to the total capacitance associated with the second node N2, and the ratio of the capacitance value of C2 to the total capacitance associated with the fourth node N4, can be such that when the voltage value of the voltage signal provided by the data line DT changes, causing the potential of the third node N3 to change, due to capacitive coupling, ΔVN4 = ΔVN2, thereby maintaining the gate-source voltage of the drive transistor TD unchanged and suppressing changes in the current flowing through O1, thereby effectively reducing crosstalk. ΔVN4 is the voltage change of N4, and ΔVN2 is the voltage change of N2.

[0195] As shown in FIG14 , when at least one embodiment of the pixel circuit shown in FIG13 of the present disclosure is in operation, a display cycle may include an initialization phase S1 , a compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are sequentially arranged;

[0196] In the initialization phase S1, R1 provides a high voltage signal, CS1 provides a high voltage signal, CS2 provides a low voltage signal, CS3 provides a high voltage signal, EM and GT both provide low voltage signals, T3, T1 and T5 are turned on, at this time, the potentials of N1, N3 and N4 are reset to Vref1, and the potential of N2 is reset to Vref2, so that TD can be turned on when the compensation phase S2 begins;

[0197] In the compensation phase S2, CS1, CS2, and CS3 provide high voltage signals, EM, R1, and GT all provide low voltage signals, T2, T3, and T1 are turned on, and the potentials of N3 and N4 are maintained at Vref1;

[0198] At the beginning of the compensation phase S2, TD is turned on until the potential of N1 and the potential of N2 become Vef1 + Vth, and then TD is turned off, where Vth is the threshold voltage of TD.

[0199] In the compensation stage S2, the potential of N1 and the potential of N2 are finally stabilized at Vref1 + Vth due to the diode compensation structure;

[0200] In the data writing phase S3, EM, CS1 and CS2 all provide low voltage signals, CS3 provides a high voltage signal, R1 provides a low voltage signal, GT provides a high voltage signal, T4 and T3 are turned on, at this time, N2 is in a floating state, DT provides the data voltage Vdata, when the potential of N3 changes from Vref1 to Vdata, due to the presence of C1, through the capacitive coupling effect, the potential of N2 changes from Vref1+Vth to Vdata+Vth; the potential of N4 remains at Vref1; the state of TD will be determined according to the voltage value of Vdata; if Vdata is greater than Vref1, the gate-source voltage Vgs of TD is greater than Vth, at this time, the potential of N1 is Vref1; if Vdata is less than Vref1, the gate-source voltage Vgs of TD can be regarded as a cut-off state, and the potential of N1 is close to Vref1+Vth;

[0201] In the light-emitting stage S4, EM provides a high voltage signal, CS1, CS2, CS3, R1 and GT all provide low voltage signals, and T6 is turned on. After T6 is turned on, the potential of N4 will gradually change from Vref1 to Vs (Vs is the source voltage of TD, which is a variable positively correlated with the gate voltage). At this time, since N2 and N3 are in the floating state, the potential of N2 and N3 will also change through occasional action of the capacitor. Without considering parasitic capacitance, the potential of N3 changes from Vdata to Vdata+Vs-Vref1, and the potential of N2 changes from Vdata+Vth to Vdata+Vth+Vs-Vref1. Id is equal to K×(Vdata-Vref1). 2 ; K is the current coefficient of TD, and Id is the driving current generated by TD.

[0202] In at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure, the compensation phase and the data writing phase are independent of each other during operation, so as to increase the duration of the compensation phase and enhance the threshold voltage compensation effect.

[0203] The difference between at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure is as follows:

[0204] At least one embodiment of the pixel circuit shown in FIG15 of the present disclosure further includes a second light emitting control circuit;

[0205] The second light emitting control circuit includes a seventh transistor T7;

[0206] A gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, a drain of the seventh transistor T7 is electrically connected to the fourth node N4, and a source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1.

[0207] In at least one embodiment of the pixel circuit shown in FIG. 15 , T7 is an n-type transistor, and T7 is an oxide thin film transistor, but the present invention is not limited thereto.

[0208] The difference between at least one embodiment of the pixel circuit shown in FIG. 16 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure is as follows:

[0209] The source of T1 is electrically connected to the first reference voltage terminal REF1.

[0210] As shown in FIG14 , when at least one embodiment of the pixel circuit shown in FIG16 of the present disclosure is in operation, a display cycle may include an initialization phase S1 , a compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are sequentially arranged;

[0211] In the initialization phase S1, R1 provides a high voltage signal, CS1 provides a high voltage signal, CS2 provides a low voltage signal, CS3 provides a high voltage signal, EM and GT both provide low voltage signals, T3, T1 and T5 are turned on, at this time, the potentials of N1, N3 and N4 are reset to Vref1, and the potential of N2 is reset to Vref2, so that TD can be turned on when the compensation phase S2 begins;

[0212] In the compensation phase S2, CS1, CS2, and CS3 provide high voltage signals, EM, R1, and GT all provide low voltage signals, T2, T3, and T1 are turned on, and the potentials of N3 and N4 are maintained at Vref1;

[0213] At the beginning of the compensation phase S2, TD is turned on to charge the capacitor until the potential of N1 and the potential of N2 become Vef1 + Vth, and TD is turned off, where Vth is the threshold voltage of TD.

[0214] In the compensation stage S2, the potential of N1 and the potential of N2 are finally stabilized at Vref1 + Vth due to the diode compensation structure;

[0215] In the data writing phase S3, EM, CS1 and CS2 all provide low voltage signals, CS3 provides a high voltage signal, R1 provides a low voltage signal, GT provides a high voltage signal, T4 and T3 are turned on, at this time, N2 is in a floating state, DT provides the data voltage Vdata, when the potential of N3 changes from Vref1 to Vdata, due to the presence of C1, through the capacitive coupling effect, the potential of N2 changes from Vref1+Vth to Vdata+Vth; the potential of N4 remains at Vref1; the state of TD will be determined according to the voltage value of Vdata; if Vdata is greater than Vref1, the gate-source voltage Vgs of TD is greater than Vth, at this time, the potential of N1 is Vref1; if Vdata is less than Vref1, the gate-source voltage Vgs of TD can be regarded as a cut-off state, and the potential of N1 is close to Vref1+Vth;

[0216] In the light-emitting stage S4, EM provides a high voltage signal, CS1, CS2, CS3, R1 and GT all provide low voltage signals, and T6 is turned on. After T6 is turned on, the potential of N4 will gradually change from Vref1 to Vs (Vs is the source voltage of TD, which is a variable positively correlated with the gate voltage). At this time, since N2 and N3 are in the floating state, the potential of N2 and N3 will also change through occasional action of the capacitor. Without considering parasitic capacitance, the potential of N3 changes from Vdata to Vdata+Vs-Vref1, and the potential of N2 changes from Vdata+Vth to Vdata+Vth+Vs-Vref1. Id is equal to K×(Vdata-Vref1). 2 ; K is the current coefficient of TD, and Id is the driving current generated by TD.

[0217] The difference between at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure is as follows:

[0218] The driving transistor TD is a dual-gate transistor;

[0219] A first gate of the driving transistor TD is electrically connected to the second node N2 , and a second gate of the driving transistor TD is electrically connected to the fourth node N4 .

[0220] In at least one embodiment of the pixel circuit shown in FIG17 , the first gate may be a top gate, and the second gate may be a bottom gate.

[0221] In at least one embodiment of the pixel circuit shown in FIG17 , when in operation, the bottom gate of TD is electrically connected to the source of TD, such that VBS of TD is equal to 0, and thus the threshold voltage of TD is greater than 0. VBS is the difference between the potential of the bottom gate of TD and the potential of the source of TD.

[0222] In the pixel circuit described in at least one embodiment of the present disclosure, since threshold voltage compensation needs to be performed through a diode connection of the driving transistor, the threshold voltage of the driving transistor needs to be controlled so as to be a positive value.

[0223] In at least one embodiment of the present disclosure, the second gate of the driving transistor TD may also be electrically connected to the first gate of the driving transistor TD; or,

[0224] The second gate of the driving transistor TD may be electrically connected to a DC voltage terminal, so that the VBS of TD is less than 0.

[0225] As shown in FIG18 , based on at least one embodiment of the pixel circuit shown in FIG9 ,

[0226] The driving circuit includes a driving transistor TD; the driving transistor TD is a dual-gate transistor; the pixel circuit also includes a third energy storage circuit 171 and a third initialization circuit 172;

[0227] The first gate of the driving transistor TD is electrically connected to the second node N2; the drain of the driving transistor TD is electrically connected to the first node N1; and the source of the driving transistor TD is electrically connected to the fourth node N4.

[0228] A first end of the third energy storage circuit 171 is electrically connected to the second gate of the driving transistor TD, a second end of the third energy storage circuit 171 is electrically connected to the fourth node N4, and the third energy storage circuit 171 is used to store electrical energy;

[0229] The third initialization circuit 172 is electrically connected to the fourth control terminal CS4, the third reference voltage terminal REF3 and the second gate of the driving transistor TD, respectively, and is used to write the third reference voltage Vref3 provided by the third reference voltage terminal REF3 into the second gate of the driving transistor TD under the control of the fourth control signal provided by the fourth control terminal CS4.

[0230] As shown in FIG19 , based on at least one embodiment of the pixel circuit shown in FIG10 ,

[0231] The driving circuit includes a driving transistor TD; the driving transistor TD is a dual-gate transistor; the pixel circuit also includes a third energy storage circuit 171 and a third initialization circuit 172;

[0232] The first gate of the driving transistor TD is electrically connected to the second node N2; the drain of the driving transistor TD is electrically connected to the first node N1; and the source of the driving transistor TD is electrically connected to the fourth node N4.

[0233] A first end of the third energy storage circuit 171 is electrically connected to the second gate of the driving transistor TD, a second end of the third energy storage circuit 171 is electrically connected to the fourth node N4, and the third energy storage circuit 171 is used to store electrical energy;

[0234] The third initialization circuit 172 is electrically connected to the fourth control terminal CS4, the third reference voltage terminal REF3 and the second gate of the driving transistor TD, respectively, and is used to write the third reference voltage Vref3 provided by the third reference voltage terminal REF3 into the second gate of the driving transistor TD under the control of the fourth control signal provided by the fourth control terminal CS4.

[0235] As shown in FIG20, based on at least one embodiment of the pixel circuit shown in FIG18,

[0236] The driving circuit includes a driving transistor TD; the light emitting element is an organic light emitting diode O1; the driving transistor TD is a dual-gate transistor; the third energy storage circuit includes a third capacitor C3, and the third initialization circuit includes an eighth transistor T8;

[0237] A first end of the third capacitor C3 is electrically connected to the second gate of the driving transistor TD, and a second end of the third capacitor C3 is electrically connected to the fourth node N4;

[0238] The gate of the eighth transistor T8 is electrically connected to the fourth control terminal CS4, the drain of the eighth transistor T8 is electrically connected to the third reference voltage terminal REF3, and the source of the eighth transistor T8 is electrically connected to the second gate of the driving transistor TD; the third reference voltage terminal REF3 is used to provide a third reference voltage Vref3;

[0239] The first gate of the driving transistor TD is electrically connected to the second node N2;

[0240] The drain of the driving transistor TD is electrically connected to the first node N1, and the source of the driving transistor TD is electrically connected to the fourth node N4;

[0241] The first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, the control circuit includes a first transistor T1, and the compensation control circuit includes a second transistor T2;

[0242] A first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the second node N2;

[0243] The first end of the second capacitor C2 is electrically connected to the third node N3, and the second end of the second capacitor C2 is electrically connected to the fourth node N4; the fourth node N4 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0244] The gate of the first transistor T1 is electrically connected to the first control terminal CS1, the drain of the first transistor T1 is electrically connected to the third node N3, and the source of the first transistor T1 is electrically connected to the fourth node N4;

[0245] The gate of the second transistor T2 is electrically connected to the second control terminal CS2, the drain of the second transistor T2 is electrically connected to the first node N1, and the source of the second transistor T2 is electrically connected to the second node N2;

[0246] The first initialization circuit includes a third transistor T3;

[0247] The gate of the third transistor T3 is electrically connected to the third control terminal CS3, the drain of the third transistor T3 is electrically connected to the first reference voltage terminal REF1, and the source of the third transistor T3 is electrically connected to the fourth node N4; the first reference voltage terminal REF1 is used to provide a first reference voltage Vref1;

[0248] The data writing circuit includes a fourth transistor T4;

[0249] The gate of the fourth transistor T4 is electrically connected to the scanning terminal GT, the drain of the fourth transistor T4 is electrically connected to the data line DT, and the source of the fourth transistor T4 is electrically connected to the third node N3;

[0250] The second initialization circuit includes a fifth transistor T5;

[0251] The gate of the fifth transistor T5 is electrically connected to the reset control terminal R1, the drain of the fifth transistor T5 is electrically connected to the second reference voltage terminal REF2, and the source of the fifth transistor T5 is electrically connected to the second node N2; the second reference voltage terminal REF2 is used to provide a second reference voltage Vref2;

[0252] The first light emitting control circuit includes a sixth transistor T6;

[0253] A gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, a drain of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and a source of the sixth transistor T6 is electrically connected to the first node N1.

[0254] In at least one embodiment of the pixel circuit shown in FIG20 , an eighth transistor T8 and a third capacitor C3 are provided; in the initialization stage and the compensation stage, the potential of the second gate of TD is Vref3, the source potential of TD is Vref1, and Vref1 is set to be greater than Vref3, so that VBS of TD is less than 0, and the threshold voltage Vth of TD is positively biased, thereby ensuring that the threshold voltage of TD is a positive value and ensuring the normal effectiveness of the diode compensation structure.

[0255] In at least one embodiment of the pixel circuit shown in FIG20 , Vref2 is set to be greater than Vref1. In the initialization phase, the potential of N2 is Vref2 and the potential of N4 is Vref1, so that TD can be turned on and threshold voltage compensation can be performed at the beginning of the compensation phase.

[0256] In at least one embodiment of the pixel circuit shown in FIG. 20 , all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.

[0257] At least one embodiment of the pixel circuit shown in Figure 20 of the present disclosure is an optimized circuit for the situation where the threshold voltage Vth of the oxide thin film transistor becomes negative due to process fluctuation problems, resulting in the inability to compensate for Vth; wherein, Vref2 is greater than Vref1, and Vref1 is greater than Vref3, so that in certain time periods, the VBS of TD is equal to Vref3-Vref1, VBS is a negative value, and Vth is positively biased. It is necessary to ensure that the threshold voltages of the driving transistors of all pixel circuits are positive under the current process conditions to ensure the normal effectiveness of the diode compensation results; wherein, CS1 and CS4 can be provided by the same signal line or by different signal lines.

[0258] In at least one embodiment of the present disclosure, the difference between Vref1 and Vss can be greater than or equal to -2V and less than or equal to 2V, so as to facilitate clearing the residual charge on the anode of O1 and control O1 not to emit light when CS3 controls T3 to turn on; the difference between Vref2 and Vref1 can be greater than 3V, and the difference between Vref3 and Vref1 can be less than -2V; wherein Vss is the voltage value of the low voltage signal provided by VSS.

[0259] As shown in FIG21 , when at least one embodiment of the pixel circuit shown in FIG20 of the present disclosure is in operation, a display cycle may include an initialization phase S1 , a compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are arranged in sequence;

[0260] In the initialization phase S1, R1 provides a high voltage signal, CS1 provides a high voltage signal, CS2 provides a low voltage signal, CS3 provides a high voltage signal, EM and GT both provide low voltage signals, T3, T1 and T5 are turned on, at this time, the potentials of N1, N3 and N4 are reset to Vref1, and the potential of N2 is reset to Vref2, so that TD can be turned on when the compensation phase S2 begins; CS4 provides a high voltage signal, T8 is turned on, and the bottom gate of TD is connected to Vref3;

[0261] In the compensation phase S2, CS1, CS2, and CS3 provide high voltage signals, EM, R1, and GT all provide low voltage signals, T2, T3, and T1 are turned on, and the potentials of N3 and N4 are kept at Vref1; CS4 provides a high voltage signal, T8 is turned on, and the bottom gate of TD is connected to Vref3;

[0262] At the beginning of the compensation phase S2, TD is turned on until the potential of N1 and the potential of N2 become Vref1 + Vth, and then TD is turned off, where Vth is the threshold voltage of TD.

[0263] In the compensation stage S2, the potential of N1 and the potential of N2 are finally stabilized at Vref1 + Vth due to the diode compensation structure;

[0264] In the data writing phase S3, EM, CS1 and CS2 all provide low voltage signals, CS3 provides a high voltage signal, R1 provides a low voltage signal, GT provides a high voltage signal, CS4 provides a low voltage signal, T4 and T3 are turned on, at this time, N2 is in a floating state, DT provides the data voltage Vdata, when the potential of N3 changes from Vref1 to Vdata, due to the presence of C1, through the capacitive coupling effect, the potential of N2 changes from Vref1+Vth to Vdata+Vth; the potential of N4 remains at Vref1; the state of TD will be determined according to the voltage value of Vdata; if Vdata is greater than Vref1, the gate-source voltage Vgs of TD is greater than Vth, at this time, the potential of N1 is Vref1; if Vdata is less than Vref1, the gate-source voltage Vgs of TD can be regarded as a cut-off state, and the potential of N1 is close to Vref1+Vth;

[0265] In the light-emitting stage S4, EM provides a high voltage signal, CS1, CS2, CS3, R1 and GT all provide low voltage signals, CS4 provides a low voltage signal, and T6 is turned on. After T6 is turned on, the potential of N4 will gradually change from Vref1 to Vs (Vs is the source voltage of TD, which is a variable positively correlated with the gate voltage). At this time, since N2 and N3 are in the floating state, the potential of N2 and the potential of N3 will also change through capacitive coupling. Without considering parasitic capacitance, the potential of N3 changes from Vdata to Vdata+Vs-Vref1, and the potential of N2 changes from Vdata+Vth to Vdata+Vth+Vs-Vref1. Id is equal to K×(Vdata-Vref1). 2 ; K is the current coefficient of TD, and Id is the driving current generated by TD.

[0266] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0267] The driving circuit drives the light emitting element under the control of the potential of the second node;

[0268] The control circuit controls the third node to be connected to the control voltage terminal under the control of the first control signal;

[0269] The compensation control circuit controls the connection between the first node and the second node under the control of the second control signal;

[0270] The pixel circuit further includes a first initialization circuit and a data writing circuit;

[0271] The display cycle includes a compensation phase and a data writing phase which are arranged in sequence; the driving method includes:

[0272] During the compensation phase, the compensation control circuit controls the first node and the second node to be connected under the control of the second control signal, the first initialization circuit writes the first reference voltage to the fourth node under the control of the third control signal, and the control circuit controls the third node to be connected to the control voltage terminal under the control of the first control signal;

[0273] In the data writing phase, the first initialization circuit writes the first reference voltage into the fourth node under the control of the third control signal, and the data writing circuit writes the data voltage into the third node under the control of the scan signal;

[0274] The display cycle further includes an initialization phase before the compensation phase, and the pixel circuit further includes a first initialization circuit and a second initialization circuit; the driving method further includes:

[0275] During the initialization stage, the first initialization circuit writes the first reference voltage into the fourth node under the control of the third control signal, and the control circuit controls the connection between the third node and the control voltage terminal under the control of the first control signal; the second initialization circuit writes the second reference voltage into the second node under the control of the reset control signal.

[0276] In at least one embodiment of the present disclosure, the display period further includes a light emitting phase arranged after the data writing phase, the pixel circuit further includes a first light emitting control circuit; and the driving method further includes:

[0277] In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first node under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

[0278] In at least one embodiment of the present disclosure, the driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; the pixel circuit further includes a third energy storage circuit and a third initialization circuit;

[0279] The driving method may further include:

[0280] During the initialization phase and the compensation phase, the third initialization circuit writes a third reference voltage into the second gate of the driving transistor under the control of a fourth control signal.

[0281] In a specific implementation, the driving transistor may be a dual-gate transistor, and the pixel circuit may further include a third energy storage circuit and a third initialization circuit. Under the control of a fourth control signal, the third initialization circuit writes a third reference voltage into the second gate of the driving transistor to control VBS of the driving transistor so that the threshold voltage of the driving transistor is forward biased. VBS is the difference between the potential of the bottom gate of the driving transistor and the potential of the source of the driving transistor.

[0282] Optionally, the second reference voltage is greater than the first reference voltage; and the first reference voltage is greater than the third reference voltage.

[0283] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0284] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising a light-emitting element, a driving circuit, a compensation control circuit, a first energy storage circuit, a second energy storage circuit, and a control circuit; A first terminal of the driving circuit is electrically connected to a first node, a control terminal of the driving circuit is electrically connected to a second node, a first terminal of the first energy storage circuit is electrically connected to a third node, and a second terminal of the driving circuit is electrically connected to the light-emitting element via a fourth node, wherein the driving circuit is configured to drive the light-emitting element under control of a potential of the second node; The second end of the first energy storage circuit is electrically connected to the second node, and the first energy storage circuit is used to store electrical energy; A first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to the fourth node, and the second energy storage circuit is used to store electrical energy; The control circuit is electrically connected to the first control terminal, the third node, and the control voltage terminal, respectively, and is configured to control the communication between the third node and the control voltage terminal under the control of a first control signal provided by the first control terminal; the control voltage terminal is electrically connected to the fourth node, or the control voltage terminal is a first reference voltage terminal; The compensation control circuit is electrically connected to the second control terminal, the first node and the second node respectively, and is used to control the connection between the first node and the second node under the control of a second control signal provided by the second control terminal.

2. The pixel circuit according to claim 1, wherein: Also included is a first initialization circuit; The first initialization circuit is electrically connected to the third control terminal, the first reference voltage terminal and the fourth node respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the fourth node under the control of a third control signal provided by the third control terminal.

3. The pixel circuit according to claim 2, wherein: Also included is a data writing circuit; The data writing circuit is electrically connected to the scan end, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scan signal provided by the scan end.

4. The pixel circuit according to claim 3, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the reset control terminal, the second reference voltage terminal and the second node respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the second node under the control of the reset control signal provided by the reset control terminal.

5. The pixel circuit according to claim 1, wherein: Also includes a first light emitting control circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the first node respectively, and is used to control the connection between the power supply voltage terminal and the first node under the control of the light-emitting control signal provided by the light-emitting control terminal.

6. The pixel circuit according to claim 5, wherein: Also includes a second light emitting control circuit; The second light emitting control circuit is electrically connected to the light emitting control terminal, the fourth node and the first electrode of the light emitting element respectively, and is used to control the fourth node and the first electrode of the light emitting element under the control of the light emitting control signal. The poles are connected; The second electrode of the light emitting element is electrically connected to the first voltage end.

7. The pixel circuit according to claim 1, wherein: The driving circuit includes a driving transistor; A gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the fourth node.

8. The pixel circuit according to claim 1, wherein: The driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; The first gate of the driving transistor is electrically connected to the second node, and the second gate of the driving transistor is electrically connected to the second electrode of the driving transistor, the first gate of the driving transistor or the DC voltage terminal; A first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the fourth node.

9. The pixel circuit according to claim 1, wherein: The driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; the pixel circuit also includes a third energy storage circuit and a third initialization circuit; The first gate of the driving transistor is electrically connected to the second node; the first electrode of the driving transistor is electrically connected to the first node; and the second electrode of the driving transistor is electrically connected to the fourth node. A first end of the third energy storage circuit is electrically connected to the second gate of the driving transistor, a second end of the third energy storage circuit is electrically connected to the fourth node, and the third energy storage circuit is used to store electrical energy; The third initialization circuit is electrically connected to the fourth control terminal, the third reference voltage terminal and the second gate of the driving transistor respectively, and is used to write the third reference voltage provided by the third reference voltage terminal into the second gate of the driving transistor under the control of the fourth control signal provided by the fourth control terminal.

10. The pixel circuit according to claim 9, wherein: The first control end and the fourth control end are the same control end.

11. The pixel circuit according to claim 1, wherein: The first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the control circuit includes a first transistor, and the compensation control circuit includes a second transistor; The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the second node; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node; The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the third node, and the second electrode of the first transistor is electrically connected to the control voltage terminal; A gate of the second transistor is electrically connected to the second control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node.

12. The pixel circuit according to claim 2, wherein: The first initialization circuit includes a third transistor; The gate of the third transistor is electrically connected to the third control terminal, and the first electrode of the third transistor is electrically connected to the first control terminal. A reference voltage terminal is electrically connected, and the second electrode of the third transistor is electrically connected to the fourth node.

13. The pixel circuit according to claim 3, wherein: The data writing circuit includes a fourth transistor; A gate of the fourth transistor is electrically connected to the scan end, a first electrode of the fourth transistor is electrically connected to the data line, and a second electrode of the fourth transistor is electrically connected to the third node.

14. The pixel circuit according to claim 4, wherein: The second initialization circuit includes a fifth transistor; A gate of the fifth transistor is electrically connected to the reset control terminal, a first electrode of the fifth transistor is electrically connected to the second reference voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

15. The pixel circuit according to claim 5, wherein: The first light emitting control circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node.

16. The pixel circuit according to claim 6, wherein: The second light emitting control circuit includes a seventh transistor; The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

17. The pixel circuit according to claim 9, wherein: The third energy storage circuit includes a third capacitor, and the third initialization circuit includes an eighth transistor; A first end of the third capacitor is electrically connected to the second gate of the driving transistor, and a second end of the third capacitor is electrically connected to the fourth node; The gate of the eighth transistor is electrically connected to the fourth control terminal, the first electrode of the eighth transistor is electrically connected to the third reference voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second gate of the driving transistor.

18. A driving method, applied to the pixel circuit according to any one of claims 1 to 17, the driving method comprising: The driving circuit drives the light emitting element under the control of the potential of the second node; The control circuit controls the third node to be connected to the control voltage terminal under the control of the first control signal; The compensation control circuit controls the connection between the first node and the second node under the control of the second control signal; The pixel circuit further includes a first initialization circuit and a data writing circuit; The display cycle includes a compensation phase and a data writing phase which are arranged in sequence; the driving method includes: During the compensation phase, the compensation control circuit controls the first node and the second node to be connected under the control of the second control signal, the first initialization circuit writes the first reference voltage to the fourth node under the control of the third control signal, and the control circuit controls the third node to be connected to the control voltage terminal under the control of the first control signal; In the data writing phase, the first initialization circuit writes the first reference voltage into the fourth node under the control of the third control signal, and the data writing circuit writes the data voltage into the third node under the control of the scan signal; The display cycle further includes an initialization phase before the compensation phase, and the pixel circuit further includes a first initialization circuit and a second initialization circuit; the driving method further includes: In the initialization phase, the first initialization circuit writes the first reference voltage into the fourth node under the control of the third control signal, and the control circuit controls the connection between the third node and the control voltage terminal under the control of the first control signal; The initialization circuit writes the second reference voltage into the second node under the control of the reset control signal.

19. The driving method according to claim 18, wherein: The display cycle further includes a light emitting phase arranged after the data writing phase, and the pixel circuit further includes a first light emitting control circuit; and the driving method further includes: In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first node under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

20. The driving method according to claim 18, wherein: The driving circuit includes a driving transistor; the driving transistor is a dual-gate transistor; the pixel circuit also includes a third energy storage circuit and a third initialization circuit; The driving method further includes: During the initialization phase and the compensation phase, the third initialization circuit writes a third reference voltage into the second gate of the driving transistor under the control of a fourth control signal.

21. A display device comprising the pixel circuit according to any one of claims 1 to 17.

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