Packaging structure, integrated circuit, memory and electronic device

Abstract

The present application belongs to the technical field of semiconductors. Provided are a packaging structure, an integrated circuit, a memory and an electronic device. The packaging structure comprises: a packaging substrate; a first ball grid array, which is located on a first surface of the packaging substrate and comprises a first metal ball and a second metal ball adjacent to the first metal ball, wherein the first metal ball is electrically coupled to the first surface by means of a first bonding pad, and the second metal ball is electrically coupled to the first surface by means of a second bonding pad; a connecting component, the connecting component being electrically coupled with the first bonding pad; and a functional component, which is connected to the first metal ball by means of the connecting component and comprises a plurality of metal discs and a plurality of metal wires that are located above the second bonding pad, wherein every two adjacent metal discs are connected by means of one metal wire. The present application can reduce far-end crosstalk and impedance discontinuity between the first metal ball and the second metal ball when an electric signal is transmitted by means of the first metal ball.

Description

Packaging structures, integrated circuits, memories and electronic devices

[0001] This application claims priority to Chinese patent application No. 2024102456332, filed on March 4, 2024, with invention name “Packaging structure, integrated circuit, memory and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a packaging structure, an integrated circuit, a memory, and an electronic device. Background Art

[0003] High-speed signaling systems such as DDR5 (Double Data Rate 5-generation synchronous dynamic random-access memory) require a large number of tightly packed single-ended traces. As signal transmission rates increase, crosstalk between adjacent transmission paths increases. Far-end crosstalk (FEXT), in particular, has become a major factor affecting DDR5 performance. To improve the performance of high-speed signaling systems like DDR5, it is necessary to reduce or eliminate FEXT.

[0004] Summary of the Invention

[0005] The present invention provides a packaging structure, an integrated circuit, a memory, and an electronic device that can reduce or eliminate far-end crosstalk and impedance discontinuity. The technical solution is as follows:

[0006] In a first aspect, a packaging structure is provided, the packaging structure comprising:

[0007] Package substrate;

[0008] a first ball grid array, the first ball grid array being located on a first surface of the package substrate, the first ball grid array comprising a first metal ball and a second metal ball adjacent to the first metal ball, the first metal ball being electrically coupled to the first surface via a first pad, and the second metal ball being electrically coupled to the first surface via a second pad;

[0009] a connecting component electrically coupled to the first pad;

[0010] A functional component, wherein the functional component is connected to the first metal ball through the connecting component, the functional component includes multiple metal pads and multiple metal traces located above the second pad, and two adjacent metal pads are connected by a metal trace, and the functional component is used to reduce far-end crosstalk and impedance discontinuity between the first metal ball and the second metal ball when an electrical signal is transmitted through the first metal ball.

[0011] In a second aspect, an integrated circuit is provided, comprising:

[0012] A packaging structure, wherein the packaging structure is the packaging structure described in the first aspect;

[0013] a printed circuit board, the printed circuit board being electrically coupled to the packaging structure through the first ball grid array in the packaging structure;

[0014] a second ball grid array, the second ball grid array being located on a second surface of the package substrate in the package structure, the second surface being a surface corresponding to the first surface of the package substrate;

[0015] A chip is electrically coupled to the packaging structure through the second ball grid array.

[0016] According to a third aspect, a memory is provided, wherein the memory includes the integrated circuit according to the second aspect.

[0017] In a fourth aspect, an electronic device is provided, comprising a processor and a memory, wherein the memory is the memory described in the third aspect, and the memory is used to store at least one program code, and the at least one program code is loaded and executed by the processor to realize the function of the electronic device.

[0018] The beneficial effects of the technical solution provided by the embodiments of the present application are:

[0019] An embodiment of the present application provides a packaging structure, which includes a packaging substrate, a first ball grid array, a connecting component and a functional component. The first ball grid array is electrically coupled to the packaging substrate. For the first metal ball therein, when transmitting an electrical signal, there will be far-end crosstalk and impedance discontinuity between the first metal ball and the adjacent second metal ball. By providing a functional component for the first metal ball, multiple metal disks in the functional component can form mutual capacitance, and metal traces connecting adjacent metal disks can form self-inductance. The far-end crosstalk between the first metal ball and the second metal ball can be reduced or eliminated through self-inductance and mutual capacitance. The impedance discontinuity between the first metal ball and the second metal ball can be reduced or eliminated through local compensation of mutual capacitance by self-inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] FIG1 is a schematic diagram of a packaging structure provided by the related art;

[0022] FIG2 is a schematic diagram of impedance changes during electrical signal transmission;

[0023] FIG3 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

[0024] FIG4 is a detailed schematic diagram of a functional component provided in an embodiment of the present application;

[0025] FIG5 is a detailed schematic diagram of a functional component provided in an embodiment of the present application;

[0026] FIG6 is a schematic diagram of a packaging structure provided in an embodiment of the present application;

[0027] FIG7 is a schematic diagram of a packaging structure provided in an embodiment of the present application;

[0028] FIG8 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0029] FIG9 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0031] It should be understood that the terms "each," "plurality," and "any" used in the embodiments of this application include two or more, "each" refers to each of the corresponding plurality, and "any" refers to any one of the corresponding plurality. For example, if a plurality of words includes 10 words, "each" refers to each of the 10 words, and "any" refers to any one of the 10 words.

[0032] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0033] Taking DDR5 as an example, integrated circuits in high-speed signaling systems are often packaged using ball grid arrays (BGAs). BGA packaging is a common packaging technology used to connect the pins of electronic components (such as CPUs) to circuit boards, effectively improving important performance of electronic products such as reliability, thermal conductivity, and portability. In particular, as a high-sealing packaging technology for chip packaging, BGA packaging can achieve electrical and mechanical connections between chip systems. However, when using BGA packaging, crosstalk will exist between different signal paths associated with adjacent metal balls in the BGA.

[0034] Crosstalk refers to the undesirable effect of electromagnetic coupling on adjacent transmission lines when an electrical signal is transmitted along a transmission channel. This effect manifests as a certain amount of coupled voltage and current being injected into the interfered signal. According to Maxwell's laws, any current will produce a magnetic field, and the interference between these magnetic fields is the source of crosstalk. Crosstalk includes near-end crosstalk (NEXT) and far-end crosstalk (FEXT). NEXT occurs when an electrical signal from the transmitting end of one transmission line couples to an electrical signal from the near-end receiving end of another adjacent transmission line. FEXT occurs when an electrical signal from the transmitting end of one transmission line couples to an electrical signal from the far-end receiving end of another adjacent transmission line. FEXT, a significant factor affecting high-speed signaling systems, can cause circuit false triggering, data loss and transmission errors, and even cause the high-speed signaling system to malfunction. Therefore, there is a need to reduce or eliminate FEXT in high-speed signaling systems.

[0035] According to a transmission line theory, the magnitude of far-end crosstalk is expressed as:

[0036] Among them, V FEXT is the size of far-end crosstalk, Cm is mutual capacitance, Lm is mutual inductance, Cs is self-capacitance, Ls is self-inductance, V agg is the voltage of the interference source signal, t pd Is the propagation delay of the electrical signal. In the substrate (such as the package substrate, socket or printed circuit board), the inductance is usually dominant, making V FEXT Less than zero, that is, far-end crosstalk often has a negative polarity (negative value relative to the excitation source of the rising edge). According to the above transmission line theory, it can be seen that far-end crosstalk can be reduced or eliminated by increasing self-inductance and mutual capacitance.

[0037] In order to reduce the far-end crosstalk on the signal path, the related art provides a packaging structure for improving far-end crosstalk. The packaging structure reduces or eliminates the far-end crosstalk between the two metal balls by increasing the mutual capacitance between the two metal balls where the far-end crosstalk exists. FIG1 shows a packaging structure of the related art. The packaging structure is illustrated by taking the metal balls 101 and 102 in the ball grid array as an example. When an electrical signal is transmitted on the metal ball 101, far-end crosstalk is generated on the electrical signal on the metal ball 102. In FIG1 , a connecting line extending toward the metal ball 102 is added to the metal ball 101, and a metal disk is added at the far end of the connecting line to increase the mutual capacitance between the metal balls 101 and 102, thereby reducing or eliminating the far-end crosstalk between the metal balls 101 and 102.

[0038] However, ball grid array packaging also presents the problem of impedance discontinuity when electrical signals are transmitted through the metal balls. Impedance refers to the resistance to current flow in a circuit composed of resistors, capacitors, and inductors. If the characteristic impedance of the transmission path changes during signal transmission, the signal will be reflected at the node where the impedance discontinuity occurs. In practical applications, impedance discontinuity poses several challenges for signal processing and circuit design. First, impedance discontinuity can cause different transmission delays of electrical signals in different circuit components, affecting the time consistency of the electrical signal, which is critical for systems requiring high-precision signal processing and timing control. Second, impedance discontinuity can cause phase distortion of the electrical signal. In high-frequency circuits and communication systems, phase distortion can lead to signal distortion and error, thus affecting system performance and reliability. Therefore, impedance discontinuity needs to be minimized in circuit design and signal processing.

[0039] According to another theory of transmission lines, the impedance can be expressed as:

[0040] Where Z is the impedance. Whether the impedance is continuous or not depends on the changes in inductance and capacitance.

[0041] Although the package structure shown in FIG1 can reduce or eliminate far-end crosstalk, it cannot reduce the impedance discontinuity on the transmission path. Therefore, when using this package structure to transmit electrical signals, the performance of the high-speed signaling system will still be affected.

[0042] Figure 2 shows the effect of the arrangement of capacitors and self-inductance coils on the signal path on impedance. Figure 2 (A) shows that by adding a capacitor to the signal path, the impedance value on the signal path can be lowered; Figure 2 (B) shows that by adding a self-inductance coil to the signal path, the impedance value on the signal path can be increased; Figure 2 (C) shows that by adding a self-inductance coil and a capacitor to the signal path, the impedance value on the signal path can be first increased and then lowered. For high-speed signaling transmission systems, the transmission rate of electrical signals is relatively fast. When the inductance generated by the self-inductance coil is used to compensate for the capacitance generated by the capacitor, the closer the distance between the self-inductance coil and the capacitor, the less obvious the impedance change. If the capacitor and inductance on the transmission path are changed to LC cascade, then L total =L1+L2+…+L n , C total =C1+C2+…+C n , then the impedance discontinuity can be improved.

[0043] According to the capacitor series and parallel theory, for two capacitors C1 and C2, the capacitance after series connection C = C1*C2 / (C1+C2) is smaller than either capacitor before series connection; the capacitance after parallel connection C = C1 and C2 is larger than either capacitor before parallel connection.

[0044] In view of the above theory, an embodiment of the present application provides a packaging structure, which uses multiple metal plates to generate mutual capacitance. Under the premise of ensuring that the mutual capacitance remains unchanged, multiple small capacitance structures are constructed, and two adjacent metal plates are connected by metal traces. The metal traces can generate self-inductance in the process of transmitting electrical signals. The self-inductance generated by the metal traces can compensate for the mutual capacitance generated by adjacent metal plates, thereby not only reducing far-end crosstalk, but also the smaller LC cascade can reduce impedance discontinuity.

[0045] An embodiment of the present application provides a packaging structure. Figure 3 is a schematic diagram of the cross-section of the packaging structure. Referring to Figure 3, the packaging structure includes: a packaging substrate 301, a first ball grid array 302, a connecting component 303, a functional component 304, a first solder pad 305 and a second solder pad 306.

[0046] The package substrate 301 comprises multiple conductive layers and multiple dielectric layers. The conductive layers are used to transmit electrical signals and can be made of metal materials, such as copper, aluminum, gold, silver, tungsten, titanium, or alloys thereof. The multiple conductive layers are stacked vertically on the first surface of the package substrate 301 and extend horizontally toward the first surface, which is electrically coupled to the first ball grid array 302. FIG3 illustratively illustrates four conductive layers E1, E2, E3, and E4. In actual applications, the number of conductive layers can be set based on process requirements. The dielectric layers are used to isolate different conductive layers to prevent short circuits or leakage. The dielectric layers can be made of dielectric materials, such as polypropylene (PP), silicon oxide (SiO2), silicon nitride (SiN), or other dielectric materials. The multiple dielectric layers are stacked vertically on the first surface of the package substrate 301 and extend horizontally toward the first surface. FIG3 illustratively illustrates four dielectric layers D1, D2, D3, and D4. In actual applications, the number of dielectric layers can be set based on process requirements.

[0047] The first ball grid array 302 is located on the first surface of the package substrate 301. The first ball grid array 302 includes a first metal ball 3021 and a second metal ball 3022 adjacent to the first metal ball, thereby generating far-end crosstalk when the multiple metal balls transmit electrical signals. For example, when the electrical signal is transmitted through the first metal ball 3021, the electrical signal on the first metal ball 3021 is coupled to the electrical signal on the second metal ball 3022, thereby generating far-end crosstalk. The package structure of the embodiment of the present application is described by taking the reduction or elimination of far-end crosstalk and impedance discontinuity between the first metal ball 3021 and the second metal ball 3022 as an example. Specifically, the first metal ball 3021 is electrically coupled to the first surface of the package substrate 301 through the first solder pad 305, and the second metal ball 3022 is electrically coupled to the first surface of the package substrate 301 through the second solder pad 306.

[0048] The connection component 303 is electrically coupled to the first pad 305 , and thus can be electrically connected to the first metal ball 3021 through the first pad 305 , so as to transmit an electrical signal passing through the first metal ball 3021 .

[0049] Functional component 304 is electrically connected to connecting component 303, and connecting component 303 is electrically connected to first metal ball 3021. Thus, functional component 304 can be electrically connected to first metal ball 3021 via connecting component 303. Functional component 304 includes multiple metal pads and multiple metal traces located above second pad 306. Each metal pad and metal trace can be made of a conductive metal such as copper, aluminum, gold, silver, tungsten, titanium, or alloys of these materials. The shape of each metal pad can be arbitrary, such as a regular shape such as a circle, triangle, semicircle, square, rectangle, or other irregular shapes. The shape of each metal pad in the multiple metal pads can be the same or different. The total area of ​​the multiple metal pads can be set according to process requirements, and the area of ​​each metal pad in the multiple metal pads can be the same or different. Two adjacent metal pads in the multiple metal pads can be connected by at least one metal trace to form a composite metal pad. The number of metal traces connecting two adjacent metal plates can be the same, for example, two metal traces are connected between any two adjacent metal plates. The number of metal traces connecting two adjacent metal plates can also be different, for example, one metal trace is connected between some adjacent metal plates, and two metal traces are connected between some adjacent metal plates. The shape of each metal trace can be any open shape, and the length and width of each metal trace can be determined based on the mutual capacitance generated between the connected metal plate and the second pad, preferably to compensate for the mutual capacitance of the connected metal plates.

[0050] Due to the limited scope of the cross-sectional view, Figure 3 does not fully illustrate the detailed structure of the functional component. Figures 4 and 5 are top views of the functional component. Referring to Figure 4 , the functional component includes metal plates 30411 and 30412, which are electrically connected via metal traces 30421 to form a mutual capacitance-self-inductance-mutual capacitance compensation structure. 5 , the functional components include metal plates 30411, 30412, 30413, and 30414. Metal plates 30411 and 30412 are electrically connected via metal traces 30421, 30412 and 30413 are electrically connected via metal traces 30422, and 30413 and 30414 are electrically connected via metal traces 30423, thereby forming a mutual capacitance-self-inductance-mutual capacitance-self-inductance-mutual capacitance-self-inductance-mutual capacitance compensation structure. Of course, FIG4 and FIG5 are merely exemplary, and the number of metal plates in the embodiments of the present application is not limited to two or four, and can be any number greater than two.

[0051] In the embodiment of the present application, two adjacent metal plates are connected by metal routing to form a mutual capacitance-self-inductance-mutual capacitance compensation unit, thereby reducing far-end crosstalk and impedance discontinuity between the first metal ball and the second metal ball when the electrical signal is transmitted through the first metal ball.

[0052] In another embodiment of the present application, the first pad 305 and the second pad 306 are both located in the first conductive layer among multiple conductive layers, which is any conductive layer among the multiple conductive layers, for example, located in the conductive layer E1 in the packaging structure shown in Figure 3.

[0053] In another embodiment of the present application, referring to FIG6 , the connecting component 303 may include a first through-hole structure 3031 and a second through-hole structure 3032. The first through-hole structure 3031 is located above the first pad 305 and is electrically coupled to the first pad 305. To connect electronic components located in different conductive layers of the package substrate 301, the first through-hole structure 3031 includes at least one conductive pad. Different conductive pads can be located in different conductive layers, and conductive pads in adjacent conductive layers can be electrically connected via metal vias. Referring to FIG6 , the first through-hole structure 3031 includes a conductive pad 303121, a conductive pad 303122, and a conductive pad 303123. The conductive pad 303121 is electrically coupled to the first pad 305 via a metal via 303111. The conductive pad 303122 is electrically connected to the conductive pad 303123 via a metal via 303112. The conductive pad 303123 is coupled to a metal via 303113 or a metal trace 303113.

[0054] Second via structure 3032 is located above first pad 305 but is not electrically coupled thereto. Second via structure 3032 is connected to first via structure 3031 via a metal trace, allowing electrical signals in second via structure 3032 to be transmitted to first via structure 3031. To connect electronic components located in different conductive layers of package substrate 301, second via structure 3032 includes at least one conductive pad. Different conductive pads can be located in different conductive layers, and conductive pads in adjacent conductive layers can be electrically connected via metal vias. Referring to FIG. 6 , second via structure 3032 includes conductive pad 303221 and conductive pad 303222. Conductive pad 303221 is electrically connected to conductive pad 303222 via metal via 30321.

[0055] It's worth noting that there's no connection between the conductive pads 303121 and 303122 in the first through-hole structure 3031. Therefore, the electrical signal passing through the first metal ball 3021 doesn't continue to propagate upward after passing through the conductive pads 303121. The conductive pads 303221 in the second through-hole structure 3032 aren't electrically coupled to the first pad 305. Therefore, the electrical signal passing through the second through-hole structure 3032 is transmitted back to the first through-hole structure 3031, allowing for continued signal transmission. Furthermore, because both the first through-hole structure 3031 and the second through-hole structure 3032 are located directly above the first pad 305, mutual capacitance is generated between them and the first pad 305, thereby reducing or eliminating far-end crosstalk between the first metal ball 3021 and the second metal ball 3022.

[0056] Referring to Figure 6, the functional component 304 also includes a first connecting line 3043 and a second connecting line 3044. The first connecting line 3043 and the second connecting line 3044 can transmit electrical signals and can be made of metal materials. All or part of the first connecting line 3043 and the second connecting line 3044 can be straight, curved, or spiral-shaped, and the length and width of the first connecting line 3043 and the second connecting line 3044 can be set according to process requirements. One end of the first connecting line 3043 is connected to the first metal disk among the multiple metal disks, and the other end is connected to the first through-hole structure 3031. One end of the second connecting line 3044 is connected to the second metal disk among the multiple metal disks, and the other end is connected to the second through-hole structure 3032. The first metal disk and the second metal disk are two metal disks located on the end side of the combined metal disk formed by connecting multiple metal traces. Specifically referring to Figure 6, one end of the first connecting line 3043 is connected to the conductive pad 303121 of the first through-hole structure 3031, and the other end is connected to the metal disk 30411. The metal disk 30411 is connected to the metal disk 30412 through the metal trace 30421. One end of the second connecting line 3044 is connected to the metal disk 30421, and the other end is connected to the conductive pad 303222 in the second through-hole structure 3032.

[0057] In another embodiment of the present application, for the packaging structure shown in Figure 6, multiple metal plates, multiple metal traces, first connecting lines and second connecting lines can be located in the second conductive layer among multiple conductive layers, and the second conductive layer can be the conductive layer E2.

[0058] Based on the package structure shown in FIG6 , the transmission process of the electrical signal in the first metal ball 3021 can be as follows: after passing through the first metal ball 3021, the electrical signal reaches the conductive pad 303121 in the first through-hole structure 3031 through the metal through-hole 303111, and then is transmitted to the metal plate 30411 through the first connecting wire 3043, and then is transmitted from the metal plate 30411 to the metal trace 3042, and then is transmitted to the metal plate 30412 through the metal trace 3042, and then reaches the second through-hole structure 3031 through the second connecting wire 3044 connected to the metal plate 30412. The conductive pad 303221 in the first through-hole structure 3032 is transmitted from the conductive pad 303221 to the metal through-hole 30321, and then from the metal through-hole 30321 to the conductive pad 303222. The conductive pad 303222 is transmitted to the conductive pad 303122 of the first through-hole structure through the metal trace connected to the first through-hole structure 3031. The conductive pad 303122 is transmitted to the metal through-hole 303112, and then from the metal through-hole 303112 to the conductive pad 303123. The conductive pad 303123 is transmitted to other electronic components through the metal through-holes or metal traces.

[0059] In another embodiment of the present application, referring to FIG7 , the connection component 303 may include a first through-hole structure 3031 and a third through-hole structure 3033. The first through-hole structure 3031 is located above the first pad 305 and is electrically coupled to the first pad 305. To connect electronic components located in different conductive layers of the package substrate 301, the first through-hole structure 3031 includes at least one conductive pad. Different conductive pads may be located in different conductive layers, and conductive pads in adjacent conductive layers may be electrically connected via metal through-holes. 7 , the first through-hole structure 3031 includes a conductive pad 303121, a conductive pad 303122, and a conductive pad 303123. The conductive pad 303121 is electrically coupled to the first pad 305 via a metal through-hole 303111. The conductive pad 303122 is electrically connected to the conductive pad 303123 via a metal through-hole 303112. The conductive pad 303123 is coupled to a metal through-hole 303113 or a metal trace 303113.

[0060] The third via structure 3033 is located above and electrically coupled to a third metal disk among the multiple metal disks. The third metal disk can be any of the multiple metal disks, that is, the third metal disk can be the first metal disk, the second metal disk, or any other metal disk other than the first and second metal disks. The third via structure 3033 is connected to the first via structure 3031 via a metal trace, allowing electrical signals in the third via structure 3033 to be transmitted to the first via structure 3031. To connect electronic components located in different conductive layers of the package substrate 301, the third via structure 3032 includes at least one conductive pad. Different conductive pads can be located in different conductive layers, and conductive pads in adjacent conductive layers can be electrically connected via metal vias. Referring to FIG. 7 , the third via structure 3033 includes a conductive pad 303321 and a conductive pad 303322. The conductive pad 303321 is electrically coupled to the metal disk 30412 and electrically connected to the conductive pad 303322 via the metal via 30331.

[0061] It is worth noting that there is no connection between the conductive pads 303121 and 303122 in the first through-hole structure 3031. Therefore, the electrical signal passing through the first metal ball 3021 does not continue to propagate upward after passing through the conductive pad 303121. Furthermore, because the first through-hole structure 3031 is located directly above the first solder pad 305, mutual capacitance is generated between the first through-hole structure 3031 and the first solder pad 305, thereby reducing or eliminating far-end crosstalk between the first metal ball 3021 and the second metal ball 3022. Furthermore, the conductive pad 303322 of the third through-hole structure 3032 is located above the metal plate 30412, thus also generating mutual capacitance with the metal plate 30412, similarly reducing or eliminating far-end crosstalk between the first metal ball 3021 and the second metal ball 3022.

[0062] Referring to FIG7 , the functional component 304 further includes a first connecting line 3043 and a second connecting line 3044. The first connecting line 3043 and the second connecting line 3044 are capable of transmitting electrical signals and can be made of metal materials. All or part of the first connecting line 3043 and the second connecting line 3044 can be straight, curved, or spiral-shaped, and the length and width of the first connecting line 3043 and the second connecting line 3044 can be set according to process requirements. One end of the first connecting line 3043 is connected to a first metal disk among the multiple metal disks, and the other end is connected to the first through-hole structure 3031. One end of the second connecting line 3044 is connected to a second metal disk among the multiple metal disks, and the other end is connected to the third through-hole structure 3033. Specifically referring to Figure 7, one end of the first connecting wire 3043 is connected to the conductive pad 303121 of the first through-hole structure 3031, and the other end is connected to the metal disk 30411. The metal disk 30411 and the metal disk 30412 are connected through the metal trace 30421. One end of the second connecting wire 3044 is connected to the conductive pad 303322 of the third through-hole structure 3031, and the other end is connected to the conductive pad 303122 in the first through-hole structure 3031.

[0063] In another embodiment of the present application, for the package structure shown in FIG7 , the combined metal plates include a first combined structure and a second combined structure. The first combined structure includes a plurality of metal plates, including the first to third metal plates, and the metal traces therebetween. The second combined structure includes a plurality of metal plates, including the fourth to second metal plates, and the metal traces therebetween. The fourth metal plate is the next metal plate adjacent to the third metal plate in the combined metal plates. The first combined structure and the first connecting line are located in a second conductive layer, for example, conductive layer E2, among the plurality of conductive layers. The second combined structure and the second connecting line are located in a third conductive layer, for example, conductive layer E3, among the plurality of conductive layers.

[0064] Based on the packaging structure shown in Figure 7, the transmission process of the electrical signal in the first metal ball 3021 can be as follows: after the electrical signal passes through the first metal ball 3021, it reaches the conductive pad 303121 in the first through-hole structure through the metal through-hole 303111, and then is transmitted to the metal disk 30411 through the first connecting line 3043. Then, it is transmitted from the metal disk 30411 to the conductive pad 303321 of the third through-hole structure electrically coupled with the metal disk 30411. The conductive pad 303321 is transmitted to the conductive pad 303322 through the metal through-hole 30331, and then is transmitted to the conductive pad 303122 in the first through-hole structure through the second connecting line 3044 connected to the conductive pad 303322. Then, it is transmitted from the conductive pad 303122 to the metal through-hole 303112, and then is transmitted from the metal through-hole 303112 to the conductive pad 303123. The conductive pad 303123 is transmitted to other electronic components through the metal through-hole or metal traces.

[0065] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0066] 8 , an embodiment of the present application provides an integrated circuit, which includes: a packaging structure 801 , a printed circuit board 802 , a second ball grid array 803 , and a chip 804 .

[0067] The package structure 801 is as shown in Figures 3 to 7 above. A printed circuit board 802 can be electrically coupled to the package structure 801 via a first ball grid array (BGA) within the package structure 801. A second BGA 803 is located on a second surface of the package substrate within the package structure, the second surface corresponding to the first surface of the package substrate. A chip 804 can be electrically coupled to the package structure 801 via the second BGA 803. The number of second BGAs 803 is the same as the number of chips 804, and the chips 804 can be electrically coupled to the package structure 801, thereby achieving electrical connection between the package structure and the chip, enabling transmission of electrical signals within the integrated circuit.

[0068] Optionally, the integrated circuit may further include a protective film 805 , which is used to wrap the chip 804 , thereby better protecting the chip 804 .

[0069] Of course, the integrated circuit may also include other components, which will not be described one by one here.

[0070] An embodiment of the present application provides a memory including the integrated circuit shown in Figure 8. The memory may be a memory having a high-speed signaling system such as DDR4 or DDR5.

[0071] FIG9 shows a block diagram of an electronic device 900 according to an exemplary embodiment of the present application. Generally, the electronic device 900 includes a processor 901 and a memory 902 .

[0072] The processor 901 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 901 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state; the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 901 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 901 may also include an artificial intelligence processor, which is used to process computing operations related to machine learning.

[0073] The memory 902 may include one or more computer-readable storage media, which may be non-transitory computer-readable storage media. For example, the non-transitory computer-readable storage medium may be a CD-ROM (Compact Disc Read-Only Memory), ROM, RAM (Random Access Memory), magnetic tape, floppy disk, or optical data storage device. The computer-readable storage medium stores at least one computer program, which, when executed, can implement the functions of the electronic device.

[0074] Of course, the electronic device described above may also include other components, such as input / output interfaces and communication components. The input / output interface provides an interface between the processor and a peripheral interface module, which may be an output device, an input device, etc. The communication component is configured to facilitate wired or wireless communication between the electronic device and other devices.

[0075] Those skilled in the art will appreciate that the structure shown in FIG. 9 does not limit the electronic device 900 , and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0076] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0077] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: Package substrate; a first ball grid array, the first ball grid array being located on a first surface of the package substrate, the first ball grid array comprising a first metal ball and a second metal ball adjacent to the first metal ball, the first metal ball being electrically coupled to the first surface via a first pad, and the second metal ball being electrically coupled to the first surface via a second pad; a connecting component electrically coupled to the first pad; A functional component, wherein the functional component is connected to the first metal ball through the connecting component, the functional component includes multiple metal disks and multiple metal traces located above the second pad, and two adjacent metal disks are connected by at least one metal trace, and the functional component is used to reduce far-end crosstalk and impedance discontinuity between the first metal ball and the second metal ball when an electrical signal is transmitted through the first metal ball.

2. The packaging structure according to claim 1, wherein: The packaging substrate has multiple conductive layers and multiple dielectric layers, which are stacked along the vertical direction of the packaging substrate, and two adjacent conductive layers are isolated by the dielectric layer. The first solder pad and the second solder pad are both located in the first conductive layer among the multiple conductive layers.

3. The packaging structure according to claim 2, wherein: The connecting component includes a first through-hole structure and a second through-hole structure; The first through-hole structure is located above the first pad and is electrically coupled to the first pad; The second through-hole structure is located above the first pad but is not electrically coupled to the first pad. The second through-hole structure is connected to the first through-hole structure through a metal trace.

4. The packaging structure according to claim 3, wherein: The functional component further includes a first connecting line and a second connecting line; One end of the first connecting wire is connected to the first metal disk among the plurality of metal disks, and the other end is connected to the first through-hole structure; One end of the second connecting wire is connected to the second metal disk among the plurality of metal disks, and the other end is connected to the second through-hole structure; The first metal plate and the second metal plate are two metal plates located on the end side of a combined metal plate formed by connecting the plurality of metal traces.

5. The packaging structure according to claim 4, wherein: The plurality of metal plates, the plurality of metal traces, the first connecting line, and the second connecting line are all located in a second conductive layer among the plurality of conductive layers.

6. The packaging structure according to claim 1, wherein: The connecting component includes a first through-hole structure and a third through-hole structure; The first through-hole structure is located above the first pad and is electrically coupled to the first pad; The third through-hole structure is located above a third metal plate among the plurality of metal plates and is electrically coupled to the third metal plate. The third metal plate is any one of the plurality of metal plates.

7. The packaging structure according to claim 6, wherein: The functional component further includes a first connecting line and a second connecting line; One end of the first connecting wire is connected to the first metal disk among the plurality of metal disks, and the other end is connected to the first through-hole structure; One end of the second connecting wire is connected to the second metal disk among the plurality of metal disks, and the other end is connected to the third through-hole structure; The first metal plate and the second metal plate are two metal plates located on the end side of a combined metal plate formed by connecting the plurality of metal traces.

8. The packaging structure according to claim 7, wherein: The combined metal plate includes a first combined structure and a second combined structure, wherein the first combined structure includes a plurality of metal plates from the first metal plate to the third metal plate and metal traces therebetween, and the second combined structure includes a plurality of metal plates from the fourth metal plate to the second metal plate and metal traces therebetween, wherein the fourth metal plate is the next metal plate adjacent to the third metal plate in the combined metal plate; The first combined structure and the first connecting line are located in a second conductive layer among the plurality of conductive layers, and the second combined structure and the second connecting line are located in a third conductive layer among the plurality of conductive layers.

9. The packaging structure according to claim 4 or 7, characterized in that: The first connecting line, the second connecting line, and the plurality of metal traces are in any open, random shape.

10. An integrated circuit, characterized in that: The integrated circuit comprises: A packaging structure, the packaging structure comprising the packaging structure according to any one of claims 1 to 9; a printed circuit board, the printed circuit board being electrically coupled to the packaging structure through the first ball grid array in the packaging structure; a second ball grid array, the second ball grid array being located on a second surface of the package substrate in the package structure, the second surface being a surface corresponding to the first surface of the package substrate; A chip is electrically coupled to the packaging structure through the second ball grid array.

11. A memory, characterized in that: The memory comprises the integrated circuit of claim 10.

12. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory is the memory according to claim 11, and the memory is used to store at least one program code, and the at least one program code is loaded and executed by the processor to realize the function of the electronic device.

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