Memory controller, memory chip, memory system, and electronic device

Abstract

A memory controller, a memory chip, a memory system, and an electronic device, relating to the technical field of storage. The memory controller is connected to the memory chip, the memory chip comprises a peripheral circuit and a plurality of memory cells, and each memory cell comprises a memory device and a gating device. The memory controller is configured to: control the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the refresh voltage being used for turning on a gating device in a first memory cell so as to reduce a threshold switching voltage of the gating device, and the first memory cell being a memory cell in which a corresponding memory device is in a low resistance state (501); and control the peripheral circuit to apply a read voltage to at least one memory cell to obtain a read result (502). The impact of the drift of a threshold switching voltage of a gating device on a memory cell can be avoided, thereby improving the accuracy of reading the memory cell.

Description

Storage controllers, storage chips, storage systems, and electronic devices

[0001] This application claims priority to Chinese patent application No. 202410268669.2 filed on March 8, 2024, entitled “Storage Controller, Memory Chip, Storage System and Electronic Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage controller, a storage chip, a storage system and an electronic device. Background Art

[0003] The one selector one resistor (1S1R) memory cell in the phase change memory chip consists of a phase change memory (PCM) and an ovonic threshold switch (OTS).

[0004] When a 1S1R memory cell stores a "0," it is in a high-resistance state with a higher threshold voltage. When a 1S1R memory cell stores a "1," it is in a low-resistance state with a lower threshold voltage. Therefore, the data stored in the 1S1R memory cell can be determined by detecting its threshold voltage.

[0005] The threshold voltage of the 1S1R memory cell is related to the threshold voltage of the PCM and the threshold transition voltage of the OTS. Changes in the threshold voltage of the PCM or the threshold transition voltage of the OTS will affect the threshold voltage of the 1S1R memory cell.

[0006] The threshold transition voltage of the OTS exhibits significant drift. For example, after each read or write operation on a 1S1R memory cell, the threshold transition voltage of the OTS slowly increases over time. When the 1S1R memory cell is read or written again, the threshold transition voltage of the OTS returns to its pre-increase value. This drift in the threshold transition voltage of the OTS affects the threshold voltage of the 1S1R memory cell, increasing the probability of errors when reading from the 1S1R memory cell. Summary of the Invention

[0007] The embodiments of the present application provide a storage controller, a storage chip, a storage system, and an electronic device, which can reduce the error probability of reading a storage unit. The corresponding technical solutions are as follows:

[0008] In a first aspect, a memory controller is provided. The memory controller is connected to a memory chip, the memory chip including peripheral circuits and a plurality of memory cells, each of which includes a storage device and a gating device. The memory controller is configured to: control the peripheral circuits to apply a refresh voltage to at least one memory cell to be read, the refresh voltage being used to turn on the gating device in the first memory cell to lower the threshold transition voltage of the gating device; the first memory cell being a memory cell whose corresponding storage device is in a low-resistance state; and control the peripheral circuits to apply a read voltage to the at least one memory cell to obtain a read result.

[0009] In the solution described in this application, when performing a read operation on a memory cell, the memory controller can first control the peripheral circuitry of the memory chip to apply a refresh voltage to the memory cell to be read, thereby turning on the gating device included in the memory cell and refreshing the threshold transition voltage of the gating device to a lower level. This way, when the peripheral circuitry is then controlled to perform a read operation on the memory cell using the read voltage, the effect of drift in the threshold transition voltage of the gating device on the memory cell can be avoided, thereby improving the accuracy of memory cell reading.

[0010] In one achievable manner, before controlling the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the storage controller is further used to: control the peripheral circuit to sequentially apply multiple levels of read voltages to at least one memory cell to be read, and determine that the read results obtained after applying each level of read voltage meet the read failure condition, wherein the voltage values ​​of the applied multiple levels of read voltages increase sequentially and are less than the refresh voltage.

[0011] In the solution described in this application, after a normal read operation fails on a memory cell, a refresh voltage can be applied before retrying the read operation on the memory cell. This eliminates the need to apply a refresh voltage before each read operation on the memory cell, improving the efficiency of the read operation and reducing the power consumption of the memory chip.

[0012] In one achievable manner, the storage controller is used to: control the peripheral circuit to apply a refresh voltage to a second storage cell in at least one storage cell, where the second storage cell refers to a storage cell whose corresponding storage device is read as a high-impedance state after applying a multi-level read voltage.

[0013] The read result obtained after applying multiple read voltages to a memory cell can indicate whether the memory device included in the memory cell is in a low-resistance state or a high-resistance state. For memory cells indicated in the read result as corresponding to the memory device being in the low-resistance state, the memory cell is a memory cell that is turned on after the read voltage is applied. That is, the gating device in the memory cell is turned on by the read voltage, meaning that the threshold transition voltage of the gating device in the memory cell has been refreshed. For memory cells indicated in the read result as corresponding to the memory device being in the high-resistance state, the memory cell is a memory cell that is not turned on after the read voltage is applied. Some of these non-conducting memory cells may not be turned on due to drift in the threshold transition voltage of the gating device. In other words, memory cells that experience read errors due to drift in the threshold transition voltage of the gating device are all memory cells indicated in the read result as corresponding to the memory device being in the high-resistance state. Therefore, by controlling the application of the refresh voltage to only these memory cells, the accuracy of memory cell read operations can be improved and the power consumption of the memory chip can be reduced.

[0014] In one achievable manner, the read failure condition includes that the number of storage cells corresponding to read error results in the read result exceeds a threshold value.

[0015] In one achievable manner, the read failure condition includes that a difference between a check code generated for a read result and a check code generated when storing data in at least one storage unit is greater than a first difference threshold.

[0016] In one achievable manner, the absolute value of the difference between the refresh voltage and the threshold voltage corresponding to the memory cell in the high-resistance state is smaller than the second difference threshold.

[0017] In the solution shown in the present application, the refresh voltage is as close as possible to the threshold voltage corresponding to the high-resistance memory cell. This can not only turn on the selection device in the low-resistance memory cell whose threshold transition voltage has already had a large offset, but also avoid the refresh voltage causing read disturb to the high-resistance memory cell.

[0018] In a second aspect, a memory chip is provided, comprising a peripheral circuit and a plurality of memory cells, each memory cell comprising a memory device and a gating device. The peripheral circuit is configured to: upon receiving a refresh voltage application instruction, apply a refresh voltage to at least one memory cell to be read, the refresh voltage being used to turn on the gating device in a first memory cell to lower the threshold transition voltage of the gating device, the first memory cell being a memory cell in which the corresponding memory device is in a low-resistance state; and apply a read voltage to the at least one memory cell to obtain a read result. The refresh voltage application instruction may be sent to the peripheral circuit by a memory controller connected to the memory chip.

[0019] In one achievable embodiment, the peripheral circuit includes a control circuit and a driver circuit. The driver circuit includes multiple driver devices, each of which is connected to a portion of memory cells in a memory chip via word lines and bit lines. The lengths of the bit lines and word lines between each driver device and the connected memory cell are less than a length threshold. The control circuit is configured to control the driver device connected to at least one memory cell to apply a refresh voltage to the at least one memory cell.

[0020] In the solution shown in the present application, the driving device can be used to apply a refresh voltage to the memory cell. The word line and bit line between the driving device and the memory cell are less than the length threshold, which can reduce the voltage division of the word line and bit line on the refresh voltage, so that the refresh voltage applied by the driving device acts more on the memory cell, which can reduce power consumption and improve the effect of applying the refresh voltage to the memory cell.

[0021] In one achievable embodiment, the driving circuit further includes a power supply, and the driving device includes a capacitor. The control circuit is configured to control the power supply to charge the capacitors connected to the plurality of storage cells to a refresh voltage, and then control the capacitor connected to at least one storage cell to discharge the capacitor to the at least one storage cell via a word line and a bit line.

[0022] In the scheme shown in the present application, the driving device can be a capacitor. Each capacitor can be pre-charged to a refresh voltage before the read operation triggers a read failure condition. When the read operation triggers the read failure condition, the capacitor can be controlled to discharge to the storage cell, thereby improving the efficiency of applying the refresh voltage to the storage cell.

[0023] In one achievable manner, the driving device may include a plurality of capacitors connected in series. Thus, when precharging the capacitors, the plurality of capacitors connected in series may be precharged simultaneously, thereby improving the efficiency of precharging the capacitors.

[0024] In one achievable manner, the driving device includes a power supply, and the control circuit is configured to control the power supply connected to the at least one memory cell to apply a refresh voltage to the at least one memory cell.

[0025] In a third aspect, a method for controlling a memory controller is provided, wherein the memory controller is connected to a memory chip, the memory chip including a peripheral circuit and a plurality of memory cells, each memory cell including a storage device and a gating device, the method comprising:

[0026] Controlling the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, wherein the refresh voltage is used to turn on a gating device in a first memory cell to reduce a threshold transition voltage of the gating device, wherein the first memory cell refers to a memory cell whose corresponding storage device is in a low-resistance state; controlling the peripheral circuit to apply a read voltage to the at least one memory cell to obtain a read result.

[0027] In one feasible manner, before controlling the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the method further includes: controlling the peripheral circuit to sequentially apply multiple levels of read voltages to the at least one memory cell to be read, and determining that the read results obtained after applying each level of read voltage meet the read failure condition, wherein the voltage values ​​of the applied multiple levels of read voltages increase sequentially and are less than the refresh voltage.

[0028] In one feasible manner, controlling the peripheral circuit to apply a read voltage to the at least one memory cell includes: controlling the peripheral circuit to apply a refresh voltage to a second memory cell in the at least one memory cell, wherein the second memory cell refers to a memory cell whose corresponding memory device is read as a high-impedance state after applying multiple levels of read voltages.

[0029] In one achievable manner, the read failure condition includes that the number of storage units corresponding to read error results in the read result exceeds a threshold value.

[0030] In one achievable manner, the read failure condition includes that a difference between a check code generated for the read result and a check code generated when storing data in the at least one storage unit is greater than a difference threshold.

[0031] In a fourth aspect, a storage system is provided, which includes one or more storage controllers as described in the first aspect and / or any implementable embodiment of the first aspect, and a storage chip connected to the storage controller.

[0032] In a fifth aspect, an electronic device is provided, comprising a processor and the storage system as described in the fourth aspect, wherein the processor is configured to send read and write instructions to the storage system so that the storage system performs read and write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic structural diagram of a memory chip provided in an embodiment of the present application;

[0034] FIG2 is a schematic structural diagram of a peripheral circuit provided in an embodiment of the present application;

[0035] FIG3 is a schematic structural diagram of a storage system provided in an embodiment of the present application;

[0036] FIG4 is a threshold voltage distribution diagram of a 1S1R memory cell provided in an embodiment of the present application;

[0037] FIG5 is a flow chart of a method for controlling a memory chip provided in an embodiment of the present application;

[0038] FIG6 is a flow chart of a method for controlling a memory chip provided in an embodiment of the present application;

[0039] FIG7 is a flow chart of a method for controlling a memory chip provided in an embodiment of the present application;

[0040] FIG8 is a timing diagram of applying UOPXX provided in an embodiment of the present application;

[0041] FIG9 is a schematic structural diagram of a driving circuit provided in an embodiment of the present application;

[0042] FIG10 is a schematic structural diagram of a driving device provided in an embodiment of the present application;

[0043] FIG11 is a schematic structural diagram of a driving device provided in an embodiment of the present application;

[0044] FIG12 is a schematic structural diagram of a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0046] To facilitate understanding of the memory chip and the memory chip control method provided in the embodiments of the present application, some terms involved in the embodiments of the present application are explained below:

[0047] Phase Change Memory (PCM): A new type of non-volatile semiconductor memory based on chalcogenides that utilizes the electrical properties of the crystalline and amorphous phase change materials to store "0" and "1." When the phase change material is in the crystalline state, it is in a high-resistance state, meaning it has a high resistance value, defined as the RESET (0) state. When the phase change material is in the amorphous state, it is in a low-resistance state, meaning it has a low resistance value, defined as the SET (1) state.

[0048] Ovonic Threshold Switch (OTS): A novel bidirectional gating device based on chalcogenides. When an electrical pulse in either positive or negative direction, below the threshold voltage, is applied to the OTS, the response current is low, resulting in a high-resistance, non-conducting state. When an electrical pulse in either positive or negative direction, above the threshold voltage, is applied to the OTS, the response current is high, resulting in a low-resistance, conducting state.

[0049] 1S1R memory cell: A memory cell consisting of an OTS and a PCM. In one implementation, when the PCM in the 1S1R memory cell is in the RESET (0) state, the 1S1R memory cell stores "0" and, in this case, the 1S1R memory cell has a higher threshold voltage, Vthr. When the PCM in the 1S1R memory cell is in the SET (1) state, the 1S1R memory cell stores "1" and, in this case, the 1S1R memory cell has a lower threshold voltage, Vths. Vthr is equal to the threshold transition voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET (0) state, and Vths is equal to the threshold transition voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET (1) state.

[0050] Based on the above characteristics, it can be seen that when a 1S1R memory cell stores a "0," the 1S1R device cell responds with a small current at a specific read voltage Vread (greater than Vths and less than Vthr). When a 1S1R memory cell stores a "1," the 1S1R device cell responds with a large current at a specific read voltage Vread. In this way, the data stored in the 1S1R memory cell can be read by applying the read voltage Vread.

[0051] Write operation: This is achieved by applying a high-amplitude, narrow-width electric pulse to the 1S1R memory cell. The amplitude of this electric pulse is higher than the threshold transition voltage of the OTS. Under the action of this electric pulse, the temperature of the PCM in the 1S1R memory cell is rapidly raised to above the melting point and then suddenly cooled. Because the microscopic atoms do not have sufficient time to crystallize, they remain in a high-resistance amorphous state, which realizes the storage of "0".

[0052] The erase operation is achieved by applying an electric pulse with a lower amplitude than the write operation but a longer duration to the 1S1R memory cell. The amplitude of this electric pulse is higher than the threshold transition voltage of the OTS. Under the action of this electric pulse, the temperature of the PCM in the 1S1R memory cell is raised to above the crystallization temperature but below the melting temperature. The PCM can then transform into a low-resistance state through a thermally induced crystallization process, thus realizing the storage of "1".

[0053] Read operation: Data stored in the 1S1R memory cell can be read by applying a fixed read voltage Vread across the 1S1R memory cell and according to the response current of the 1S1R memory cell.

[0054] Word line: The signal line required to select a row of 1S1R memory cells in the memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.

[0055] Bit line: A signal line used to select a column in a memory array. It works in conjunction with the word line to select a 1S1R memory cell. By applying corresponding electrical pulses to the word and bit lines, write, erase, or read operations can be performed on the selected 1S1R memory cell.

[0056] OTS threshold transition voltage drift: The threshold transition voltage of OTS is affected by the voltage applied to OTS and the ambient temperature during the time from the last turn-on to the current turn-on, and thus changes, which is called OTS threshold transition voltage drift.

[0057] The OTS exhibits a high current conduction capability when subjected to voltages above the corresponding threshold voltage. This is caused by the transition of equilibrium, non-conducting electrons in a low-energy state to a high-energy, non-equilibrium, conductive state under high voltage. When the threshold voltage is removed, the high-energy non-equilibrium carriers in the OTS, excited by the threshold transition voltage, do not all return to equilibrium instantly. Instead, they gradually return to a low-energy, equilibrium, non-conducting state with a certain probability. Therefore, after each operation on the 1S1R memory cell, the threshold transition voltage of the OTS in the 1S1R memory cell decreases suddenly and then gradually increases over time. The higher the ambient temperature of the OTS, the faster its threshold voltage drifts. Furthermore, if the OTS is left unused for a long time, its threshold transition voltage will also drift to a higher state.

[0058] FIG1 is a schematic diagram of the structure of a memory chip provided in an embodiment of the present application. As shown in FIG1 , the memory chip 100 includes at least one memory array 110 and a peripheral circuit 120. The memory array 110 includes a plurality of memory cells distributed in an array. Among the plurality of memory cells, memory cells in the same row are connected to the same word line (WL), and memory cells in the same column are connected to the same bit line (BL). Each memory cell may be composed of a memory device and a gating device. The memory device may be a resistive memory device, such as a phase change memory, a ferroelectric memory, a magnetic random access memory, and a resistive random access memory. The gating device may be a bidirectional threshold switch. When the memory device is a PCM, the memory cell may be referred to as a 1S1R memory cell, and the memory chip may be referred to as a phase change memory chip. The memory chip 100 shown in the embodiment of the present application may be a two-dimensional memory chip, i.e., the memory chip includes a single memory array 110, or a three-dimensional memory chip, i.e., the memory chip includes multiple memory arrays 110.

[0059] FIG2 is a schematic diagram of a peripheral circuit 120 provided in an embodiment of the present application. As shown in FIG2 , the peripheral circuit 120 includes a control circuit 121 , a read / write driver circuit 122 , a word line control circuit 123 , and a bit line control circuit 124 .

[0060] After receiving an operation request corresponding to a read operation, a write operation, or an erase operation, the control circuit 121 can control the read / write drive circuit 122 to apply an operation voltage corresponding to the read operation, the write operation, or the erase operation to one or more storage units corresponding to the operation request, so as to implement the read operation, the write operation, or the erase operation on the storage unit.

[0061] The read / write driver circuit 122 can select a memory cell corresponding to an operation request by controlling the word line control circuit 123 and the bit line control circuit 124 , and then apply a corresponding operation voltage to the selected memory cell.

[0062] The word line control circuit 123 includes a word line switch circuit 1231 and a first sensing circuit 1232. The bit line control circuit 124 includes a bit line switch circuit 1241 and a second sensing circuit 1242. The word line switch circuit 1231 is connected to each word line in the memory array 110 via a switch (not shown in FIG. 2 ). The word line control circuit 123 can turn on the word line connected to the selected memory cell. The bit line switch circuit 1241 is connected to each bit in the memory array 110 via a switch (not shown in FIG. 2 ).

[0063] Among them, the word line control circuit 1231 can turn on the switch tube corresponding to the word line connected to a storage unit, and the bit line switch circuit 1241 can turn on the switch tube corresponding to the bit line connected to the storage unit, thereby selecting the storage unit so that the read-write drive circuit 122 applies the corresponding operating voltage to the selected storage unit.

[0064] The first sensing circuit 1232 or the second sensing circuit 1242 can be used to detect the current on the word line or bit line connected to the selected memory cell, thereby realizing the perception of the storage state corresponding to the memory cell.

[0065] A memory controller is also a hardware device used to control the read and write operations of a memory chip. The memory controller can send read, write, or erase operation requests to the memory chip, enabling the peripheral circuitry in the memory chip to select a memory cell via word lines and bit lines and apply a read voltage, write voltage, or erase voltage to the selected memory cell to perform the corresponding read, write, or erase operation. The memory controller can also receive the read results of the read operation performed by the peripheral circuitry and perform verification and error correction on the read results.

[0066] The memory controller and memory chips can form a memory system. Figure 3 is a schematic diagram of a memory system provided by an embodiment of the present application. As shown in Figure 3, the memory system includes a memory controller and one or more memory chips as shown in Figure 1.

[0067] FIG4 is a diagram showing the threshold voltage distribution of a 1S1R memory cell under different conditions provided by an embodiment of the present application. As shown in FIG4:

[0068] Ideally, each 1S1R memory cell in a memory chip has a corresponding threshold voltage distribution when storing "1" or "0." That is, there is a clear window between the threshold voltage distribution of a 1S1R memory cell storing "1" and the threshold voltage of a 1S1R memory cell storing "0." In this case, by applying a read voltage Vread to the memory cell, it is possible to accurately determine whether the 1S1R memory cell stores "0" or "1."

[0069] However, when the threshold transition voltage corresponding to the selection device of some memory cells in the memory chip drifts, the threshold voltage of these memory cells will increase. This may cause the threshold voltage corresponding to some low-resistance memory cells (that is, memory cells storing "1", that is, memory cells whose corresponding memory devices are in a low-resistance state) to be greater than the read voltage Vread. In this way, when the memory cells are read using the read voltage Vread, Vread cannot turn on the memory cells storing "1" and whose corresponding threshold transition voltage drift is too large, causing these memory cells storing "1" to be read as "0". In this way, the read voltage Vread cannot accurately distinguish whether the 1S1R memory cell stores "0" or "1", which seriously affects the accuracy of memory chip reading.

[0070] An embodiment of the present application provides a method for controlling a storage controller, which can be applied to and executed by the above-mentioned storage controller. The storage controller can be connected to a storage chip, wherein the storage chip can include a peripheral circuit and a storage array, the storage array includes multiple storage cells, and each storage cell includes a storage device and a gating device. Figure 5 is a flow chart of a method for controlling a storage controller provided by an embodiment of the present application, which can be executed by the storage controller. Referring to Figure 5, the method includes:

[0071] Step 501: The memory controller controls the peripheral circuit to apply a refresh voltage to at least one memory cell to be read. The refresh voltage is used to turn on a gating device in a first memory cell to reduce a threshold transition voltage of the gating device. The first memory cell refers to a memory cell whose corresponding memory device is in a low-resistance state.

[0072] The refresh voltage can be determined based on the maximum voltage drift corresponding to the threshold transition voltage of the gating device. For example, when the refresh voltage is greater than the maximum drift of the threshold transition voltage of the gating device, the threshold voltage of the memory cell in the low-resistance state to which the gating device belongs. In this way, it can be ensured that after the refresh voltage is applied to the memory cell, the refresh voltage can turn on any corresponding memory cell in the low-resistance state of the memory device, that is, it can turn on the corresponding memory device. In addition, the maximum refresh voltage does not exceed the minimum write voltage for performing a write operation on the memory cell. In this way, it can be avoided that the refresh voltage performs a write operation on the memory cell, thereby changing the storage state of the memory cell.

[0073] In one example, the absolute value of the difference between the refresh voltage and the threshold voltage corresponding to the memory cell in the high-resistance state is less than a second difference threshold. The second difference threshold can be pre-set by a technician, for example, it can be 0.3V. Since the threshold voltage corresponding to the memory cell in the high-resistance state is relatively large relative to the read voltage, when the voltage value of the refresh voltage is close to the threshold voltage corresponding to the memory cell in the high-resistance state, it can ensure that the refresh voltage turns on the gating device that generates the threshold transition voltage drift in the memory cell in the low-resistance state. When the refresh voltage is less than the threshold voltage corresponding to the memory cell in the high-resistance state, it can also avoid the refresh voltage being too large and causing read interference to the memory cell. When the refresh voltage is greater than the threshold voltage corresponding to the memory cell in the high-resistance state, it can also avoid the problem that the drift corresponding to the threshold transition voltage of the gating device in the memory cell in the low-resistance state is too large and the gating device cannot be turned on.

[0074] Step 502: The memory controller controls the peripheral circuit to apply a read voltage to at least one memory cell to obtain a read result.

[0075] In practice, when the memory controller controls the peripheral circuit to perform a read operation on a memory cell to be read in the memory chip, it can first send a refresh voltage application instruction to the peripheral circuit, causing the peripheral circuit to apply a refresh voltage to the memory cell to be read. In this way, the refresh voltage can turn on the gating device in the low-resistance memory cell that causes the threshold transition voltage to drift, thereby refreshing the threshold transition voltage of the gating device to a lower level. Therefore, after the memory controller controls the peripheral circuit to apply the refresh voltage to the memory cell to be read, and then controls the peripheral circuit to apply the read voltage to perform a read operation, the impact of threshold transition voltage drift on the read result can be avoided, thereby improving the accuracy of the read operation.

[0076] It should be noted that because the threshold voltage of a high-resistance memory cell is always higher than the corresponding read voltage, any drift in the threshold transition voltage of the gating device in the high-resistance memory cell will not affect the read result. Therefore, the accuracy of the read operation can be improved by only addressing the threshold transition voltage drift of the gating device in the low-resistance memory cell.

[0077] In the above embodiment, the memory cell is refreshed by applying a refresh voltage before reading data to prevent the selection device from drifting and causing reading errors. In other embodiments, the memory cell may be refreshed by applying a refresh voltage after multiple read failures. The specific implementation is shown in FIG6 .

[0078] FIG6 is a flow chart of a control method for a storage controller provided in an embodiment of the present application. The method can be executed by the storage controller. Referring to FIG6 , the method includes:

[0079] Step 601: The memory controller controls the peripheral circuit to apply a read voltage to at least one selected memory cell to obtain a first read result corresponding to the at least one memory cell.

[0080] In practice, the peripheral circuit can perform read and write operations on batches of memory cells. The number of memory cells that can be read and written at one time can be pre-set by a technician. For example, multiple memory cells connected to the same word line or bit line can be read and written at one time. The at least one memory cell in step 601 is the memory cell corresponding to the peripheral circuit's read operation at one time. Generally, to improve read operation efficiency, the at least one memory cell is a plurality of memory cells.

[0081] When the memory controller controls the peripheral circuit to perform a read operation on multiple memory cells, the peripheral circuit can select the multiple memory cells that need to be read through the word lines and bit lines, and then implement the read operation on the multiple memory cells by applying a read voltage to the word lines and bit lines. After applying the read voltage to the word lines and bit lines, the current on the word lines or bit lines connected to each memory cell can be sensed by the sensing circuit included in the peripheral circuit. The memory cell whose corresponding current is greater than the set current threshold is the memory cell storing "1", and the memory cell whose corresponding current is less than the set current threshold is the memory cell storing "0". The read result corresponding to each memory cell can be recorded in the first read result, that is, whether each memory cell stores "1" or "0".

[0082] Step 602: In response to the first read result satisfying the read fail condition, the memory controller controls the peripheral circuit to apply a refresh voltage to at least one memory cell, where the refresh voltage is used to turn on a gating device in a memory cell in a low-resistance state.

[0083] In one example, the read failure condition includes that the number of storage cells corresponding to read error results in the first read result exceeds a threshold value.

[0084] In implementation, the multiple storage cells corresponding to a read operation and a write operation may be the same. Therefore, after performing a write operation on a batch of storage cells, the number of storage cells in which "1" is written and the number of storage cells in which "0" is written can be recorded. When a read operation is performed on the same batch of storage cells next time, the number of storage cells in which "1" is read and the number of storage cells in which "0" is read can be determined based on the first read result. If the number of storage cells determined to be read as "1" by the read operation is different from the number of storage cells written as "1" recorded by the write operation, or the number of storage cells determined to be read as "0" by the read operation is different from the number of storage cells written as "0" recorded by the write operation, then it indicates that the result of the read error is stored in the first storage cell. The difference between the number of storage cells that read "1" determined by the read operation and the number of storage cells that write "1" recorded by the write operation, or the difference between the number of storage cells that read "0" determined by the read operation and the number of storage cells that write "0" recorded by the write operation, is the number of storage cells corresponding to the read error result in the first read result.

[0085] After determining that the number of storage cells corresponding to the error results read in the first read result exceeds a number threshold, the storage controller can determine that the first read result meets the read failure condition. The number threshold can be set according to the error correction capability of the error correction algorithm set in the memory chip. The storage controller is generally provided with an error correction algorithm, such as an Error Correcting Code (ECC) algorithm, a Low Density Parity Check (LDPC) algorithm, etc. If the error results included in the read result are within a certain range, the error correction algorithm can implement error correction of the error results of this part in software. Therefore, after the number of storage cells corresponding to the error results read in the first read result exceeds the maximum number that the error correction algorithm can correct, a refresh voltage can be applied to the read storage cell to refresh the threshold transition voltage of the selection device in the storage cell, and then the read operation is performed on the storage cell again.

[0086] In one example, the read fail condition includes a difference between a check code generated for the first read result and a check code generated when storing data in at least one memory cell being greater than a first difference threshold.

[0087] In implementation, after performing a write operation on a batch of memory cells, the memory controller can generate a check code corresponding to the write operation using a check algorithm. The check algorithm can be an ECC check algorithm, an LDPC check algorithm, or the like, and the check code is related to the write data corresponding to the write operation. The next time a read operation is performed on the same batch of memory cells, a check code corresponding to the first read result can be generated again using the check algorithm. The check code corresponding to the write operation and the check code corresponding to the read operation can then be compared. If the difference is greater than a set first difference threshold, it indicates that the number of memory cells corresponding to the read error results in the first read result is relatively large, meaning that the first read result meets the read failure condition. The first difference threshold can also be set based on the error correction capability of the error correction algorithm set in the memory chip. Therefore, after determining that the check code corresponding to the operation and the check code corresponding to the read operation are greater than the set first difference threshold, the memory controller can control the peripheral circuit to apply a refresh voltage to the read memory cell to refresh the threshold transition voltage of the selection device in the memory cell, and then perform a read operation on the memory cell again.

[0088] Step 603: The memory controller controls the peripheral circuit to apply a read voltage to at least one memory cell again to obtain a second read result.

[0089] After a read operation meets a read failure condition, a refresh voltage is applied to the memory cells corresponding to the read operation, turning on the gating devices included in each low-resistance memory cell. Consequently, even if the threshold transition voltage of these gating devices has a significant drift, it is refreshed to a lower level, i.e., a threshold transition voltage without voltage drift. Thus, when a read operation is performed on the memory cell again, the gating devices in the low-resistance memory cell will not experience a drift in the threshold transition voltage, thereby preventing the impact of threshold transition voltage drift on the read result, thereby improving the accuracy of the memory chip's read operation.

[0090] In one achievable manner, in step 602 , the memory controller may also apply a refresh voltage to a memory cell in a high-resistance state in the at least one memory cell according to the first read result.

[0091] The first read result obtained in step 601 includes a result indicating whether the read memory cell is in a high-resistance state or a low-resistance state. If the first read result satisfies a read failure condition, this indicates that some memory cells in a low-resistance state in the first read result have been identified as being in a high-resistance state due to a shift in the threshold transition voltage of the gating device. Even if the threshold transition voltage of the gating device in a high-resistance memory cell shifts, the threshold voltage of the high-resistance memory cell is still greater than the read voltage, meaning that the high-resistance memory cell will still be identified as being in a high-resistance state.

[0092] That is, among the memory cells identified as being in a low-resistance state in the first read result, there are no memory cells that have read errors due to drift in the threshold transition voltage of the gating device. Furthermore, the memory cells identified as being in a low-resistance state indicate that the gating device in the corresponding memory cell has been turned on, that is, the threshold transition voltage of the gating device in the memory cells identified as being in a low-resistance state in the first read result has been refreshed to the threshold transition voltage before drift. However, among the memory cells identified as being in a high-resistance state in the first read result, there are memory cells that have read errors due to drift in the threshold transition voltage of the gating device, that is, low-resistance memory cells are mistakenly identified as high-resistance memory cells. In other words, all memory cells that have read errors are in the memory cells identified as being in a high-resistance state in the first read result.

[0093] Therefore, when the memory controller controls the peripheral circuit to apply the refresh voltage, the refresh voltage can be applied only to the memory cells identified as being in a high-resistance state in the first read result. In this way, among the memory cells identified as being in a high-resistance state in the first read result, the gate devices of the memory cells that were mistakenly identified as being in a low-resistance state will be turned on, and the threshold transition voltages of the gate devices of these memory cells will be refreshed to the threshold transition voltages that would be present if no drift occurred.

[0094] Therefore, when the peripheral circuit is controlled to perform a read operation on the memory cells again, the threshold transition voltages of the selection devices in the low-resistance memory cells have all been refreshed to the threshold transition voltages before drift. This can prevent the impact of threshold transition voltage drift on the read results, thereby improving the accuracy of the memory chip's read operations. In addition, by applying the refresh voltage only to the memory cells identified as being in a high-resistance state in the first read result, the power consumption of the memory chip can be further reduced.

[0095] In one achievable manner, the read voltage in step 601 can be a multi-level read voltage, and the voltage values ​​of the multi-level read voltages increase sequentially. The control method for the memory chip provided in the embodiment of the present application is further described below with reference to FIG. 7 and taking the case where the read voltage is divided into three levels as an example:

[0096] For a selected target memory cell in a memory array, assuming that the target memory cell has drifted for a certain period of time in an initial state, the control circuit can select the logical address corresponding to the target memory cell, set the test read enable to 1, and apply a normal read voltage to the target memory cell. A specific implementation includes a read driver circuit applying a read voltage UOP11 to the target memory cell. The first level of the multi-level read voltage in UOP11 is characterized by ensuring that the error rate of reading 0x55 and 0xaa within the drift time of 1us to 10ms is the lowest possible read voltage after the memory cell undergoes an operation refresh (i.e., after the gating device in the memory cell is turned on), and the threshold voltage of the entire memory cell reaches the lowest possible read voltage within the drift time of 1us to 10ms. Experimental measurements show that UOP11 shows that after the hexadecimal values ​​of 0x55 and 0xaa are converted to binary storage, the number of "0" and "1" stored is relatively evenly distributed.

[0097] If no true uncorrected error (UCE) is triggered during the reading process using UOP11, the data read by UOP11 is directly read out. If UCE is triggered during the reading process using UOP11, it is necessary to implement a read drive circuit to apply a read voltage UOP21 to the target memory cell. Among them, the second-level read voltage in the multi-level read voltage in the UOP21 is characterized by the memory cell being refreshed after the operation, and the threshold voltage of the entire memory cell being within the drift time of 10ms to 10s, which can ensure that the error rate of reading 0x55 and 0xaa within the drift time reaches the lowest read voltage. Among them, UOP21 can be measured through experiments.

[0098] If UCE is not triggered during the reading process using UOP21, the data read by UOP21 is directly read out. If UCE is triggered during the reading process using UOP21, it is necessary to implement a read drive circuit to apply a read voltage UOP31 to the target memory cell. Among them, the third level read voltage in the multi-level read voltage in UOP31, the characteristic of UOP31 is that after the memory cell is refreshed by the operation, and the threshold voltage of the entire memory cell has a drift time of more than 10s, it can ensure that the error rate of reading 0x55 and 0xaa within the drift time reaches the lowest read voltage. Among them, UOP31 can be measured through experiments.

[0099] If UCE is not triggered during the reading process using UOP31, the data read out by UOP31 will be read directly. If UCE is triggered during the reading process using UOP31, it is necessary to implement a read drive circuit to apply a read instruction UOPXX to the target storage unit. Among them, the UOPXX is the refresh voltage in the above embodiment. Features related to the UOPXX include: 1. The read instruction UOPXX uses an ultra-long read time and an ultra-high read voltage. 2. The read instruction is started after UOP11, UOP21, and UOP31 all trigger UCE. 3. For storage cells where UOP11, UOP21, and UOP31 all trigger UCE, the storage cells that detect "0" (that is, in a high-resistance state) are screened and UOPXX is applied, and the storage cells that detect "1" (that is, in a low-resistance state) are not applied. 4. For storage cells that detect "0", the bit error rate is not detected during the period. 5. The UOPXX voltage of the newly added read instruction cannot be too high. The limited range is greater than UOP31 and less than the threshold voltage of the storage cell in the high-impedance state. The purpose is to avoid the read disturb problem caused by excessive UOPXX.

[0100] Finally, after applying the newly added read instruction UOPXX to the storage unit and then applying the read voltage UOP11 for verification, the data read by UOP11 is directly read out.

[0101] The read instruction timing diagram characteristics corresponding to the newly added read instruction UOPXX are as follows:

[0102] FIG8 is a timing diagram of applying UOPXX provided by an embodiment of the present application. As shown in FIG8 , Icell is the current response collected by the sensing circuit (SA), VWL is the gated word line voltage, VBL1 is the gated bit line voltage, and VBL0 is the unselected bit line voltage. The overall read operation is divided into 6 stages. Stage 1 is the initial state, in which VWL, VBL1, and VBL0 are all applied to a 0 level. Stage 2 is the precharge stage, in which the unselected bit line voltage VBL0 is discharged to a negative voltage V1. Stage 3 is the charge sharing stage, in which the unselected bit line voltage VBL0 and the selected bit line voltage VBL1 are directly connected, and both voltages are adjusted to the reference voltage. Phase 4 is the discharge phase, in which the selected bit line VBL1 is discharged to the second negative voltage V2; Phase 5 is the read process, in which the selected word line VWL is powered on; and Phase 6 pulls the selected bit line voltage VBL1 above the reference voltage maintained by the unselected bit line VBL0. The read voltages on the selected word line are UOP11, UOP21, and UOP31 in the conventional scheme. In the newly added read instruction timing diagram, the read voltage difference between the selected word line and the selected bit line is UOPXX.

[0103] In an embodiment of the present application, after the read operations using UOP11, UOP21, and UOP31 all trigger UCE, the threshold transition voltage of the selection device in the storage unit can be refreshed through UOPXX, and then UOP11 can be used to perform the read operation again, thereby avoiding the influence of the drift of the threshold transition voltage of the selection device on the read operation, and improving the accuracy of the read data of the storage chip.

[0104] Based on the same inventive concept, an embodiment of the present application further provides a memory chip comprising a peripheral circuit and a plurality of memory cells, each of which comprises a memory device and a gating device. The peripheral circuit is configured to, upon receiving a refresh voltage application instruction, apply a refresh voltage to at least one memory cell to be read, the refresh voltage being used to turn on the gating device in a first memory cell to lower the threshold transition voltage of the gating device. The first memory cell is a memory cell whose corresponding memory device is in a low-resistance state. A read voltage is applied to the at least one memory cell to obtain a read result.

[0105] Among them, the refresh voltage application instruction can be sent by the storage controller connected to the storage chip. After applying the refresh voltage, the peripheral circuit can further apply the read voltage to the storage unit to be read to obtain the read result, and can return the read result to the storage controller.

[0106] In the memory chip provided in the embodiment of the present application, when performing a read operation on a memory cell, the peripheral circuit can first apply a refresh voltage to the memory cell to be read, thereby turning on the gating device included in the memory cell and refreshing the threshold transition voltage of the gating device to a lower level. In this way, when the memory cell is read again using the read voltage, the impact of the drift of the threshold transition voltage of the gating device on the memory cell can be avoided, thereby improving the accuracy of reading the memory cell. The specific processing process of performing a read operation on the memory chip provided in the embodiment of the present application is similar to the control method of the memory controller described in the above embodiment, and will not be repeated in the embodiment of the present application.

[0107] In order to further improve the efficiency of applying the refresh voltage, an embodiment of the present application further provides a peripheral circuit, as shown in FIG9 , the peripheral circuit includes a control circuit and a drive circuit, and the drive circuit is used to apply the refresh voltage to the memory cell.

[0108] Referring to FIG9 , the driver circuit includes multiple driver devices, each of which is connected to a portion of the memory cells in the memory chip via word lines and bit lines. The lengths of the bit lines and word lines between each driver device and the connected memory cells are less than a length threshold. FIG9 only illustrates the connection relationship between a portion of the memory cells in a memory array.

[0109] In implementation, the memory array can be divided into multiple memory areas, wherein for each memory cell included in each memory area, one or more driver devices can be set nearby so that the one or more driver devices apply a refresh voltage to the memory cell in the corresponding memory area. Each driver device can be connected to the word line and bit line connected to the memory cell, and the length of the word line and bit line between the driver device and the memory cell is less than a length threshold, for example, the length threshold is less than or equal to half of the word line length or bit line length. In this way, the distance between the driver device and the memory cell is relatively close, and after the driver device applies the refresh voltage to the memory cell through the word line and bit line, the word line and bit line between the driver device and the memory cell have a smaller voltage division on the refresh voltage, which can achieve that the refresh voltage applied by the driver device acts more on the memory cell, which can reduce the power consumption of the memory chip and improve the effect of applying the refresh voltage to the memory cell.

[0110] In one example, a driving device can be connected to multiple memory cells, and a switch tube is provided between the driving device and the word lines and bit lines corresponding to the memory cells. The control circuit can control the disconnection and conduction of the switch tube to control the driving device to apply a refresh voltage to the selected memory cell.

[0111] In one example, the driver device is a capacitor, and the driver circuit also includes a power supply for charging the capacitor. In this case, the control circuit can control the power supply in the driver short circuit to pre-charge the capacitor, that is, pre-charge the capacitor included in each driver device to the refresh voltage. When the control circuit determines that the first read result meets the read failure condition, the capacitor can be controlled to discharge to the memory cell to which the refresh voltage needs to be applied, so as to apply the refresh voltage to the memory cell. In this way, by pre-charging the capacitor, after the read operation triggers the read failure condition, the capacitor can be controlled to discharge to the memory cell, which can improve the efficiency of applying the refresh voltage to the memory cell.

[0112] Wherein, the driving device may include a plurality of capacitors connected in series, and the first or last capacitor is removed from the plurality of capacitors connected in series, and one end of each capacitor having a high potential can be connected to one end of another capacitor having a high potential. Figure 10 is a schematic diagram of a driving device provided by an embodiment of the present application, in which two capacitors C1 and C2 are connected in series, and the power supply can charge C1 and C2 to 6V. The end of C1 having +6V can be connected to the 0V end of C2, thereby forming a +12V high-voltage refresh module, and the +12V is the size of the refresh voltage. It can be seen that setting the driving device to multiple capacitors in series can pre-charge multiple capacitors at the same time, which can improve the efficiency of predicting charging of the driving device. And a higher voltage refresh voltage can be formed by multiple capacitors with smaller voltages, without directly providing a higher voltage through the power supply, which can improve the safety and stability of the memory chip.

[0113] In another example, the driver device includes a power supply. FIG11 is a schematic diagram of a driver device provided in an embodiment of the present application. As shown in FIG11 , in addition to a power supply, the driver device may also include a voltage divider resistor. The voltage divider resistor can divide the voltage provided by multiple power supplies, thereby achieving a refresh voltage applied to the storage cell. In this way, after the control circuit determines that the first read result meets the read failure condition, the switch tube between the storage cell to which the refresh voltage is to be applied and the power supply can be closed to enable the power supply to apply the refresh voltage to the storage cell.

[0114] An embodiment of the present application further provides a memory controller connected to a memory chip, the memory chip including peripheral circuits and multiple memory cells, each of which includes a storage device and a gating device. The memory controller is configured to: control the peripheral circuits to apply a refresh voltage to at least one memory cell to be read, the refresh voltage being used to turn on the gating device in a first memory cell to lower the threshold transition voltage of the gating device; the first memory cell being a memory cell whose corresponding storage device is in a low-resistance state; and control the peripheral circuits to apply a read voltage to the at least one memory cell to obtain a read result.

[0115] In one achievable manner, before controlling the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the storage controller is further used to: control the peripheral circuit to sequentially apply multiple levels of read voltages to at least one memory cell to be read, and determine that the read results obtained after applying each level of read voltage meet the read failure condition, wherein the voltage values ​​of the applied multiple levels of read voltages increase sequentially and are less than the refresh voltage.

[0116] In one achievable manner, the storage controller is used to: control the peripheral circuit to apply a refresh voltage to a second storage cell in at least one storage cell, where the second storage cell refers to a storage cell whose corresponding storage device is read as a high-impedance state after applying a multi-level read voltage.

[0117] In one achievable manner, the read failure condition includes that the number of storage cells corresponding to read error results in the read result exceeds a threshold value.

[0118] In one achievable manner, the read failure condition includes that a difference between a check code generated for a read result and a check code generated when storing data in at least one storage unit is greater than a first difference threshold.

[0119] In one achievable manner, the absolute value of the difference between the refresh voltage and the threshold voltage corresponding to the memory cell in the high-resistance state is smaller than the second difference threshold.

[0120] When the memory controller provided in the embodiment of the present application performs a read operation on a memory cell in a memory chip, the memory controller can control the peripheral circuit to first apply a refresh voltage to the memory cell to be read, thereby turning on the gating device included in the memory cell and refreshing the threshold transition voltage of the gating device to a lower level. In this way, when the memory cell is read again using the read voltage, the impact of the drift of the threshold transition voltage of the gating device on the memory cell can be avoided, thereby improving the accuracy of reading the memory cell. The specific processing process of the memory controller provided in the embodiment of the present application performing a read operation is similar to the control method of the memory controller described in the above embodiment, and will not be repeated in the embodiment of the present application.

[0121] FIG12 is a schematic diagram of the structure of an electronic device further provided in an embodiment of the present application. As shown in FIG12 , the electronic device includes a processor and a storage system as described in the above embodiment. The processor is used to send read and write instructions to the storage system so that the storage system can perform read and write operations. The processor can be a central processing unit (CPU), and the processor can further include a CPU memory controller for controlling the storage chip, which is used to control the storage chip. The processor can also include an I / O controller that can send I / O requests to the storage chip so that the storage chip performs corresponding read and write operations, etc.

[0122] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are simply used to distinguish one element from another. For example, without departing from the scope of various examples, the first difference threshold may be referred to as the second difference threshold, and similarly, the second difference threshold may be referred to as the first difference threshold. The first difference threshold and the second difference threshold may both be collectively referred to as difference thresholds, and in some cases, may be separate and different numerical difference thresholds.

[0123] The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more.

[0124] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A storage controller, characterized in that: The memory controller is connected to a memory chip, the memory chip includes a peripheral circuit and a plurality of memory cells, each memory cell includes a storage device and a gating device; The storage controller is configured to: controlling the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the refresh voltage being used to turn on a gating device in a first memory cell to lower a threshold transition voltage of the gating device, the first memory cell being a memory cell whose corresponding storage device is in a low-resistance state; The peripheral circuit is controlled to apply a read voltage to the at least one memory cell to obtain a read result.

2. The storage controller according to claim 1, wherein: Before the memory controller controls the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the memory controller is further configured to: The peripheral circuit is controlled to apply multiple levels of read voltage to the at least one memory cell to be read in sequence, and it is determined that the read results obtained after applying each level of read voltage meet the read failure condition, wherein the voltage values ​​of the applied multiple levels of read voltage increase in sequence and are less than the refresh voltage.

3. The storage controller according to claim 2, wherein: The storage controller is further configured to: The peripheral circuit is controlled to apply a refresh voltage to a second memory cell in the at least one memory cell, where the second memory cell refers to a memory cell whose corresponding memory device is read as a high-resistance state after applying a multi-level read voltage.

4. The storage controller according to claim 2 or 3, wherein: The read failure condition includes that the number of storage units corresponding to read error results in the read result exceeds a number threshold.

5. The storage controller according to claim 2 or 3, characterized in that: The read failure condition includes that a difference between a check code generated for the read result and a check code generated when storing data in the at least one storage unit is greater than a difference threshold.

6. A memory chip, characterized in that: The memory chip includes a peripheral circuit and a plurality of memory cells, each memory cell includes a storage device and a gating device, The peripheral circuit is used for: In response to receiving a refresh voltage application instruction, applying a refresh voltage to at least one memory cell to be read, wherein the refresh voltage is used to turn on a gating device in a first memory cell to reduce a threshold transition voltage of the gating device, wherein the first memory cell is a memory cell whose corresponding storage device is in a low-resistance state; A read voltage is applied to the at least one memory cell to obtain a read result.

7. The memory chip according to claim 6, wherein: The peripheral circuit includes a control circuit and a driving circuit, the driving circuit includes a plurality of driving devices, each of which is connected to a portion of the memory cells in the memory chip via a word line and a bit line, and the length of the bit line and word line between each driving device and the connected memory cell is less than a length threshold; The control circuit is used to: A driving device that controls the connection of the at least one memory cell applies a refresh voltage to the at least one memory cell.

8. The memory chip according to claim 7, wherein: The driving circuit further includes a power supply, and the driving device includes a capacitor; The control circuit is used to: controlling the power supply to charge the capacitors connected to the plurality of storage units respectively to the refresh voltage; The capacitor connected to the at least one memory cell is controlled to discharge the capacitor to the at least one memory cell through the word line and the bit line.

9. The memory chip according to claim 7, wherein: The driving device includes a power supply; The control circuit is used to: A power source connected to the at least one memory cell is controlled to apply a refresh voltage to the at least one memory cell.

10. The memory chip according to claim 8, wherein: The driving device includes a plurality of capacitors connected in series.

11. A method for controlling a storage controller, characterized in that: The memory controller is connected to a memory chip, the memory chip includes a peripheral circuit and a plurality of memory cells, each memory cell includes a storage device and a gating device, and the method includes: The memory controller controls the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, wherein the refresh voltage is used to turn on a gating device in a first memory cell to reduce a threshold transition voltage of the gating device, wherein the first memory cell is a memory cell whose corresponding storage device is in a low-resistance state; The memory controller controls the peripheral circuit to apply a read voltage to the at least one memory cell to obtain a read result.

12. The method according to claim 11, characterized in that Before controlling the peripheral circuit to apply a refresh voltage to at least one memory cell to be read, the method further includes: The peripheral circuit is controlled to apply multiple levels of read voltage to the at least one memory cell to be read in sequence, and it is determined that the read results obtained after applying each level of read voltage meet the read failure condition, wherein the voltage values ​​of the applied multiple levels of read voltage increase in sequence and are less than the refresh voltage.

13. The method according to claim 12, characterized in that The controlling the peripheral circuit to apply a read voltage to the at least one memory cell comprises: The peripheral circuit is controlled to apply a refresh voltage to a second memory cell in the at least one memory cell, where the second memory cell refers to a memory cell whose corresponding memory device is read as a high-resistance state after applying a multi-level read voltage.

14. The method according to claim 12 or 13, characterized in that The read failure condition includes that the number of storage units corresponding to read error results in the read result exceeds a number threshold.

15. The method according to claim 12 or 13, characterized in that The read failure condition includes that a difference between a check code generated for the read result and a check code generated when storing data in the at least one storage unit is greater than a difference threshold.

16. A storage system, characterized in that: The storage system includes one or more storage controllers according to any one of claims 1 to 10, and a storage chip connected to the storage controller.

17. An electronic device, characterized in that: The electronic device comprises a processor and the storage system according to claim 16; The processor is used to send read and write instructions to the storage system, so that the storage system can implement read and write operations.

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