Trench mosfet device and array of trench mosfet devices

Abstract

A trench MOSFET device and an array of trench MOSFET devices. By separately forming a buried region and a third doped region, the width of the buried region and the width of the third doped region can be accurately controlled. Consequently, for adjacent trench MOSFET devices, the distances between buried regions and the distances between third doped regions can be accurately controlled. Since JFET regions are formed between adjacent buried regions and between adjacent third doped regions, by making the distance between adjacent third doped regions greater than that between adjacent buried regions, a JFET region having lower resistance can be formed between the adjacent third doped regions. Thus, the on-resistance of the devices is reduced, the current spreading space is increased, and the on-current of the devices is enhanced, thereby improving the conduction characteristics of the trench MOSFET devices. In addition, the buried regions effectively protect gate trench corners, thereby enhancing the overall device performance of the trench MOSFET.

Description

A trench MOSFET device and a trench MOSFET device array

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 7, 2024, with application number 202410263359.1 and invention name “A Trench MOSFET Device and Trench MOSFET Device Array”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, for example, to a trench MOSFET device and a trench MOSFET device array. Background Art

[0003] With the rapid development of semiconductor technology, trench metal-oxide-semiconductor field-effect transistor (MOSFET) devices have become a research hotspot. However, existing trench MOSFET devices still face a conflict between utilizing the JFET region to protect the gate trench angle and their relatively high on-resistance, hindering further improvements in device performance. Therefore, providing a novel trench MOSFET device has become an urgent technical challenge. Summary of the Invention

[0004] The present application provides a trench MOSFET device and a trench MOSFET device array, which reduces the on-resistance of the device, increases the on-current of the device, improves the conduction characteristics of the trench MOSFET device, and improves the device performance of the trench MOSFET.

[0005] In a first aspect, an embodiment of the present application provides a trench MOSFET device, comprising:

[0006] A drain metal layer, a substrate layer, an epitaxial layer, a current spreading layer, a well layer, a source region, and a source metal layer stacked in sequence along a first direction; the substrate layer, the epitaxial layer, and the current spreading layer have a first doping type, and the well layer has a second doping type opposite to the first doping type;

[0007] a gate structure disposed in the trench and located in the same layer as the current spreading layer, the well layer, the source region, and the source metal layer; the source region including a first doping region having the first doping type and a second doping region having the second doping type, the first doping region being adjacent to the gate structure;

[0008] a buried region within the epitaxial layer, the buried region having the second doping type;

[0009] A third doped region is provided in the same layer as the current spreading layer and has the second doping type, wherein the third doped region is connected to the buried region; in adjacent trench MOSFET devices, a distance between adjacent third doped regions is greater than a distance between adjacent buried regions.

[0010] In some embodiments of the present application, a distance between the third doping region and a sidewall of the trench is less than a preset distance, and the third doping region connects the buried region and the well layer.

[0011] In some embodiments of the present application, the third doping region is in contact with at least one sidewall of the trench.

[0012] In some embodiments of the present application, the third doping region and the second doping region are formed simultaneously by ion implantation.

[0013] In some embodiments of the present application, the length of the buried region in a second direction is greater than the length of the trench, and the second direction is a direction perpendicular to the first direction.

[0014] In some embodiments of the present application, the trench MOSFET device also includes a fourth doping region having the first doping type, the fourth doping region is located in the buried region and the current spreading layer, and the fourth doping region is in contact with one side wall and bottom of the trench.

[0015] In some embodiments of the present application, the buried region includes a plurality of buried layers, and the plurality of buried layers are located at different depths of the epitaxial layer;

[0016] Alternatively, the thickness of the buried region is greater than a preset thickness.

[0017] In a second aspect, an embodiment of the present application further provides a trench MOSFET device array, comprising a plurality of the trench MOSFET devices, wherein the plurality of the trench MOSFET devices are arranged in an array in a first direction and a second direction.

[0018] In some embodiments of the present application, the plurality of trench MOSFET devices include a first trench MOSFET device, wherein the distance between the third doped region in the first trench MOSFET device and the sidewall of the trench is less than a preset distance, and the third doped region connects the buried region and the well layer.

[0019] In some embodiments of the present application, the plurality of trench MOSFET devices further include a second trench MOSFET device, the third doped region in the second trench MOSFET device is located between the bottom of the trench and the buried region, and the first trench MOSFET devices and the second trench MOSFET devices are alternately arranged in the first direction.

[0020] The trench MOSFET device and trench MOSFET device array of the present application are used. The trench MOSFET device includes a drain metal layer, a substrate layer, an epitaxial layer, a current spreading layer, a well layer, a source region, and a source metal layer stacked in sequence along a first direction, as well as a gate structure, a buried layer, and a third doped region. The substrate layer, the epitaxial layer, and the current spreading layer have a first doping type, the well layer has a second doping type opposite to the first doping type, the gate structure is on the same layer as the current spreading layer, the well layer, the source region, and the source metal layer, and is disposed within the trench. The source region includes a first doped region having the first doping type and a second doped region having the second doping type, the first doped region and the gate structure being adjacent. The buried region is located within the epitaxial layer and has the second doping type. The third doped region is disposed on the same layer as the current spreading layer and has the second doping type, and the third doped region is connected to the buried region.

[0021] It can be seen that by forming the buried region and the third doped region respectively, the width of the buried region and the third doped region can be precisely controlled. Furthermore, for adjacent trench MOSFET devices, the distance between the buried regions and the distance between the third doped regions can be precisely controlled. Since JFET regions are formed between adjacent buried regions and adjacent third doped regions, by setting the distance between adjacent third doped regions to be greater than the distance between adjacent buried regions, the distance between adjacent third doped regions can be made larger, thereby forming JFET regions with lower resistance between adjacent third doped regions, reducing the on-resistance of the device, increasing the current expansion space, increasing the on-current of the device, and improving the on-characteristics of the trench MOSFET device. At the same time, the buried region can well protect the gate groove angle and improve the overall device performance of the trench MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 shows a schematic structural diagram of a trench MOSFET device provided in an embodiment of the present application;

[0023] 2-6 show a schematic structural diagram of another trench MOSFET device provided in an embodiment of the present application;

[0024] FIG7 shows a schematic structural diagram of a trench MOSFET device array provided in an embodiment of the present application;

[0025] FIG8 shows a top view of a trench MOSFET device array provided in an embodiment of the present application;

[0026] FIG9 shows a schematic structural diagram of a trench MOSFET device array provided in an embodiment of the present application;

[0027] 10-16 are schematic diagrams showing a process for forming a trench MOSFET device according to an embodiment of the present application;

[0028] 17-19 show schematic structural diagrams of a trench MOSFET device array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] As described in the background technology, in existing trench MOSFET devices, there is still a contradictory relationship between using the JFET region to protect the gate groove angle and its large on-resistance. That is, the gate groove angle can be protected by using the JFET region, but the JFET region has a large on-resistance, which affects the device performance.

[0030] Specifically, in the related art, in order to better protect the gate oxide layer of the trench MOSFET, especially the bottom and trench corners, the common device structure of the products of companies in the industry is to use auxiliary P-type injection masking at the bottom or both sides of the trench gate. However, the P-type masking structure of the existing products will cause a deeper JFET area in the current path, and the masking effect of reducing the electric field in the trench corners is inconsistent with the design of the JFET area resistance. At the same time, due to the priority of the P-type ion implantation depth of silicon carbide, the P-type shielding layer has limited masking protection effect on the electric field at the trench corners and bottom, making it difficult to achieve deeper masking while maintaining a lower JFET area resistance.

[0031] In order to solve the above technical problems, the embodiments of the present application provide a trench MOSFET device and a trench MOSFET device array. By forming a buried region and a third doped region respectively, the width of the buried region and the third doped region can be precisely controlled. Furthermore, for adjacent trench MOSFET devices, the distance between the buried regions and the distance between the third doped regions can be precisely controlled. Since JFET regions are formed between adjacent buried regions and adjacent third doped regions, by setting the distance between adjacent third doped regions to be greater than the distance between adjacent buried regions, the distance between adjacent third doped regions can be made larger, thereby forming a JFET region with lower resistance between adjacent third doped regions, reducing the on-resistance of the device, increasing the current expansion space, increasing the on-current of the device, and improving the on-characteristics of the trench MOSFET device. At the same time, the buried region can well protect the gate groove angle and improve the overall device performance of the trench MOSFET.

[0032] For ease of understanding, a trench MOSFET device and a trench MOSFET device array provided in an embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0033] Referring to Figure 1, which is a schematic structural diagram of a trench MOSFET device provided in an embodiment of the present application, the trench MOSFET device includes a drain metal layer 101, a substrate layer 102, an epitaxial layer 103, a current spreading layer 104, a well layer 105, a source region 106, a source metal layer 111, a gate structure 108, a buried region 109 and a third doped region 110.

[0034] Specifically, the source metal layer 111, substrate layer 102, epitaxial layer 103, current spreading layer 104, well layer 105, source region 106, and source metal layer 111 are stacked sequentially along a first direction, which is the stacking direction of each film layer. The substrate layer 102, epitaxial layer 103, and current spreading layer 104 have a first doping type, and the well layer 105 has a second doping type opposite to the first doping type. The first doping type and the second doping type are each one of P-type doping and N-type doping.

[0035] For example, when the first doping type is N-type doping and the second doping type is P-type doping, the following description will be based on the example of the first doping type being N-type doping and the second doping type being P-type doping for ease of description. Thus, the substrate layer 102, epitaxial layer 103, and current spreading layer 104 all have N-type doping, and the well layer 105 has P-type doping. The substrate layer 102 and current spreading layer 104 can be set to a high doping concentration, while the epitaxial layer 103 can be set to a low doping concentration. The higher the doping concentration, the lower the resistance of the layer. This can result in lower resistance in the substrate layer 102 and current spreading layer 104, thereby increasing the on-state current of the device.

[0036] For convenience of representation, the substrate layer 102 can be recorded as the N+ substrate layer, the epitaxial layer 103 can be recorded as the N- epitaxial layer, the current spreading layer 104 can be recorded as the N+ current spreading layer, and the well layer 105 can be recorded as the P- well layer (P-well layer), so as to clarify the doping type and doping concentration.

[0037] The gate structure 108 may be disposed inside the trench 107 . The trench 107 may be in the same layer as the current spreading layer 104 , the well layer 105 , the source region 106 and the source metal layer 111 . The gate structure 108 may include a gate dielectric layer, a gate polysilicon layer and an interlayer dielectric layer.

[0038] Specifically, the structure of the trench 107 can be a primary trench 107, a secondary trench 107, or even a multi-level trench 107. The trench 107 in FIG1 is a secondary trench 107. For example, in the case of an N-level trench 107, the trench 107 can be divided into multiple sub-trenches 107, each with a different cross-sectional width. By constructing a multi-level trench 107, due to the deeper depth of the trench 107, a deeper buried region 109 can be constructed, which can provide better electric field protection for the bottom gate and corners of the trench 107.

[0039] Among them, the source region 106 may include a first doping region 1061 with a first doping type, and a second doping region 1062 with a second doping type. For example, the first doping region 1061 has N-type doping, and the second doping region 1062 has P-type doping. The first doping region 1061 with N-type doping can be adjacent to the gate structure 108 so that current can flow when the source and drain are turned on.

[0040] The buried region 109 is located inside the epitaxial layer 103. The surface of the buried region 109 can be flush with the surface of the epitaxial layer 103. The buried region 109 has a second doping type, that is, P-type doping. The buried region 109 can also be set to have a higher doping concentration. The buried region 109 can be recorded as a buried P+ region. By providing the buried region 109, the bottom of the gate of the trench 107 can be protected, avoiding the intensification of the electric field at the corner of the trench 107, thereby improving the electric field shielding effect. In addition, the thickness of the buried region 109 can be minimized. By reducing the thickness of the buried region 109, the resistance of the JFET region can be reduced while ensuring a good electric field shielding effect.

[0041] The third doping region 110 can be arranged inside the current spreading layer 104, that is, arranged in the same layer as the current spreading layer 104, and the third doping region 110 has the second doping type. The third doping region 110 can be connected to the buried region 109 to achieve grounding of the buried region 109, thereby avoiding the dynamic carrier capture and aggregation effect, which causes the masking layer to gradually lose its function of protecting the bottom of the gate of the trench 107, and can also avoid the problem of increased switching loss caused by parasitic capacitance.

[0042] Since the buried region 109 and the third doped region 110 in the trench MOSFET device are two independent film layers, the buried region 109 and the third doped region 110 are independently formed. During the formation process, the film size of each layer, such as the width of the film layer in the horizontal direction, can be precisely controlled. In this way, when forming multiple trench MOSFET devices, for adjacent trench MOSFET devices, since the width of the buried region 109 and the width of the third doped region 110 in each device can be precisely controlled, the distance between adjacent buried regions 109 and the distance between adjacent third doped regions 110 can be precisely controlled.

[0043] Since a JFET region will be formed between adjacent buried regions 109 and a JFET region will also be formed between adjacent third doped regions 110, compared to the related art in which only a thicker doped region is formed around the trench 107, resulting in the thicker doped region forming a whole larger JFET region, in the present application, multiple smaller JFET regions can be formed separately. For each JFET region, the distance between adjacent buried regions 109 or third doped regions 110 can be controlled, and the distance size can be controlled more accurately.

[0044] Furthermore, in this embodiment, the distance between adjacent third doped regions 110 is greater than the distance between adjacent buried regions 109. Thus, for the JFET region formed between adjacent third doped regions 110, the greater distance can reduce the resistance of the JFET region, thereby reducing the JFET region resistance in the entire device, reducing the on-resistance of the device, increasing the current expansion space, reducing the impact of the depletion layer in the JFET region on the device current, increasing the device on-current, and improving the on-characteristics of the trench MOSFET device, thereby improving the performance of the trench MOSFET device.

[0045] In the embodiment of the present application, the distance between the third doping region 110 and the sidewall of the trench 107 can be set to be less than a preset distance. The preset distance can be determined based on the structure of the trench 107 and the distance between the second doping region 1062 and the sidewall of the trench 107. For example, when the trench 107 is a first-level trench 107, the width of the cross section at each position of the trench 107 is the same, and the preset distance can be the distance between the second doping region 1062 and the sidewall of the trench 107. For example, when the trench 107 is a multi-level trench 107, the preset distance can be slightly greater than the distance between the second doping region 1062 and the sidewall of the trench 107.

[0046] By setting a smaller distance between the third doping region 110 and the side wall of the trench 107, it can be ensured that the device conduction current can flow near the side wall of at least one side of the trench 107, and it can also be ensured that the third doping region 110 and the buried region 109 can be connected. The third doping region 110 can connect the buried region 109 and the well layer 105. In this way, the grounding potential of the source metal layer 111 can be transmitted to the buried region 109 through the contacting buried region 109, the third doping region 110, the well layer 105, the second doping region 1062 and the source metal layer 111, so that the buried region 109 is grounded, which can avoid the difficulty in grounding the buried region 109 due to the large distance, thereby ensuring the normal flow of current in the trench MOSFET device.

[0047] In the embodiment of the present application, the third doped region 110 may be provided to contact at least one sidewall of the trench 107. The third doped region 110 may contact one sidewall of the trench 107, referring to the trench MOSFET device on the right side in FIG2 .

[0048] By arranging the third doped region 110 in contact with one sidewall of the trench 107, the distance between adjacent third doped regions 110 can be maximized, further reducing the JFET resistance and improving the device's on-state characteristics. Furthermore, this facilitates the formation of the third doped region 110. Specifically, after etching the trench 107, the third doped region 110 can be formed by ion implantation or other methods. This ensures that the doping concentration of the third doped region 110 meets the requirements, thereby improving the doping quality of the third doped region 110.

[0049] Among them, the third doped region 110 can also contact the side walls on both sides of the trench 107. Of course, the third doped region 110 can also contact part of the bottom of the trench 107. Refer to the trench MOSFET device on the right side of Figure 1. In this way, it can further ensure that the buried region 109 can be normally grounded. The position area of ​​the third doped region 110 can be determined according to the ion implantation angle.

[0050] In an embodiment of the present application, the third doping region 110 can be formed simultaneously with the second doping region 1062 by ion implantation. At this time, there is a certain distance between the third doping region 110 and the side wall of the trench 107. Referring to Figure 3, the third doping region 110 and the second doping region 1062 have the same extension direction. In this way, when forming the second doping region 1062, this scheme can increase the implantation depth of the P-type ions, thereby forming the third doping region 110 downward at the same time. In this way, no additional steps are required for ion implantation. Only one ion implantation is required to simultaneously form the second doping region 1062 and the third doping region 110, thereby connecting the third doping region 110 and the buried region 109, simplifying the process flow.

[0051] In addition, since there is a certain distance between the second doped region 1062 and the trench 107, there is also a certain distance between the third doped region 110 and the trench 107. In this way, channels can be formed on both sides of the gate structure 108, and both channels on both sides can be turned on, further improving the conduction characteristics of the device.

[0052] In an embodiment of the present application, the direction perpendicular to the first direction can be recorded as the second direction. In the second direction, the length of the buried area 109 can be greater than the length of the groove 107, that is, in the horizontal direction, the width of the buried area 109 can be greater than the width of the groove 107. In this way, the buried area 109 can completely surround the bottom of the groove 107, thereby protecting the bottom of the groove 107 to a greater extent and improving the electric field shielding effect on the bottom of the groove 107 and the groove corner of the groove 107.

[0053] In an embodiment of the present application, the trench MOSFET device may further include a fourth doping region 112 having a first doping type, as shown in FIG4 . For example, the fourth doping region 112 having N-type doping may be recorded as an N-type island region. The fourth doping region 112 may be located within the buried region 109 and the current spreading layer 104 . The fourth doping region 112 may be in contact with a side wall and a bottom of the trench 107 .

[0054] In this way, when the size of the buried P+ region is large enough, for example, the width and thickness are large enough to wrap the entire gate trench 107, the third doping region 110 can be used to keep the buried P+ region grounded, and at the same time, an additional N-type ion implantation can be performed to form an N-type island region, thereby better protecting the gate oxide and improving the dynamic characteristics of the device.

[0055] In an embodiment of the present application, the buried region 109 may include multiple buried layers, and the multiple buried layers may be located at different depths of the epitaxial layer 103, wherein the number of layers of the multiple buried layers may be M, M ≥ 1, thereby modulating the electric field distribution and improving the breakdown characteristics of the device. In addition, the multiple buried layers may be connected to each other, so that the suspended junction can be kept in a grounded state, which can further improve the dynamic characteristics of the device. Referring to Figure 5, the buried region 109 includes two mask layers, and the two mask layers are connected through the third doped region 110.

[0056] In an embodiment of the present application, the thickness of the buried region 109 may be greater than a preset thickness. By setting the thickness of the buried region 109 to be sufficiently large, a super junction structure may be formed, thereby improving the overall characteristics of the device. Referring to FIG. 6 , the buried region 109 is relatively thick.

[0057] An embodiment of the present application provides a trench MOSFET device. By forming a buried region and a third doped region respectively, the widths of the buried region and the third doped region can be precisely controlled. Furthermore, for adjacent trench MOSFET devices, the distance between the buried regions and the distance between the third doped regions can be precisely controlled. Since JFET regions are formed between adjacent buried regions and between adjacent third doped regions, by setting the distance between adjacent third doped regions to be greater than the distance between adjacent buried regions, the distance between adjacent third doped regions can be made larger, thereby making the resistance of the JFET region formed between adjacent third doped regions smaller, reducing the on-resistance of the device, increasing the current expansion space, increasing the on-current of the device, and improving the on-characteristics of the trench MOSFET device. At the same time, the buried region can well protect the gate groove angle and improve the device performance of the trench MOSFET.

[0058] Based on a trench MOSFET device provided in the above embodiment, an embodiment of the present application further provides a trench MOSFET device array. The trench MOSFET device array may include multiple trench MOSFET devices, and the multiple trench MOSFET devices are arranged in an array in a first direction and a second direction.

[0059] In this way, whether in the first direction or the second direction, for the JFET region between two adjacent trench MOSFET devices, by setting the distance between adjacent third doping regions 110 to be greater than the distance between adjacent buried regions 109, the distance between adjacent third doping regions 110 can be made larger, thereby making the resistance of the JFET region formed between adjacent third doping regions 110 smaller, and increasing the current expansion space, increasing the device on-current, and improving the conduction characteristics of the trench MOSFET device and the performance of the trench MOSFET device.

[0060] In an embodiment of the present application, the plurality of trench MOSFET devices may include a first trench MOSFET device. In the first trench MOSFET device, the distance between the third doping region 110 and the sidewall of the trench 107 may be less than a predetermined distance, and the third doping region 110 connects the buried region 109 and the well layer 105. In other words, the third doping region 110 and the sidewall of the trench 107 may be in direct contact or may be at a certain distance. In this case, the third doping region 110 and the second doping region 1062 are formed simultaneously. All trench MOSFET devices in the trench MOSFET device array may be first trench MOSFET devices, or some may be first trench MOSFET devices.

[0061] In an embodiment of the present application, the multiple trench MOSFET devices also include a second trench MOSFET device 1102. In the second trench MOSFET device 1102, the third doped region 110 is located between the bottom of the trench 107 and the buried region 109, that is, the third doped region 110 is not connected to the well layer 105, and the buried region 109 cannot be grounded.

[0062] The first trench MOSFET devices 1101 and the second trench MOSFET devices 1102 may be arranged alternately in a first direction, so that a plurality of first trench MOSFET devices 1101 and a plurality of second trench MOSFET devices 1102 may form a MOSFET device array.

[0063] Referring to Figure 7, which is a structural schematic diagram of a trench MOSFET device array provided in an embodiment of the present application, including a first trench MOSFET device 1101 and a second trench MOSFET device 1102 arranged at intervals, cross-sectional views can be obtained at different positions of the device array in the first direction, respectively recorded as cross-section A and cross-section B. The device structures of cross-section A and cross-section B are different. Due to the alternating arrangement, in cross-section A, the first trench MOSFET device 1101 is located to the right of the second trench MOSFET device 1102, and in cross-section B, the first trench MOSFET device 1101 is located to the left of the second trench MOSFET device 1102.

[0064] In the first trench MOSFET device 1101, the third doped region 110 connects the well layer 105 and the buried region 109. The third doped region 110 also surrounds the sidewalls and bottom of the trench 107. The thickness of the third doped region 110 on the right sidewall of the trench 107 is greater than the thickness on the left sidewall of the trench 107. In the second trench MOSFET device 1102, the third doped region 110 is located between the bottom of the trench 107 and the buried region 109. For convenience of description, the third doped region 110 in the second trench MOSFET device 1102 can be denoted as the P1 region, and the third doped region 110 in the first trench MOSFET device 1101 can be denoted as the P2 region.

[0065] A JFET region can be formed between adjacent third doping regions 110 or buried regions 109. In cross section A, the JFET region between adjacent third doping regions 110 can be recorded as JFET2 region. In cross section B, the JFET region between adjacent third doping regions 110 can be recorded as JFET1 region, and the JFET region between adjacent buried regions 109 can be recorded as JFET3 region.

[0066] It can be understood that both the JFET1 region and the JFET2 region are JFET regions formed between adjacent third doped regions 110. However, the JFET1 region is the distance between the third doped region 110 of the second trench MOSFET device 1102 and the third doped region 110 located on the left side of the trench 107 in the first trench MOSFET device 1101, while the JFET2 region is the distance between the third doped region 110 of the second trench MOSFET device 1102 and the third doped region 110 located on the right side of the trench 107 in the first trench MOSFET device 1101. The widths of the JFET1 and JFET2 regions may differ slightly, but the difference is not significant. Both the JFET1 and JFET2 regions are wider than the JFET3 region.

[0067] Referring to Figure 8, a top view of a trench MOSFET device array provided in an embodiment of the present application is shown, wherein cross-section A and cross-section B correspond to Figure 7, and mainly show the position distribution of the buried P+ region, P1 region, and P2 region, forming three regions: JFET1 region, JFET2 region, and JFET3 region. Compared with JFET3, JFET1 region and JFET2 region have wider JFET regions, and therefore have smaller JFET resistance, which can improve the conduction characteristics of the device. At the same time, the P1 region and P2 region are arranged at intervals, and the P2 region keeps all buried P+ regions at the bottom of the trench 107 grounded.

[0068] In this way, the third doped region 110 in the first trench MOSFET device 1101 can be connected to the source metal layer 111 to achieve grounding of the buried region 109. In the first direction, the first trench MOSFET device 1101 and the second trench MOSFET device 1102 are set adjacent to each other, so that the two third doped regions 110 can be connected, and then the buried region 109 in the second trench MOSFET device 1102 can be connected to the source metal layer 111 through the two connected third doped regions 110, thereby achieving grounding of the buried layer in the second trench MOSFET device 1102.

[0069] Therefore, since the third doped region 110 in the first trench MOSFET device 1101 only needs to be connected to the buried region 109, the formation range of the third doped region 110 can be reduced, doping can be reduced, and device cost can be reduced. By setting the first trench MOSFET device 1101 and the second trench MOSFET device 1102 adjacent to each other, it can be ensured that each trench MOSFET device can operate normally, thereby improving the reliability of the trench MOSFET device array and improving the performance of the device array.

[0070] When the trench MOSFET device array is entirely composed of first trench MOSFET devices 1101, as shown in FIG9 , the device structures of cross sections A and B at different locations are identical. That is, in each trench MOSFET device in the trench MOSFET device array, the third doped region 110 is sufficiently close to the sidewall of the trench 107. Thus, each trench MOSFET device can be located at any position in the array without considering the device structure of adjacent trench MOSFET devices, which can simplify the device array construction process and improve the reliability of the device array.

[0071] In addition, in the trench MOSFET device array, the third doped region 110 of the first trench MOSFET device 1101 does not contact the side wall of the trench 107, and there is a certain distance between the two. In this way, a conductive path can be formed on one side wall of the trench 107 of the first trench MOSFET device 1101, and even near the side walls on both sides, so that current can flow. In this way, the conduction characteristics of the device can be improved, and the conduction current of the device can be further increased, thereby improving the conduction characteristics of the device array.

[0072] An embodiment of the present application provides a trench MOSFET device array. By forming a buried region and a third doped region respectively, the widths of the buried region and the third doped region can be precisely controlled. Furthermore, for adjacent trench MOSFET devices, the distance between the buried regions and the distance between the third doped regions can be precisely controlled. Since JFET regions are formed between adjacent buried regions and between adjacent third doped regions, by setting the distance between adjacent third doped regions to be greater than the distance between adjacent buried regions, the distance between adjacent third doped regions can be made larger, thereby making the resistance of the JFET region formed between adjacent third doped regions smaller, reducing the on-resistance of the device, increasing the current expansion space, increasing the on-current of the device, and improving the on-characteristics of the trench MOSFET device. At the same time, the buried region can well protect the gate groove angle and improve the overall device performance of the trench MOSFET.

[0073] Next, the formation process of the trench MOSFET device can be introduced. Referring to Figures 10 to 16, there are schematic diagrams of the formation process of a trench MOSFET device provided in an embodiment of the present application.

[0074] In the embodiment of the present application, an epitaxial layer 103 can be grown on a wide bandgap semiconductor material substrate layer 102. The wide bandgap semiconductor material may include SiC, GaN, Ga2O3, C, AlN, etc. Subsequently, a buried region 109 is formed on the epitaxial layer 103 by ion implantation, and then a current spreading layer 104 is grown on the epitaxial layer 103. Of course, when forming the buried region 109 and the current spreading layer 104, the current spreading layer 104 can also be first grown on the epitaxial layer 103, and then the buried region 109 can be formed in the epitaxial layer 103 by ion implantation. Subsequently, the well layer 105 is formed by ion implantation, secondary epitaxy, growth of a P-type or N-type oxide, etc.

[0075] Specifically, referring to Figure 11, a second doped region 1062 is formed in the well layer 105 by ion implantation, such as forming a source P+ region. Then, referring to Figure 12, a first doped region 1061 is formed in the second doped region 1062 by ion implantation, such as forming a source N+ region.

[0076] Next, referring to FIG13 , a trench 107 is formed by dry etching or the like. Then, a third doped region 110 is formed by ion implantation. Although the present embodiment takes the simultaneous formation of two trench MOSFET devices as an example for explanation, the present embodiment is not limited to forming only two trench MOSFET devices, and one or more trench MOSFET devices may also be formed.

[0077] Ion implantation can be used to form the P1 region, i.e., the third doped region 110, as shown in FIG14 . Subsequently, ion implantation is performed at a certain implantation angle to form the P2 region, i.e., the third doped region 110, as shown in FIG15 . Next, the gate structure 108 is grown in the trench 107, and the gate dielectric layer is grown, the gate polysilicon is grown and etched, and the interlayer dielectric layer is grown and etched, as shown in FIG16 . A source metal layer 111 is deposited and etched above the gate structure 108, and a drain metal layer 101 is deposited and etched on the substrate, ultimately forming the device structure shown in FIG1 .

[0078] In one possible implementation, when the groove 107 is a multi-level structure, such as a two-level structure, the second-level groove 107 can be in the middle of the first-level groove 107, or on the leftmost side, or on the rightmost side. Those skilled in the art do not make specific limitations here. Referring to Figure 17, the second-level groove 107 is located on the rightmost side of the first-level groove 107.

[0079] In one possible implementation, when the device array is composed of alternating first trench MOSFET devices 1101 and second trench MOSFET devices 1102, or when the device array is entirely composed of first trench MOSFET devices 1101, a narrower P2 region is formed by applying a larger angle injection. The width of the P2 region only needs to ensure that the well layer 105 and the buried region 109 can be connected. By forming a narrower P2 region, a wider JFET2 region can be formed, which can further reduce the resistance of the JFET2 region and further improve the conduction characteristics of the device.

[0080] 18 , the width of the third doped region 110 is relatively small to reduce the resistance of the JFET 2 region. Of course, for each trench MOSFET device in the device array, the third doped region 110 may be located near the left sidewall of the trench 107 or near the right sidewall of the trench 107. Those skilled in the art may select the appropriate location based on actual circumstances.

[0081] In one possible implementation, the structure of the groove 107 can be a multi-level structure or a primary structure. Referring to FIG19 , the groove 107 is a primary structure, and the cross-sectional widths at all positions of the groove 107 are equal.

[0082] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0083] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A trench MOSFET device comprising: A drain metal layer, a substrate layer, an epitaxial layer, a current spreading layer, a well layer, a source region and a source metal layer stacked in sequence along a first direction; The substrate layer, the epitaxial layer and the current spreading layer have a first doping type, and the well layer has a second doping type opposite to the first doping type; a gate structure disposed in the trench and located in the same layer as the current spreading layer, the well layer, the source region, and the source metal layer; the source region including a first doping region having the first doping type and a second doping region having the second doping type, the first doping region being adjacent to the gate structure; a buried region within the epitaxial layer, the buried region having the second doping type; A third doped region is provided in the same layer as the current spreading layer and has the second doping type, wherein the third doped region is connected to the buried region; in adjacent trench MOSFET devices, a distance between adjacent third doped regions is greater than a distance between adjacent buried regions. 2 . The trench MOSFET device according to claim 1 , wherein a distance between the third doping region and a sidewall of the trench is less than a preset distance, and the third doping region connects the buried region and the well layer. 3 . The trench MOSFET device according to claim 2 , wherein the third doped region is in contact with at least one sidewall of the trench. The trench MOSFET device according to claim 2 , wherein the third doping region and the second doping region are formed simultaneously by ion implantation. 5 . The trench MOSFET device according to claim 1 , wherein a length of the buried region in a second direction is greater than a length of the trench, and the second direction is a direction perpendicular to the first direction.

6. The trench MOSFET device according to claim 1, further comprising a fourth doping region having the first doping type, wherein the fourth doping region is located within the buried region and the current spreading layer, and the fourth doping region contacts a sidewall and a bottom of the trench.

7. The trench MOSFET device according to claim 1 , wherein the buried region comprises a plurality of buried layers, and the plurality of buried layers are located at different depths of the epitaxial layer; Alternatively, the thickness of the buried region is greater than a preset thickness.

8. A trench MOSFET device array, comprising a plurality of trench MOSFET devices according to any one of claims 1 to 7, wherein the plurality of trench MOSFET devices are arranged in an array in a first direction and a second direction.

9. The trench MOSFET device array according to claim 8, wherein the plurality of trench MOSFET devices include a first trench MOSFET device, wherein the distance between the third doped region in the first trench MOSFET device and the sidewall of the trench is less than a preset distance, and the third doped region connects the buried region and the well layer.

10. The trench MOSFET device array according to claim 9, wherein the plurality of trench MOSFET devices further comprises a second trench MOSFET device, the third doped region in the second trench MOSFET device is located between the bottom of the trench and the buried region, and the first trench MOSFET devices and the second trench MOSFET devices are alternately arranged in the first direction.

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