Method for producing and separating MEMS components
Patent Information
- Application Number
- PCT/EP2025/054053
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-07
- Filing Date
- 2025-02-14
- Publication Date
- 2025-10-02
AI Technical Summary
Existing methods for producing and singulating MEMS components with sensitive surfaces often result in damage to these surfaces during processing steps.
A method involving the application of a protective wafer to cover MEMS components, followed by a 180° turn and separation using stealth dicing, ensuring the sensitive surfaces are protected and allowing for edgeless separation of individual MEMS chips or arrays.
Effectively protects sensitive surfaces like micromirror plates during processing, enabling further operations on the backside of the wafer and achieving almost edgeless separation of MEMS components.
Smart Images
Figure EP2025054053_02102025_PF_FP_ABST
Abstract
Description
[0001] Description
[0002] title
[0003] Process for the production and separation of MEMS components
[0004] Technical area
[0005] The invention relates to a method for producing and singulating MEMS components and / or MEMS arrays having sensitive surfaces. Furthermore, the invention relates to the use of the method for producing and singulating MEMS components embodied as MEMS chips or MEMS arrays with sensitive surfaces.
[0006] State of the art
[0007] DE 10 2015 206 996 A1 relates to a method for producing microelectromechanical structures in a layer sequence and a corresponding electronic component with a microelectromechanical structure. This method comprises providing a carrier substrate with a first surface, applying an insulating layer to the first surface, epitaxially growing a first silicon layer on the insulating layer, and structuring the first silicon layer to form trenches in the first silicon layer. Furthermore, passivation of the first silicon layer is provided, wherein the trenches are filled and a passivation layer is formed on a side facing away from the first surface.Furthermore, the passivation layer is structured, whereby sacrificial regions and functional regions are formed in the first silicon layer and the sacrificial regions on a side facing away from the carrier substrate are at least partially free of the passivation layer and finally a removal of the sacrificial regions.
[0008] DE 10 2016 212 261 A1 concerns error correction in multiple mirror arrangements. A multiple mirror arrangement comprises a plurality of mirrors, each of which is tiltably mounted, such that the mirrors can each be tilted from a first position into at least one second position, different from the first, by means of at least one actuator. At least one of the mirrors is assigned a switch-off arrangement, with which the mirror can be moved to a third position, different from the first and second positions, which is an off position in which radiation reflected by the mirror is neither used for operation nor interferes with it.
[0009] Disclosure of the invention
[0010] According to the invention, a method for producing and singulating MEMS components and / or MEMS arrays from silicon wafers, each having sensitive surfaces, is proposed, comprising the following method steps: a) Providing the silicon wafer with pre-structured individual MEMS components as MEMS chips or as MEMS arrays, b) Inserting a frame to expose the MEMS components as MEMS chips or as MEMS arrays around them in the silicon wafer, c) Applying at least one protective wafer to the silicon wafer to cover the MEMS components as MEMS chips or as MEMS arrays, d) Turning the silicon wafer 180°, provided with the at least one protective wafer, and placing it on a base for carrying out tests and / or equipping it with electrical / electronic components on its backside,e) creating at least one predetermined breaking point in the at least one protective wafer and performing separation operations on a rear side of the frame in the silicon wafer, f) applying the arrangement according to method step e) to an expandable base and expanding it with a lateral expansion movement, and g) picking up the separated MEMS components as MEMS chips or as a MEMS array by means of a removal tool.
[0011] By means of the method proposed according to the invention, sensitive surfaces of the wafer, such as pre-structured mirror plates of micromirrors, can be very effectively protected during further processing steps.
[0012] In an advantageous further development of the method proposed according to the invention, according to method step b), the frame for the release in the material of the silicon wafer is produced by means of an etching process, in particular by means of trench etching (DR IE) in a defined frame width
[0013] In a further advantageous development of the method proposed according to the invention, a depth of the frame is produced in such a way that it extends at least to a bulk material7solid material area in the silicon wafer.
[0014] In a further advantageous development of the method proposed according to the invention, the at least one protective wafer is applied to a front side of the silicon wafer by means of an adhesive connection or a temporary or permanent bond connection.
[0015] In an advantageous development of the method proposed according to the invention, the at least one protective wafer is made of silicon, glass, silicon carbide, ceramic, plastic or metal.
[0016] In the method proposed according to the invention, it is provided that at least one predetermined breaking point is produced in the material of the at least one protective wafer either by perforations or during application according to method step c) or before the separation of the MEMS components as a MEMS chip or as a MEMS array or by weakening the crystal structure by laser irradiation.
[0017] Furthermore, the method proposed according to the invention is characterized in that after carrying out the method step b), a connecting surface for the adhesive connection or the temporary or permanent bond connection is formed by means of a structuring step with a recess in the material of the silicon wafer.
[0018] In an advantageous further development of the method proposed according to the invention, the recess for the clearance is designed with a height difference, related to a depth of the frame, or at a depth identical to the frame.
[0019] In an advantageous development of the method proposed according to the invention, the recess can be combined with the frame for isolation by means of a widening. This simplifies production through structuring.
[0020] In the method proposed according to the invention, it is provided that the recess is produced separately from the frame for the purpose of exposure.
[0021] In an advantageous embodiment of the method proposed according to the invention, after the 180° turning according to method step d), wafer level tests, assembly with electrical and / or electronic components and / or connection with a ceramic plate can be carried out on the back side of the silicon wafer.
[0022] In an advantageous development of the method proposed according to the invention, according to method step f), the expandable base is laminated onto an upper side of the at least one silicon wafer.
[0023] In the method proposed according to the invention, it is further advantageously provided that, according to method step e), the separation operations on the back side of the silicon wafer are carried out by stealth dicing.
[0024] The invention further relates to the use of the method for the production and separation of MEMS components, embodied as individual MEMS chips or MEMS arrays with sensitive surfaces, in particular micromirror surfaces. Advantages of the invention
[0025] The method proposed according to the invention advantageously allows sensitive wafer surfaces, such as mirror plates of micromirrors, to be effectively protected by applying at least one protective wafer during further processing of the silicon wafer. The silicon wafer can be placed on the wafer side with the respective sensitive surfaces of the MEMS components, which in turn are effectively protected against damage by the at least one protective wafer. Further processing steps can be performed on the backside of the silicon wafer using a backside metallization or using electrical contacts embedded in the backside.
[0026] Furthermore, the method proposed according to the invention can achieve an almost edgeless separation of individual MEMS chips or MEMS arrays.
[0027] Short description of the drawings
[0028] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.
[0029] They show:
[0030] Figure 1 shows a silicon wafer with MEMS components and sensitive surfaces,
[0031] Figure 2 is a schematic representation of the application of a protective wafer to a front side of the pre-structured silicon wafer,
[0032] Figure 3 shows a 180° turn of the silicon wafer provided with at least one protective cap,
[0033] Figure 4 is a schematic representation of processing steps that are carried out on the back of the silicon wafer provided with at least one protective cap, Figure 5 is a schematic representation of an assembly with ASIC components,
[0034] Figure 6 shows the creation of predetermined breaking points in the at least one protective wafer and the placement on the front side of the at least one protective wafer, as well as the application of an expandable base and a separation on the back side of the silicon wafer by stealth dicing.
[0035] Figure 7 shows a lateral expansion movement and recording of the separated middle part of the silicon wafer,
[0036] Figures 8.1 -8.4 show different variants of the connections between the at least one protective cap and the material of the silicon wafer.
[0037] Embodiments of the invention
[0038] In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.
[0039] A silicon wafer 10, for example, has at least one movable micromirror 26 or micromirror array 20. The pre-structured silicon wafer 10 comprises a micromechanics system created using EPyC process blocks and includes, for example, MEMS components 24 with sensitive surfaces 28 in the form of mirror plates on a front side 12 of the silicon wafer 10. On a back side 14, for example, there is a backside metallization 16, which may include one or more metallic contacts 18.
[0040] Figure 1 schematically shows the silicon wafer 10, which has 12 MEMS components 24 on its front side, which are formed as a MEMS array 20 with MEMS structures 22. Said MEMS components 24 are created in pre-structuring steps in the material of the silicon wafer 10. The MEMS components 24, shown as individual MEMS chips or as MEMS arrays 20, can be, for example, micromirrors 26, which have very sensitive surfaces 28, namely the aforementioned mirror surfaces.
[0041] From the illustration in Figure 1, it can be seen that a frame 30 for exposure and singulation is formed in the silicon wafer 10. The frame 30 for exposure extends in a defined frame width 72 and a frame depth 32 around a MEMS array 20, shown here as an example, designed as a micromirror. The depth 32 of the frame 30 for exposure extends to a bulk material region / solid material region 34 in the material of the silicon wafer 10. The front side of this frame is identified by reference numeral 12, and the back side by reference numeral 14. On the back side 14 of the silicon wafer 10 there is, for example, a backside metallization 16, which can comprise individual metallic contacts 18 or metallic contacts 18 arranged in pairs.
[0042] The depth 32 of the frame 30 for the clearance, which encompasses the entire micromechanics area and extends to the top of the bulk material area / solid material area 34, ensures that the micromechanics and the sensitive surfaces 28 are not damaged by the resulting fracture edges during subsequent singulation. The frame 30 for the clearance is created, in particular, within an EPyC process sequence or exclusively by trench etching (DRIE). This allows a very narrow border with a defined minimum frame width 72 to be realized around each of the MEMS components 24, whether individual MEMS chips or MEMS arrays 20. The border depends solely on the process tolerance of the structuring sequences used.
[0043] From the illustration in Figure 2, it can be seen that a cover in the form of at least one protective wafer 40 is applied to the front side 12 of the pre-structured silicon wafer 10. The at least one protective wafer 40 can be applied to the front side 12 of the pre-structured silicon wafer 10, for example, by means of an adhesive connection 42 or a temporary or permanent bond connection 44. The at least one protective wafer 40 comprises a top side 46 and defines a cavity 48 above the sensitive surfaces 28 of the MEMS components 24, which are embodied either as individual MEMS chips or as MEMS arrays 20. The at least one protective wafer 40, which substantially covers the front side 12 of the silicon wafer 10, protects the sensitive surfaces 28 from damage.
[0044] Although in the illustration according to Figure 2 the adhesive connections 42 or the temporary or permanent bond connections 44 are applied to the front side 12 of the silicon wafer 10, it is possible to also form them in other embodiments, as can be seen, for example, from the embodiments of the figure sequence of Figures 8.1 to 8.4.
[0045] Figure 2 shows that the frame 30 has a frame depth 32 for clearance, which extends to the top of the bulk solid material area 34. The frame 30 is formed with a defined frame width 72.
[0046] According to Figure 3, a 180° turn 50 of the pre-structured silicon wafer 10, on which the at least one protective wafer 40 is applied to protect the sensitive surfaces 28 against damage, takes place. The pre-structured silicon wafer 10, provided with the at least one protective wafer 40, is applied to a base 52 with the top side 46 of the at least one protective wafer 40. As before, the sensitive surfaces 28 of the MEMS components 24, whether formed as individual MEMS chips or as a MEMS array 20, are protected against damage.
[0047] Further processing of the backside 14 of the silicon wafer 10 can now be carried out according to the illustrations in Figures 3 and 4. As already described above with reference to Figures 1 and 2, the backside 14 of the silicon wafer is provided with a backside metallization 16, which can comprise metallic contacts 18 arranged individually, in pairs, or in groups. These contacts are now accessible, so that further processing or assembly steps can be carried out on the backside 14 of the pre-structured silicon wafer 10, either manually or automatically.
[0048] This is shown in more detail in the illustrations in Figures 4 and 5. From the illustration in Figure 4, for example, it can be seen that the silicon wafer 10, placed with its top side 46 on the base 52, can be processed on its rear side 14, for example via electrical contact needles 54. As shown in Figure 4, the electrical contact needles 54 each contact individual metallic contacts 18 arranged in pairs or groups on the rear side 14 of the pre-structured silicon wafer 10. Alternatively, as shown in Figure 5, it is possible to connect, for example, ASIC components 56 to the electrical contacts 18 provided individually, in pairs or in groups on the rear side 14 of the pre-structured silicon wafer 10. Instead of the ASIC components 56, as shown in Figure 5, other electrical or electronic components can also be connected to the metallic contacts 18 via electrical contacts 58.Advantageously, the arrangement according to Figures 4 and 5 can ensure that, during the processing of the rear side 14 of the pre-structured silicon wafer 10, the sensitive surfaces 28 arranged on its front side 12 are effectively protected against damage by the applied, at least one protective wafer 40.
[0049] From the illustration in Figure 6, it can be seen that predetermined breaking points 70 are created in the material of the protective wafer 40 either by introduced perforations or during the application of the at least one protective wafer 40, or the at least one predetermined breaking point 70 is created before the separation of the MEMS components 24. Beforehand, the arrangement of pre-structured silicon wafer 10 with the at least one protective wafer 40 is laminated with its upper side 46 onto an expandable base 76, for example a tape that performs lateral expansion movements 78. Furthermore, separation operations 80 are carried out on the rear side 14 of the pre-structured silicon wafer 10, preferably by means of stealth dicing. As a result, the bulk material region or the solid material region 34 of the pre-structured silicon wafer 10 is separated, preferably in the region of the frame 30, for exposure.At the same time, the parts of the pre-structured silicon wafer 10 separated by the separation operation 80 using stealth dicing are fixed by a suitably designed removal tool 82. Advantageously, the separation joints formed by the separation operations 80 extend in such a way that they open into the deep-formed frames 30 for dicing. Thus, the inner part of the pre-structured silicon wafer 10, which is gripped by the removal tool 82, is fixed, and a dicing operation can be performed. This is carried out, for example, by a lateral expansion movement 78 of the horizontally expandable base 76, preferably in the form of a tape.
[0050] Figure 7 shows that after the lateral expansion movement 78 of the tape 76, a removal movement in the vertical removal direction 84 of the pre-structured silicon wafer 10 grasped by the removal tool 82 takes place. The laterally remaining remnants of the bulk material region or the solid material region 34 are removed laterally from the pre-structured silicon wafer 10, the central region of which is fixed by the removal tool 82. The at least one protective wafer 40 expands laterally during the lateral expansion movement 78 of the expandable base 76 and breaks open at the at least one predetermined breaking point 70. It can be separated due to the frame 30 for release and the aligned joints created by the separation operations 80.
[0051] The sequence of figures 8.1, 8.2, 8.3 and 8.4 shows various possibilities for forming an adhesive connection 42, a temporary or permanent bond connection 44 with the pre-structured silicon wafer 10.
[0052] Figure 8.1 shows, for example, that the at least one protective wafer 40, only partially shown here, is attached to the front side 12 of the pre-structured silicon wafer 10 on a connecting surface, for example by means of the adhesive connection 42. Instead of the adhesive connection 42, a temporary or permanent bond connection 44 can also be created between a leg 96 of the at least one protective wafer 40 and the front side 12 or the connecting surface 45 of the pre-structured silicon wafer 10. A thickness of the material of the at least one protective wafer 40 is indicated by reference numeral 74. The frame 30 for the release extends over the frame depth 32 from the front side 12 of the pre-structured silicon wafer 10 to the beginning of the bulk material region 34 or the solid material region 34 as shown in Figure 8.1.
[0053] Figure 8.2 shows a possible connection between the at least one protective wafer 40 and the pre-structured silicon wafer 10 such that a recess 86 is formed in the material of the pre-structured silicon wafer 10 next to the frame 30 for the release, forming a connection surface 45. The depth of the recess 86 can, for example, differ by a height difference 88 from the depth 32 of the frame 30 for the release. However, it is also possible (see Figure 8.3) to form the recess 86 in the material of the pre-structured silicon wafer 10 at a depth identical to the depth 32 of the frame 30 for singulation.The connecting surface 45 can be formed by means of a structuring step within the recess 86 in the material of the pre-structured silicon wafer 10 in order to achieve the greatest possible vertical distance between the adhesive connection 42 or the temporary or permanent bond connection 44 and the sensitive surfaces 28 of the MEMS components 24.
[0054] As already indicated, Figure 8.3 shows a variant embodiment in which the depth 32 of the frame 30 for the clearance and the depth of the recess 86, which terminates with the connecting surface 45, have an identical depth 90. Here, too, the material thickness of the at least one protective wafer 40 is designated by reference numeral 74. The material thickness 74 of the at least one protective wafer 40 corresponds to a leg width 98 of the leg 96 of the at least one protective wafer 40, which extends into the recess 86.
[0055] Figure 8.4 shows one possible embodiment for securing the at least one protective wafer 40 in the material of the pre-structured silicon wafer 10, such that in this embodiment, a widening 92 of the frame 30 for the release is provided. The frame 30 for the release and the recess 86 form a common space, which is implemented in a widening 92 with respect to the embodiments outlined above in Figures 8.2 and 8.3. The material parameters of the at least one protective wafer 40 are essentially identical with respect to the embodiments presented above. Using the embodiment according to Figure 8.4, the recess 86 can be combined with the frame 30 for the release. From the embodiment according to Figure 8.3, it can be seen that the frame 30 for the release of the recess 86 for receiving the leg 96 of the at least one protective wafer 40 can also be separated at different depths (cf.Representation according to Figure 8.2). Furthermore, the invention relates to the use of the method for producing and singulating MEMS components 24, either designed as MEMS chips or as MEMS arrays 20 with sensitive surfaces 28, in particular designed as micromirrors.
[0056] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art.
Claims
Claims 1 . Method for producing and singulating MEMS components (24) and / or MEMS arrays (20) having sensitive surfaces (28) from silicon wafers (10), comprising at least the following method steps: h) providing the silicon wafer (10) with pre-structured individual MEMS components (24) as MEMS chips or as MEMS arrays (20), i) introducing a frame (30) for exposing the MEMS components (24) as MEMS chips or as MEMS arrays (20) around them in the silicon wafer (10), j) applying at least one protective wafer (40) to the silicon wafer (10) for covering the MEMS components (24) as MEMS chips or as MEMS arrays (20), k) 180° turning (50) of the silicon wafer (10), provided with the at least one protective wafer (40) and placing it on a base (52) for carrying out tests and / or assembling electrical / electronic components (56) on its back (14),l) producing at least one predetermined breaking point (70) in the at least one protective wafer (40) and performing separation operations (80) on a rear side of the frame (30) in the silicon wafer (10), m) applying the arrangement according to method step e) to an expandable base (76) and expanding it with a lateral expansion movement (78), and n) receiving the separated MEMS components (24) as MEMS chips or as a MEMS array (20) by means of a removal tool (82).
2. Method according to claim 1, characterized in that according to method step b) the frame (30) in the material of the silicon wafer (10) is produced by means of an etching process, in particular by means of trench etching (DRIE) in a defined frame width (72).
3. Method according to claims 1 and 2, characterized in that a depth (32) of the frame (30) is produced such that it extends at least to a bulk material region / solid material region (34) in the silicon wafer (10).
4. Method according to claims 1 to 3, characterized in that according to method step c) the at least one protective wafer (40) is applied to a front side (12) of the silicon wafer (10) by means of an adhesive connection (42) or a temporary or permanent bond connection (44).
5. Method according to claims 1 to 4, characterized in that the at least one protective wafer (40) is made of silicon, glass, silicon carbide, ceramic, plastic or metal.
6. Method according to claims 1 to 5, characterized in that in the material of the at least one protective wafer (40) at least one predetermined breaking point (70) is produced either by perforation or during the application according to method step c) or before the separation of the MEMS components (24), designed as MEMS chips or MEMS array (20) or by weakening the crystal structure by laser irradiation.
7. Method according to claims 1 to 6, characterized in that after carrying out method step b), a connecting surface (45) for the adhesive connection (42) or the temporary or permanent bond connection (44) is formed by means of a structuring step with a recess (86) in the material of the silicon wafer (10).
8. Method according to claim 7, characterized in that the recess (86) for the release is provided with a height difference (88) relative to a depth of the frame (30), or in a depth (90) identical to the frame (30).
9. Method according to claim 7, characterized in that the recess (86) is designed by a widening (92) combined with the frame (30) for clearance.
10. Method according to claim 7, characterized in that the recess (86) is produced separately from the frame (30) for the purpose of exposure.
11. Method according to claims 1 to 10, characterized in that after the 180° turning (50) according to method step d), wafer level tests, an assembly with electrical and / or electronic components (56) and / or a connection with a ceramic plate are carried out on the back side (14) of the silicon wafer (10).
12. Method according to claims 1 to 11, characterized in that according to method step f) the expandable base (76) is laminated onto an upper side (46) of the at least one protective wafer (40).
13. Method according to claims 1 to 12, characterized in that according to method step e) the separating operations (80) on the back side (14) of the silicon wafer (10) are carried out by stealth dicing.
14. Use of the method according to one or more of claims 1 to 13 for producing and singulating MEMS structures (22) from MEMS components (24), designed as MEMS chips or as MEMS arrays (20) with sensitive surfaces (28).