Reference circuit and method

Abstract

A reference circuit comprises: a first current generator comprising first and second current branches respectively comprising first and second bipolar transistors of different emitter areas for generating a first current in the first branch that has a positive temperature coefficient; a second current generator comprising a third current branch for generating a second current that mirrors the first current; a third bipolar transistor in a fourth current branch for generating a first voltage that has a negative temperature coefficient; and a resistor network arranged to combine the second current and the first voltage to produce an output reference voltage that is compensated against variation in temperature.

Description

[0001] REFERENCE CIRCUIT AND METHOD

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to a circuit or method for generating a reference voltage or reference current.

[0004] BACKGROUND OF THE INVENTION

[0005] Most integrated circuits require an on-chip voltage reference circuit that produces a constant reference voltage for use as a standard reference. The reference voltage is ideally independent of power supply variations, circuit load, and has very low temperature drift. Historically, the reference voltage was around 1.25 V, close to the bandgap of silicon, so was called a ‘bandgap reference’ (BGR) voltage, and the circuit for generating it was called a bandgap reference circuit. However, more recently, the reference voltage required has been lower, such as less than 1 V, but the circuits are still referred to in the art as bandgap reference circuits, for historical reasons, so references herein to ‘bandgap reference’, ‘BGR’, and the like should be understood simply as meaning ‘standard’ or ‘reference’ and vice versa.

[0006] Fig. 1 shows a conventional sub-lV or current mode Bandgap reference circuit. It consists of bipolar junction transistors (BJTs) Qi, Q2 with different emitter areas. The opamp OP adjusts the current through field effect transistors (FETs) Mo, Mi such that the potentials at nodes A and B will be equal. The current 7RI through Ri can be obtained as follows: where EBEX is the base-emitter voltage across transistor Qx. This relationship is obtained by noting that the potential at node A is FBEI (the transistor Qi is diode-connected); the potential at node B is the sum of FBE2 plus the voltage drop across Ri; and setting these two potentials equal to each other and rearranging.

[0007] The general formula for a BJT base-emitter voltage is: where: VT is the thermal equivalent voltage (=ET / q, where k is the Boltzmann constant, T is the junction temperature in Kelvin, and q is the electron charge); Ic is the bias current in the BJT core; and Is is the reverse saturation current of the BJT. Substituting this into (la) yields: where n is the ratio of the current densities in Qi and Q2 (inversely proportional to their emitter areas).

[0008] The two resistors labelled R2A and R2B in Fig. 1 both have substantially the same resistance value, which will simply be called R2, and these resistors may also each be referred to as R2. The current ZR2 through each resistor R2 is simply given by:

[0009] From (1) it is clear that 7RI has a positive temperature coefficient (from the VT term), so the current carried by Ri is ‘proportional to absolute temperature’ (PTAT). From (2) in conjunction with (lb) it can be found that each R2 carries a current that is inversely related to temperature i.e. ‘complementary to absolute temperature’ (CTAT) [from (lb), VBE has an element proportional to temperature in FT, but Is is even more strongly temperature dependent and is in a denominator. Overall, this makes the slope of ZR2 with respect to temperature have a negative gradient.]

[0010] The core current Io flowing through Mi is given by the sum of the currents through Ri and R2B:

[0011] M2 is configured as a current mirror, so also passes current h, which flows through R3 to give the bandgap reference voltage VBG across R3 of:

[0012] Equation (4) shows that output voltage will be generated by the summation of PTAT and CTAT voltages, hence by adjusting the scaling ratio one could achieve very low temperature coefficient (TC) of the output voltage. Typically, VBE has TC of -2mV / °C and the PTAT term has +250pV / °C hence the PTAT voltage has to be amplified with gain of 8, which can be adjusted with the ratio of R2 / R1. From (4), one can understand that the output voltage can be adjusted and tuned to less than IV, this is an essential requirement for CMOS technologies, such as the 65nm process, where the supply voltage is limited to 1.2V.

[0013] Like any self-bias circuit, this architecture also typically requires a startup circuit to avoid a zero current operating point (an undesirable, but stable, state of the bandgap reference circuit, in which zero core current is flowing, and so the output voltage is zero and not the required reference voltage). Transistor Msi-S3 and the NAND gate GT1 form a conventional startup circuit. Msi acts as current mirror transistor and MS2 acts as triode region biased resistor. This works as follows, if the bandgap core bias current Io is effectively zero (i.e. at or below the leakage level of a MOSFET), then the current through Msi is zero and hence the potential at node N1 stays very close to the ground potential and the output logic level of the NAND gate GT1 is in the ‘high’ state. Due to the high output of the NAND gate, the transistor Mss will turn on and pulls the opamp output node Z close to ground potential, switching on transistors Mo, Mi, M2, and hence current will flow and the bandgap reference circuit will reach the desired steady state value. Once the current reaches the desired value, the potential at node N1 reaches close to the VDD, hence transistor Mss turns off and lets the bandgap reference circuit operate normally. A main important property of the start-up circuit is it should reliably turn off as soon as the reference circuit reaches the normal mode of operation, otherwise it will impact the bandgap reference performance.

[0014] However, the above BGR circuit and start-up circuit architecture of Fig. 1 can have several problems, including:

[0015] • Although the TC is reduced, the output voltage can still drift with temperature, and it is desired to make the TC smaller.

[0016] • Trimming is required (e.g. laser trimming of R3) which uses automatic test equipment (ATE) to measure the output voltage, and then adjust the BGR output voltage post silicon fabrication. When operating, the opamp OP inputs will have a small offset voltage, such as 2mV; in other words, the nodes A and B are not at exactly the same potential. The opamp offset differential voltage will be amplified by a large factor, which corrupts the output. This will compromise the temperature coefficient. This mandates multi-point trimming and hence additional ATE time and cost.

[0017] • The resistors R2A and R2B take up a lot of area (which is valuable chip real estate - for example one resistor can require the same area as 5000 logic gates); so for a circuit with dimensions of say 40 microns x 50 microns, the resistors R2 might occupy about 80% of that area. In a conventional circuit, the value of R1 can be around 20kQ which implies the value of R2 must be slightly less than about 200kQ, such as around 160kQ.

[0018] • The start-up circuit has multiple stable operating points, so can get stuck at several undesirable operating currents (whereas the voltage mode BGR gets stuck only at the zero current point). So, reliability of performance of the start- up circuit is a problem. In chip manufacture, roughly 8% of the loss of rejected chips is due to failure of the start-up circuit, which brings down the total yield.

[0019] The present invention has been devised in view of the above problems.

[0020] SUMMARY OF THE INVENTION

[0021] According to a first aspect of the invention there is provided a reference circuit comprising: a first current generator comprising first and second current branches respectively comprising first and second bipolar transistors of different emitter areas for generating a first current in the first branch that has a positive temperature coefficient; a second current generator comprising a third current branch for generating a second current that mirrors the first current; a third bipolar transistor in a fourth current branch for generating a first voltage that has a negative temperature coefficient; a resistor network arranged to combine the second current and the first voltage to produce an output reference voltage that is compensated against variation in temperature.

[0022] Another aspect of the invention provides a method for generating a reference voltage that is compensated against variation in temperature, the method comprising: generating a first current that has a positive temperature coefficient using a first current generator comprising first and second current branches respectively comprising first and second bipolar transistors of different emitter areas for generating the first current in the first branch; generating a second current that mirrors the first current using a second current generator comprising a third current branch in which the second current is generated; generating a first voltage that has a negative temperature coefficient using a third bipolar transistor in a fourth current branch; combining the second current and the first voltage using a resistor network to produce an output reference voltage that is compensated against variation in temperature.

[0023] A further aspect of the invention provides a start-up circuit arranged receive an input signal and to provide an output voltage to cause current to flow in an external circuit when the input signal is in a first state, and the start-up circuit arranged to be in an off state when the input signal is in a second state, wherein the start-up circuit comprises: at least one FET which is arranged to be switched on by the input signal being in the first state, and which thereby pulls a first node to a first voltage; and an inverter gate comprising an input connected to the first node and an output connected to the gate of a further FET and arranged to switch the further FET to provide the output voltage to the external circuit, whereby when the input signal is in the second state, the at least one FET and the further FET are switched off.

[0024] Further optional features of the invention are defined in the dependent claims.

[0025] DESCRIPTION OF THE DRAWINGS

[0026] Embodiments of the invention will now be described, by way of non-limiting example, with reference to the accompanying drawings. The invention may further comprise, in any combination, any features of the embodiments which will now be described.

[0027] Fig. 1 is a schematic circuit depiction of a conventional bandgap reference circuit;

[0028] Fig. 2A is a schematic circuit depiction of a reference circuit according to an embodiment of the invention;

[0029] Fig. 2B is a schematic flow chart illustrating the method of operation of a reference circuit according to an embodiment of the invention;

[0030] Fig. 2C is a schematic circuit depiction of a reference circuit according to another embodiment of the invention;

[0031] Fig. 3 is a schematic circuit depiction of an exemplary opamp circuit for use in an embodiment of the invention such as depicted in Fig. 2C;

[0032] Fig. 4 is a schematic circuit depiction of a portion of an exemplary chopping clock network for use in an embodiment of the invention such as depicted in Fig. 2C, together with schematic output waveforms;

[0033] Fig. 5 is a schematic circuit depiction of a start-up circuit according to an embodiment of the invention; and

[0034] Fig. 6 is a graph showing output reference voltage as a function of temperature for a conventional reference circuit and for a reference circuit according to an embodiment of the invention. In the drawings, like parts are indicated with like reference numerals, and, for conciseness, description thereof will not be repeated.

[0035] DETAILED DESCRIPTION OF THE INVENTION

[0036] Fig. 2A shows a reference circuit according to one embodiment of the invention which has a first current generator 100 comprising transistors MIO and Mi l, opamp OP1, BJTs QI and Q2, and the resistors as shown within the dashed line denoting the first current generator. The first current generator comprises a first current branch from node Y through QI, and a second current branch from node X through Q2. A second current generator comprises transistor M13 and provides a third current branch taking current flowing through that transistor M13. A fourth current branch comprises BJT Q3. The reference circuit further comprises a resistor network comprising resistors RA, RB and RC.

[0037] In general, most of the transistors used in embodiments of the invention throughout this description are preferably field effect transistors (i.e. unipolar transistors, such as MOSFETs) as shown in the drawings, but are referred to simply as just transistors or FETs, though other transistor types could be used; except for when bipolar transistors are explicitly required, such as Q I, Q2, which are also referred to as bipolar junction transistors or BJTs, and are shown with the appropriate circuit symbol in the drawings.

[0038] The circuit works as follows with reference to Figs. 2A and 2B. Rp defines the core current as expressed in equations (la) and (1) (with Rp in place of Ri). The resistors RM enable the same current in the BGR core in each of the first and second current branches, and this first current, labelled IPTAT in Fig. 2A in the first current branch is a current that is PTAT. This is the step S 10 in Fig. 2B of generating a first current that is PTAT in a first current branch.

[0039] The transistor M13 is connected as a current mirror and so acts as a second current generator that generates a second current in the third current branch which is the same PTAT current IPTAT as the first current in the first current branch. This is the step S12 in Fig. 2B.

[0040] Next, node C will have a CTAT voltage nature due to the base-emitter voltage relationship (VBE) provided by the third transistor Q3 which is in the fourth current branch. This completes the step S14 of generating a first voltage that is CTAT (the voltage at node C).

[0041] Finally, in Step SI 6, the resistor network, comprising resistors RA, RB and RC, combines the second current (which is PTAT) and first voltage (which is CTAT) to produce an output reference voltage VRef that is compensated against temperature variation. The compensation reduces the TC of the reference voltage.

[0042] The output reference voltage VRef, also equivalently referred to as the bandgap reference voltage VBG, is given by the following equation:

[0043] Equation (5) shows the expression for the output voltage, which is similar to the conventional current mode BGR without having its disadvantages. The value of n (the ratio of the current densities in QI and Q2) can be selected by choice of the relative emitter areas of QI and Q2; and the ratio of resistor values RC / Rp can also be selected. In this way the compensation can be optimized to minimize the temperature coefficient (TC) of the output voltage for a desired operating point. Similarly, the values of the resistors RA, RB and RC can be selected to provide an output voltage of a desired magnitude. In some embodiments, the resistor RB is a trim network that can be adjusted post-silicon fabrication in order to set VBG to a desired specific value such as 0.5 V. In some embodiments of this invention RBI and / or RB2 can play a significant role because it provides curvature compensation due to the non-linear beta dependent voltage across it so that it can compensate the non-linear 2ndorder term inherent in the nature of the BJT base-emitter voltage, VBE.

[0044] In this embodiment of the invention, instead of using large resistors R2A, R2B (as in Fig. 1), in this circuit PTAT current has been mixed with CTAT voltage elsewhere so that the opamp inputs are not loaded, so that the offset effect is reduced. In a further optional feature, the opamp OP2 adjusts the gate of transistor M14 such that for transistors M12 and MIO their drain-source voltage VDS will be equal, so that current mirroring error due to channel length modulation will be minimized or eliminated.

[0045] Fig. 2C illustrates a further embodiment of the invention that in general is the same as Fig. 2A, but with additional preferred features: (i) an adaptive bias opamp; (ii) chopper stabilization; and (iii) a start-up circuit. Each of these further features can be included individually (i.e. separately), or in any combination of pairs of features, or all three together. For convenience and conciseness they are all included together in this embodiment, as explained below, but this is not essential.

[0046] Fig. 3 shows the adaptive bias opamp, for use as the first opamp OP1 in Fig. 2C, with the inputs at nodes X and Y and output at node P. Being adaptive bias means it does not require any bias current from any external circuit. Fig. 3 depicts a folded cascode opamp with an opamp driven tail current. The tail current driven opamp OP3 has inputs connected to node W and to output node P. The tail current driven opamp OP3 will adjust the bias current such that nodes W and P will have equal potential (which is equal to the output voltage Vout at the node P), hence there is much less systematic offset.

[0047] To reduce the offset effect on the BGR output, the first opamp OP1 can be implemented with chopper stabilization, as is known in the art, as indicated schematically by the rectangles with crosses in Fig. 2C, which will swap the opamp inputs and outputs with a slow clock. A chopping clock network 60 is provided to drive the chopper circuitry. Fig. 4 shows a portion of the chopping clock network 60, which is driven by a basic clock signal Clk_Chop received at the input 62. The circuit is based on a SR latch with additional inverter gates to introduce propagation delay. Accordingly, when one output changes from high to low, there is a delay until the other output changes from low to high. In this way the clock signals (clkp,clkn) present at the outputs 64 and 66 are never both high simultaneously. This is illustrated in the clock output waveforms in the lower portion of Fig. 4. So, this circuit provides a non-overlap clock phase generator for chopping purposes. The output clocks (clkp,clkn) toggle the switching transistors (not shown) which are driving the inputs of the first opamp OP1 in Fig. 2C (a form of chopping operation).

[0048] Fig. 5 depicts details of an embodiment of the start-up circuit 70 (also known in the art as a kick-up circuit or kick-start circuit) of a preferred embodiment of Fig. 2C. This circuit can improve the reliability of the BGR compared to that of Fig. 1. The start-up circuit receives an input at the nodes labelled EN; the input is a ‘disable’ signal, so that when it is ‘high’ the function is to turn off (disable) the start-up circuit; and the input signal is switched to Tow’ when it is required for the start-up circuit to be enabled to generate an output to start-up the voltage reference circuit (to prevent it being stuck in an operating state with no current flowing). The field effect transistors M30, M31, M34 are operated by the input signal applied to their gates (EN). When the input signal is high, transistors M30 and M31 are switched off so that no current flows from the supply VDD; and transistor M34 is conductive to pull the gates of transistors M33 and M35 low so that they are also switched off to prevent current flow to ground in that part of the circuit. This makes sure the start-up circuit will be in the off state so that power will be saved during power down state (hence better battery lifetime). When the input (EN) is low (to enable the start-up circuit to kick-start a BGR circuit), the transistors M30, M31, M33 and M35 are all switched on. Transistor M32 copies (mirrors) the current from the BGR core (because the gate of M32 is connected to node P - see Fig. 2A or 2C), and M31 carries a fixed current defined by the resistor Ro and transistor M33. If there is no current in the BGR core (i.e. it is stuck in the no current state), then transistor M32 will also not be passing any current (switched off), which means that node F will be stuck at low potential (pulled by M35), and hence the output of the inverter gate INV will be high, which will switch on transistor M37 to pull down the output node P (which is common with the node P in Fig. 2A, 2C) such that current will be initiated in the voltage reference circuit (switching on e.g. transistors MO, Ml, M2, M3 in Fig. 2A and equivalent in Fig. 2C). This, of course, also switches on transistor M32, and as soon as the potential at node F rises enough to flip the inverter INV to having a Tow’ output at node Z, this switches off transistor M37 such that the potential at node P can rise and stabilize to whatever value is dictated by the BGR circuit (so that the final output reference voltage of the BGR circuit is not affected by the start-up circuit). A further preferred feature of this circuit is the transistor M36, which will try to pull back node F much more quickly compared to the conventional circuit technique.

[0049] The circuit of Fig. 5 can be used on its own for providing a start-up for other circuits and is not limited only to voltage reference or BGR circuits.

[0050] Figure 6 is a graph showing plots of simulated results of the output voltage of a voltage reference circuit (BGR circuit) as a function of temperature. The plot 80 is for a conventional circuit, such as Fig. 1 ; and the plot 82 is for a circuit according to an embodiment of the invention. As can be seen, the variation in output voltage over the illustrated temperature range is reduced by a factor of about 3 with the embodiment of the invention.

[0051] Typically, the fourth current branch (as referred to herein, i.e. the branch comprising the third bipolar transistor Q3) is a PTAT current branch only (whilst the adjacent node C has a CTAT voltage, current in the fourth current branch is PTAT).

[0052] The bandgap reference voltage may therefore be generated by effectively summing CTAT voltage and PTAT current - in particular in the examples described above, the second current (which is generated by the third current branch and is PTAT) is combined with the first voltage (which is the voltage at node C in the example shown, and is CTAT) by a resistor network RA, RB and RC so as to generate the bandgap reference voltage. Due to the circuit design, the PTAT current in the fourth branch is equivalent to the current generated by the third branch - all branch currents are the same, so the second current may equivalently be referred to as the current in the fourth current branch.

[0053] This use of CTAT voltage and PTAT current provides a more accurate reference voltage than circuits which use both CTAT and PTAT current. This also allows the circuit to work under a lower voltage supply than circuits which use both a CTAT and PTAT current. In particular the circuit may be effective at less than 1000 mV, such as less than 900 mV supply, hence at least 10% lower power consumption. This makes the present invention suitable for automotive applications, bio-medical, and wireless applications. Also due to low supply voltage requirements, the present invention will be very suitable for use in designing circuits in advanced CMOS technologies like 28 nm, 16 nm.

[0054] Furthermore, the fourth current branch typically comprises a third transistor (Q3) which has a resistor (RB2, see Fig 2b and 2c) which can cancel the base current- induced error. This may improve the output voltage accuracy of the present circuit by implementing the curvature compensation as mentioned above.

[0055] A further advantage of the present invention is the use of an adaptive bias in the opamp, which changes the bias current of the opamp according to the temperature rather than being fixed as in the previous state of art. This may improve the systematic offset performance of the opamp.

[0056] It will be understood that the invention is not limited to the embodiments described above. Various modifications and improvements can be made without departing from the concepts disclosed herein and the scope of the appended claims. Except where mutually exclusive, any of the features may be employed separately or in combination with any other features and the disclosure extends to all combinations and sub-combinations of one or more features disclosed herein. Applications:

[0057] Although generally applicable to any circuit that requires a reference voltage, embodiments of the invention are particularly useful in precision sensors, for example fuel gauges. Therefore the present invention may relate to a sensor, often a precision sensor, comprising a reference circuit as described herein.

[0058] Main Fuel gauges need high performance bandgap reference circuits (BGR) to accurately sense the fuel level. This requires a multi -temperature trimming cycle in the manufacturing process which consumes money and time. With particular embodiments of the invention, trimming is no longer required because the output variation due to the temperature is reduced. Therefore, the present invention may relate to a fuel gauge, such as a main fuel gauge, comprising a reference circuit as described herein.

[0059] Other examples of applications of the invention include electric vehicles (EVs) and in ADC / DAC reference generators. Therefore, the present invention may relate to an electric vehicle, comprising a reference circuit as described herein. Furthermore, the present invention may relate to a generator, often a ADC / DAC reference generator, comprising a reference circuit as described herein.

[0060] A further application of the reference circuits described herein is in biomedical sensors for the ECG signals. The present invention is especially beneficial for such applications as the accuracy is highly important, and the present invention provides the necessary precision. Therefore, the present invention may relate to a biomedical sensor, such as biomedical sensor for ECG signals, comprising a reference circuit as described herein.

[0061] It is possible to implement embodiments the invention as one or more hard-wired electronic circuits, some or all of which can be integrated onto a single electronic chip (IC, integrated circuit). A single chip can also be provided with multiple reference circuits each embodying the present invention.

Claims

CLAIMS1. A reference circuit comprising: a first current generator comprising first and second current branches respectively comprising first and second bipolar transistors of different emitter areas for generating a first current in the first branch that has a positive temperature coefficient; a second current generator comprising a third current branch for generating a second current that mirrors the first current; a third bipolar transistor in a fourth current branch for generating a first voltage that has a negative temperature coefficient; and a resistor network arranged to combine the second current and the first voltage to produce an output reference voltage that is compensated against variation in temperature.

2. A reference circuit according to claim 1, wherein each current branch comprises a respective FET, and the gates of the FETs are connected in common.

3. A reference circuit according to claim 2, wherein the gate of each said FET is connected to a voltage supply through a respective resistor.

4. A reference circuit according to any preceding claim, further comprising a first opamp with inputs connected to the first and second current branches, and arranged to reduce systematic voltage off-set between nodes in the first and second current branches.

5. A reference circuit according to claim 4, wherein said first opamp comprises an adaptive bias opamp employing a slave opamp driving a tail current.

6. A reference circuit according to claim 4 or 5, further comprising switching circuitry to repeatedly swap over the inputs of the first opamp to reduce systematic voltage off-set.

7. A reference circuit according to claim 6, further comprising a SR-latch-based circuit for generating non-overlapped clock signals for driving the switching circuitry.

8. A reference circuit according to claim 2 or any claim when dependant on claim 2, wherein the fourth current branch comprises a further opamp, wherein one input of the further opamp is connected to the common connection of the gates of the FETs, another input of the further opamp is connected to the drain of the FET in the fourth current branch, and the output of the further opamp is connected to the gate of a further FET in the fourth current branch.

9. A reference circuit according to any preceding claim, wherein said resistor network comprises a potential divider circuit.

10. A reference circuit according to any preceding claim, wherein the second current is a proportional to absolute temperature, PTAT, current, and wherein the first voltage is a complementary to absolute temperature, CTAT, voltage.

11. A reference circuit according to any preceding claim, wherein the output reference voltage is less than 1 V.

12. A reference circuit according to any preceding claim, further comprising a startup circuit arranged receive an input signal and to provide an output voltage to cause current to flow in the reference circuit when the input signal is in a first state, and the start-up circuit arranged to be in an off state when the input signal is in a second state, wherein the start-up circuit comprises: at least one FET which is arranged to be switched on by the input signal being in the first state, and which thereby pulls a first node to a first voltage; and an inverter gate comprising an input connected to the first node and an output connected to the gate of a further FET and arranged to switch the further FET to provide the output voltage to the reference circuit, whereby when the input signal is in the second state, the at least one FET and the further FET are switched off.

13. A reference circuit according to claim 12, wherein the start-up circuit further comprises a pull-back FET comprising a gate, a source and a drain, wherein the gate is connected to the output of the inverter gate and to the gate of a further FET, and wherein one of the source and drain is connected to the first node at the input of the inverter gate.

14. A method for generating a reference voltage that is compensated against variation in temperature, the method comprising: generating a first current that has a positive temperature coefficient using a first current generator comprising first and second current branches respectively comprising first and second bipolar transistors of different emitter areas for generating the first current in the first branch; generating a second current that mirrors the first current using a second current generator comprising a third current branch in which the second current is generated; generating a first voltage that has a negative temperature coefficient using a third bipolar transistor in a fourth current branch; combining the second current and the first voltage using a resistor network to produce an output reference voltage that is compensated against variation in temperature.

15. A start-up circuit arranged receive an input signal and to provide an output voltage to cause current to flow in an external circuit when the input signal is in a first state, and the start-up circuit arranged to be in an off state when the input signal is in a second state, wherein the start-up circuit comprises: at least one FET which is arranged to be switched on by the input signal being in the first state, and which thereby pulls a first node to a first voltage; and an inverter gate comprising an input connected to the first node and an output connected to the gate of a further FET and arranged to switch the further FET to provide the output voltage to the external circuit, whereby when the input signal is in the second state, the at least one FET and the further FET are switched off.

16. A start-up circuit according to claim 15, further comprising a pull-back FET comprising a gate, a source and a drain, wherein the gate is connected to the output of the inverter gate and to the gate of a further FET, and wherein one of the source and drain is connected to the first node at the input of the inverter gate.

17. A start-up circuit according to claim 15 or 16, wherein the external circuit is a reference circuit.

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