Solder resist evaluation model, solder resist evaluation method, solder resist composition selection method, semiconductor device manufacturing method, and solder resist composition

Abstract

This solder resist evaluation model comprises: a semiconductor package substrate comprising a core substrate, at least one build-up layer provided on one surface of the core substrate, a copper pad provided on a surface of an uppermost layer of the build-up layer, and a solder resist layer for evaluation object, provided on the uppermost layer of the build-up layer and comprising an opening part at a location where the copper pad is provided; a semiconductor element disposed on a surface of the semiconductor package substrate on the side where the solder resist layer is provided and connected to the semiconductor package substrate via a solder ball disposed on the copper pad; and a sealing resin layer disposed between a surface of the semiconductor element on the side facing the semiconductor package substrate and the surface of the semiconductor package substrate on the side facing the semiconductor element.

Description

Model for evaluating solder resist, method for evaluating solder resist, method for selecting solder resist composition, method for manufacturing semiconductor device, and solder resist composition

[0001] The present disclosure relates to a solder resist evaluation model, a solder resist evaluation method, a method for selecting a solder resist composition, a method for manufacturing a semiconductor device, and a solder resist composition.

[0002] In recent years, in semiconductor devices such as semiconductor packages, there has been a demand for more pins, along with smaller package size, lighter weight, and higher density, in response to the miniaturization and increased functionality of electronic devices. Conventional pin-insertion-type dual in-line packages (DIPs) and peripheral terminal-type quad flat packages (QFPs) using connection terminals are no longer able to meet these demands. Therefore, semiconductor packages are shifting to surface-mount packages using wire-bonding technology, such as ball grid arrays (BGAs), chip size packages (CSPs), and multi-chip modules (MCMs). These semiconductor packaging methods use multilayer printed circuit boards made of various materials, such as plastics and ceramics, to establish electrical connections with semiconductor elements. When electrically connecting a semiconductor element to a multilayer printed circuit board, fine wiring is connected in a high-temperature atmosphere by solder reflow or the like, so a solder resist is used as a protective layer on the surface of the multilayer printed circuit board on which the semiconductor element is mounted (see, for example, Patent Documents 1 and 2).

[0003] JP 2000-31628 A JP 2002-296776 A

[0004] The solder resist used in a multilayer printed circuit board is in contact with the build-up layer that constitutes the multilayer printed circuit board, the encapsulating resin layer that encapsulates the electrical connection between the semiconductor element and the multilayer printed circuit board, the solder balls, and other components, and is therefore susceptible to thermal stress from these surrounding materials. When stress concentrates on the solder resist, cracks and peeling may occur in the solder resist. Cracks and peeling in the solder resist can cause deterioration of semiconductor devices. From the perspective of evaluation accuracy, it is desirable to evaluate the solder resist while a TEG (Test Elementary Group) is mounted on the multilayer printed circuit board. However, multilayer printed circuit boards are manufactured through multiple processes, such as film formation of build-up material on a core substrate, electroless copper plating, resist patterning, electrolytic copper plating, resist stripping, and seed etching, and preparing the multilayer printed circuit board requires a long period of time. Therefore, a simpler method for evaluating the solder resist while a TEG is mounted on the multilayer printed circuit board has been desired. The present disclosure has been made in view of the above-mentioned conventional circumstances, and an object of one aspect of the present disclosure is to provide a solder resist evaluation model and a solder resist evaluation method that enable easy evaluation of solder resists. Another object of the present disclosure is to provide a method for selecting a solder resist composition using the above-mentioned method, a solder resist composition selected by the method, and a method for manufacturing a semiconductor device using the same.

[0005] Specific means for achieving the above object are as follows: <1> A solder resist evaluation model comprising: a semiconductor package substrate having a core substrate, at least one buildup layer provided on one surface of the core substrate, copper pads provided on the surface of the uppermost layer of the buildup layers, and a solder resist layer to be evaluated that is provided on the uppermost layer of the buildup layers and has openings where the copper pads are provided; a semiconductor element disposed on the surface of the semiconductor package substrate on which the solder resist layer is provided and connected to the semiconductor package substrate via solder balls disposed on the copper pads; and an encapsulating resin layer disposed between a surface of the semiconductor element facing the semiconductor package substrate and a surface of the semiconductor package substrate facing the semiconductor element. <2> The solder resist evaluation model according to <1>, wherein the pitch of the copper pads is 0.005 mm to 10 mm. <3> The solder resist evaluation model according to <1> or <2>, wherein the diameter of the solder balls before melting is 0.01 mm to 0.50 mm. <4> A solder resist evaluation method, comprising: carrying out an environmental test on the solder resist evaluation model according to any one of <1> to <3>, in which cooling under a first temperature condition of -200°C to 0°C and heating under a second temperature condition of 0°C to 300°C are repeated multiple times; and observing a solder resist layer as an evaluation target included in the solder resist evaluation model after the environmental test.<5> A method for selecting a solder resist composition to be used in manufacturing a semiconductor package substrate constituting a semiconductor device, from among a plurality of types of solder resist compositions, the method comprising: preparing cured films of the plurality of types of solder resist compositions; heating the cured films at a temperature of 200°C to 300°C to prepare cured films after thermal history; obtaining information on a room temperature elongation at 25°C, a low temperature elongation at -60°C, and a low temperature storage modulus at -55°C for the cured films after thermal history; inputting the obtained information into the following formula (1) to calculate a failure rate, including cracking and peeling, when the solder resist composition is applied to the semiconductor package substrate; and selecting solder resist compositions having a failure rate of 60% or less from the plurality of types of solder resist compositions. Failure rate (%) = room temperature elongation + low temperature elongation + low temperature storage modulus + constant (1) <6> The method for selecting a solder resist composition according to <5>, wherein the cured film has an average thickness of 0.5 μm to 50 μm. <7> A method for manufacturing a semiconductor device, comprising: preparing a semiconductor package substrate using a solder resist composition selected by the method for selecting a solder resist composition according to <5> or <6>, connecting the semiconductor package substrate and a semiconductor element, and providing an encapsulating resin layer that covers the connection between the semiconductor package substrate and the semiconductor element. <8> A solder resist composition selected by the method for selecting a solder resist composition according to <5> or <6>. <9> A solder resist composition comprising a photopolymerizable compound having an ethylenically unsaturated group, a photopolymerization initiator, an epoxy resin, and a curing accelerator, wherein when a cured film of the solder resist composition is heated at 200°C to 300°C to form a cured film after thermal history, the cured film after thermal history has a failure rate (%) including cracking and peeling, which is expressed by formula (1) based on the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C, of ​​60% or less.Failure rate (%) = room temperature elongation rate + low temperature elongation rate + low temperature storage modulus + constant (1).

[0006] According to certain aspects of the present disclosure, it is possible to provide a solder resist evaluation model and a solder resist evaluation method that enable simple evaluation of solder resists. Also, according to other aspects of the present disclosure, it is possible to provide a method for selecting a solder resist composition using these methods, a solder resist composition selected by this method, and a method for manufacturing a semiconductor device using the same.

[0007] Fig. 1 is a cross-sectional view of an embodiment of a solder resist evaluation model of the present disclosure; Fig. 2 is a diagram showing the relationship between room temperature elongation (%) and failure incidence when a reflow process is performed, which is the result of JMP analysis; Fig. 3 is a diagram showing the relationship between low temperature elongation (%) and failure incidence when a reflow process is performed, which is the result of JMP analysis; Fig. 4 is a diagram showing the relationship between low temperature storage elastic modulus and failure incidence when a reflow process is performed, which is the result of JMP analysis; Fig. 5 is a diagram showing the relationship between predicted values ​​of failure incidence rate and actual measured values ​​of failure incidence rate; Fig. 6 is a diagram showing the results of JMP analysis.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments. In the following embodiments, components (including element steps, etc.) are not essential unless otherwise specified. The same applies to numerical values ​​and their ranges, and do not limit the present disclosure.

[0009] In the present disclosure, the term "process" includes not only processes that are independent of other processes, but also processes that cannot be clearly distinguished from other processes as long as the purpose of the process is achieved. In the present disclosure, numerical ranges indicated using "to" include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In numerical ranges described in stages in the present disclosure, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another numerical range described in stages. Furthermore, in numerical ranges described in the present disclosure, the upper or lower limit value of that numerical range may be replaced with a value shown in the examples. In the present disclosure, each component may contain multiple corresponding substances. When multiple substances corresponding to each component are present in the composition, the content or amount of each component means the total content or amount of the multiple substances present in the composition, unless otherwise specified. In the present disclosure, particles corresponding to each component may contain multiple types of particles. When multiple types of particles corresponding to each component are present in a composition, the particle size of each component refers to the value for the mixture of those multiple types of particles present in the composition, unless otherwise specified. In this disclosure, the terms "layer" and "film" include cases where the layer or film is formed over the entire area when the layer or film is observed, as well as cases where the layer or film is formed only in a portion of the area. In this disclosure, the term "laminated" refers to stacking layers, and two or more layers may be bonded or detachable. In this disclosure, "(meth)acrylate" refers to at least one of acrylate and methacrylate. In this disclosure, the average thickness of a layer or film is determined by measuring the thickness at five points on the layer or film and calculating the arithmetic mean value. The thickness of a layer or film can be measured using a micrometer or the like. In this disclosure, if the thickness of a layer or film can be measured directly, it is measured using a micrometer. On the other hand, the thickness of a single layer or the total thickness of multiple layers can be measured by observing the cross-section of the target object using an electron microscope.

[0010] <Solder Resist Evaluation Model> The solder resist evaluation model of the present disclosure includes a semiconductor package substrate having a core substrate, at least one buildup layer provided on one surface of the core substrate, copper pads provided on the surface of an uppermost layer of the buildup layers, and a solder resist layer to be evaluated that is provided on the uppermost layer of the buildup layers and has openings where the copper pads are provided, a semiconductor element disposed on the surface of the semiconductor package substrate on the side where the solder resist layer is provided and connected to the semiconductor package substrate via solder balls disposed on the copper pads, and an encapsulating resin layer disposed between the surface of the semiconductor element facing the semiconductor package substrate and the surface of the semiconductor package substrate facing the semiconductor element. The solder resist evaluation model of the present disclosure enables easy evaluation of solder resists.

[0011] Hereinafter, an embodiment of a solder resist evaluation model according to the present disclosure will be described with reference to the drawings. Note that the configuration of this embodiment is not limited to the configuration shown in the drawings. Furthermore, the sizes of components in the drawings are conceptual, and the relative size relationships between components are not limited to these.

[0012] FIG. 1 is a cross-sectional view of one embodiment of a solder resist evaluation model according to the present disclosure. The solder resist evaluation model 1 shown in FIG. 1 illustrates a configuration in which one buildup layer 20 is provided on one surface of a core substrate 10. Note that, in the solder resist evaluation model according to the present disclosure, two or more buildup layers 20 may be provided on one surface of the core substrate 10. The solder resist evaluation model 1 includes a semiconductor package substrate 50 having a core substrate 10, a buildup layer 20 provided on one surface of the core substrate 10, a plurality of copper pads 30 provided on the surface of the buildup layer 20, and a solder resist layer 40 as an evaluation target provided on the buildup layer 20 and having openings 42 at the locations where the copper pads 30 are provided. The solder resist evaluation model 1 also includes a semiconductor element 60. The semiconductor element 60 includes a polyimide layer 70 and a copper pad 80 provided on the polyimide layer 70. The semiconductor element 60 is disposed on the surface of the semiconductor package substrate 50 on which the solder resist layer 40 is provided, with the surface on which the copper pads 80 are provided facing the surface of the semiconductor package substrate 50 on which the solder resist layer 40 is provided. The semiconductor element 60 is connected to the semiconductor package substrate 50 via solder balls 90 that are disposed on the copper pads 30 and in contact with the copper pads 80. Furthermore, in the solder resist evaluation model 1, a sealing resin layer 100 is disposed between the surface of the semiconductor element 60 facing the semiconductor package substrate 50 and the surface of the semiconductor package substrate 50 facing the semiconductor element 60.

[0013] By configuring the solder resist evaluation model 1 as described above, the solder resist layer 40 comes into contact with or is located near the sealing resin layer 100, the copper pad 30, and the solder ball 90. As a result, the effects of thermal stress occur between the solder resist layer 40 and the sealing resin layer 100, between the solder resist layer 40 and the copper pad 30, and between the solder resist layer 40 and the solder ball 90, making it easier for cracks and peeling due to thermal stress to occur in the solder resist layer 40 being evaluated.

[0014] The core substrate used in the solder resist evaluation model of the present disclosure is not particularly limited and may be the same as or different from the core substrate constituting the semiconductor device. Examples of the core substrate include glass epoxy substrates, polyester substrates, polyimide substrates, BT resin substrates, and thermosetting polyphenylene ether substrates. A patterned conductor layer (circuit) may be formed on one or both sides of the core substrate, or no conductor layer may be formed on either side of the core substrate. From the viewpoint of the likelihood of warping, it is preferable to use a core substrate having a patterned conductor layer formed on one side.

[0015] The average thickness of the core substrate is not particularly limited, and may be the same as or different from the average thickness of the core substrate constituting the semiconductor device. The average thickness of the core substrate is preferably 0.2 mm to 3.0 mm, more preferably 0.4 mm to 1.4 mm, and even more preferably 0.7 mm to 1.0 mm.

[0016] The glass transition temperature of the core substrate is not particularly limited, and may be the same as or different from the glass transition temperature of the core substrate constituting the semiconductor device. The glass transition temperature of the core substrate is preferably 100°C to 500°C, more preferably 150°C to 400°C, and even more preferably 200°C to 300°C. The glass transition temperature of the core substrate refers to a value measured by the method described in the examples.

[0017] The thermal expansion coefficient of the core substrate below its glass transition temperature is not particularly limited, and may be the same as or different from the thermal expansion coefficient of the core substrate constituting the semiconductor device below its glass transition temperature. The thermal expansion coefficient of the core substrate below its glass transition temperature is preferably 1 ppm / °C to 30 ppm / °C, more preferably 3 ppm / °C to 20 ppm / °C, and even more preferably 5 ppm / °C to 15 ppm / °C. The thermal expansion coefficient of the core substrate refers to a value measured by the method described in the Examples. The thermal expansion coefficient of the core substrate above its glass transition temperature is not particularly limited, and may be the same as or different from the thermal expansion coefficient of the core substrate constituting the semiconductor device above its glass transition temperature. The thermal expansion coefficient of the core substrate above its glass transition temperature is preferably 0.01 ppm / °C to 4.0 ppm / °C, more preferably 0.1 ppm / °C to 3.0 ppm / °C, and even more preferably 0.5 ppm / °C to 2.1 ppm / °C. The thermal expansion coefficient of the core substrate is a value measured by the method described in the examples.

[0018] The elastic modulus of the core substrate is not particularly limited, and may be the same as or different from the elastic modulus of the core substrate constituting the semiconductor device. The elastic modulus of the core substrate is preferably 5 GPa to 80 GPa, more preferably 15 GPa to 60 GPa, and even more preferably 25 GPa to 45 GPa. The elastic modulus of the core substrate refers to a value measured by dynamic mechanical analysis (DMA).

[0019] When a conductor layer is formed on the core substrate, the average thickness of the conductor layer is not particularly limited and may be the same as or different from the thickness of the conductor layer constituting the semiconductor device. The average thickness of the conductor layer is preferably 5 μm to 40 μm, more preferably 8 μm to 30 μm, and even more preferably 10 μm to 25 μm.

[0020] In the solder resist evaluation model of the present disclosure, a buildup layer is provided on one surface of a core substrate. In the solder resist evaluation model of the present disclosure, a buildup layer may or may not be provided on other surfaces of the core substrate. From the viewpoint of facilitating evaluation, it is preferable that a buildup layer be provided only on one surface of the core substrate. When the solder resist evaluation model of the present disclosure is configured such that a buildup layer is provided only on one surface of the core substrate, it is more likely to warp due to thermal history than a typical multilayer printed circuit board in which buildup layers are provided on both surfaces of the core substrate. When warping occurs in the solder resist evaluation model, stress is more likely to be applied to the solder resist layer in contact with the buildup layer, encapsulating resin layer, solder balls, etc., making cracks and peeling of the solder resist more likely to occur. Furthermore, when the solder resist evaluation model of the present disclosure is configured such that a buildup layer is provided only on one surface of the core substrate, the number of steps required to form the buildup layer can be reduced. Therefore, evaluation can be performed more easily than with conventional multilayer printed circuit boards.

[0021] The buildup layer used in the solder resist evaluation model of the present disclosure may be one layer or two or more layers. From the viewpoint of enabling easier production of the solder resist evaluation model, the buildup layer is preferably one or two layers, and more preferably one layer. The material constituting the buildup layer is not particularly limited, and may be the same as or different from the components of the buildup layer constituting the semiconductor device.

[0022] The average thickness of the buildup layer (when there are two or more buildup layers, the average thickness of each layer) is preferably 5 μm to 50 μm, more preferably 10 μm to 40 μm, and even more preferably 15 μm to 30 μm.

[0023] The glass transition temperature of the buildup layer is not particularly limited, and may be the same as or different from the glass transition temperature of the buildup layer constituting the semiconductor device. The glass transition temperature of the buildup layer is preferably 80°C to 220°C, more preferably 100°C to 200°C, and even more preferably 150°C to 170°C. The glass transition temperature of the buildup layer refers to a value measured by thermomechanical analysis (TMA) described in the examples.

[0024] The thermal expansion coefficient of the buildup layer below its glass transition temperature is not particularly limited, and may be the same as or different from the thermal expansion coefficient of the buildup layer constituting the semiconductor device below its glass transition temperature. The thermal expansion coefficient of the buildup layer below its glass transition temperature is preferably 5 ppm / °C to 60 ppm / °C, more preferably 10 ppm / °C to 50 ppm / °C, and even more preferably 20 ppm / °C to 40 ppm / °C. The thermal expansion coefficient of the buildup layer above its glass transition temperature is not particularly limited, and may be the same as or different from the thermal expansion coefficient of the buildup layer above its glass transition temperature. The thermal expansion coefficient of the buildup layer above its glass transition temperature is preferably 30 ppm / °C to 180 ppm / °C, more preferably 50 ppm / °C to 150 ppm / °C, and even more preferably 80 ppm / °C to 120 ppm / °C. The thermal expansion coefficient of the buildup layer refers to a value measured by the method described in the Examples.

[0025] The material constituting the build-up layer contains a resin component and an inorganic filler, and may contain a curing agent, a curing accelerator, etc. as needed. Examples of the resin component include acrylate resin, epoxy resin, polyimide resin, bismaleimide resin, maleimide resin, cyanate resin, polyphenylene ether resin, polyphenylene oxide resin, olefin resin, fluorine-containing resin, polyetherimide resin, polyether ether ketone resin, and liquid crystal resin. These resin components may be used alone or in combination of two or more. Among these, it is preferable to use an epoxy resin, which is easy to desmear and has excellent plating adhesion. The epoxy resin preferably contains an epoxy resin having two or more epoxy groups per molecule. Specific examples of epoxy resins include bisphenol A type epoxy resins, bisphenol F type epoxy resins, bisphenol S type epoxy resins, bisphenol AF type epoxy resins, phenol novolac type epoxy resins, naphthalene type epoxy resins, glycidyl amine type epoxy resins, glycidyl ester type epoxy resins, cresol novolac type epoxy resins, biphenyl type epoxy resins, linear aliphatic epoxy resins, alicyclic epoxy resins, heterocyclic epoxy resins, halogenated epoxy resins, etc. These may be used alone or in combination of two or more.

[0026] Examples of inorganic fillers include alumina, silica, aluminum nitride, magnesium oxide, silicon oxide, aluminum hydroxide, and barium sulfate, with silica and alumina being preferred, and silica being more preferred. These may be used alone or in combination of two or more. The content of the inorganic filler is not particularly limited, but in order to reduce the linear thermal expansion coefficient of the build-up layer, the inorganic filler content is preferably 50% by mass or more in terms of the proportion of the components constituting the build-up layer. On the other hand, in order to prevent the build-up layer from becoming brittle, the inorganic filler content is preferably 95% by mass or less in terms of the proportion of the components constituting the build-up layer.

[0027] When a curing agent and a curing accelerator are used as materials constituting the build-up layer, the type is not particularly limited and is appropriately selected according to the resin component used. When an epoxy resin is used as the resin component, examples of the curing agent include an acid anhydride-based curing agent, a phenol-based curing agent, and an amine-based curing agent. When an epoxy resin is used as the resin component, examples of the curing accelerator include a phosphorus-based curing accelerator and an imidazole-based curing accelerator.

[0028] Copper pads are provided on the surface of the top layer of the build-up layers. The copper pads may form part of the conductor layer formed on the surface of the top layer of the build-up layers. The shape of the copper pads is not particularly limited and may be circular, rectangular, or the like. From the viewpoint of stress concentration, a circular shape is preferred. From the viewpoint of increasing the load on the solder resist layer and making it easier for cracks to occur, the pitch of the copper pads is preferably 0.005 mm to 10 mm, more preferably 0.05 mm to 5 mm, and even more preferably 0.1 mm to 3 mm. The pitch of the copper pads refers to the distance between the centers of two adjacent solder balls arranged on the copper pads. When the copper pads are circular, the diameter of the copper pads is preferably 50 μm to 500 μm, more preferably 100 μm to 400 μm, and even more preferably 200 μm to 300 μm. When the copper pad is rectangular, the length of the short side of the copper pad is preferably 50 μm to 500 μm, more preferably 100 μm to 400 μm, and even more preferably 200 μm to 300 μm.

[0029] The solder balls used in the solder resist evaluation model of the present disclosure may be made of lead-containing solder or lead-free solder. Examples of lead-containing solders include Sn-Pb, Sn-Pb-Bi, and Sn-Pb-Ag solders. Examples of lead-free solders include Sn-Sb, Sn-Cu, Sn-Cu-Ni, Sn-Ag, Sn-Cu-Ag, Sn-Ag, Sn-Ag-Cu, Sn-Zn, Sn-Zn-Bi, Bi-Sn, and Sn-In solders. The solder balls are preferably made of lead-free solder. In this disclosure, lead-free solder refers to a solder composed of tin, silver, antimony, bismuth, copper, indium, zinc, nickel, germanium, phosphorus, and gallium, with a lead content of 0.10% (mass fraction) or less. The diameter of the solder balls before melting is set appropriately depending on the distance between the semiconductor package substrate and the semiconductor element, and may be, for example, 0.20 mm to 0.30 mm, 0.10 mm to 0.40 mm, or 0.01 mm to 0.50 mm.

[0030] The surface of the copper pad may be subjected to an anti-rust treatment, or may be subjected to a roughening treatment to improve adhesion with the solder resist layer.

[0031] When the build-up layer has two or more layers, the layers other than the uppermost layer of the build-up layers may or may not have a conductor layer formed thereon.

[0032] A TEG may be used as the semiconductor element used in the solder resist evaluation model of the present disclosure. The specifications of the TEG are not particularly limited, and specifications suitable for process monitoring in a mass production line of semiconductor devices may be adopted, or specifications suitable for evaluation monitoring of processes, devices, and design rules in the development stage of semiconductor devices may be adopted. The structures, materials, characteristics, etc. of the polyimide layer and copper pads of the semiconductor element, as well as other components provided as needed, are also not particularly limited, and specifications suitable for process monitoring or evaluation monitoring may be adopted. Furthermore, the specifications of the TEG may be appropriately set in accordance with the shape, pitch, etc. of the copper pads on the semiconductor package substrate.

[0033] The encapsulating resin layer of the solder resist evaluation model of the present disclosure may be a cured product of an underfill material used in semiconductor encapsulation, such as a capillary underfill material or a mold underfill material, which is primarily composed of an epoxy resin and an inorganic filler. The average thickness of the encapsulating resin layer is appropriately set depending on the distance between the semiconductor package substrate and the semiconductor element. The average thickness of the encapsulating resin layer may be, for example, 20 μm to 30 μm, 10 μm to 40 μm, or 0.1 μm to 50 μm.

[0034] The size of the solder resist evaluation model of the present disclosure when viewed from above is not particularly limited, and may be, for example, one with short sides of 5 mm to 340 mm and long sides of 10 mm to 510 mm.

[0035] The solder resist layer used in the solder resist evaluation model of the present disclosure is formed using the solder resist to be evaluated. Details of the solder resist will be described later. The average thickness of the solder resist layer is preferably 1 μm to 40 μm, more preferably 5 μm to 30 μm, and even more preferably 10 μm to 25 μm.

[0036] The openings in the solder resist layer are formed at the locations where the copper pads are provided. As shown in Fig. 1, the size of the openings may be smaller than the copper pads and the entire opening may be formed on the copper pads, or the size of the openings may be larger than the copper pads and the solder resist layer may not be attached to the edges of the copper pads. From the viewpoint of making the solder resist layer more susceptible to cracks or peeling, it is preferable that the size of the openings is smaller than the copper pads and the entire opening is formed on the copper pads.

[0037] When the copper pad and the opening are both circular, it is preferable that the diameter of the opening is 0.19 to 0.95 and the diameter of the solder ball before melting is 0.5 to 1.92 when the diameter of the copper pad is 1. When the copper pad and the opening are both circular, by ensuring that the diameter of the copper pad, the diameter of the opening, and the diameter of the solder ball before melting have the above-mentioned relationship, cracks are more likely to occur in the solder resist layer, making it possible to easily evaluate the solder resist.

[0038] The method for manufacturing the solder resist evaluation model of the present disclosure is not particularly limited, and the solder resist evaluation model of the present disclosure can be manufactured in accordance with a standard method.

[0039] <Method for Evaluating Solder Resist> The method for evaluating a solder resist according to the present disclosure includes: conducting an environmental test on a solder resist evaluation model according to the present disclosure, in which cooling under a first temperature condition of −200° C. to 0° C. and heating under a second temperature condition of 0° C. to 300° C. are repeated multiple times; and observing a solder resist layer as an evaluation target included in the solder resist evaluation model after the environmental test. Because the solder resist evaluation model according to the present disclosure has a configuration in which cracking and peeling of the solder resist are likely to occur, cracking and peeling are likely to occur in the solder resist layer as an evaluation target even in an environmental test of a shorter duration than conventional tests, making it possible to evaluate the solder resist in a short period of time.

[0040] The first temperature condition is -200°C to 0°C, preferably -100°C to -20°C, and more preferably -70°C to -40°C. The holding time under the first temperature condition is preferably 3 minutes to 30 minutes, and more preferably 5 minutes to 15 minutes. The second temperature condition is 0°C to 300°C, preferably 15°C to 200°C, and more preferably 25°C to 160°C. The holding time under the second temperature condition is preferably 3 minutes to 30 minutes, and more preferably 5 minutes to 15 minutes. The temperature difference between the first temperature condition and the second temperature condition is preferably 200°C to 300°C, more preferably 205°C to 260°C, and even more preferably 210°C to 220°C.

[0041] In the solder resist evaluation method of the present disclosure, the environmental test applied to the solder resist evaluation model of the present disclosure may begin with cooling or may begin with heating. The number of cooling and heating repetitions is appropriately set in consideration of the characteristics and physical properties of the solder resist. If cooling and heating are counted as one cycle, the environmental test preferably repeats cooling and heating 50 to 1,000 times, and more preferably 300 to 700 times.

[0042] In the solder resist evaluation method of the present disclosure, after an environmental test is performed, the solder resist layer included in the solder resist evaluation model as an evaluation target is observed. The observation method is not particularly limited, and examples include non-destructive transmission X-ray observation, ultrasonic microscope observation, and cross-sectional observation of the solder resist evaluation model. Among these, cross-sectional observation of the solder resist evaluation model is preferred because it allows for more detailed observation of cracks and peeling in the solder resist.

[0043] When observing the cross section of the solder resist evaluation model, the cross section may be observed in the thickness direction of the solder resist evaluation model, or in the surface direction of the solder resist evaluation model (the surface direction of the solder resist layer). From the viewpoint of easily observing peeling that occurs at the interface between the solder resist layer and the copper pad, it is preferable to observe the cross section of the solder resist evaluation model in the thickness direction. A scanning electron microscope (SEM) is preferably used for observing the cross section of the solder resist evaluation model.

[0044] The cross section of the solder resist evaluation model may be observed to check for the occurrence of cracks and peeling in the solder resist layer near the solder balls, and the ratio of the number of solder balls in which at least one of cracks and peeling has occurred to the total number of solder balls may be calculated, and this may be used as the actual failure rate (%).

[0045] <Method for selecting solder resist composition> The method for selecting a solder resist composition according to the present disclosure selects a solder resist composition to be used in manufacturing a semiconductor package substrate that constitutes a semiconductor device from among multiple types of solder resist compositions, and includes the steps of: preparing cured films of the multiple types of solder resist compositions; heating the cured films at a temperature of 200°C to 300°C to prepare cured films after thermal history; obtaining information on the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C for the cured films after thermal history; inputting the obtained information into the following formula (1) to calculate a failure rate, including cracking and peeling, when the solder resist composition is applied to the semiconductor package substrate; and selecting solder resist compositions from the multiple types of solder resist compositions that have a failure rate of 60% or less. Failure rate (%) = room temperature elongation rate term + low temperature elongation rate term + low temperature storage modulus term + constant term (1) In the method for selecting a solder resist composition of the present disclosure, the room temperature elongation rate at 25°C, the low temperature elongation rate at -60°C, and the low temperature storage modulus at -55°C of cured films of multiple types of solder resist compositions after thermal history are added together to calculate a predicted failure rate of a semiconductor device manufactured using each solder resist composition, and solder resist compositions having a predicted failure rate within a predetermined range are selected. The prediction of the failure rate of the solder resist layer in a semiconductor device based on formula (1) is highly accurate, and by using this selection method, it is possible to control the occurrence of failures in semiconductor devices manufactured using solder resist compositions.

[0046] In the present disclosure, the measured value of the failure rate used to derive formula (1) is preferably a result obtained using the solder resist evaluation model of the present disclosure. The solder resist evaluation model of the present disclosure enables easy evaluation of the solder resist layer, and the number of evaluation points can be easily increased. Therefore, the measured value of the failure rate can be used to improve the accuracy of failure rate prediction.

[0047] The present inventors utilized the fact that the solder resist evaluation model of the present disclosure enables easy evaluation of solder resist layers to investigate the correlation between the susceptibility of cracking and peeling of multiple types of solder resist layers and the physical properties of cured films of solder resist compositions. As a result, they heated a cured film of the solder resist composition at 200°C to 300°C to obtain a cured film after thermal history, and found that, among various physical properties of the cured film after thermal history, information on the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C showed a high correlation with the susceptibility of cracking and peeling of the solder resist layer, and derived formula (1).

[0048] The process for deriving equation (1) is as follows. The inventors investigated the correlation between the mechanical properties of cured films of solder resist compositions and the measured values ​​of the failure rates, including cracking and delamination, and extracted the mechanical properties that contribute to reducing delamination and cracking. To extract the mechanical properties that contribute to reducing delamination and cracking, a "multivariate correlation" analysis was performed using software JMP manufactured by SAS Institute Inc. Note that JMP software has a function for constructing a linear model of stepwise regression, and this function makes it possible to analyze the "multivariate correlation." Multiple types of solder resist compositions were used as test specimens, and cured films of each solder resist composition and cured films after thermal history were prepared. From the viewpoint of reliability, the average thickness of the cured films of the solder resist compositions is preferably 0.5 μm to 50 μm, more preferably 0.5 μm to 30 μm, and even more preferably 3 μm to 20 μm.

[0049] As the mechanical properties, the following mechanical properties were selected, such as adhesion, elastic modulus, and elongation, which are thought to contribute significantly to the peeling and cracking properties of the solder resist. Specifically, for a cured film of the solder resist composition and a cured film after thermal history, the following were selected: critical stress at 25°C (MPa), room temperature elongation at 25°C (%), room temperature stress at 25°C (MPa), low temperature elongation at -60°C (%), low temperature stress at rupture at -60°C (MPa), glass transition temperature (°C), storage modulus at -55°C (low temperature storage modulus), storage modulus at 220°C (high temperature storage modulus), linear expansion coefficient in the temperature range from -65°C to 150°C, linear expansion coefficient below the glass transition temperature CTEα1, linear expansion coefficient above the glass transition temperature CTEα2, and peel strength (N / mm). Details of the measurement conditions for these mechanical properties will be mentioned in the Examples section.

[0050] The present inventors investigated the correlation between the above-mentioned mechanical properties of a cured film of a solder resist composition before heating at 200°C to 300°C and the measured values ​​of the failure rate, including cracking and delamination. The results suggested a correlation between the measured values ​​of the failure rate, including cracking and delamination, and the glass transition temperature and storage modulus at 220°C. However, the measured values ​​of the failure rate, including cracking and delamination, only weakly correlated with these mechanical properties, and even multiple regression analysis failed to create an accurate analytical model. Next, the cured film of the solder resist composition was heated at 200°C to 300°C to form a cured film after thermal history. It is presumed that heating the cured film of the solder resist composition at 200°C to 300°C will result in a cured film of the solder resist composition exhibiting mechanical properties similar to those of a solder resist layer after a reflow process. The correlation between the above-mentioned mechanical properties of the cured film after thermal history and the measured values ​​of the failure rate, including cracking and delamination, was investigated. As a result of multiple regression analysis, it was possible to create an analytical model with high accuracy between the measured values ​​of the failure incidence rate, including cracking and delamination, and the room temperature elongation at 25° C., the low temperature elongation at −60° C., and the low temperature storage modulus at −55° C. More specifically, it was suggested that the use of a solder resist composition that has an excellent elongation at 25° C. or −60° C. and a high low temperature storage modulus at −55° C. for the cured film after thermal history is effective in reducing delamination and cracking.

[0051] The process of deriving the above formula (1) using the software JMP will be described below. The values ​​in Tables 2 and 3 in the Examples section were used as the measured values ​​of the failure rate (%) and the measured values ​​of the explanatory variables for the cured film of the solder resist composition and the cured film after thermal history. The prediction formula for predicting the failure rate (%), which is the objective variable, is shown in Formula (1A). Note that the glass transition temperature (Tg), coefficient of linear expansion (CTE), and peel strength are correlated, and since multicollinearity may reduce the accuracy of the prediction formula, the terms for glass transition temperature (Tg), coefficient of linear expansion (CTE), and peel strength were omitted from Formula (1A). Failure rate (%) = 141.35240164 - 0.551762455 * critical stress (MPa) - 6.539642467 * room temperature elongation (%) - 0.308388007 * room temperature breaking stress (MPa) - 7.755604027 * low temperature elongation (%) + 0.7333271578 * low temperature breaking stress (MPa) - 0.020842237 * E1 + 0.0645157199 * E2 + 0.7595383219 * α1 + 0.2611125204 * α2 ... (1A)

[0052] The explanatory variables for the cured film of the solder resist composition in formula (1A) are shown below. E1: storage modulus at -55°C (low-temperature storage modulus, MPa) E2: storage modulus at 220°C (high-temperature storage modulus, MPa) α1... linear expansion coefficient of the cured product (ppm / °C) α2... linear expansion coefficient of the cured product (ppm / °C) The above coefficients are set as appropriate using the simulation software described above. In a method for using this software, a prediction formula for deriving the failure incidence rate (%), including cracking and delamination, is calculated by a stepwise regression method from the actual measured values ​​of the failure incidence rate, including cracking and delamination, and the square terms and cross products of the explanatory variables (parameters) of the mechanical properties of the cured film of the solder resist composition or the cured film after thermal history.

[0053] Furthermore, the above-mentioned formula (1A) can also be simplified to formula (1B) consisting of the main parts. The explanatory variable terms in formula (1B) are only those relating to the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C, and formula (1B) shows a prediction formula with an R-squared value approaching 1. The "R-squared value" is a value that indicates the correlation between the actual measured value of the failure rate (%) and the simulated value (predicted value) of the failure rate (%), and an R-squared value approaching 1 can indicate a strong positive correlation between the two.

[0054] Failure rate (%) = 203.05738208 - 5.693548887 * room temperature elongation (%) - 8.781256314 * low temperature elongation (%) - 0.013682139 * E1 ... (1B)

[0055] The explanatory variables for the cured film of the solder resist composition or the cured film after thermal history in formula (1B) are shown below. E1: Storage modulus at -55°C (low-temperature storage modulus, MPa) The above coefficients are values ​​set appropriately using the simulation software described above. The physical property determined from the failure rate (%) is calculated from formula (1B) using the steepest descent method.

[0056] In the above-mentioned formula (1B), the three types of factors used to calculate the failure rate (%) are used because the influence between the factors is relatively small and the factors have a large effect on the failure rate (%). Based on these three types of factors, the above-mentioned formula (1A) can be further summarized as the following formula (1): Failure rate (%) = room temperature elongation rate term + low temperature elongation rate term + low temperature storage modulus term + constant term (1)

[0057] As is clear from a comparison between the measured and simulated values ​​of the failure rate, the above-mentioned method for simulating the failure rate makes it possible to accurately predict the failure rate of the solder resist layer by adding up, based on formula (1A) or (1B), the term for the room-temperature elongation at 25° C., the term for the low-temperature elongation at −60° C., and the term for the low-temperature storage modulus at −55° C. for a cured film of the solder resist composition after thermal history. This simulation method therefore makes it possible to control the failure rate of the solder resist layer.

[0058] In the method for selecting a solder resist composition according to the present disclosure, a solder resist composition having a failure rate of 60% or less is selected from a plurality of types of solder resist compositions, and it is preferable to select a solder resist composition having a failure rate of 50% or less, and it is more preferable to select a solder resist composition having a failure rate of 40% or less.

[0059] <Method for Manufacturing a Semiconductor Device> The method for manufacturing a semiconductor device of the present disclosure includes preparing a semiconductor package substrate using a solder resist composition selected by the method for selecting a solder resist composition of the present disclosure, connecting the semiconductor package substrate to a semiconductor element, and providing an encapsulating resin layer that covers the connection between the semiconductor package substrate and the semiconductor element. The method for manufacturing a semiconductor device of the present disclosure uses a solder resist composition that has a low failure rate and that has been selected by the method for selecting a solder resist composition of the present disclosure, thereby enabling the production of a highly reliable semiconductor device. The method for preparing a semiconductor package substrate, the method for connecting the semiconductor package substrate to the semiconductor element, and the method for providing an encapsulating resin layer that covers the connection between the semiconductor package substrate and the semiconductor element, as well as the various materials used to implement these methods, are not particularly limited, and conventionally known methods and materials can be used.

[0060] <Solder Resist Composition> A first solder resist composition of the present disclosure is one selected by the method for selecting a solder resist composition of the present disclosure. Also, a second solder resist composition of the present disclosure is a solder resist composition containing a photopolymerizable compound having an ethylenically unsaturated group, a photopolymerization initiator, an epoxy resin, and a curing accelerator, wherein when a cured film of the solder resist composition is heated at 200°C to 300°C to form a cured film after thermal history, the cured film after thermal history exhibits a failure rate (%) including cracking and delamination of 60% or less, as expressed by Formula (1) based on the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C. Failure rate (%) = room temperature elongation rate term + low temperature elongation rate term + low temperature storage modulus term + constant term (1) The first and second solder resist compositions of the present disclosure have a failure rate (%) including cracking and peeling, represented by formula (1), of 60% or less. Therefore, by using the first and second solder resist compositions of the present disclosure, it is possible to obtain a highly reliable semiconductor device.

[0061] The second solder resist composition of the present disclosure is not particularly limited in its composition as long as it contains a photopolymerizable compound having an ethylenically unsaturated group, a photopolymerization initiator, an epoxy resin, and a curing accelerator. The first solder resist composition of the present disclosure may also contain a photopolymerizable compound having an ethylenically unsaturated group, a photopolymerization initiator, an epoxy resin, and a curing accelerator. Hereinafter, the first and second solder resist compositions of the present disclosure may be collectively referred to as the solder resist composition of the present disclosure.

[0062] The solder resist composition of the present disclosure contains a photopolymerizable compound having an ethylenically unsaturated group, a photopolymerization initiator, an epoxy resin, and a curing accelerator, and may also contain other components such as an inorganic filler and a diluent, as necessary.

[0063] The photopolymerizable compound having an ethylenically unsaturated group (hereinafter, sometimes referred to as component (A)) contains, as an essential component, an acid-modified epoxy(meth)acrylate compound having an ethylenically unsaturated group and a carboxy group in the molecule. The acid-modified epoxy(meth)acrylate compound is preferably, for example, a compound obtained by reacting (a3) ​​a saturated or unsaturated group-containing polybasic acid anhydride with (A') a reaction product of (a1) an epoxy resin and (a2) an unsaturated group-containing monocarboxylic acid (i.e., a hydroxyl group-containing compound which is an esterification product of an epoxy resin and an unsaturated monocarboxylic acid) (i.e., an addition reaction product of the hydroxyl group-containing component (A') and the polybasic acid anhydride). The epoxy resin (a1) is not particularly limited as long as it is a compound having two or more epoxy groups in the molecule, and examples thereof include novolac epoxy resins, bisphenol A epoxy resins, bisphenol F epoxy resins, bisphenol S epoxy resins, salicylaldehyde epoxy resins, bisphenol A novolac epoxy resins, bisphenol F novolac epoxy resins, biphenyl novolac epoxy resins, and rubber-modified epoxy resins. Alternatively, an epoxy resin-based polyurethane resin obtained by reacting the reaction product (A') with an isocyanate may be used. These may be used alone or in combination of two or more.

[0064] Examples of the photopolymerization initiator (hereinafter, sometimes referred to as component (B)) include aromatic ketones such as benzophenone, N,N'-tetraalkyl-4,4'-diaminobenzophenone, 2-benzyl-2-dimethylamino-1-(4-morpholinophenyl)-butanone-1,2-methyl-1-[4-(methylthio)phenyl]-2-morpholino-propanone-1,4,4'-bis(dimethylamino)benzophenone (Michler's ketone), 4,4'-bis(diethylamino)benzophenone, and 4-methoxy-4'-dimethylaminobenzophenone; quinones such as alkylanthraquinone and phenanthrenequinone; benzoin compounds such as benzoin and alkylbenzoin; benzoin ether compounds such as benzoin alkyl ether and benzoin phenyl ether; benzil derivatives such as benzil dimethyl ketal; 2-(o-chlorophenyl)-4,5-diphenylimidazole dimer; 2,4,5-triarylimidazole dimers such as (m-methoxyphenyl)imidazole dimer, 2-(o-fluorophenyl)-4,5-diphenylimidazole dimer, 2-(o-methoxyphenyl)-4,5-diphenylimidazole dimer, 2,4-di(p-methoxyphenyl)-5-phenylimidazole dimer, and 2-(2,4-dimethoxyphenyl)-4,5-diphenylimidazole dimer, N-phenylglycine, and N-phenylglycine derivatives and 9-phenylacridine; oxime esters such as 1,2-octanedione and 1-[4-(phenylthio)-,2-(O-benzoyloxime)]; coumarin compounds such as 7-diethylamino-4-methylcoumarin; thioxanthone compounds such as 2,4-diethylthioxanthone; and acylphosphine oxide compounds such as 2,4,6-trimethylbenzoyl-diphenyl-phosphine oxide.

[0065] The epoxy resin (hereinafter sometimes referred to as component (C)) is not particularly limited as long as it has two or more epoxy groups in one molecule, and examples thereof include bisphenol A type epoxy resins, bisphenol F type epoxy resins, bisphenol S type epoxy resins, phenol novolac type epoxy resins, cresol novolac type epoxy resins, naphthol type epoxy resins, naphthalene type epoxy resins, naphthylene ether type epoxy resins, glycidylamine type epoxy resins, biphenyl type epoxy resins, biphenyl aralkyl type epoxy resins, alicyclic epoxy resins, heterocyclic epoxy resins, spiro ring-containing epoxy resins, cyclohexanedimethanol type epoxy resins, trimethylol type epoxy resins, and epoxidized polybutadiene resins. These may be used alone or in combination of two or more.

[0066] Examples of the curing accelerator include imidazole-based curing accelerators, phosphorus-based curing accelerators, thiol-based curing accelerators, urea-based curing accelerators, guanidine-based curing accelerators, and metal-based curing accelerators.

[0067] It is preferable to contain an inorganic filler for the purpose of improving various properties such as adhesion and coating hardness. For example, silica (SiO ２ ), alumina (Al ２ O ３ ), titania (TiO ２ ), tantalum oxide (Ta ２ O ５ ), zirconia (ZrO ２ ), silicon nitride (Si ３ N ４ ), barium titanate (BaO.TiO ２ ), barium carbonate (BaCO ３ ), magnesium carbonate, aluminum oxide, aluminum hydroxide, magnesium hydroxide, lead titanate (PbO.TiO ２ ), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), gallium oxide (Ga ２ O ３ ), spinel (MgO.Al ２ O ３ ), mullite (3Al ２ O ３2SiO ２ ), cordierite (2MgO 2Al ２ O ３／５ SiO ２ ), talc (3MgO.4SiO ２ ・H ２ O), aluminum titanate (TiO ２ -Al ２ O ３ ), yttria-containing zirconia (Y ２ O ３ -ZrO ２ ), barium silicate (BaO.8SiO ２ ), boron nitride (BN), calcium carbonate (CaCO ３ ), barium sulfate (BaSO ４ ), calcium sulfate (CaSO ４ ), zinc oxide (ZnO), magnesium titanate (MgO.TiO ２ ), hydrotalcite, mica, calcined kaolin, carbon, etc. These inorganic fillers may be used alone or in combination of two or more.

[0068] Various organic solvents can be used as the diluent, including, for example, ketones such as methyl ethyl ketone and cyclohexanone, aromatic hydrocarbons such as toluene, xylene, and tetramethylbenzene, glycol ethers such as methyl cellosolve, butyl cellosolve, methyl carbitol, butyl carbitol, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate, dipropylene glycol monoethyl ether, dipropylene glycol diethyl ether, and triethylene glycol monoethyl ether, esters such as ethyl acetate, butyl acetate, butyl cellosolve acetate, and carbitol acetate, aliphatic hydrocarbons such as octane and decane, and petroleum solvents such as petroleum ether, petroleum naphtha, hydrogenated petroleum naphtha, and solvent naphtha.

[0069] The solder resist composition can be obtained by uniformly kneading and mixing the above-mentioned various components using a roll mill, a bead mill, or the like. The solder resist composition may be in the form of a film, liquid, or paste. The composition of the solder resist composition can be appropriately determined, for example, taking into account the elongation at 25°C or -60°C and the low-temperature storage modulus at -55°C of the cured film after thermal history.

[0070] The present disclosure will be described in more detail below based on examples, but the present disclosure is not limited to the following examples.

[0071] <Preparation of Semiconductor Package Substrate> - Formation of Build-up Layer - A build-up material (manufactured by Ajinomoto Fine-Techno Co., Inc.) was laminated using a vacuum laminator onto a 150 mm square, 0.8 mm thick copper-clad laminate (core substrate, Tg: 260°C to 300°C, thermal expansion coefficient α1: 9.5 ppm / °C, thermal expansion coefficient α2: 1.1 ppm / °C, conductor layer thickness: 10 μm to 12 μm). The lamination temperature was 90°C. The laminate was then heated and cured in an oven at 180°C for 30 minutes, then at 190°C for 60 minutes to form a build-up layer (thickness: 30 μm, Tg: 153°C to 168°C, thermal expansion coefficient α1: 39 ppm / °C, thermal expansion coefficient α2: 117 ppm / °C).

[0072] - Desmear and Electroless Cu Plating - Using a desmear solution manufactured by Atotech and an electroless Cu plating solution manufactured by Uemura Kogyo Co., Ltd., the surface of the build-up layer was subjected to desmear and electroless Cu plating treatment.

[0073] -Plating Resist Patterning- As a pretreatment for plating resist film formation, the electroless Cu-plated surface was subjected to oxygen plasma treatment for 2 minutes using a plasma cleaner (Nordson March, AP-1000) under conditions of a pressure of 150 mTorr, an output of 500 W, and an oxygen flow rate of 100 sccm. Thereafter, a positive photosensitive liquid plating resist (Tokyo Ohka Kogyo Co., Ltd., PMER P-LA900PM) was spin-coated using an 8-inch spin coater (Mikasa) at 500 rpm for 5 seconds, followed by 1200 rpm for 30 seconds. This was then pre-baked on a hot plate at 120°C for 4 minutes and allowed to stand for 1 hour. Next, an i-line stepper (Therma Precision, Sc6k) was used to apply an exposure dose of 1400 mJ / cm. ２ The resist was exposed under the conditions of a focus of +25 μm. It was then developed for 445 seconds using a paddle developer (Mikasa, AD-3000) with a 2.38% by mass aqueous solution of tetramethylammonium hydroxide (TMAH) as the developer. The exposure mask pattern had a diameter of 260 μm and a pattern pitch of 1 mm.

[0074] - Electrolytic Cu plating - The resist-patterned substrate was immersed in a 500 mL / L aqueous solution of acidic degreasing solution Z-200 manufactured by Atotech Corporation at 50°C for 1 minute, then rinsed in pure water at 50°C for 1 minute and then in pure water at 25°C for 1 minute, and then immersed in a 10% by mass aqueous sulfuric acid solution at 25°C for 1 minute. Next, using 20 L of copper sulfate bath prepared by adding 32 mL of Top Lucina NSV-1, 4 mL of NSV-2, 8 mL of NSV-3 manufactured by Okuno Chemical Industries, 48 ​​mg of hydrochloric acid (manufactured by Fujifilm Wako Pure Chemical Industries), and 1,440 g of sulfuric acid (manufactured by Fujifilm Wako Pure Chemical Industries), the solution temperature was 25°C and the current density was 0.02 A / dm ２ The copper electroplating process was carried out using a copper plating method described above. The time for electroplating was adjusted so that the thickness of the copper electroplating layer from the electroless copper plating layer would be 12 μm. The copper electroplating layer was then washed with pure water and dried for 5 minutes on a hot plate set at 85° C.

[0075] -Resist removal- The electrolytic Cu-plated substrate was immersed in N-methylpyrrolidone (manufactured by Fujifilm Wako Pure Chemical Industries, Ltd.) at 25°C for 10 minutes to remove the resist. After that, it was washed with running pure water for 1 minute and dried on a hot plate set to 85°C for 5 minutes.

[0076] - Seed etching - The substrate from which the resist had been removed was immersed in SAC-700W3C (manufactured by JCU Corporation) at 25°C for 3 minutes to etch the electroless Cu seed layer, followed by rinsing with running pure water for 1 minute and drying on a hot plate set at 85°C for 5 minutes.

[0077] - CZ Treatment - The seed-etched substrate was subjected to CZ treatment using CZ-8101 and CL8300 manufactured by MEC Co., Ltd., to roughen and rust-proof the copper pad surface.

[0078] - Formation of Solder Resist Layer - Film-like photosensitive insulating materials with different physical properties were used to form the solder resist layer. Twelve types of photosensitive insulating materials were used: A, B, #1, #2, #3, #4, #5, #6, #7, #8, #9, and #10. Of the photosensitive insulating materials, photosensitive insulating material A had the following composition. Acid-modified cresol novolac epoxy acrylate "EXP-2810" (trade name, manufactured by DIC Corporation) was used as a photosensitive prepolymer having at least one ethylenically unsaturated group and a carboxyl group in the molecule. The weight-average molecular weight was 10,000, and the acid value was 70 mgKOH / g. A mixture of dipentaerythritol pentaacrylate and dipentaerythritol hexaacrylate "KAYARAD DPHA" (trade name, manufactured by Nippon Kayaku Co., Ltd.) was used as a photoreactive compound. The photopolymerization initiators used were 2,4,6-trimethylbenzoyl-diphenyl-phosphine oxide "DAROCURE-TPO" (BASF, trade name) and 2,4-diethylthioxanthone "Kayacure DETX-S" (Nippon Kayaku Co., Ltd., trade name). The epoxy resins used were biphenylaralkyl epoxy resin "NC-3000H" (Nippon Kayaku Co., Ltd., trade name) and bisphenol F epoxy resin "YSLV-80" (Nippon Steel Chemical & Material Co., Ltd., trade name). The inorganic fillers used were barium sulfate "B30" (Sakai Chemical Industry Co., Ltd., trade name) and silica ADMAFINE (Admatechs Co., Ltd.). The average particle size and maximum particle size of the inorganic filler dispersed in the photosensitive insulating material were measured using a laser diffraction / scattering microtrack particle size distribution analyzer "MT-3100" (Nikkiso Co., Ltd.). The average particle size of B30 was 0.3 μm, and that of ADMAFINE was 0.5 μm. The maximum particle size of the inorganic fillers including B30 and ADMAFINE was 3 μm or less. The particle size of the inorganic fillers after film formation was confirmed by observing the cross section of the film with an electron microscope (SEM) after curing. It was confirmed that the maximum particle size of the inorganic fillers dispersed in the film was 5 μm or less. The following were used as other components:The butadiene elastomer "Epolead PB3600" (trade name, manufactured by Daicel Corporation), the polymerization inhibitor "Antage 500" (trade name, manufactured by Kawaguchi Chemical Industry Co., Ltd.), melamine and dicyandiamide as curing accelerators and adhesion improvers, and phthalocyanine blue as a pigment were used. Methyl ethyl ketone and propylene glycol monomethyl ether acetate were used as solvents.

[0079] A photosensitive insulating material film was formed on the CZ-treated substrate using a vacuum laminator (V-130, manufactured by Nikko Materials Co., Ltd.) under conditions of a temperature of 75°C, a pressure of 0.5 MPa, and a time of 60 seconds. Next, an i-line stepper (Sc6k, manufactured by Therma Precision Co., Ltd.) was used to perform exposure under conditions of exposure amount and focus appropriate for each photosensitive insulating material. Next, a high-pressure spin developing device (manufactured by Noah Craft Co., Ltd.) was used to develop the film using 1% by mass Na ２ CO ３ The film was developed in an aqueous solution at 30°C for 130 seconds. Thereafter, a mask aligner (Mikasa Co., Ltd., ML-320FSAT) was used to expose the film to an exposure dose of 2000 mJ / cm. ２ The resulting solder resist was then post-exposed at 170°C for 60 minutes. Finally, the resulting solder resist was cured by heating at 170°C for 60 minutes to form a solder resist layer with an opening of 240 μm in diameter on the copper pad. The average thickness of the solder resist layer was 18 μm. In this manner, a semiconductor package substrate was produced.

[0080] <Fabrication of Semiconductor Element> -Insulating Layer Formation- A liquid polyimide material (HD7110) manufactured by HD Microsystems, Inc. was applied to a Si mirror wafer having a diameter of 200 mm and a thickness of 650 μm using a spin coater (MS-A2000 manufactured by Mikasa Co., Ltd.) under conditions that the film thickness after curing would be 10 μm, and the applied material was dried using a hot plate. Next, a mask aligner (ML-320FSAT manufactured by Mikasa Co., Ltd.) was used to apply an exposure dose of 500 mJ / cm. ２ Thereafter, the coating was heated and cured at 170° C. for 1 hour using an inert gas oven (manufactured by Toyo Thermo Co., Ltd., INH-51CD-S) to obtain a cured film (polyimide film).

[0081] - Seed layer formation - Using a sputtering device (MS-A200 manufactured by ULVAC), the cured film was heated and dried at 120°C for 30 minutes, and the surface of the cured film was then treated with an argon ion gun. －３ A seed layer was formed by sputtering titanium (Ti) to a thickness of 80 nm and then copper (Cu) to a thickness of 200 nm under the condition of Pa and Ar flow rate of 30 sccm.

[0082] - Resist pattern formation - Using a plasma cleaner (Nordson March, AP-1000), the seed layer was subjected to oxygen plasma treatment for 2 minutes under conditions of a pressure of 150 mTorr, an output of 500 W, and an oxygen flow rate of 100 sccm. Thereafter, a positive photosensitive liquid plating resist (Tokyo Ohka Kogyo Co., Ltd., PMER P-LA900PM) was spin-coated using an 8-inch spin coater (Mikasa) at 500 rpm for 5 seconds, followed by 1200 rpm for 30 seconds. The resist was then pre-baked on a hot plate at 120°C for 4 minutes and allowed to stand for 1 hour. Next, an i-line stepper (Therma Precision, Sc6k) was used to apply an exposure dose of 1400 mJ / cm. ２ The same pattern as that used for plating resist patterning in the production of semiconductor package substrates was exposed under the conditions of focus +25 μm. Thereafter, using a paddle developing machine (manufactured by Mikasa Co., Ltd., AD-3000), development was performed for 445 seconds with a developer of 2.38 mass % TMAH aqueous solution to obtain a resist pattern.

[0083] - Electrolytic Cu plating - The resist-patterned Si wafer was immersed in a 500 mL / L aqueous solution of acidic degreasing solution Z-200 manufactured by Atotech Corporation at 50°C for 1 minute, then rinsed in pure water at 50°C for 1 minute and then in pure water at 25°C for 1 minute, and then immersed in a 10% by mass aqueous sulfuric acid solution at 25°C for 1 minute. Next, using 20 L of copper sulfate bath prepared by adding 32 mL of Top Lucina NSV-1, 4 mL of NSV-2, 8 mL of NSV-3 manufactured by Okuno Chemical Industries, 48 ​​mg of hydrochloric acid (manufactured by Fujifilm Wako Pure Chemical Industries), and 1,440 g of sulfuric acid (manufactured by Fujifilm Wako Pure Chemical Industries), the solution temperature was 25°C and the current density was 0.02 A / dm ２The Cu electroplating treatment was carried out at 1000 kJ / min. The Cu electroplating time was adjusted so that the Cu electroplating thickness from the seed layer was 12 μm. The wafer was then washed with pure water and dried for 5 minutes on a hot plate set at 85° C. to obtain an Cu electroplated Si wafer.

[0084] -Resist removal- The electrolytic Cu-plated Si wafer was immersed in N-methylpyrrolidone (manufactured by Fujifilm Wako Pure Chemical Industries, Ltd.) at 25°C for 10 minutes to remove the resist. After that, it was washed with running pure water for 1 minute and dried on a hot plate set to 85°C for 5 minutes.

[0085] - Seed etching - The Si wafer from which the resist had been stripped was immersed in SAC-700W3C (manufactured by JCU Corporation) at 25°C for 3 minutes to etch the seed layer. After that, the wafer was washed with running pure water for 1 minute and dried on a hot plate set at 85°C for 5 minutes to produce a semiconductor device.

[0086] <Assembly of TEG for evaluation> The semiconductor package substrate and semiconductor element obtained as described above were cut into individual pieces of 13.7 mm x 7.3 mm square. The individual pieces were immersed in a 10% by mass aqueous solution of sulfuric acid at 25°C for 1 minute and then washed with running water for 1 minute. ２ After plasma treatment, the semiconductor device was immersed in a 5% by mass aqueous solution of sodium persulfate for 50 seconds to remove the anti-corrosion layer on the copper pad. The device was then rinsed with running water for 60 seconds. The individual semiconductor devices were immersed in a 10% by mass aqueous solution of sulfuric acid at 25°C for 1 minute and rinsed with running water for 1 minute. ２Plasma treatment was performed, followed by 60 seconds of running water washing. A water-soluble flux (SPARKLE FLUX WF-6400, manufactured by Senju Metal Industry Co., Ltd.) was applied to the solder ball mounting surface of the singulated substrate, and a solder ball mounting machine (Shinapex, metal mask type ball mounting jig SMU-50) was used to mount a Φ0.25 mm solder ball (Eco Solder Ball M705, manufactured by Senju Metal Industry Co., Ltd.) on the copper pad of the singulated substrate. Using a nitrogen reflow machine (SNR-1065GT, manufactured by Senju Metal Industry Co., Ltd.), the copper pad and solder ball were bonded at a maximum temperature of 260 ° C. Then, the substrate was immersed in pure water at 98 ° C. and ultrasonically cleaned at a frequency of 170 kHz for 3 minutes to remove excess flux. Next, water-soluble flux was applied to the copper pad surface on the semiconductor element, and the copper pads and solder balls on the Si chip were visually aligned. The semiconductor element was then mounted on a semiconductor package substrate. Using a nitrogen reflow device, the copper pads and solder balls on the semiconductor element were bonded at a maximum temperature of 260°C. Subsequently, the solder balls were ultrasonically cleaned in a flux cleaner at frequencies of 120 kHz and 170 kHz for 10 minutes each to remove excess flux. Finally, capillary underfill (CUF, manufactured by Resonac Corporation, CEL-C-3730N-5F) was manually injected between the semiconductor element and the semiconductor package substrate, and the CUF was heat-cured at 165°C for 120 minutes to obtain an evaluation TEG.

[0087] <Temperature Cycle Test> A temperature cycle test was performed on the evaluation TEG obtained as described above. The number of cycles was 600, and the test conditions were an air bath, cooling to −60° C., and heating to 150° C. The cooling and heating holding times were each 15 minutes.

[0088] <Cross-Section Observation of Evaluation TEG> To observe the solder ball connections of the evaluation TEG in detail after the temperature cycle test, a polisher was used to polish the surface of the evaluation TEG from the semiconductor element side to the solder resist layer surface in the thickness direction, and the solder ball positions were confirmed. Next, the evaluation TEG was cross-sectionally polished from the edge of the evaluation TEG to the center of the solder ball. The cracking mode on the copper pad was then observed using a scanning electron microscope (SEM) under conditions of an acceleration voltage of 15 kV, a current value of 10 A, and a working distance (WD) of 15 mm. As a result, it was found that delamination at the interface between the solder resist layer and the copper pad occurred at the top and edge of the copper pad. Meanwhile, cracks in the solder resist layer were found to occur at the outer edge of the copper pad. The incidence rates (failure incidence rates) of these failure modes were investigated for each photosensitive insulating material and are summarized in Table 1. To calculate the failure incidence rate, 98 copper pads were observed.

[0089]

[0090] The ranking of failure rates among the photosensitive insulating material types confirmed in this study showed that A had more defects than B. This result coincides with the ranking shown in the evaluation results of a large TEG similar to a general-purpose package, and it was found that the evaluation TEG (solder resist evaluation model) of this example has a TEG configuration appropriate for simple evaluation of failure rates.

[0091] <Evaluation of Mechanical Properties of Cured Film> -Preparation of Test Pieces- The above-described 12 types of film-like photosensitive insulating material were used to prepare test pieces. Solder resist strip samples for measuring mechanical properties, each 10 mm wide, 120 mm long, and 18 μm in average thickness, were prepared as follows. First, a Cu foil with an average thickness of 18 μm was attached to a 0.8 mm thick copper-clad laminate using polyimide tape, and a film of the photosensitive insulating material was formed thereon using a vacuum laminator (V-130, manufactured by Nikko Materials Co., Ltd.) under conditions of a temperature of 75°C, a pressure of 0.5 MPa, and a time of 60 seconds. Next, using a mask with a slit formed therein having a width of 10 mm and a length of 120 mm, a mask aligner (ML-320FSAT, manufactured by Mikasa Co., Ltd.) was used to form a film of the photosensitive insulating material at 50 mJ / cm. ２After that, the film was exposed to light under the following conditions: Then, a high-pressure spin developing device was used to develop the film using a developer containing 1% by mass of Na ２ CO ３ The film was developed in an aqueous solution at 30°C for 130 seconds. A mask aligner was used to expose the film to an exposure dose of 2000 mJ / cm. ２ The photosensitive insulating material was post-cured by heating at 170°C for 60 minutes. For strip samples not subjected to reflow treatment, the Cu foil was peeled off from the copper-clad laminate after heat curing, and the Cu foil was etched with an aqueous ammonium peroxodisulfate solution to obtain a sample for measuring the desired physical properties. For strip samples subjected to reflow treatment, the Cu foil was subjected to a reflow process at 260°C three times after heat curing, and then the Cu foil was peeled off from the copper-clad laminate and etched with an aqueous ammonium peroxodisulfate solution to obtain a sample for measuring the desired physical properties.

[0092] -Tensile Test- To measure the elongation and breaking stress of the cured solder resist film, a tensile test was performed on each strip sample using Autograph (AG-X plus, manufactured by Shimadzu Corporation). The test width was 20 mm and the tensile speed was 5 mm / min. The temperature conditions were 25°C and the lowest temperature of the temperature cycle test was -60°C, so the low temperature side was -60°C. In addition, to measure the limit stress, an SN test was performed with a test width of 20 mm and a tensile speed of 5 N / sec.

[0093] -DMA Measurement- To measure the elastic modulus (storage modulus) of the cured solder resist film, DMA measurement was performed on each strip sample using a Hitachi High-Tech Science Model 7100. The test conditions were: test mode: tension, temperature conditions: -60°C to 350°C, temperature rise rate: 5°C / min, test frequency: 1 Hz, strain: 0.1%, temperature adjustment: N ２ The test was carried out under the conditions of a chuck distance of 20 mm.

[0094] -TMA Measurement- To measure the linear expansion coefficient and glass transition temperature (Tg) of the cured solder resist film, TMA measurement was performed on each strip sample using a TMA device (SS 7100 model, manufactured by Hitachi High-Tech Science Corporation). The test conditions were: test mode: tension, load 0.049 N, temperature adjustment: N ２The measurement was carried out under these conditions, with a chuck distance of 10 mm. The temperature rise and fall conditions for the TMA measurement were as follows: First heating: temperature range 30°C to 200°C, heating rate 5°C / min, holding time 10 minutes First cooling: temperature range 200°C to -65°C, cooling conditions 20°C / min, holding time 0 minutes Second heating: temperature range -65°C to 350°C, heating rate 5°C / min, holding time 0 minutes During the second heating stage, the coefficient of linear expansion (CTE) was measured in the temperature range of -65°C to 150°C, CTEα1 was measured during the second heating stage, and CTEα2 was measured during the second heating stage. The glass transition temperature (Tg) was determined as the intersection of the tangents before and after the inflection point of the chart obtained during the second heating stage.

[0095] - Peel test sample preparation conditions and peel strength measurement - The above-mentioned 12 types of film-like photosensitive insulating material were used to prepare test pieces for the peel test. CZ treatment was performed on the Cu surface of a 1.4 mm thick copper-clad laminate and 18 μm thick Cu foil using MEC Co., Ltd.'s CZ-8101 and CL8300. Next, using a vacuum laminator (Nikko Materials Co., Ltd.'s V-130), the film-like photosensitive insulating material was laminated on the CZ-treated surface of the Cu foil at 75°C for 60 seconds. Thereafter, an exposure dose of 2000 mJ / cm was applied using a mask aligner (Mikasa Co., Ltd.'s ML-320FSAT). ２ The resulting films were then exposed to light at 1000 W and heat-cured at 170°C for 60 minutes. The surface of the photosensitive insulating material side of the Cu foil laminated with the photosensitive insulating material was roughened with #800 abrasive paper, and the photosensitive insulating material side was then bonded to the Cu surface of a 1.4 mm thick copper-clad laminate with an adhesive, and the film was left to stand until the adhesive cured. A slit was made in the edge of the Cu foil, and peel strength was measured using a small tabletop tester (Shimadzu EZ-SX) with a test piece width of 10 mm and a peel speed of 50 mm / min. The peel test was performed with two samples, and the average of the results was taken as the peel strength.

[0096] The measurement results are shown in Table 2 (without reflow process) and Table 3 (with reflow process).

[0097]

[0098]

[0099] - JMP Analysis - Using the failure rate listed in Table 1 as the objective variable and the critical stress (MPa), room temperature elongation (%), room temperature stress at break (MPa), low temperature elongation (%), low temperature stress at break (MPa), glass transition temperature (°C), storage modulus at -55°C (low temperature storage modulus, MPa), storage modulus at 220°C (high temperature storage modulus, MPa), linear expansion coefficient in the temperature range of -65°C to 150°C, CTEα1, CTEα2, and peel strength (N / mm) listed in Table 2 or Table 3 as explanatory variables, a "multivariate correlation" analysis was performed using JMP software manufactured by SAS Institute Inc. As a result, a strong correlation was found between the room temperature elongation (%), low temperature elongation (%), and low temperature storage modulus and the failure rate (600 cycle delamination crack occurrence rate) in the case where a reflow process was performed. The relationship between room temperature elongation (%) and failure rate, the relationship between low temperature elongation (%) and failure rate, and the relationship between low temperature storage modulus and failure rate are shown in Figures 2, 3, and 4, respectively. The predicted failure rate was calculated based on the following formula:

[0100] Failure rate (%) = 203.05738208 - 5.693548887 * room temperature elongation (%) - 8.781256314 * low temperature elongation (%) - 0.013682139 * E1 ... (1B)

[0101] The relationship between the predicted failure rate calculated from the above formula and the actually measured failure rate is shown in Figure 5. The results of the JMP analysis are shown in Figure 6. As is clear from Figure 5, the predicted failure rate is close to the actually measured failure rate. These results show that the above method makes it possible to select a solder resist composition with a low failure rate from multiple solder resist compositions.

[0102] REFERENCE SIGNS LIST 1 Solder resist evaluation model 10 Core substrate 20 Build-up layer 30, 80 Copper pad 40 Solder resist layer 42 Opening 50 Semiconductor package substrate 60 Semiconductor element 70 Polyimide layer 90 Solder ball 100 Sealing resin layer

Claims

1. A solder resist evaluation model comprising: a semiconductor package substrate having a core substrate, at least one buildup layer provided on one surface of the core substrate, a copper pad provided on the surface of the uppermost layer of the buildup layers, and a solder resist layer to be evaluated which is provided on the uppermost layer of the buildup layers and has an opening where the copper pad is provided; a semiconductor element disposed on the surface of the semiconductor package substrate on the side where the solder resist layer is provided and connected to the semiconductor package substrate via solder balls disposed on the copper pad; and an encapsulating resin layer disposed between the surface of the semiconductor element facing the semiconductor package substrate and the surface of the semiconductor package substrate facing the semiconductor element.

2. The solder resist evaluation model according to claim 1, wherein the pitch of the copper pads is 0.005 mm to 10 mm.

3. The solder resist evaluation model according to claim 1, wherein the diameter of the solder ball before melting is 0.01 mm to 0.50 mm.

4. A solder resist evaluation method comprising: conducting an environmental test on the solder resist evaluation model according to claim 1, in which cooling under a first temperature condition of -200°C to 0°C and heating under a second temperature condition of 0°C to 300°C are repeated multiple times; and observing the solder resist layer as an evaluation target included in the solder resist evaluation model after the environmental test.

5. A method for selecting a solder resist composition to be used in manufacturing a semiconductor package substrate that constitutes a semiconductor device, from among multiple types of solder resist compositions, the method comprising: preparing cured films of the multiple types of solder resist compositions; heating the cured films at 200°C to 300°C to prepare cured films after thermal history; obtaining information on the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C for the cured films after thermal history; inputting the obtained information into the following formula (1) to calculate a failure rate, including cracking and peeling, when the solder resist composition is applied to the semiconductor package substrate; and selecting solder resist compositions from the multiple types of solder resist compositions whose failure rate is 60% or less. Failure rate (%) = room temperature elongation + low temperature elongation + low temperature storage modulus + constant (1) 6. The method for selecting a solder resist composition according to claim 5, wherein the average thickness of the cured film is 0.5 μm to 50 μm.

7. A method for manufacturing a semiconductor device, comprising: preparing a semiconductor package substrate using a solder resist composition selected by the method for selecting a solder resist composition according to claim 5; connecting the semiconductor package substrate to a semiconductor element; and providing an encapsulating resin layer that covers the connection between the semiconductor package substrate and the semiconductor element.

8. A solder resist composition selected by the method for selecting a solder resist composition according to claim 5.

9. A solder resist composition comprising a photopolymerizable compound having an ethylenically unsaturated group, a photopolymerization initiator, an epoxy resin, and a curing accelerator, wherein when a cured film of the solder resist composition is heated at 200°C to 300°C to form a cured film after thermal history, the cured film after thermal history has a failure rate (%) including cracking and delamination, expressed by formula (1) based on the room temperature elongation at 25°C, the low temperature elongation at -60°C, and the low temperature storage modulus at -55°C, of ​​60% or less: Failure rate (%) = Room temperature elongation + Low temperature elongation + Low temperature storage modulus + Constant (1)

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