Power conversion device and control method

Abstract

A power conversion device (1) comprises a main inductor (L1), a switch group (10), and a control circuit (20), wherein: the switch group (10) has a main switch unit (11) that is a half-bridge circuit including two main switches (Q1, Q2) connected in series, and an auxiliary circuit (12) having an auxiliary inductor (L2) and an auxiliary switch unit (13) including two auxiliary switches (Q3, Q4) connected in series; and the control circuit (20) determines the total value of overlap time and dead time on the basis of the current flowing through the main inductor (L1), and when turning off the first main switch (Q1), the control circuit (20) turns on the first auxiliary switch (Q4), turns off the first main switch (Q1) after the overlap time has elapsed, turns on the second main switch (Q2) after the dead time has elapsed, and then turns off the first auxiliary switch (Q4).

Description

Power conversion device and control method

[0001] The present disclosure relates to a power conversion device and a control method thereof.

[0002] Reducing switching losses through soft switching is an effective way to improve converter efficiency. For example, Patent Document 1 discloses a DC-DC converter that uses an auxiliary circuit to achieve zero-volt switching (ZVS) when the main converter is turned on. Specifically, while the main switch, which has a forward current flowing in the on state, is turned off, the current flowing through the main inductor is drawn into an auxiliary inductor to complete the discharge of the charge accumulated in the parasitic capacitance of the main switch, and then the main switch is turned on, thereby achieving ZVS.

[0003] Patent No. 7180511

[0004] Whether ZVS can be achieved or not depends on the time between when current starts to be drawn into the auxiliary inductor and when the main switch is turned on, but the time required to achieve ZVS changes depending on changes in the circuit state. If the time between when current starts to be drawn into the auxiliary inductor and when the main switch is turned on is shorter than the time required to achieve ZVS in the current circuit state, ZVS cannot be achieved and switching losses increase. Furthermore, if the time between when current starts to be drawn into the auxiliary inductor and when the main switch is turned on is longer than the time required to achieve ZVS in the current circuit state, the time current flows in the auxiliary circuit becomes longer, resulting in increased conduction losses. In the DC-DC converter disclosed in Patent Document 1, losses increase and efficiency may decrease when the circuit state changes.

[0005] Therefore, the present disclosure provides a power conversion device and the like that can achieve high efficiency even when the circuit state changes.

[0006] a control circuit for controlling the group of switches; a main switch unit and an auxiliary circuit; the main switch unit being a half-bridge circuit including two main switches connected in series; the auxiliary circuit having an auxiliary switch unit including two auxiliary switches connected in series; and an auxiliary inductor; a high-voltage side terminal of the main switch unit and a high-voltage side terminal of the auxiliary switch unit being connected to each other and to one terminal of the second input / output terminal pair; a low-voltage side terminal of the main switch unit and a low-voltage side terminal of the auxiliary switch unit being connected to each other and to the other terminal of the second input / output terminal pair; and a second intermediate node between the auxiliary switches, and one of the first intermediate node and the second intermediate node is connected to one terminal of the first input / output terminal pair. The control circuit determines, based on the current flowing in the main inductor, a total value of an overlap time, which is a time during which a first main switch of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch of the two auxiliary switches, through which a forward current flows in an on state, are both in an on state, and a dead time, which is a time during which the two main switches are both in an off state, and turns on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch, turns off the first main switch after the overlap time has elapsed, and turns on a second main switch of the two main switches, through which a forward current flows in an on state, after the dead time has elapsed, and then turns off the first auxiliary switch.

[0007] a high-voltage side terminal of the main switch unit and a high-voltage side terminal of the auxiliary switch unit are connected to each other and to one terminal of the second input / output terminal pair, a low-voltage side terminal of the main switch unit and a low-voltage side terminal of the auxiliary switch unit are connected to each other and to the other terminal of the second input / output terminal pair, and the auxiliary inductor is connected between a first intermediate node between the two main switches and the a second intermediate node between two auxiliary switches, and one of the first intermediate node and the second intermediate node is connected to one terminal of the first input / output terminal pair; and the control method determines, based on the current flowing in the main inductor, a total value of an overlap time, which is a time during which a first main switch of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch of the two auxiliary switches, through which a forward current flows in an on state, are both in an on state, and a dead time, which is a time during which the two main switches are both in an off state; turns on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch; turns off the first main switch after the overlap time has elapsed; turns on the second main switch of the two main switches, through which a forward current flows in an on state, after the dead time has elapsed; and then turns off the first auxiliary switch.

[0008] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0009] According to a power conversion device according to an aspect of the present disclosure, high efficiency can be achieved even when the circuit state changes.

[0010] 9 is a circuit configuration diagram showing an example of a power conversion device according to embodiment 1. FIG. 10 is a block diagram showing an example of a control circuit according to embodiment 1. FIG. 11 is a diagram for explaining a first example of operation of the power conversion device according to embodiment 1. FIG. 12 is a diagram for explaining a second example of operation of the power conversion device according to embodiment 1. FIG. 13 is a diagram for explaining a third example of operation of the power conversion device according to embodiment 1. FIG. 14 is a diagram for explaining a fourth example of operation of the power conversion device according to embodiment 1. FIG. 15 is a diagram for explaining an example of dead time and overlap time in embodiment 1. FIG. 16 is a circuit configuration diagram showing an example of a power conversion device according to embodiment 2. FIG. 17 is a diagram for explaining a first example of operation of the power conversion device according to embodiment 2. FIG. 18 is a diagram for explaining a second example of operation of the power conversion device according to embodiment 2. FIG. 19 is a diagram for explaining a third example of operation of the power conversion device according to embodiment 2. FIG. 19 is a diagram for explaining a fourth example of operation of the power conversion device according to embodiment 2. FIG. 19 is a diagram for explaining an application example of the power conversion device according to embodiment 1 or 2. FIG. 19 is a diagram for explaining an example of dead time and overlap time in the application example of FIG. 9. FIG. 19 is a diagram for explaining another example of dead time and overlap time in the application example of FIG. 9. Fig. 1 is a diagram showing an application example of a power conversion device according to embodiment 1 or 2. Fig. 2 is a diagram showing an application example of a power conversion device according to embodiment 1 or 2. Fig. 3 is a diagram showing an application example of a power conversion device according to embodiment 1 or 2. Fig. 4 is a flowchart showing an example of a control method according to another embodiment.

[0011] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0012] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0013] (First embodiment) Hereinafter, a power conversion device according to a first embodiment will be described.

[0014] Fig. 1 is a circuit configuration diagram showing an example of a power conversion device 1 according to embodiment 1. In addition to the power conversion device 1, Fig. 1 also shows a voltage source 100, diodes D1 and D2, and capacitor C1. Note that the voltage source 100, diodes D1 and D2, or capacitor C1 may be provided in the power conversion device 1.

[0015] The power conversion device 1 is a power conversion device that converts an input voltage and outputs a desired voltage. The circuit configuration of the power conversion device 1 is not limited as long as the main switch unit 11, which will be described later, includes a half-bridge circuit. For example, the power conversion device 1 may be a grid-connected PFC (Power Factor Correction) circuit (totem-pole PFC) that converts AC to DC, as shown in FIG. 1 . Other application examples of the power conversion device 1 will be described later.

[0016] The voltage source 100 is, for example, an AC voltage source. For example, the voltage source 100 has a frequency f ａｃ AC voltage V ａｃ Note that the voltage source 100 may be an AC voltage source or a DC voltage source depending on the application of the power conversion device 1.

[0017] The diodes D1 and D2 are a rectifier circuit for rectifying the voltage output from the switch group 10, which will be described later. The DC voltage rectified by the diodes D1 and D2 and output is applied to the capacitor C1. This allows the capacitor C1 to operate as a DC voltage source. The voltage output from the capacitor C1 is converted to a voltage vｃ Let's say.

[0018] The power conversion device 1 includes terminals t1, t2, t3, and t4. The terminals t1 and t2 are an example of a first input / output terminal pair. The terminals t3 and t4 are an example of a second input / output terminal pair. The voltage between the second input / output terminal pair is a voltage output from the capacitor C1, and is a voltage v ｃ is.

[0019] The power conversion device 1 includes an inductor L1, a group of switches 10, and a control circuit 20.

[0020] The inductor L1 is an example of a main inductor connected in series between the first input / output terminal pair. For example, the inductor L1 is connected in series between the terminal t1 and the terminal t2 via the voltage source 100. The current flowing through the inductor L1 is referred to as a current i Ｌ Let us assume that Ｌ If .gtoreq.0, the current flows from the left to the right of the inductor L1 in FIG. 1, and i Ｌ <0, it is assumed that a current flows from the right side to the left side of the inductor L1 in FIG.

[0021] The switch group 10 converts the input voltage to obtain a desired output voltage by controlling each switch included in the switch group 10 with the control circuit 20. The switch group 10 is connected to at least one terminal of the first input / output terminal pair and both terminals of the second input / output terminal pair. In the power conversion device 1 shown in Fig. 1 , the switch group 10 is connected to terminal t1 of the first input / output terminal pair and to both terminals t3 and t4 of the second input / output terminal pair.

[0022] The switch group 10 includes a main switch unit 11 and an auxiliary circuit 12 .

[0023] The main switch unit 11 is a half-bridge circuit including switches Q1 and Q2, which are an example of two main switches connected in series.

[0024] The switch Q1 is, for example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The drain of the switch Q1 is connected to the terminal t3, and the source of the switch Q1 is connected to the terminal t1 and the drain of the switch Q2. The switch Q2 is, for example, an N-channel MOSFET. The drain of the switch Q2 is connected to the terminal t1 and the source of the switch Q1, and the source of the switch Q2 is connected to the terminal t4.

[0025] The auxiliary circuit 12 has an auxiliary switch unit 13 and an inductor L2. The auxiliary switch unit 13 includes switches Q3 and Q4. The switches Q3 and Q4 are an example of two auxiliary switches connected in series. The inductor L2 is an example of an auxiliary inductor. The auxiliary circuit 12 is, for example, a half-bridge circuit as shown in FIG. 1. The auxiliary circuit 12 may be a circuit configured with a multi-level converter (flying capacitor) as described in Patent Document 1.

[0026] The switch Q3 is, for example, an N-channel MOSFET. The drain of the switch Q3 is connected to the terminal t3, and the source of the switch Q3 is connected to the drain of the switch Q4. The switch Q4 is, for example, an N-channel MOSFET. The drain of the switch Q4 is connected to the source of the switch Q3, and the source of the switch Q4 is connected to the terminal t4.

[0027] When the switch Q3 or Q4 is turned on, a current flows through the switch Q3 or Q4 that is turned on via the inductor L2, and the inductor L2 is excited.

[0028] Note that FIG. 1 shows an anti-parallel diode connected to each switch, and each anti-parallel diode is connected in parallel to the corresponding switch. Specifically, the anode of each anti-parallel diode is connected to the source of the corresponding switch, and the cathode is connected to the drain of the corresponding switch. For example, each anti-parallel diode may be the body diode of the corresponding switch. Furthermore, each switch has a parasitic capacitance. The capacitance value of the parasitic capacitance of switches Q1 and Q2 is defined as a parasitic capacitance value C ｏｓｓ Let's say.

[0029] The inductor L2 is connected between a node N1 between the switches Q1 and Q2 and a node N2 between the switches Q3 and Q4. The node N1 is an example of a first intermediate node, and the node N2 is an example of a second intermediate node. The inductance value of the inductor L2 is set to an inductance value L ｓｕｂ The current flowing through the inductor L2 is defined as current i Ｌｓｕｂ Let us assume that Ｌｓｕｂ If .gtoreq.0, the current flows from the left to the right of the inductor L2 in FIG. 1, and i Ｌｓｕｂ <0, it is assumed that a current flows from the right side to the left side of the inductor L2 in FIG.

[0030] One of the nodes N1 and N2 is connected to one terminal of the first input / output terminal pair. In the power conversion device 1 shown in Fig. 1, the node N1, which is one of the nodes N1 and N2, is connected to the terminal t1, which is one terminal of the first input / output terminal pair.

[0031] The high-voltage side terminal of the main switch unit 11 (e.g., the terminal connected to the drain of switch Q1) and the high-voltage side terminal of the auxiliary switch unit 13 (e.g., the terminal connected to the drain of switch Q3) are connected to each other and to one terminal t3 of the second input / output terminal pair. The low-voltage side terminal of the main switch unit 11 (e.g., the terminal connected to the source of switch Q2) and the low-voltage side terminal of the auxiliary switch unit 13 (e.g., the terminal connected to the source of switch Q4) are connected to each other and to the other terminal t4 of the second input / output terminal pair.

[0032] The control circuit 20 controls the switch group 10. Specifically, the control circuit 20 controls the switching of the switches Q1, Q2, Q3, and Q4. For example, the control circuit 20 controls the switching of the switches Q1, Q2, Q3, and Q4 by controlling a gate drive circuit (not shown) connected to the gates of the switches Q1, Q2, Q3, and Q4.

[0033] The control circuit 20 determines the total value of the overlap time and the dead time based on the current flowing through the inductor L1. The overlap time is the time during which the first main switch, one of the switches Q1 and Q2, through which a reverse current flows when turned on, and the first auxiliary switch, one of the switches Q3 and Q4, through which a forward current flows when turned on, are both in the on state. The dead time is the time during which the switches Q1 and Q2 are both in the off state.

[0034] The control circuit 20 also turns on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch. Then, the control circuit 20 turns off the first main switch after the overlap time has elapsed. Then, after the dead time has elapsed, the control circuit 20 turns on the second main switch, of the switches Q1 and Q2, through which a forward current flows in the on state, and then turns off the first auxiliary switch. The overlap time is set to time T ｏｖｅｒｒａｐ and the dead time is T ｄ The operation of the control circuit 20 will be described in detail later.

[0035] The first main switch through which a reverse current flows in the on state is a switch through which a current flows from the source to the drain in the on state. Ｌ If i is greater than 0, the first main switch that is turned on and through which a reverse current flows is switch Q1, and i Ｌ <0, the first main switch that is on and through which a reverse current flows is switch Q2.

[0036] The first auxiliary switch through which a forward current flows in the on state is a switch through which a current flows from the drain to the source in the on state. Ｌ If i is greater than 0, the first auxiliary switch through which a forward current flows in the on state is the switch Q4, and i Ｌ <0, the first auxiliary switch through which a forward current flows in the on state is switch Q3.

[0037] The second main switch through which a forward current flows in the on state is a switch through which a current flows from the drain to the source in the on state. ＬIf i is greater than 0, the second main switch that is on and through which a forward current flows is switch Q2, and i Ｌ <0, the second main switch that is on and through which a forward current flows is switch Q1.

[0038] Next, the configuration of the control circuit 20 will be described in detail with reference to FIG.

[0039] FIG. 2 is a block diagram showing an example of the control circuit 20 according to the first embodiment.

[0040] The control circuit 20 has a voltage command value generating unit 21, a PWM control unit 22, and a determining unit 23. The control circuit 20 is realized by a computer including, for example, a processor (microprocessor) and a memory. The memory is a read-only memory (ROM) or a random access memory (RAM), and can store programs executed by the processor. The voltage command value generating unit 21, the PWM control unit 22, and the determining unit 23 are realized by, for example, a processor that executes programs stored in the memory.

[0041] The voltage command value generator 21 generates a voltage command value for making the voltage of the capacitor C1 (the voltage between the terminals t3 and t4) a target voltage. For example, the voltage command value generator 21 generates a voltage command value for making the AC voltage v ａｃ , the current i flowing through the inductor L1 Ｌ and the voltage v of the capacitor C1 ｃ The voltage command value generating unit 21 outputs the generated voltage command value to the PWM control unit 22.

[0042] The PWM control unit 22 generates PWM signals for controlling the switching of the switches Q1 and Q2 and the switches Q3 and Q4 based on the voltage command value generated by the voltage command value generating unit 21 .

[0043] The determination unit 23 determines the total value of the overlap time and the dead time. The determination unit 23 determines the total value of the current i flowing through at least the inductor L1. Ｌ For example, the determination unit 23 determines the total value based on the current i flowing through the inductor L1. Ｌ, the voltage v between the second input / output terminal pair ｃ , the inductance value L of the inductor L2 ｓｕｂ 2, the determining unit 23 further determines the total value based on the parasitic capacitance value C ｏｓｓ The method for determining the total value will be described in detail later.

[0044] For example, the power conversion device 1 may be provided with an ammeter and a voltmeter, and the voltage command value generating unit 21 and the determining unit 23 may calculate the current i measured by the ammeter. Ｌ and the voltage measured by the voltmeter, v ｃ Alternatively, the voltage command value generating unit 21 and the determining unit 23 may obtain the current i Ｌ The command value and voltage v ｃ By obtaining the command value for outputting the current i Ｌ and voltage v ｃ For example, the inductance value L ｓｕｂ may be corrected based on the DC superposition characteristics.

[0045] The determination unit 23 reflects the overlap time and dead time corresponding to the determined total value in the PWM signal generated by the PWM control unit 22. Then, the determination unit 23 outputs the PWM signal for the switches Q1 and Q2, in which the overlap time and dead time are reflected, to the gates of the switches Q1 and Q2 as a main switch gate signal, and outputs the PWM signal for the switches Q3 and Q4, in which the overlap time and dead time are reflected, to the gates of the switches Q3 and Q4 as an auxiliary switch gate signal.

[0046] Next, first to fourth examples of the operation of the power conversion device 1 (control circuit 20) according to the first embodiment will be described. First, a first example of the operation of the power conversion device 1 according to the first embodiment will be described with reference to FIG. 3A .

[0047] 3A is a diagram for explaining a first example of the operation of the power conversion device 1 according to the first embodiment. Ｌ and current i Ｌｓｕｂ, the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q4 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｄ is indicated by a solid arrow, and the time T ｄ is indicated by a dashed arrow.

[0048] In FIG. 3A, i Ｌ >0, time T ｄ is variable, T ｏｖｅｒｒａｐ = 0. In this case, the total value of the overlap time and the dead time is T ｏｖｅｒｒａｐ = 0, so time T ｄ In addition, i Ｌ If >0, switch Q3 is in the off state.

[0049] The duty ratios of switches Q1 and Q2 are adjusted by PWM control unit 22 so that the voltage at node N1 becomes a voltage corresponding to the voltage command value. As shown in FIG. 3A, switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, a dead time is determined by determination unit 23 so that switches Q1 and Q2 are not turned on simultaneously. Furthermore, if switch Q2 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of switch Q2, switching loss increases. Therefore, it is necessary to turn on switch Q2 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0050] Therefore, when the switch Q4 is turned on, a current is drawn from the node N1 to the inductor L2. In other words, the inductor L2 is excited. Ｌ >0, time T ｄ is variable, T ｏｖｅｒｒａｐ If .times. ... ＬｓｕｂIncreasingly, i Ｌｓｕｂ = i Ｌ After this state is reached, the charge accumulated in the parasitic capacitance of the switch Q2 is extracted. Note that no current flows through the switch Q4 until it is turned on, and the current through the switch Q4 increases via the inductor L2 after it is turned on, achieving ZCS (zero current switching) of the switch Q4.

[0051] The total overlap time and dead time required to achieve ZVS varies with changes in circuit conditions. In the case of FIG. 3A, the total overlap time and dead time is equal to the time T ｄ As shown in FIG. 3A, when the load changes, the current flowing through the inductor L1 changes, and accordingly the current flowing through the inductor L2 also changes. As a result, the time T ｄ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0052] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to magnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2, and the time required to magnetize inductor L2 can be expressed by the following equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2 can be expressed by the following equation 2. In other words, the total value of the overlap time and dead time required to achieve ZVS can be expressed by the following equation 3.

[0053]

[0054]

[0055]

[0056] Therefore, by determining the total value of the overlap time and the dead time based on the current flowing through inductor L1, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0057] After ZVS is achieved, switch Q4 is turned off, allowing current to flow through switch Q2.

[0058] The total value of the overlap time and the dead time required to achieve ZVS changes not only in response to changes in the current flowing through inductor L1, but also in response to changes in the voltage across the second input / output terminal pair, as shown in the above formula 1, and also in response to the inductance value of inductor L2. Therefore, by determining the total value of the overlap time and the dead time based on the current flowing through inductor L1, the voltage across the second input / output terminal pair, and the inductance value of inductor L2, the control circuit 20 can bring the total value of the overlap time and the dead time closer to the time required to achieve ZVS in the current circuit state.

[0059] Furthermore, as shown in the above formula 1, the total value of the overlap time and the dead time required to achieve ZVS increases as the absolute value of the current flowing through inductor L1 increases, and decreases as the voltage across the second input / output terminal pair increases. Therefore, by determining the total value of the overlap time and the dead time so that it increases as the absolute value of the current flowing through inductor L1 increases and decreases as the voltage across the second input / output terminal pair increases, the control circuit 20 can bring the total value of the overlap time and the dead time closer to the time required to achieve ZVS in the current circuit state.

[0060] Furthermore, the total value of the overlap time and the dead time required to achieve ZVS increases as the absolute value of the current flowing through inductor L1 increases, decreases as the voltage between the second input / output terminal pair increases, increases as the inductance value of inductor L2 increases, and increases as the parasitic capacitance value of switch Q2 increases, as shown in equation 3. Therefore, by setting the total value of the overlap time and the dead time to a value equal to or greater than the value expressed by equation 3, the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0061] Furthermore, by setting the total value of the overlap time and the dead time to the same value as the value expressed by the above equation 3, the total value of the overlap time and the dead time can be set to the exact time required to achieve ZVS in the current circuit state.

[0062] If the dead time is too short, there is a risk that the switches Q1 and Q2 will be turned on at the same time. Therefore, if the lower limit value set for the dead time is greater than the value expressed by the above formula 2, the dead time may be set to the lower limit value. This prevents the switches Q1 and Q2 from being turned on at the same time.

[0063] Next, a second example of the operation of the power conversion device 1 according to the first embodiment will be described with reference to FIG. 3B.

[0064] 3B is a diagram for explaining a second example of the operation of the power conversion device 1 according to the first embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q3 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｄ is indicated by a solid arrow, and the time T ｄ is indicated by a dashed arrow.

[0065] In FIG. 3B, i Ｌ <0, time T ｄ is variable, T ｏｖｅｒｒａｐ = 0. In this case, the total value of the overlap time and the dead time is T ｏｖｅｒｒａｐ = 0, so time T ｄ In addition, i Ｌ If <0, switch Q4 is in the OFF state.

[0066] The duty ratios of switches Q1 and Q2 are adjusted by PWM control unit 22 so that the voltage at node N1 becomes a voltage corresponding to the voltage command value, and as shown in FIG. 3B , switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, a dead time is determined by determination unit 23 so that switches Q1 and Q2 are not turned on simultaneously. Furthermore, if switch Q1 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of switch Q1, switching loss increases. Therefore, it is necessary to turn on switch Q1 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0067] Therefore, when the switch Q3 is turned on, a current is drawn from the node N1 to the inductor L2. In other words, the inductor L2 is excited. Ｌ <0, time T ｄ is variable, T ｏｖｅｒｒａｐ If .times. ... Ｌｓｕｂ decreases (current i Ｌｓｕｂ The absolute value of increases, i Ｌｓｕｂ = i Ｌ After this state is reached, the charge accumulated in the parasitic capacitance of the switch Q1 is extracted. Note that no current flows through the switch Q3 until the switch Q3 is turned on, and the current through the switch Q3 gradually increases via the inductor L2 after the switch Q3 is turned on, thereby achieving ZCS of the switch Q3.

[0068] The total overlap time and dead time required to achieve ZVS varies with changes in circuit conditions. In the case of FIG. 3B, the total overlap time and dead time is equal to the time T ｄ As shown in FIG. 3B, when the load changes, the current flowing through the inductor L1 changes, and accordingly the current flowing through the inductor L2 also changes. As a result, the time T ｄ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0069] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to magnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1. The time required to magnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1 can be expressed by the above equation 2 below. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0070] Therefore, by determining the total value of the overlap time and the dead time in the same manner as in the first example of the operation of the power conversion device 1 according to the first embodiment, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0071] After ZVS is achieved, switch Q3 is turned off, allowing current to flow through switch Q1.

[0072] Next, a third example of the operation of the power conversion device 1 according to the first embodiment will be described with reference to FIG. 4A.

[0073] 4A is a diagram for explaining a third example of the operation of the power conversion device 1 according to the first embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q4 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｏｖｅｒｒａｐ and the sum of the overlap time and the dead time T ｄ +T ｏｖｅｒｒａｐ is indicated by a solid arrow, and the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ is indicated by a dashed arrow. Whether the load is heavy or light, the time Tｄ is indicated by a solid arrow.

[0074] In FIG. 4A, i Ｌ >0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ is variable. Ｌ If >0, switch Q3 is in the off state.

[0075] The duty ratios of switches Q1 and Q2 are adjusted by PWM control unit 22 so that the voltage at node N1 becomes a voltage corresponding to the voltage command value, and as shown in Fig. 4A, switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, a dead time is determined by determination unit 23 so that switches Q1 and Q2 are not turned on simultaneously. Furthermore, if switch Q2 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of switch Q2, switching loss increases. Therefore, it is necessary to turn on switch Q2 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0076] Therefore, when the switch Q4 is turned on, a current is drawn from the node N1 to the inductor L2. In other words, the inductor L2 is excited. Ｌ >0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ When the current i is variable, the control circuit 20 turns on the switch Q4 before turning off the switch Q1. As a result, as shown in FIG. 4A, the current i Ｌｓｕｂ Increasingly, i Ｌｓｕｂ = i Ｌ After this state is reached, the charge accumulated in the parasitic capacitance of the switch Q2 is extracted. Note that no current flows through the switch Q4 until the switch Q4 is turned on, and the current through the switch Q4 gradually increases via the inductor L2 after the switch Q4 is turned on, thereby achieving ZCS of the switch Q4.

[0077] The total overlap time and dead time required to achieve ZVS varies with changes in the circuit conditions. As shown in FIG. 4A, when the load changes, the current flowing through inductor L1 changes, and the current flowing through inductor L2 also changes accordingly. As a result, the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0078] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to magnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2. The time required to magnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2 can be expressed by the above equation 2 below. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0079] Therefore, by determining the total value of the overlap time and the dead time in the same manner as in the first example of the operation of the power conversion device 1 according to the first embodiment, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0080] After ZVS is achieved, switch Q4 is turned off, allowing current to flow through switch Q2.

[0081] Furthermore, the control circuit 20 may determine the overlap time and the dead time separately, or may determine the total value of the overlap time and the dead time by determining the overlap time and the dead time separately.

[0082] For example, the control circuit 20 may set a lower limit value for the dead time. If the dead time is too short, there is a risk that the switches Q1 and Q2 will be turned on simultaneously. Therefore, by setting a lower limit value for the dead time, the switches Q1 and Q2 will not be turned on simultaneously, and the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0083] For example, as shown in FIG. 1, when node N1 is connected to one terminal t1 of the first input / output terminal pair, control circuit 20 may determine the overlap time so that switch Q1 is turned off at or before the timing at which the current flowing through inductor L2 coincides with the current flowing through inductor L1.

[0084] When node N1 is connected to one terminal t1 of the first input / output terminal pair, turning on switch Q4 causes commutation from switch Q1 to inductor L2. By determining the overlap time so that switch Q1 is turned off at or before the timing when current stops flowing through switch Q1 after commutation, it is possible to prevent the conduction time of the anti-parallel diode of switch Q1 from becoming long and the conduction loss of the anti-parallel diode from increasing, while also preventing the current flowing through inductor L2 from increasing more than necessary.

[0085] For example, the control circuit 20 may determine the overlap time to increase as the absolute value of the current flowing through the inductor L1 increases, and to decrease as the voltage across the second input / output terminal pair increases.

[0086] The overlap time required to achieve ZVS increases as the absolute value of the current flowing through inductor L1 increases, and decreases as the voltage across the second input / output terminal pair increases, as shown in the above formula 1. Therefore, by determining the overlap time so that it increases as the absolute value of the current flowing through inductor L1 increases and decreases as the voltage across the second input / output terminal pair increases, the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0087] For example, the control circuit 20 may determine the overlap time to be a value within the value expressed by the above formula 1.

[0088] When node N1 is connected to one terminal t1 of the first input / output terminal pair, if the overlap time exceeds the value expressed by the above formula 1, the current flowing through inductor L2 will increase more than necessary. Therefore, by setting the overlap time to be equal to or less than the value expressed by the above formula 1, it is possible to prevent the current flowing through inductor L2 from increasing more than necessary.

[0089] In the third example of the operation of the power conversion device 1 according to the first embodiment, the time T ｄ and time T ｏｖｅｒｒａｐ In this case, the control circuit 20 may determine the overlap time to be the value expressed by the above formula 1, and determine the dead time to be the larger of the lower limit value set for the dead time and the value expressed by the above formula 2.

[0090] The overlap time required to achieve ZVS increases as the absolute value of the current flowing through inductor L1 increases, decreases as the voltage across the second input / output terminal pair increases, and increases as the inductance value of inductor L2 increases. The dead time required to achieve ZVS increases as the inductance value of inductor L2 increases and as the parasitic capacitance of switch Q2 increases. Therefore, by setting the overlap time to the value expressed by Equation 1 and the dead time to the value expressed by Equation 2, the sum of the overlap time and the dead time can be brought closer to the time required to achieve ZVS in the current circuit state. However, if the dead time is too short, there is a risk that switches Q1 and Q2 will be turned on simultaneously. Therefore, if the lower limit value set for the dead time is greater than Equation 2, setting the dead time to the lower limit can prevent switches Q1 and Q2 from being turned on simultaneously.

[0091] Next, a fourth example of the operation of the power conversion device 1 according to the first embodiment will be described with reference to FIG. 4B.

[0092] 4B is a diagram for explaining a fourth example of the operation of the power conversion device 1 according to the first embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q3 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｏｖｅｒｒａｐ and the sum of the overlap time and the dead time T ｄ +T ｏｖｅｒｒａｐ is indicated by a solid arrow, and the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ is indicated by a dashed arrow. Whether the load is heavy or light, the time T ｄ is indicated by a solid arrow.

[0093] In FIG. 4B, i Ｌ <0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ is variable. Ｌ If <0, switch Q4 is in the OFF state.

[0094] The duty ratios of the switches Q1 and Q2 are adjusted by the PWM control unit 22 so that the voltage at the node N1 becomes a voltage corresponding to the voltage command value, and as shown in FIG. 4B , the switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, the determining unit 23 determines a dead time so that the switches Q1 and Q2 are not turned on simultaneously. Furthermore, if the switch Q1 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of the switch Q1, switching loss increases. Therefore, it is necessary to turn on the switch Q1 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0095] Therefore, when the switch Q3 is turned on, a current is drawn from the node N1 to the inductor L2. In other words, the inductor L2 is excited. Ｌ <0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ When the current i is variable, the control circuit 20 turns on the switch Q3 before turning off the switch Q2. As a result, as shown in FIG. 4B, the current i Ｌｓｕｂ Increasingly, i Ｌｓｕｂ = i Ｌ After this state is reached, the charge accumulated in the parasitic capacitance of the switch Q1 is extracted. Note that no current flows through the switch Q3 until the switch Q3 is turned on, and after the switch Q3 is turned on, the current gradually increases due to the influence of the inductor L2, thereby achieving ZCS of the switch Q3.

[0096] The total overlap time and dead time required to achieve ZVS varies with changes in the circuit conditions. As shown in FIG. 4B, when the load changes, the current flowing through inductor L1 changes, and the current flowing through inductor L2 also changes accordingly. As a result, the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0097] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to magnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1. The time required to magnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1 can be expressed by the above equation 2 below. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0098] Therefore, as in the third example of the operation of the power conversion device 1 according to the first embodiment, by determining the total value of the overlap time and the dead time, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0099] After ZVS is achieved, switch Q3 is turned off, allowing current to flow through switch Q1.

[0100] Furthermore, the control circuit 20 may determine the overlap time and the dead time, respectively, basically in the same manner as in the third example of the operation of the power conversion device 1 according to embodiment 1, or may determine the total value of the overlap time and the dead time by determining the overlap time and the dead time, respectively. Below, differences from the third example of the operation of the power conversion device 1 according to embodiment 1 will be described.

[0101] For example, as shown in FIG. 1, when node N1 is connected to one terminal t1 of the first input / output terminal pair, control circuit 20 may determine the overlap time so that switch Q2 is turned off at or before the timing at which the current flowing through inductor L2 coincides with the current flowing through inductor L1.

[0102] When node N1 is connected to one terminal t1 of the first input / output terminal pair, turning on switch Q3 causes commutation from switch Q2 to inductor L2. By determining the overlap time so that switch Q2 is turned off at or before the timing when current stops flowing through switch Q2 after commutation, it is possible to prevent the conduction time of the anti-parallel diode of switch Q2 from becoming longer and the conduction loss of the anti-parallel diode from increasing, while also preventing the current flowing through inductor L2 from increasing more than necessary.

[0103] Next, examples of dead time and overlap time in the first and second examples of operation of the power conversion device 1 according to embodiment 1 will be explained using Figure 5A, and examples of dead time and overlap time in the third and fourth examples of operation of the power conversion device 1 according to embodiment 1 will be explained using Figure 5B.

[0104] 5A is a diagram showing an example of the dead time and the overlap time in the first embodiment. FIG. 5B is a diagram showing another example of the dead time and the overlap time in the first embodiment. In FIGS. 5A and 5B, the AC voltage v ａｃ , current i Ｌ , time T ｄ and time T ｏｖｅｒｒａｐ A graph showing the change over time is shown.

[0105] As shown in FIG. 5A, at time T ｄ is variable, T ｏｖｅｒｒａｐ If = 0, the current i Ｌ The time T required to achieve ZVS depending on the change ｄ is determined. ｄ is the lower limit of the dead time T ｄｍｉｎ , so that the time T ｄ is the lower limit T ｄｍｉｎ That's all.

[0106] As shown in FIG. 5B, at time T ｄ is fixed (for example, T ｄ =T ｄｍｉｎ ), time T ｏｖｅｒｒａｐ When is variable, the current i Ｌ The time T required to achieve ZVS depending on the change ｏｖｅｒｒａｐ Since the minimum value of the overlap time is 0, the time T ｏｖｅｒｒａｐ is greater than or equal to 0.

[0107] As explained above, the sum of the overlap time and the dead time is Ｌ If >0, switch Q4, i Ｌ <0, the switch Q3) is turned on, and then the second main switch (i Ｌ If >0, switch Q2, i Ｌ< 0, the time until the switch Q1 is turned on determines whether ZVS is achieved. The total value of the overlap time and dead time required to achieve ZVS changes depending on changes in the current flowing through inductor L1 as the circuit state changes. Therefore, by determining the total value of the overlap time and dead time based on the current flowing through inductor L1, the total value of the overlap time and dead time can be made closer to the time required to achieve ZVS in the current circuit state. This prevents the total value of the overlap time and dead time from being shorter than the time required to achieve ZVS in the current circuit state, which would result in ZVS not being achieved and an increase in switching loss. Furthermore, by setting the total value of the overlap time and dead time to a time sufficient to achieve ZVS in the current circuit state, an increase in conduction loss due to an increase in the conduction time of switch Q3 or Q4 can be prevented. Therefore, high efficiency can be achieved even when the circuit state changes.

[0108] Second Embodiment Next, a power conversion device according to a second embodiment will be described.

[0109] FIG. 6 is a circuit configuration diagram showing an example of a power conversion device 2 according to the second embodiment.

[0110] In the power conversion device 2, the arrangement of the components of the switch group 10 is different from that of the switch group 10 included in the power conversion device 1 according to the first embodiment. Specifically, in the power conversion device 2 shown in FIG. 6 , the node N2, which serves as one of the nodes N1 and N2, is connected to the terminal t1, which serves as one terminal of the first input / output terminal pair. As a result, in the second embodiment, when the switches Q3 and Q4 are both off, the current flowing through the inductor L1 and the current flowing through the inductor L2 are the same. Furthermore, when the switch Q3 or Q4 is turned on, the current flowing through the inductor L2 flows to the switch Q3 or Q4, which is in the on state, and the inductor L2 is demagnetized. The other points are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0111] First to fourth examples of the operation of the power conversion device 2 (control circuit 20) according to the second embodiment will be described below. First, a first example of the operation of the power conversion device 2 according to the second embodiment will be described with reference to FIG. 7A .

[0112] 7A is a diagram for explaining a first example of the operation of the power conversion device 2 according to the second embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q4 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｄ is indicated by a solid arrow, and the time T ｄ is indicated by a dashed arrow.

[0113] In FIG. 7A, i Ｌ >0, time T ｄ is variable, T ｏｖｅｒｒａｐ = 0. In this case, the total value of the overlap time and the dead time is T ｏｖｅｒｒａｐ = 0, so time T ｄ In addition, i Ｌ If >0, switch Q3 is in the off state.

[0114] The duty ratios of switches Q1 and Q2 are adjusted by PWM control unit 22 so that the voltage at node N2 becomes a voltage corresponding to the voltage command value. As shown in Fig. 7A, switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, a dead time is determined by determination unit 23 so that switches Q1 and Q2 are not turned on simultaneously. Furthermore, if switch Q2 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of switch Q2, switching loss increases. Therefore, it is necessary to turn on switch Q2 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0115] Therefore, when the switch Q4 is turned on, the current flowing through the inductor L2 is drawn to the switch Q4. In other words, the inductor L2 is demagnetized. Ｌ >0, time T ｄ is variable, T ｏｖｅｒｒａｐ If .times. ... Ｌｓｕｂ decreases, and i Ｌｓｕｂ = 0, the charge accumulated in the parasitic capacitance of the switch Q2 is extracted. Note that no current flows through the switch Q4 until the switch Q4 is turned on, and the current through the switch Q4 gradually increases via the inductor L2 after the switch Q4 is turned on, thereby achieving ZCS of the switch Q4.

[0116] The total overlap time and dead time required to achieve ZVS varies with changes in circuit conditions. In the case of FIG. 7A, the total overlap time and dead time is equal to the time T ｄ As shown in FIG. 7A, when the load changes, the current flowing through the inductor L1 changes, and accordingly the current flowing through the inductor L2 also changes. As a result, the time T ｄ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0117] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to demagnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2. The time required to demagnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2 can be expressed by the following equation 2. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0118] Therefore, by determining the total value of the overlap time and the dead time in the same manner as in the first example of the operation of the power conversion device 1 according to the first embodiment, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0119] After ZVS is achieved, switch Q4 is turned off, allowing current to flow through switch Q2.

[0120] Next, a second example of the operation of the power conversion device 2 according to the second embodiment will be described with reference to FIG. 7B.

[0121] 7B is a diagram for explaining a second example of the operation of the power conversion device 2 according to the second embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q3 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｄ is indicated by a solid arrow, and the time T ｄ is indicated by a dashed arrow.

[0122] In FIG. 7B, i Ｌ <0, time T ｄ is variable, T ｏｖｅｒｒａｐ = 0. In this case, the total value of the overlap time and the dead time is T ｏｖｅｒｒａｐ = 0, so time T ｄ In addition, i Ｌ If <0, switch Q4 is in the OFF state.

[0123] The duty ratios of the switches Q1 and Q2 are adjusted by the PWM control unit 22 so that the voltage at the node N2 becomes a voltage corresponding to the voltage command value, and as shown in FIG. 7B , the switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, the determining unit 23 determines a dead time so that the switches Q1 and Q2 are not turned on simultaneously. Furthermore, if the switch Q1 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of the switch Q1, switching loss increases. Therefore, it is necessary to turn on the switch Q1 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0124] Therefore, when the switch Q3 is turned on, the current flowing through the inductor L2 is drawn to the switch Q3. In other words, the inductor L2 is demagnetized. Ｌ <0, time T ｄ is variable, T ｏｖｅｒｒａｐ If .times. ... Ｌｓｕｂ increases (current i Ｌｓｕｂ The absolute value of decreases), i Ｌｓｕｂ = 0, the charge accumulated in the parasitic capacitance of the switch Q1 is extracted. Note that no current flows through the switch Q3 until the switch Q3 is turned on, and the current through the switch Q3 gradually increases via the inductor L2 after the switch Q3 is turned on, thereby achieving ZCS of the switch Q3.

[0125] The total overlap time and dead time required to achieve ZVS varies with changes in circuit conditions. In the case of FIG. 7B, the total overlap time and dead time is equal to the time T ｄ As shown in FIG. 7B, when the load changes, the current flowing through the inductor L1 changes, and accordingly the current flowing through the inductor L2 also changes. As a result, the time T ｄ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0126] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to demagnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1. The time required to demagnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1 can be expressed by the above equation 2 below. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0127] Therefore, by determining the total value of the overlap time and the dead time in the same manner as in the first example of the operation of the power conversion device 2 according to the second embodiment, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0128] After ZVS is achieved, switch Q3 is turned off, allowing current to flow through switch Q1.

[0129] Next, a third example of the operation of the power conversion device 2 according to the second embodiment will be described with reference to FIG. 8A.

[0130] 8A is a diagram for explaining a third example of the operation of the power conversion device 2 according to the second embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q4 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂ is shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｏｖｅｒｒａｐ and the sum of the overlap time and the dead time T ｄ +T ｏｖｅｒｒａｐ is indicated by a solid arrow, and the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ is indicated by a dashed arrow. Whether the load is heavy or light, the time Tｄ is indicated by a solid arrow.

[0131] In FIG. 8A, i Ｌ >0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ is variable. Ｌ If >0, switch Q3 is in the off state.

[0132] The duty ratios of switches Q1 and Q2 are adjusted by PWM control unit 22 so that the voltage at node N2 becomes a voltage corresponding to the voltage command value. As shown in FIG. 8A , switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, a dead time is determined by determination unit 23 so that switches Q1 and Q2 are not turned on simultaneously. Furthermore, if switch Q2 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of switch Q2, switching loss increases. Therefore, it is necessary to turn on switch Q2 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0133] Therefore, when the switch Q4 is turned on, the current flowing through the inductor L2 is drawn to the switch Q4. In other words, the inductor L2 is demagnetized. Ｌ >0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ When the current i is variable, the control circuit 20 turns on the switch Q4 before turning off the switch Q1. As a result, as shown in FIG. 8A, the current i Ｌｓｕｂ decreases, and i Ｌｓｕｂ = 0, the charge accumulated in the parasitic capacitance of the switch Q2 is extracted. Note that no current flows through the switch Q4 until the switch Q4 is turned on, and the current through the switch Q4 gradually increases via the inductor L2 after the switch Q4 is turned on, thereby achieving ZCS of the switch Q4.

[0134] The total overlap time and dead time required to achieve ZVS varies depending on the circuit conditions. As shown in FIG. 8A, when the load changes, the current flowing through inductor L1 changes, and the current flowing through inductor L2 also changes accordingly. As a result, the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0135] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to demagnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2. The time required to demagnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q2 can be expressed by the following equation 2. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0136] Therefore, by determining the total value of the overlap time and the dead time in the same manner as in the first example of the operation of the power conversion device 2 according to the second embodiment, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0137] After ZVS is achieved, switch Q4 is turned off, allowing current to flow through switch Q2.

[0138] Furthermore, the control circuit 20 may determine the overlap time and the dead time, respectively, basically in the same manner as in the third example of the operation of the power conversion device 1 according to embodiment 1, or may determine the total value of the overlap time and the dead time by determining the overlap time and the dead time, respectively. Below, differences from the third example of the operation of the power conversion device 1 according to embodiment 1 will be described.

[0139] For example, as shown in FIG. 6, when the node N2 is connected to one terminal t1 of the first input / output terminal pair, the control circuit 20 may determine the overlap time so that the switch Q1 is turned off at or before the timing when the current flowing through the inductor L2 becomes zero.

[0140] When node N2 is connected to one terminal t1 of the first input / output terminal pair, switch Q4 is turned on, causing commutation from inductor L2 to switch Q4. By determining the overlap time so that switch Q1 is turned off at or before the timing when current stops flowing through inductor L2 after commutation, it is possible to prevent the current flowing through inductor L2 from increasing more than necessary while suppressing an increase in conduction loss in the anti-parallel diode due to a longer conduction time of the anti-parallel diode of switch Q1.

[0141] For example, the control circuit 20 may determine the overlap time to be a value within the value expressed by the above formula 1.

[0142] When node N2 is connected to one terminal t1 of the first input / output terminal pair, if the overlap time exceeds the value expressed by the above formula 1, the polarity of the current flowing through inductor L2 will be reversed. Therefore, by setting the overlap time to be equal to or less than the value expressed by the above formula 1, it is possible to prevent the polarity of the current flowing through inductor L2 from being reversed.

[0143] Next, a fourth example of the operation of the power conversion device 2 according to the second embodiment will be described with reference to FIG. 8B.

[0144] 8B is a diagram for explaining a fourth example of the operation of the power conversion device 2 according to the second embodiment. Ｌ and current i Ｌｓｕｂ , the gate signals of the switches Q1 and Q2, and the gate signal of the switch Q3 are shown. In addition, when the load connected to the capacitor C1 is a heavy load, the current i Ｌ and current i Ｌｓｕｂ is shown by a solid line, and the current i Ｌ and current i Ｌｓｕｂis shown by a dashed line. In addition, when the load connected to the capacitor C1 is a heavy load, the time T ｏｖｅｒｒａｐ and the sum of the overlap time and the dead time T ｄ +T ｏｖｅｒｒａｐ is indicated by a solid arrow, and the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ is indicated by a dashed arrow. Whether the load is heavy or light, the time T ｄ is indicated by a solid arrow.

[0145] In FIG. 8B, i Ｌ <0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ is variable. Ｌ If <0, switch Q4 is in the OFF state.

[0146] The duty ratios of the switches Q1 and Q2 are adjusted by the PWM control unit 22 so that the voltage at the node N2 becomes a voltage corresponding to the voltage command value, and as shown in FIG. 8B , the switches Q1 and Q2 are alternately turned on at the adjusted duty ratios, thereby converting the input voltage into a predetermined voltage. However, the determining unit 23 determines a dead time so that the switches Q1 and Q2 are not turned on simultaneously. Furthermore, if the switch Q1 is turned on after the dead time has elapsed while charge is accumulated in the parasitic capacitance of the switch Q1, switching loss increases. Therefore, it is necessary to turn on the switch Q1 with as little charge accumulated as possible, i.e., to achieve ZVS.

[0147] Therefore, when the switch Q3 is turned on, the current flowing through the inductor L2 is drawn to the switch Q3. In other words, the inductor L2 is demagnetized. Ｌ <0, time T ｄ is fixed, time T ｏｖｅｒｒａｐ When the current i is variable, the control circuit 20 turns on the switch Q3 before turning off the switch Q2. As a result, as shown in FIG. 8B, the current i Ｌｓｕｂ increases (current i Ｌｓｕｂ The absolute value of decreases), i Ｌｓｕｂ= 0, the charge accumulated in the parasitic capacitance of the switch Q1 is extracted. Note that no current flows through the switch Q3 until the switch Q3 is turned on, and the current through the switch Q3 gradually increases via the inductor L2 after the switch Q3 is turned on, thereby achieving ZCS of the switch Q3.

[0148] The total overlap time and dead time required to achieve ZVS varies with changes in the circuit conditions. As shown in FIG. 8B, when the load changes, the current flowing through inductor L1 changes, and the current flowing through inductor L2 also changes accordingly. As a result, the time T ｏｖｅｒｒａｐ and the total value T ｄ +T ｏｖｅｒｒａｐ As can be seen, the total value of the overlap time and the dead time required to achieve ZVS changes in accordance with the change in the current flowing through the inductor L1.

[0149] The total value of the overlap time and dead time required to achieve ZVS can be divided into the time required to demagnetize inductor L2 and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1. The time required to demagnetize inductor L2 can be expressed by the above equation 1, and the time required to discharge the charge accumulated in the parasitic capacitance of switch Q1 can be expressed by the above equation 2 below. The total value of the overlap time and dead time required to achieve ZVS can be expressed by the above equation 3.

[0150] Therefore, by determining the total value of the overlap time and the dead time in the same manner as in the third example of the operation of the power conversion device 2 according to the second embodiment, the total value of the overlap time and the dead time can be brought close to the time required to achieve ZVS in the current circuit state.

[0151] After ZVS is achieved, switch Q3 is turned off, allowing current to flow through switch Q1.

[0152] Furthermore, the control circuit 20 may determine the overlap time and the dead time, respectively, basically in the same manner as in the third example of the operation of the power conversion device 2 according to embodiment 2, or may determine the total value of the overlap time and the dead time by determining the overlap time and the dead time, respectively. Below, differences from the third example of the operation of the power conversion device 2 according to embodiment 2 will be described.

[0153] For example, as shown in FIG. 6, when the node N2 is connected to one terminal t1 of the first input / output terminal pair, the control circuit 20 may determine the overlap time so that the switch Q2 is turned off at or before the timing when the current flowing through the inductor L2 becomes zero.

[0154] When node N2 is connected to one terminal t1 of the first input / output terminal pair, the switch Q3 is turned on, causing commutation from inductor L2 to switch Q3. By determining the overlap time so that the switch Q2 is turned off at or before the timing when current stops flowing through inductor L2 after commutation, it is possible to prevent the current flowing through inductor L2 from increasing more than necessary while suppressing an increase in conduction loss in the anti-parallel diode due to a longer conduction time of the anti-parallel diode of switch Q2.

[0155] (Application Examples) Next, application examples of the power conversion device according to the first or second embodiment will be described with reference to Figs. 9 to 14 .

[0156] FIG. 9 is a diagram illustrating an application example of the power conversion device according to the first or second embodiment.

[0157] For example, the power conversion device according to the first or second embodiment may be a bidirectional chopper that exchanges power between batteries, as shown in FIG. 9 . In the power conversion device shown in FIG. 9 , the switch group 10 is connected to both of the first input / output terminal pair. Specifically, the source of the switch A1 and the drain of the switch A2 in the switch group 10 are connected to one terminal of the first input / output terminal pair (the terminal connected to one end of the inductor L1), and the source of the switch A2 and the source of the switch A4 in the switch group 10 are connected to the other terminal of the first input / output terminal pair (the terminal connected to the other end of the inductor L1). When the power conversion device 1 according to the first embodiment is applied to the circuit shown in FIG. 9 , the switches A1 and A2 become switches Q1 and Q2, and the switches A3 and A4 become switches Q3 and Q4. When the power conversion device 2 according to the second embodiment is applied to the circuit shown in FIG. 9 , the switches A1 and A2 become switches Q3 and Q4, and the switches A3 and A4 become switches Q1 and Q2. The same applies to FIGS. 11 to 14 .

[0158] 10A is a diagram showing an example of the dead time and the overlap time in the application example of FIG. 9 . FIG. 10B is a diagram showing another example of the dead time and the overlap time in the application example of FIG. 9 . In FIG. 10A and FIG. 10B , the voltage v ｃ , current |i Ｌ |, time T ｄ and time T ｏｖｅｒｒａｐ A graph showing the change over time is shown.

[0159] As shown in FIG. 10A, at time T ｄ is variable, T ｏｖｅｒｒａｐ If = 0, the current |i Ｌ The time T required to achieve ZVS depending on the change in | ｄ As shown in FIG. 10B, the time T ｄ is fixed (for example, T ｄ =T ｄｍｉｎ ), time T ｏｖｅｒｒａｐ When is variable, the current |i Ｌ The time T required to achieve ZVS depending on the change in | ｏｖｅｒｒａｐ is determined.

[0160] 11 to 14 are diagrams illustrating application examples of the power conversion device according to embodiment 1 or 2. As illustrated in Fig. 11 to 14, the power conversion device may include a plurality of switch groups 10.

[0161] For example, the power conversion apparatus according to the first or second embodiment may be a grid-connected power conditioning system (PCS) (single-phase full bridge) that converts AC to DC as shown in FIG. 11 . For example, the power conversion apparatus according to the first or second embodiment may be a single-phase full bridge (inductive load) as shown in FIG. 12 . For example, the power conversion apparatus according to the first or second embodiment may be a bidirectional multifunction chopper that exchanges power between batteries as shown in FIG. 13 . For example, the power conversion apparatus according to the first or second embodiment may be a grid-connected three-phase PCS (three-phase full bridge) that converts AC to DC as shown in FIG. 14 .

[0162] (Other Embodiments) As described above, the embodiments have been described as examples of the technology according to the present disclosure. However, the technology according to the present disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. For example, the following modifications are also included in one embodiment of the present disclosure.

[0163] For example, the present disclosure can be realized not only as a power conversion device, but also as a control method including steps (processing) performed by components (for example, the control circuit 20) that make up the power conversion device.

[0164] FIG. 15 is a flowchart showing an example of a control method according to another embodiment.

[0165] The control method is a control method for a power conversion device, the power conversion device including: a first input / output terminal pair; a second input / output terminal pair; a main inductor connected in series between the first input / output terminal pair; and a group of switches connected to at least one terminal of the first input / output terminal pair and both terminals of the second input / output terminal pair, the group of switches having a main switch unit and an auxiliary circuit, the main switch unit being a half-bridge circuit including two main switches connected in series, the auxiliary circuit having an auxiliary switch unit including two auxiliary switches connected in series, and an auxiliary inductor, a high-voltage side terminal of the main switch unit and a high-voltage side terminal of the auxiliary switch unit being connected to each other and to one terminal of the second input / output terminal pair, a low-voltage side terminal of the main switch unit and a low-voltage side terminal of the auxiliary switch unit being connected to each other and to the other terminal of the second input / output terminal pair, the auxiliary inductor being connected between a first intermediate node between the two main switches and a second intermediate node between the two auxiliary switches, One of the first and second intermediate nodes is connected to one terminal of a first input / output terminal pair, and the control method, as shown in FIG. 15 , determines the sum of an overlap time, which is the time during which a first main switch, of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch, of the two auxiliary switches, through which a forward current flows in an on state, are both in an on state, and a dead time, which is the time during which both main switches are in an off state, based on the current flowing through the main inductor (step S11). The first auxiliary switch is turned on before turning off the first main switch or simultaneously with turning off the first main switch (step S12). After the overlap time has elapsed, the first main switch is turned off (step S13). After the dead time has elapsed, the second main switch, of the two main switches, through which a forward current flows in an on state, is turned on (step S14), and then the first auxiliary switch is turned off (step S15).

[0166] For example, the present disclosure can be realized as a program for causing a computer (processor) to execute steps included in the control method. Furthermore, the present disclosure can be realized as a non-transitory computer-readable recording medium, such as a CD-ROM, on which the program is recorded.

[0167] For example, when the present disclosure is realized as a program (software), each step is performed by running the program using hardware resources such as a computer's CPU, memory, input / output circuits, etc. In other words, each step is performed by the CPU acquiring data from memory or input / output circuits, etc., performing calculations, and outputting the calculation results to memory or input / output circuits, etc.

[0168] In the above-described embodiments, each component included in the power conversion device may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0169] Some or all of the functions of the power conversion device according to the above-described embodiments are typically realized as an LSI, which is an integrated circuit. These may be individually integrated into a single chip, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized using a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI, may also be used.

[0170] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derivative technologies, that technology may naturally be used to integrate the components included in the power conversion device.

[0171] In addition, this disclosure also includes forms obtained by making various modifications to the embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.

[0172] (Additional Notes) The above description of the embodiments discloses the following techniques.

[0173] (Technology 1) A power supply comprising: a first input / output terminal pair; a second input / output terminal pair; a main inductor connected in series between the first input / output terminal pair; a group of switches connected to at least one terminal of the first input / output terminal pair and both terminals of the second input / output terminal pair; and a control circuit for controlling the group of switches, wherein the group of switches has a main switch unit and an auxiliary circuit, the main switch unit is a half-bridge circuit including two main switches connected in series, the auxiliary circuit has an auxiliary switch unit including two auxiliary switches connected in series, and an auxiliary inductor, a high-voltage side terminal of the main switch unit and a high-voltage side terminal of the auxiliary switch unit are connected to each other and to one terminal of the second input / output terminal pair, a low-voltage side terminal of the main switch unit and a low-voltage side terminal of the auxiliary switch unit are connected to each other and to the other terminal of the second input / output terminal pair, and the auxiliary inductor is connected between a first intermediate node between the two main switches and a second intermediate node between the two auxiliary switches. and a second intermediate node of a first main switch and a second auxiliary switch, and one of the first intermediate node and the second intermediate node is connected to one terminal of the first input / output terminal pair, and the control circuit determines, based on the current flowing in the main inductor, a total value of an overlap time, which is a time during which a first main switch of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch of the two auxiliary switches, through which a forward current flows in an on state, are both in an on state, and a dead time, which is a time during which the two main switches are both in an off state, and turns on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch, turns off the first main switch after the overlap time has elapsed, turns on a second main switch of the two main switches, through which a forward current flows in an on state, after the dead time has elapsed, and then turns off the first auxiliary switch.

[0174] The sum of the overlap time and the dead time is the time from when the first auxiliary switch is turned on to when the second main switch is turned on, and this time determines whether ZVS can be achieved. The sum of the overlap time and the dead time required to achieve ZVS changes depending on changes in the current flowing through the main inductor as the circuit state changes. Therefore, by determining the sum of the overlap time and the dead time based on the current flowing through the main inductor, the sum of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state. This prevents the sum of the overlap time and the dead time from becoming shorter than the time required to achieve ZVS in the current circuit state, which would result in ZVS not being achieved and an increase in switching loss. Furthermore, it prevents the sum of the overlap time and the dead time from becoming longer than the time required to achieve ZVS in the current circuit state, which would result in an increase in conduction loss due to an increase in the auxiliary switch conduction time. Therefore, high efficiency can be achieved even when the circuit state changes.

[0175] (Technology 2) The power conversion device according to Technology 1, wherein the control circuit determines the total value based on the current flowing through the main inductor, the voltage across the second input / output terminal pair, and the inductance value of the auxiliary inductor.

[0176] The total value of the overlap time and the dead time required to achieve ZVS changes in response to changes in the current flowing through the main inductor, as well as changes in the voltage across the second input / output terminal pair, which are changes in the circuit state, and also changes in response to the inductance value of the auxiliary inductor that constitutes the circuit. Therefore, by determining the total value of the overlap time and the dead time based on the current flowing through the main inductor, the voltage across the second input / output terminal pair, and the inductance value of the auxiliary inductor, the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0177] (Technology 3) The power conversion device according to Technology 1 or 2, wherein the control circuit determines the total value so that it increases as the absolute value of the current flowing through the main inductor increases and decreases as the voltage between the second input / output terminal pair increases.

[0178] The total value of the overlap time and the dead time required to achieve ZVS increases as the absolute value of the current flowing through the main inductor increases, and decreases as the voltage across the second input / output terminal pair increases. Therefore, by determining the total value of the overlap time and the dead time so that it increases as the absolute value of the current flowing through the main inductor increases and decreases as the voltage across the second input / output terminal pair increases, the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0179] (Technique 4) The current flowing through the main inductor is i Ｌ , the voltage between the second input / output terminal pair is V ｃ , the inductance value of the auxiliary inductor is L ｓｕｂ , the parasitic capacitance value of the main switch is C ｏｓｓ When the above formula 3 is satisfied, the control circuit determines the total value to be equal to or greater than the value expressed by the formula 3 above.

[0180] The total value of the overlap time and the dead time required to achieve ZVS increases as the absolute value of the current flowing through the main inductor increases, decreases as the voltage between the second input / output terminal pair increases, increases as the inductance value of the auxiliary inductor increases, and increases as the parasitic capacitance value of the main switch increases. Therefore, by setting the total value of the overlap time and the dead time to a value equal to or greater than the value expressed by Equation 3 above, the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state. Furthermore, by setting the total value of the overlap time and the dead time to the same value as Equation 3 above, the total value of the overlap time and the dead time can be made just enough to achieve ZVS in the current circuit state.

[0181] (Technology 5) The power conversion device according to any one of Technologies 1 to 4, wherein the control circuit determines the overlap time and the dead time.

[0182] In this way, the overlap time and the dead time may be determined separately, thereby determining the total value of the overlap time and the dead time.

[0183] (Technology 6) The power conversion device according to Technology 5, wherein the control circuit sets a lower limit value of the dead time.

[0184] If the dead time is too short, there is a risk that the two main switches will be turned on simultaneously. Therefore, by setting a lower limit for the dead time, the simultaneous turning on of the two main switches can be prevented, and the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0185] (Technology 7) A power conversion device described in Technology 5 or 6, wherein the first intermediate node is connected to one terminal of the first input / output terminal pair, and the control circuit determines the overlap time so as to turn off the first main switch at or before the timing at which the current flowing through the auxiliary inductor coincides with the current flowing through the main inductor.

[0186] When the first intermediate node is connected to one terminal of the first input / output terminal pair, turning on the first auxiliary switch causes commutation from the first main switch to the auxiliary inductor. By determining the overlap time so that the first main switch is turned off at or before the timing at which current stops flowing through the first main switch after commutation, it is possible to prevent an increase in conduction loss in the anti-parallel diode due to a longer conduction time of the anti-parallel diode of the first main switch, and also to prevent an unnecessary increase in the current flowing through the auxiliary inductor.

[0187] (Technology 8) A power conversion device described in Technology 5 or 6, wherein the second intermediate node is connected to one terminal of the first input / output terminal pair, and the control circuit determines the overlap time so as to turn off the first main switch at or before the timing when the current flowing through the auxiliary inductor becomes zero.

[0188] When the second intermediate node is connected to one terminal of the first input / output terminal pair, the first auxiliary switch is turned on, causing commutation from the auxiliary inductor to the first auxiliary switch. By determining the overlap time so that the first main switch is turned off at or before the timing when current stops flowing through the auxiliary inductor after commutation, it is possible to prevent the current flowing through the auxiliary inductor from increasing more than necessary, which would otherwise increase the conduction time of the anti-parallel diode of the first main switch and cause conduction loss in the anti-parallel diode.

[0189] (Technology 9) A power conversion device according to any one of Techniques 5 to 8, wherein the control circuit determines the overlap time so that it increases with an increase in the absolute value of the current flowing through the main inductor and decreases with an increase in the voltage between the second input / output terminal pair.

[0190] The overlap time required to achieve ZVS increases as the absolute value of the current flowing through the main inductor increases, and decreases as the voltage across the second input / output terminal pair increases. Therefore, by determining the overlap time so that it increases as the absolute value of the current flowing through the main inductor increases and decreases as the voltage across the second input / output terminal pair increases, the total value of the overlap time and the dead time can be made closer to the time required to achieve ZVS in the current circuit state.

[0191] (Technology 10) The current flowing through the main inductor is i Ｌ , the voltage between the second input / output terminal pair is V ｃ , the inductance value L of the auxiliary inductor ｓｕｂ When the above formula 1 is set, the control circuit determines the overlap time to be a value within the value represented by the above formula 1.

[0192] When the first intermediate node is connected to one terminal of the first input / output terminal pair, if the overlap time exceeds the value expressed by the above formula 1, the current flowing through the auxiliary inductor increases more than necessary. Also, when the second intermediate node is connected to one terminal of the first input / output terminal pair, if the overlap time exceeds the value expressed by the above formula 1, the polarity of the current flowing through the auxiliary inductor is reversed. Therefore, by setting the overlap time to be equal to or less than the value expressed by the above formula 1, it is possible to prevent the current flowing through the auxiliary inductor from increasing more than necessary or the polarity of the current flowing through the auxiliary inductor from being reversed.

[0193] (Technology 11) The current flowing through the main inductor is i Ｌ , the voltage between the second input / output terminal pair is V ｃ , the inductance value of the auxiliary inductor is L ｓｕｂ , the parasitic capacitance value of the main switch is C ｏｓｓ In this case, the control circuit determines the overlap time to be the value expressed by the above formula 1, and determines the dead time to be the larger value of a lower limit value set for the dead time and the value expressed by the above formula 2.

[0194] The sum of the overlap time and dead time required to achieve ZVS increases as the inductance value of the auxiliary inductor increases and as the parasitic capacitance value of the main switch increases. Therefore, by setting the overlap time to the value expressed by Equation 1 and the dead time to the value expressed by Equation 2, the sum of the overlap time and dead time approaches the time required to achieve ZVS in the current circuit state, while preventing the current flowing through the auxiliary inductor from increasing more than necessary or reversing polarity. However, if the dead time is too short, there is a risk that the two main switches will be turned on simultaneously. Therefore, if the lower limit value set for the dead time is greater than the value expressed by Equation 2, setting the dead time to the lower limit can prevent the two main switches from being turned on simultaneously.

[0195] (Technology 12) The power conversion device according to any one of Techniques 1 to 11, wherein the power conversion device includes a plurality of the switch groups.

[0196] Even in a power conversion device having a plurality of switch groups, high efficiency can be achieved even when the circuit state changes.

[0197] (Technology 13) A control method for a power conversion device, the power conversion device comprising: a first input / output terminal pair; a second input / output terminal pair; a main inductor connected in series between the first input / output terminal pair; and a group of switches connected to at least one terminal of the first input / output terminal pair and both terminals of the second input / output terminal pair, the group of switches having a main switch unit and an auxiliary circuit, the main switch unit being a half-bridge circuit including two main switches connected in series, the auxiliary circuit having an auxiliary switch unit including two auxiliary switches connected in series, and an auxiliary inductor, a high-voltage side terminal of the main switch unit and a high-voltage side terminal of the auxiliary switch unit being connected to each other and to one terminal of the second input / output terminal pair, a low-voltage side terminal of the main switch unit and a low-voltage side terminal of the auxiliary switch unit being connected to each other and to the other terminal of the second input / output terminal pair, the auxiliary inductor connecting a first intermediate node between the two main switches and a second intermediate node between the two auxiliary switches a second intermediate node between the first and second auxiliary switches, and one of the first intermediate node and the second intermediate node is connected to one terminal of the first input / output terminal pair, and the control method determines, based on the current flowing in the main inductor, a total value of an overlap time, which is a time during which a first main switch of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch of the two auxiliary switches, through which a forward current flows in an on state, are both in an on state, and a dead time, which is a time during which the two main switches are both in an off state, and turns on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch, turns off the first main switch after the overlap time has elapsed, turns on a second main switch of the two main switches, through which a forward current flows in an on state, after the dead time has elapsed, and then turns off the first auxiliary switch.

[0198] This provides a control method that can achieve high efficiency even when the circuit state changes.

[0199] The present disclosure can be applied to a power conversion device that converts an input voltage and controls it to a desired output voltage.

[0200] REFERENCE SIGNS LIST 1, 2 Power conversion device 10 Switch group 11 Main switch section 12 Auxiliary circuit 13 Auxiliary switch section 20 Control circuit 21 Voltage command value generation section 22 PWM control section 23 Determination section 100 Voltage source A1, A2, A3, A4, Q1, Q2, Q3, Q4 Switch C1 Capacitor D1, D2 Diode L1, L2 Inductor N1, N2 Node t1, t2, t3, t4 Terminal

Claims

1. A power supply comprising: a first input / output terminal pair; a second input / output terminal pair; a main inductor connected in series between the first input / output terminal pair; a group of switches connected to at least one terminal of the first input / output terminal pair and both terminals of the second input / output terminal pair; and a control circuit for controlling the group of switches, wherein the group of switches has a main switch unit and an auxiliary circuit, wherein the main switch unit is a half-bridge circuit including two main switches connected in series, and the auxiliary circuit has an auxiliary switch unit including two auxiliary switches connected in series, and an auxiliary inductor, wherein a high-voltage side terminal of the main switch unit and a high-voltage side terminal of the auxiliary switch unit are connected to each other and to one terminal of the second input / output terminal pair, and a low-voltage side terminal of the main switch unit and a low-voltage side terminal of the auxiliary switch unit are connected to each other and to the other terminal of the second input / output terminal pair, and the auxiliary inductor is connected between a first intermediate node between the two main switches and a second intermediate node between the two auxiliary switches, one of the first intermediate node and the second intermediate node is connected to one terminal of the first input / output terminal pair, and the control circuit determines, based on the current flowing through the main inductor, a total value of an overlap time, which is a time during which a first main switch of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch of the two auxiliary switches, through which a forward current flows in an on state, are both in an on state, and a dead time, which is a time during which the two main switches are both in an off state, and turns on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch, turns off the first main switch after the overlap time has elapsed, turns on a second main switch of the two main switches, through which a forward current flows in an on state, after the dead time has elapsed, and then turns off the first auxiliary switch.

2. The power conversion device according to claim 1, wherein the control circuit determines the total value based on the current flowing through the main inductor, the voltage across the second input / output terminal pair, and the inductance value of the auxiliary inductor.

3. The power conversion device according to claim 1, wherein the control circuit determines the total value so that it increases as the absolute value of the current flowing through the main inductor increases, and decreases as the voltage across the second input / output terminal pair increases.

4. Let the current flowing through the main inductor be i Ｌ , the voltage between the second input / output terminal pair is V ｃ , the inductance value of the auxiliary inductor is L ｓｕｂ , the parasitic capacitance value of the main switch is C ｏｓｓ When the sum is The power conversion device according to claim 1 , wherein the value is determined to be equal to or greater than the above.

5. The power conversion device according to claim 1, wherein the control circuit determines the overlap time and the dead time, respectively.

6. The power conversion device according to claim 5, wherein the control circuit sets a lower limit value for the dead time.

7. The power conversion device according to claim 5, wherein the first intermediate node is connected to one terminal of the first input / output terminal pair, and the control circuit determines the overlap time so that the first main switch is turned off at or before the timing at which the current flowing through the auxiliary inductor coincides with the current flowing through the main inductor.

8. The power conversion device according to claim 5, wherein the second intermediate node is connected to one terminal of the first input / output terminal pair, and the control circuit determines the overlap time so as to turn off the first main switch at or before the timing at which the current flowing through the auxiliary inductor becomes zero.

9. The power conversion device according to claim 5, wherein the control circuit determines the overlap time so that it increases with an increase in the absolute value of the current flowing through the main inductor and decreases with an increase in the voltage across the second input / output terminal pair.

10. Let the current flowing through the main inductor be i Ｌ , the voltage between the second input / output terminal pair is V ｃ , the inductance value L of the auxiliary inductor ｓｕｂ When the overlap time is The power conversion device according to claim 5 , wherein the value is determined to be within a range of 0.5 to 1.

0.

11. Let the current flowing through the main inductor be i Ｌ , the voltage between the second input / output terminal pair is V ｃ , the inductance value of the auxiliary inductor is L ｓｕｂ , the parasitic capacitance value of the main switch is C ｏｓｓ In this case, the control circuit sets the overlap time as and determining the dead time as a lower limit value set for the dead time. The power conversion device according to claim 5 , wherein the larger value of 12. The power conversion device according to any one of claims 1 to 11, wherein the power conversion device includes a plurality of groups of switches.

13. A control method for a power conversion device, comprising: the power conversion device comprising: a first input / output terminal pair; a second input / output terminal pair; a main inductor connected in series between the first input / output terminal pair; and a group of switches connected to at least one terminal of the first input / output terminal pair and both terminals of the second input / output terminal pair, the group of switches having a main switch unit and an auxiliary circuit, the main switch unit being a half-bridge circuit including two main switches connected in series, the auxiliary circuit having an auxiliary switch unit including two auxiliary switches connected in series, and an auxiliary inductor, the high-voltage side terminal of the main switch unit and the high-voltage side terminal of the auxiliary switch unit being connected to each other and to one terminal of the second input / output terminal pair, the low-voltage side terminal of the main switch unit and the low-voltage side terminal of the auxiliary switch unit being connected to each other and to the other terminal of the second input / output terminal pair, and the auxiliary inductor being connected between a first intermediate node between the two main switches and a second intermediate node between the two auxiliary switches, one of the first intermediate node and the second intermediate node is connected to one terminal of the first input / output terminal pair, and the control method comprises determining, based on the current flowing through the main inductor, a total value of an overlap time, which is a time during which a first main switch of the two main switches, through which a reverse current flows in an on state, and a first auxiliary switch of the two auxiliary switches, through which a forward current flows in an on state, are both on, and a dead time, which is a time during which the two main switches are both off; turning on the first auxiliary switch before turning off the first main switch or at the same time as turning off the first main switch, turning off the first main switch after the overlap time has elapsed, turning on the second main switch of the two main switches, through which a forward current flows in an on state, after the dead time has elapsed, and then turning off the first auxiliary switch.

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