Display panel and electronic device comprising same

Abstract

The present invention provides a display panel comprising a first pixel circuit, a second pixel circuit, and a third pixel circuit which are arranged side by side in a first direction, each of the first pixel circuit, the second pixel circuit, and the third pixel circuit including: a first transistor including a first channel region, a first source region adjacent to the first channel region, and a first gate electrode disposed on the first channel region; a second transistor including a second channel region and a second gate electrode disposed on the second channel region; a first conductive pattern disposed under the first channel region; and a second conductive pattern disposed on the first gate electrode, wherein the first source region is disposed between the first channel region and the second channel region and protrudes from the first conductive pattern and the second conductive pattern in the first direction on a plane, and the first pixel circuit and the second pixel circuit are substantially line-symmetrical with respect to a virtual straight line extending in a second direction intersecting the first direction.

Description

Display panel and electronic device including same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] A display panel may include a plurality of pixels. Each pixel may include a light-emitting diode and a pixel circuit for controlling the brightness of the light-emitting diode, etc. The pixel circuit may include transistors and capacitors connected to wires such as data lines, gate lines, and voltage lines.

[0003] Recently, display panels have become thinner and lighter, making them suitable for use in a variety of electronic devices. As these display panels become more widely used, various types of display panels and electronic devices containing them are being designed.

[0004] The background art is intended to provide a technical background useful for understanding the technology of the present invention, and the background art may include ideas, concepts, etc. that were not known or recognized by those skilled in the art prior to the effective filing date of this specification.

[0005] As display panels become increasingly high-resolution, the distance between data lines and transistors decreases, potentially causing problems where data signals applied to a single pixel affect surrounding pixels. The present invention aims to address these and other issues, and provides a display panel capable of displaying high-quality images and an electronic device including the same. However, these objectives are exemplary and should not be construed as limiting the scope of the present invention.

[0006] Additional tasks, effects and features of the present invention may be presented by the description of the invention or may be understood through the practice of the embodiments.

[0007] According to one aspect of the present invention, a first pixel circuit, a second pixel circuit, and a third pixel circuit are arranged side by side along a first direction on a substrate, and each of the first pixel circuit, the second pixel circuit, and the third pixel circuit comprises: a first transistor including a first channel region, a first source region and a first drain region adjacent to the first channel region, and a first gate electrode arranged on the first channel region; a second transistor including a second channel region and a second gate electrode arranged on the second channel region; a first conductive pattern arranged below the first channel region, and a second conductive pattern arranged on the first gate electrode; and the first source region is arranged between the first channel region and the second channel region, and protrudes in the first direction from the first conductive pattern and the second conductive pattern on a plane, and the first pixel circuit and the second pixel circuit intersect the first direction. A display panel is provided that is substantially line-symmetrical with respect to an imaginary straight line extending in a second direction.

[0008] In one embodiment, the display panel further includes a first data line electrically connected to the first pixel circuit, a second data line electrically connected to the second pixel circuit, and a third data line electrically connected to the third pixel circuit, and a first transistor of the first pixel circuit and a first transistor of the second pixel circuit may be arranged between the first data line and the second data line.

[0009] In one embodiment, the display panel further includes a first pixel electrode electrically connected to the first pixel circuit, a second pixel electrode electrically connected to the second pixel circuit, and a third pixel electrode electrically connected to the third pixel circuit, wherein the first pixel electrode and the second pixel electrode may be disposed between the first data line and the second data line, and the third pixel electrode may be disposed between the second data line and the third data line.

[0010] In one embodiment, the first pixel electrode and the second pixel electrode may be arranged alternately along the second direction.

[0011] In one embodiment, the first data line and the second data line may be spaced apart from the first pixel electrode, the second pixel electrode, and the third pixel electrode on a plane.

[0012] In one embodiment, the display panel may further include a first voltage line arranged to overlap the first transistor of the first pixel circuit and the first transistor of the second pixel circuit, and a second voltage line arranged to overlap the first transistor of the third pixel circuit.

[0013] In one embodiment, the first pixel electrode and the second pixel electrode may overlap the first voltage line, and the third pixel electrode may overlap the second voltage line.

[0014] In one embodiment, the display panel further includes a third voltage line extending in the first direction and electrically connected to the first voltage line and the second voltage line, and the third voltage line can be electrically connected to the first conductive pattern and the second conductive pattern.

[0015] In one embodiment, the display panel may further include an auxiliary voltage line extending in the second direction and positioned between the second data line and the first transistor of the third pixel circuit.

[0016] In one embodiment, the auxiliary voltage line may be substantially symmetrical with the third data line based on an imaginary straight line passing through the center of the third pixel electrode.

[0017] According to another aspect of the present invention, a first pixel circuit, a second pixel circuit, and a third pixel circuit are arranged side by side along a first direction on a substrate, and each of the first pixel circuit, the second pixel circuit, and the third pixel circuit comprises: a first conductive layer disposed on the substrate and including a first conductive pattern; a first semiconductor layer disposed on the first conductive layer and including a first channel region, a second channel region, and a first source region between the first channel region and the second channel region; a second conductive layer disposed on the first semiconductor layer and including a first gate electrode overlapping the first channel region and a second gate electrode overlapping the second channel region; and a third conductive layer disposed on the second conductive layer and including a second conductive pattern overlapping the first gate electrode, wherein the first conductive layer, the second conductive layer, and the third conductive layer expose the first source region in a plane. A display panel is provided in which an aperture area is defined, and the first pixel circuit and the second pixel circuit are substantially line-symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction.

[0018] In one embodiment, the display panel further includes a fourth conductive layer disposed on the third conductive layer, the fourth conductive layer including a first voltage line extending in the first direction and electrically connected to the second conductive pattern, and a fifth conductive layer disposed on the fourth conductive layer, the fifth conductive layer including a first data line electrically connected to the first pixel circuit, a second data line electrically connected to the second pixel circuit, and a third data line electrically connected to the third pixel circuit, wherein a first gate electrode of the first pixel circuit and a first gate electrode of the second pixel circuit may be disposed between the first data line and the second data line.

[0019] In one embodiment, the fifth conductive layer further includes a second voltage line overlapping the first gate electrode of the first pixel circuit and the first gate electrode of the second pixel circuit, and a third voltage line extending in the second direction and overlapping the first gate electrode of the third pixel circuit, wherein the first voltage line can be electrically connected to the second voltage line and the third voltage line.

[0020] In one embodiment, the first voltage line may be electrically connected to the first conductive pattern of the first pixel circuit.

[0021] In one embodiment, the display panel further includes a sixth conductive layer disposed on the fifth conductive layer and including a first pixel electrode electrically connected to the first pixel circuit, a second pixel electrode electrically connected to the second pixel circuit, and a third pixel electrode electrically connected to the third pixel circuit, wherein the first pixel electrode and the second pixel electrode may be disposed between the first data line and the second data line, and the third pixel electrode may be disposed between the second data line and the third data line.

[0022] In one embodiment, the first pixel electrode and the second pixel electrode may be arranged alternately along the second direction.

[0023] In one embodiment, the first data line and the second data line may be spaced apart from the first pixel electrode, the second pixel electrode, and the third pixel electrode on a plane.

[0024] In one embodiment, the fifth conductive layer may further include an auxiliary voltage line extending in the second direction and arranged between the second data line and the first gate electrode of the third pixel circuit.

[0025] In one embodiment, the auxiliary voltage line may be substantially symmetrical with the third data line based on an imaginary straight line passing through the center of the third pixel electrode.

[0026] According to another aspect of the present invention, a display panel is provided, wherein a plurality of pixels are arranged, and the display panel includes a first pixel circuit, a second pixel circuit, and a third pixel circuit arranged side by side in a first direction on a substrate, and each of the first pixel circuit, the second pixel circuit, and the third pixel circuit includes a first transistor including a first channel region, a first source region and a first drain region facing each other with the first channel region interposed therebetween, and a first gate electrode arranged on the first channel region, a second transistor including a second channel region and a second gate electrode arranged on the second channel region, a first conductive pattern arranged below the first channel region, and a second conductive pattern arranged on the first gate electrode, and the first source region is arranged between the first channel region and the second channel region, and protrudes in the first direction from the first conductive pattern and the second conductive pattern on a plane, and An electronic device is provided in which the first pixel circuit and the second pixel circuit are substantially line-symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction.

[0027] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0028] According to one embodiment of the present invention, which is achieved as described above, a display panel capable of displaying high-quality images and an electronic device including the same can be implemented. Of course, the scope of the present invention is not limited by these effects.

[0029] FIG. 1 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0030] FIG. 2 is an equivalent circuit diagram schematically illustrating one pixel included in a display panel according to one embodiment of the present invention.

[0031] FIGS. 3 and 4 are each drawings for explaining a flip structure of a pixel circuit according to one embodiment of the present invention.

[0032] FIG. 5 is a layout diagram schematically illustrating a portion of a display panel according to one embodiment of the present invention.

[0033] Each of FIGS. 6 to 16 is a layout diagram schematically illustrating a portion of the display panel illustrated in FIG. 5 layer by layer.

[0034] FIG. 17 is a layout diagram schematically illustrating a portion of a display panel according to one embodiment of the present invention.

[0035] Fig. 18 is a cross-sectional view schematically illustrating a cross-section along line Ⅰ-Ⅰ' of the display panel illustrated in Fig. 17.

[0036] FIG. 19 is a layout diagram schematically illustrating a portion of a display panel according to one embodiment of the present invention.

[0037] FIG. 20 is a drawing schematically illustrating the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0038] FIG. 21 is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention.

[0039] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0040] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals, and redundant descriptions thereof will be omitted.

[0041] As used herein, “and / or” includes any combination of one or more of the listed items.

[0042] In this specification, “at least one of a, b, or c” refers to a, b, c, ab, ac, bc, and abc.

[0043] In this specification, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0044] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0045] In this specification, terms such as “include” or “have” mean that a feature or component described in the specification exists, and do not preclude the possibility that one or more other features or components may be added.

[0046] In this specification, when it is said that a part such as a film, region, or component is on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

[0047] In this specification, when it is said that a film, region, component, etc. are connected, it includes cases where the film, region, component, etc. are directly connected, and / or cases where other film, region, component, etc. are interposed between the film, region, component, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are connected, it refers to cases where the film, region, component, etc. are directly connected, and / or cases where other film, region, component, etc. are interposed between them and are indirectly electrically connected.

[0048] In this specification, the x-direction, y-direction, and z-direction are not limited to directions along the three axes on the orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0049] In this specification, when we say “planar”, it means when the target portion is viewed from above (e.g., when viewed in a direction perpendicular to the upper surface of the substrate), and when we say “cross-sectional”, it means when the target portion is viewed from the side in a cross-section cut vertically.

[0050] In this specification, when a first component is said to "overlap" a second component, it means that the first component is positioned above or below the second component so that at least a portion of the first component overlaps the second component in a plane.

[0051] In this specification, "ON" used in connection with a device state may refer to an activated state of the device, and "OFF" may refer to a deactivated state of the device. "ON" used in connection with a signal received by a device may refer to a signal that activates the device, and "OFF" may refer to a signal that deactivates the device. A device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-type transistors and N-type transistors are opposite (lower versus higher) voltage levels.

[0052] In some embodiments of this specification, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0053] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0054] FIG. 1 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0055] Referring to FIG. 1, a display panel (1) may include a display area (DA) for displaying an image and a peripheral area (PA) outside the display area (DA). The display panel (1) may provide a predetermined image using light emitted from a plurality of pixels arranged in the display area (DA). In one embodiment, each pixel may emit red, green, or blue light. In another embodiment, each pixel may emit red, green, blue, or white light.

[0056] On a plane, the display area (DA) may have a rectangular shape. In other embodiments, the display area (DA) may have another polygonal shape, a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have a shape with rounded corners at the edges.

[0057] In one embodiment, the display panel (1) may have a display area (DA) whose length in the first direction (x direction) is shorter than its length in the second direction (y direction). In another embodiment, the display panel (1) may have a display area (DA) whose length in the first direction (x direction) is longer than its length in the second direction (y direction).

[0058] The peripheral area (PA) is an area arranged around the display area (DA). The peripheral area (PA) may surround at least a portion of the display area (DA) or may be adjacent to the display area (DA). In one embodiment, the peripheral area (PA) may be a type of non-display area where no pixels are arranged. Various wires, circuits, and pads to which printed circuit boards or driver IC chips are attached that transmit electrical signals to be applied to the display area (DA) may be located in the peripheral area (PA).

[0059] Hereinafter, an organic light-emitting display panel including an organic light-emitting diode will be described as an example of a display panel (1) according to one embodiment of the present invention, but the display panel of the present invention is not limited thereto. In another embodiment, the display panel (1) of the present invention may include an inorganic light-emitting diode or a quantum dot light-emitting diode.

[0060] FIG. 2 is an equivalent circuit diagram of one pixel included in a display panel according to one embodiment of the present invention.

[0061] Referring to FIG. 2, the pixel circuit (PC) may include first to eighth transistors (T1 to T8) and a storage capacitor (Cst). Depending on the type of transistor (P-type or N-type) and / or operating conditions, the first terminal of each of the first to eighth transistors (T1 to T8) may be a source or a drain, and the second terminal may be a terminal different from the first terminal. For example, when the first terminal is a source, the second terminal may be a drain. The first transistor (T1) may be a driving transistor whose size of a source-drain current is determined according to a gate-source voltage (Vgs), and each of the second to eighth transistors (T2 to T8) may be a switching transistor that transmits a signal.

[0062] The pixel circuit (PC) can be connected to a first gate line (GWL) for transmitting a first gate signal (GW), a second gate line (GCL) for transmitting a second gate signal (GC), a third gate line (GIL) for transmitting a third gate signal (GI), a fourth gate line (GBL) for transmitting a fourth gate signal (GB), an emission control line (EML) for transmitting an emission control signal (EM), a data line (DL) for transmitting a data signal (Dm), a driving voltage line (PL) for transmitting a driving voltage (ELVDD), a first initialization voltage line (VL1) for transmitting a first initialization voltage (VINT), a second initialization voltage line (VL2) for transmitting a second initialization voltage (VAINT), and a bias voltage line (VL3) for transmitting a bias voltage (VOBS).

[0063] The first transistor (T1) may include a gate connected to a second node (N2), a first terminal connected to the first node (N1), and a second terminal connected to a third node (N3). The first transistor (T1) receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current (Id) to the light-emitting element.

[0064] The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on in response to a first gate signal (GW) received through the first gate line (GWL) and may perform a switching operation to transmit a data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0065] The third transistor (T3) may include a gate connected to the second gate line (GCL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The third transistor (T3) may be turned on according to a second gate signal (GC) received through the second gate line (GCL), thereby diode-connecting the first transistor (T1).

[0066] The fourth transistor (T4) may include a gate connected to a third gate line (GIL), a first terminal connected to a first initialization voltage line (VL1), and a second terminal connected to a second node (N2). The fourth transistor (T4) may be turned on according to a third gate signal (GI) received through the third gate line (GIL), and may transmit a first initialization voltage (VINT) to the gate of the first transistor (T1) to initialize the gate voltage of the first transistor (T1).

[0067] The fifth transistor (T5) may include a gate connected to an emission control line (EML), a first terminal connected to a driving voltage line (PL), and a second terminal connected to a first node (N1). The sixth transistor (T6) may include a gate connected to the emission control line (EML), a first terminal connected to a third node (N3), and a second terminal connected to a pixel electrode of an organic light-emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) may be simultaneously turned on by an emission control signal (EM) received through the emission control line (EML), so that a driving current (Id) may flow to the organic light-emitting diode (OLED).

[0068] The seventh transistor (T7) may include a gate connected to the fourth gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and the pixel electrode of the organic light-emitting diode (OLED), and a second terminal connected to the second initialization voltage line (VL2). The seventh transistor (T7) may be turned on by the fourth gate signal (GB) received through the fourth gate line (GBL) and may transmit the second initialization voltage (VAINT) from the second initialization voltage line (VL2) to the pixel electrode of the organic light-emitting diode (OLED), thereby initializing the pixel electrode of the organic light-emitting diode (OLED).

[0069] The eighth transistor (T8) may include a gate connected to a fourth gate line (GBL), a first terminal connected to a first node (N1), and a second terminal connected to a bias voltage line (VL3). The eighth transistor (T8) may be turned on by a fourth gate signal (GB) transmitted through the fourth gate line (GBL), and may transmit a bias voltage (VOBS) from the bias voltage line (VL3) to the first node (N1).

[0070] The storage capacitor (Cst) may include a first capacitor electrode (CE1) connected to a second node (N2) and a second capacitor electrode (CE2) connected to a driving voltage line (PL).

[0071] An organic light-emitting diode (OLED) includes a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode) facing the pixel electrode, and the common electrode can receive a common voltage (ELVSS). The organic light-emitting diode (OLED) can display an image by receiving a driving current (Id) from a first transistor (T1) and emitting light with a predetermined color.

[0072] Some of the first to eighth transistors (T1 to T8) may be P-channel transistors, and the remaining some may be N-channel transistors. In one embodiment, the first transistor (T1), the second transistor (T2), and the fifth to eighth transistors (T5 to T8) may be P-channel transistors, and the third transistor (T3) and the fourth transistor (T4) may be N-channel transistors. In other embodiments, the first to eighth transistors (T1 to T8) may all be N-channel transistors, or all may be P-channel transistors.

[0073] Although FIG. 2 illustrates that the pixel circuit (PC) includes first to eighth transistors (T1 to T8) and a storage capacitor (Cst), the present invention is not limited thereto. Some of the transistors and capacitors may be omitted or added. For example, the pixel circuit (PC) may be designed in various ways, such as including two transistors and one capacitor, four transistors and one capacitor, or seven transistors and one capacitor.

[0074] FIGS. 3 and 4 are each drawings for explaining a flip structure of a pixel circuit according to one embodiment of the present invention.

[0075] Referring to FIGS. 3 and 4, pixel circuits (PCs) can be arranged (or placed) in an m×n matrix in a first direction (x direction) and a second direction (y direction). Here, m and n can be natural numbers greater than or equal to 1. Pixel circuits (PCs) arranged along the first direction (x direction) form a pixel circuit row, and pixel circuits (PCs) arranged along the second direction (y direction) form a pixel circuit column. Although FIGS. 3 and 4 illustrate a pixel circuit (PC) matrix forming a 3×6 matrix for convenience of explanation, this is merely exemplary, and the display panel (1, see FIG. 1) may include a larger number of pixel circuits (PCs).

[0076] The display panel (1) may include a plurality of data lines (DL, see FIG. 2). The data lines (DL) may be arranged in each pixel circuit column. Pixel circuits (PC) arranged in the same pixel circuit column may be connected to the same data line. For example, pixel circuits (PC11, PC21, PC31) arranged in the first pixel circuit column (n1) are connected to the first data line (DL1), pixel circuits (PC12, PC22, PC32) arranged in the second pixel circuit column (n2) are connected to the second data line (DL2), pixel circuits (PC13, PC23, PC33) arranged in the third pixel circuit column (n3) are connected to the third data line (DL3), pixel circuits (PC14, PC24, PC34) arranged in the fourth pixel circuit column (n4) are connected to the fourth data line (DL4), pixel circuits (PC15, PC25, PC35) arranged in the fifth pixel circuit column (n5) are connected to the fifth data line (DL5), and pixel circuits (PC15, PC25, PC35) arranged in the sixth pixel circuit column (n6) are connected to the fifth data line (DL5). Pixel circuits (PC16, PC26, PC36) can be connected to the sixth data line (DL6).

[0077] Pixel circuits (PC) connected to the same data line may be pixel circuits of pixels (P, see Fig. 2) that emit light of the same color. For example, each of the pixel circuits (PC11, PC14, PC21, PC24, PC31, PC34) connected to the first data line (DL1) and the fourth data line (DL4) may be connected to an organic light-emitting diode (OLED, see FIG. 2) that emits red light, each of the pixel circuits (PC12, PC15, PC22, PC25, PC32, PC35) connected to the second data line (DL2) and the fifth data line (DL5) may be connected to an organic light-emitting diode (OLED) that emits green light, and each of the pixel circuits (PC13, PC16, PC23, PC26, PC33, PC36) connected to the third data line (DL3) and the sixth data line (DL6) may be connected to an organic light-emitting diode (OLED) that emits blue light.

[0078] Pixel circuits (PCs) arranged in the same pixel circuit row can be connected to the same gate lines. The gate lines can transmit gate signals to the pixel circuits (PCs) connected to each other.

[0079] In one embodiment, as illustrated in FIG. 3, pixel circuits (PC11, PC21, PC31) arranged in a first pixel circuit column (n1) among three pixel circuit columns (n1, n2, n3) and pixel circuits (PC12, PC22, PC32) arranged in a second pixel circuit column (n2) may have a flipped structure. Here, the fact that one pixel circuit has a flipped structure with respect to another pixel circuit means that the two pixel circuits are approximately (or substantially) line-symmetrical with respect to an imaginary straight line that passes through the boundary of the two pixel circuits and extends in the second direction (y direction). In two pixel circuits that are substantially line-symmetrical, most of the corresponding components (e.g., conductive patterns and semiconductor patterns constituting transistors and capacitors) are arranged to be line-symmetrical along the imaginary straight line, but some components may be different in size, area, shape, or offset compared to the corresponding components. Accordingly, the first data line (DL1) can be connected to the pixel circuits (PC11, PC21, PC31) on the left side (-x direction) of the pixel circuits (PC11, PC21, PC31) arranged in the first pixel circuit column (n1), and the second data line (DL2) can be connected to the pixel circuits (PC12, PC22, PC32) on the right side (+x direction) of the pixel circuits (PC12, PC22, PC32) arranged in the second pixel circuit column (n2). The third data line (DL3) can be connected to the pixel circuits (PC13, PC23, PC33) on the right side (+x direction) of the pixel circuits (PC13, PC23, PC33) arranged in the third pixel circuit column (n3).

[0080] Pixel circuits (PC) and data lines (DL) may be repeatedly arranged in units of three pixel circuit columns. For example, pixel circuits (PC14, PC24, PC34) arranged in the fourth pixel circuit column (n4) and pixel circuits (PC15, PC25, PC35) arranged in the fifth pixel circuit column (n5) may have a flipped structure. The fourth data line (DL4) may be connected to the pixel circuits (PC14, PC24, PC34) on the left side (-x direction) of the pixel circuits (PC14, PC24, PC34) arranged in the fourth pixel circuit column (n4), and the fifth data line (DL5) may be connected to the pixel circuits (PC15, PC25, PC35) on the right side (+x direction) of the pixel circuits (PC15, PC25, PC35) arranged in the fifth pixel circuit column (n5). The sixth data line (DL6) can be connected to the pixel circuits (PC16, PC26, PC36) on the right side (+x direction) of the pixel circuits (PC16, PC26, PC36) arranged in the sixth pixel circuit column (n6).

[0081] In one embodiment, as illustrated in FIG. 4, pixel circuits arranged in odd pixel circuit columns may have a flipped structure with respect to pixel circuits arranged in adjacent even pixel circuit columns. For example, pixel circuits (PC11, PC21, PC31) arranged in the first pixel circuit column (n1) may have a flipped structure with respect to pixel circuits (PC12, PC22, PC32) arranged in the second pixel circuit column (n2), pixel circuits (PC13, PC23, PC33) arranged in the third pixel circuit column (n3) may have a flipped structure with respect to pixel circuits (PC14, PC24, PC34) arranged in the fourth pixel circuit column (n4), and pixel circuits (PC15, PC25, PC35) arranged in the fifth pixel circuit column (n5) may have a flipped structure with respect to pixel circuits (PC16, PC26, PC36) arranged in the sixth pixel circuit column (n6).

[0082] In one embodiment, as illustrated in FIG. 4, each of the odd-numbered data lines (DL1, DL3, DL5) may be arranged on the left side (-x direction) of the pixel circuit column to which it is connected, and each of the even-numbered data lines (DL2, DL4, DL6) may be arranged on the right side (+x direction) of the pixel circuit column to which it is connected. In another embodiment, each of the odd-numbered data lines (DL1, DL3, DL5) may be arranged on the right side (+x direction) of the pixel circuit column to which it is connected, and each of the even-numbered data lines (DL2, DL4, DL6) may be arranged on the left side (-x direction) of the pixel circuit column to which it is connected.

[0083] FIG. 5 is a layout diagram schematically illustrating a portion of a display panel according to one embodiment of the present invention, and FIGS. 6 to 16 are each layout diagrams schematically illustrating a portion of the display panel illustrated in FIG. 5 layer by layer.

[0084] Referring to FIG. 5, the display panel (1) may include a plurality of circuit areas (PCA1, PCA2, PCA3) and a wiring area (WA), which are areas in which pixel circuits (PC1, PC2, PC3) are arranged. The first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) may be arranged side by side along the first direction (x direction). That is, the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be pixel circuits arranged in the same pixel circuit row.

[0085] Each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include first to eighth transistors (T1, T2, ... T8) and a storage capacitor (Cst). Each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may further include conductive patterns for connecting the first to eighth transistors (T1, T2, ... T8) and the storage capacitor (Cst) to gate lines, voltage lines, data lines, and pixel electrodes.

[0086] Unless otherwise specified, each of the first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may include substantially identical or similar components. For convenience of explanation in this specification, the components of the first pixel circuit (PC1) are described, but the remaining pixel circuits (PC2, PC3) may also be understood to include corresponding components.

[0087] The first pixel circuit (PC1) and the second pixel circuit (PC2) may have a flipped structure. For example, the first pixel circuit (PC1) and the second pixel circuit (PC2) may be approximately line-symmetrical with respect to an imaginary straight line extending in the second direction (y direction) along the boundary between the first pixel circuit (PC1) and the second pixel circuit (PC2). For example, in the first pixel circuit (PC1), the second transistor (T2) may be arranged to the left (-x direction) with respect to the first transistor (T1), and in the second pixel circuit (PC2), the second transistor (T2) may be arranged to the right (+x direction) with respect to the first transistor (T1). Components of the third pixel circuit (PC3) may be arranged at positions approximately the same as or similar to components of the second pixel circuit (PC2).

[0088] The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may be connected to gate lines and voltage lines extending in a first direction (x direction). The gate lines may include a first gate line (GWL), a second gate line (GCL), a third gate line (GIL), a fourth gate line (GBL), and an emission control line (EML). The voltage lines extending in the first direction (x direction) may include a first initialization voltage line (VL1), a second initialization voltage line (VL2), a bias voltage line (VL3), and a horizontal driving voltage line (PLa). The second initialization voltage line (VL2) may include a second-first initialization voltage line (VL2a) and a second-second initialization voltage line (VL2b). The 2-1 initialization voltage line (VL2a) can be connected to the 1st pixel circuit (PC1), and the 2-2 initialization voltage line (VL2b) can be connected to the 2nd pixel circuit (PC2) and the 3rd pixel circuit (PC3).

[0089] The first pixel circuit (PC1) may be connected to a first data line (DL1) extending in the second direction (y direction), the second pixel circuit (PC2) may be connected to a second data line (DL2) extending in the second direction (y direction), and the third pixel circuit (PC3) may be connected to a third data line (DL3) extending in the second direction (y direction).

[0090] The first pixel circuit (PC1) and the second pixel circuit (PC2) can be connected to a first driving voltage line (PL1) extending in the second direction (y direction). The third pixel circuit (PC3) can be connected to a second driving voltage line (PL2) extending in the second direction (y direction).

[0091] A wiring area (WA) may be arranged between the second circuit area (PCA2) and the third circuit area (PCA3). An auxiliary voltage line (VLa) extending in the second direction (y direction) may be arranged in the wiring area (WA). The auxiliary voltage line (VLa) may be connected to any one of the voltage lines extending in the first direction (x direction), for example, the first initialization voltage line (VL1), the second initialization voltage line (VL2), and the bias voltage line (VL3). In this regard, FIGS. 5 to 16 illustrate that the auxiliary voltage line (VLa) is connected to the second-first initialization voltage line (VL2a). The auxiliary voltage line (VLa) may be connected to any one of the voltage lines extending in the first direction (x direction) to form a mesh structure in the display area (DA, see FIG. 1). Such a mesh structure prevents voltage drops in the constant voltages such as the first initialization voltage (VINT, see Fig. 2), the second initialization voltage (VAINT, see Fig. 2), and the bias voltage (VOBS, see Fig. 2), so that the display panel (1) can display high-quality images.

[0092] The unit areas including the first circuit area (PCA1), the second circuit area (PCA2), the wiring area (WA), and the third circuit area (PCA3) can be repeatedly arranged in the first direction (x direction) and the second direction (y direction).

[0093] A first conductive layer (1100) may be disposed on the substrate. The first conductive layer (1100) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or single layer including the above materials.

[0094] Referring to FIG. 6, the first conductive layer (1100) may include a first conductive pattern (1110). The first conductive pattern (1110) may include first body parts (1111), first horizontal connecting parts (1112) connecting the first body parts (1111) adjacent in the first direction (x direction), and first vertical connecting parts (1113) connecting the first body parts (1111) adjacent in the second direction (y direction). The first body part (1111) may overlap the first channel region (A1) of the first semiconductor layer (1200) on a plane to prevent the first transistor (T1) from being deteriorated by external light.

[0095] A first semiconductor layer (1200) may be disposed on a first conductive layer (1100). The first semiconductor layer (1200) may include a silicon-based semiconductor material, such as amorphous silicon or polycrystalline silicon. Referring to FIG. 7, the first semiconductor layer (1200) may include a first semiconductor pattern (1210). For convenience of explanation, the first semiconductor pattern (1210) arranged in the first circuit area (PCA1) may be referred to as the 1-1 semiconductor pattern (1210a), the first semiconductor pattern (1210) arranged in the second circuit area (PCA2) may be referred to as the 1-2 semiconductor pattern (1210b), and the first semiconductor pattern (1210) arranged in the third circuit area (PCA3) may be referred to as the 1-3 semiconductor pattern (1210c).

[0096] The second conductive layer (1300) may be disposed on the first semiconductor layer (1200). The first semiconductor layer (1200) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or single layer including the above materials. Referring to FIG. 8, the second conductive layer (1300) may include a second conductive pattern (1310), a third conductive pattern (1320), a fourth conductive pattern (1330), a fifth conductive pattern (1340), a fourth gate line (GBL), and a second-second initialization voltage line (VL2b).

[0097] The second conductive pattern (1310), the third conductive pattern (1320), the fourth conductive pattern (1330), and the fifth conductive pattern (1340) may have an isolated shape (island type) on a plane. The fourth gate line (GBL) and the second-second initialization voltage line (VL2b) may extend approximately in the first direction (x direction) and pass through the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The fourth gate line (GBL) may transmit a fourth gate signal (GB, see FIG. 5) to pixel circuits (PC1, PC2, PC3) arranged in the same pixel circuit row.

[0098] In one embodiment, the second initialization voltage (VAINT, see FIG. 2) may be different for each pixel. For example, the second-first initialization voltage may be transmitted to the first pixel circuit (PC1), and the second-second initialization voltage may be transmitted to the second pixel circuit (PC2) and the third pixel circuit (PC3). The second-first initialization voltage and the second-second initialization voltage may be different voltages. The second-second initialization voltage line (VL2b) may transmit the second-first initialization voltage to the second pixel circuit (PC2) and the third pixel circuit (PC3).

[0099] For convenience of explanation, FIG. 9 illustrates the first semiconductor layer (1200) and the second conductive layer (1300) overlapping each other. Referring to FIG. 9, each of the first-first semiconductor pattern (1210a), the first-second semiconductor pattern (1210b), and the first-third semiconductor pattern (1210c) may include a first channel region (A1) of the first transistor (T1), a second channel region (A2) of the second transistor (T2), a fifth channel region (A5) of the fifth transistor (T5), a sixth channel region (A6) of the sixth transistor (T6), a seventh channel region (A7) of the seventh transistor (T7), and an eighth channel region (A8) of the eighth transistor (T8). A source region and a drain region may be arranged on both sides of each of the channel regions (A1, A2, A5, A6, A7, A8). The 1-1 semiconductor pattern (1210a) may be provided integrally with the first semiconductor pattern located on the left side (-x direction) of the first circuit region (PCA1). The 1-3 semiconductor pattern (1210c) may be provided integrally with the first semiconductor pattern located on the right side (+x direction) of the third pixel circuit (PC3). The 1-2 semiconductor pattern (1210b) may be spaced apart from the neighboring first semiconductor patterns (1210).

[0100] The first channel region (A1) of the first transistor (T1) may overlap with the second conductive pattern (1310). In one embodiment, the first channel region (A1) of the 1-1 semiconductor pattern (1210a) and the first channel region (A1) of the 1-2 semiconductor pattern (1210b) may have a curved shape, and the first channel region (A1) of the 1-3 semiconductor pattern (1210c) may have a straight shape. The second conductive pattern (1310) may be the first gate electrode (G1) of the first transistor (T1). A source region (S1) and a drain region (D1) may be arranged on both sides of the first channel region (A1) of the first transistor (T1).

[0101] The second channel region (A2) of the second transistor (T2) may overlap with the third conductive pattern (1320). The third conductive pattern (1320) may be the second gate electrode (G2) of the second transistor (T2). The source region (S1) of the first transistor (T1) may be arranged between the first channel region (A1) of the first transistor (T1) and the second channel region (A2) of the second transistor (T2). In a plane, the source region (S1) of the first transistor (T1) may protrude in the first direction (x direction) from the first conductive pattern (1110) and the fourth conductive pattern (1330).

[0102] The fifth channel region (A5) of the fifth transistor (T5) may overlap with the fourth conductive pattern (1330). The fourth conductive pattern (1330) may be the fifth gate electrode (G5) of the fifth transistor (T5). The sixth channel region (A6) of the sixth transistor (T6) may overlap with the fifth conductive pattern (1340). The fifth conductive pattern (1340) may be the sixth gate electrode (G6) of the sixth transistor (T6). The fourth conductive pattern (1330) of the second pixel circuit (PC2) may be provided integrally with the fifth conductive pattern (1340) of the third pixel circuit (PC3).

[0103] The seventh channel region (A7) of the seventh transistor (T7) and the eighth channel region (A8) of the eighth transistor (T8) may overlap with the fourth gate line (GBL). A portion of the fourth gate line (GBL) overlapping with the seventh channel region (A7) may be the seventh gate electrode (G7) of the seventh transistor (T7), and a portion of the fourth gate line (GBL) overlapping with the eighth channel region (A8) may be the eighth gate electrode (G8) of the eighth transistor (T8).

[0104] Referring to FIG. 10, a third conductive layer (1400) may be disposed on a second conductive layer (1300). The third conductive layer (1400) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or single layer including the above materials. The third conductive layer (1400) may include a sixth conductive pattern (1410), a seventh conductive pattern (1420), and an eighth conductive pattern (1430). The seventh conductive pattern (1420) and the eighth conductive pattern (1430) may have an isolated shape on a plane.

[0105] The sixth challenge pattern (1410) may include second body parts (1411), second horizontal connecting parts (1412) connecting neighboring second body parts (1411) in the first direction (x direction), and shielding parts (1413) protruding in the second direction (y direction) from the second horizontal connecting parts (1412).

[0106] The second body portion (1411) may overlap the second conductive pattern (1310) on a plane to form a storage capacitor (Cst). For example, the second conductive pattern (1310) may function as a first capacitor electrode (CE1, see FIG. 2) of the storage capacitor (Cst), and the second body portion (1411) of the sixth conductive pattern (1410) may function as a second capacitor electrode (CE2, see FIG. 2) of the storage capacitor (Cst). The second body portion (1411) may define a first hole (1410h) that exposes a portion of the second conductive pattern (1310).

[0107] The shielding portions (1413) may be arranged to overlap the first data line (DL1), the second data line (DL2), and the third data line (DL3) of the sixth conductive layer (1800) on a plane. The shielding portions (1413) may be arranged between the first data line (DL1) and the first-first semiconductor pattern (1210a), between the second data line (DL2) and the first-second semiconductor pattern (1210b), and between the third data line (DL3) and the first-third semiconductor pattern (1210c), thereby reducing parasitic capacitance between the data line (DL) and the first semiconductor pattern (1210) overlapping therewith.

[0108] Referring to FIG. 11, the second semiconductor layer (1500) may be disposed on the third conductive layer (1400). It may include an oxide of at least one material selected from the group consisting of oxide-based semiconductor materials, for example, indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In one embodiment, the second semiconductor layer (1500) may be IGZO (In-Ga-Zn-O) or ITGZO (In-Sn-Ga-Zn-O). The second semiconductor layer (1500) may include second semiconductor patterns (1510). The second semiconductor pattern (1510) arranged in the first circuit area (PCA1) may be referred to as a second-first semiconductor pattern (1510a), the second semiconductor pattern (1510) arranged in the second circuit area (PCA2) may be referred to as a second-second semiconductor pattern (1510b), and the second semiconductor pattern (1510) arranged in the third circuit area (PCA3) may be referred to as a second-third semiconductor pattern (1510c).

[0109] Referring to FIG. 12, a fourth conductive layer (1600) may be disposed on a second semiconductor layer (1500). The fourth conductive layer (1600) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or single layer including the above materials. The fourth conductive layer (1600) may include a ninth conductive pattern (1610), a tenth conductive pattern (1620), and a second-first initialization voltage line (VL2a). The ninth conductive pattern (1610) and the tenth conductive pattern (1620) may have an isolated shape on a plane. The 2-1 initialization voltage line (VL2a) can extend in the first direction (x direction) and pass through the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The 2-1 initialization voltage line (VL2a) can transmit the 2-1 initialization voltage to the first pixel circuit (PC1).

[0110] For convenience of explanation, Fig. 13 illustrates the third conductive layer (1400), the second semiconductor layer (1500), and the fourth conductive layer (1600) as overlapping each other. Referring to Fig. 13, each of the second-first semiconductor pattern (1510a), the second-second semiconductor pattern (1510b), and the second-third semiconductor pattern (1510c) may include a third channel region (A3) of the third transistor (T3) and a fourth channel region (A4) of the fourth transistor (T4). A source region and a drain region may be arranged on both sides of each of the channel regions (A3, A4).

[0111] The third channel region (A3) of the third transistor (T3) may overlap with the seventh conductive pattern (1420) and the ninth conductive pattern (1610). The seventh conductive pattern (1420) may be the lower gate electrode of the third transistor (T3), and the ninth conductive pattern (1610) may be the upper gate electrode (G3) of the third transistor (T3).

[0112] The fourth channel region (A4) of the fourth transistor (T4) may overlap with the eighth conductive pattern (1430) and the tenth conductive pattern (1620). The eighth conductive pattern (1430) may be the lower gate electrode of the fourth transistor (T4), and the tenth conductive pattern (1620) may be the upper gate electrode (G4) of the fourth transistor (T4).

[0113] Referring to FIGS. 14 and 15 together, the fifth conductive layer (1700) may be disposed on the fourth conductive layer (1600), and the sixth conductive layer (1800) may be disposed on the fifth conductive layer (1700). Each of the fifth conductive layer (1700) and the sixth conductive layer (1800) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and may be a multilayer or single layer including the above materials. In one embodiment, the fifth conductive layer (1700) and the sixth conductive layer (1800) may each have a multilayer structure of Ti / Al / Ti.

[0114] The fifth conductive layer (1700) may include an eleventh conductive pattern (1710), a twelfth conductive pattern (1720), a thirteenth conductive pattern (1730), a fourteenth conductive pattern (1740), a fifteenth conductive pattern (1750), a sixteenth conductive pattern (1760), a first gate line (GWL), a second gate line (GCL), a third gate line (GIL), an emission control line (EML), a first initialization voltage line (VL1), a bias voltage line (VL3), and a horizontal driving voltage line (PLa). The sixth conductive layer (1800) may include a seventeenth conductive pattern (1810), a first data line (DL1), a second data line (DL2), a third data line (DL3), a first driving voltage line (PL1), a second driving voltage line (PL2), and an auxiliary voltage line (VLa).

[0115] The 11th challenge pattern (1710), the 12th challenge pattern (1720), the 13th challenge pattern (1730), the 14th challenge pattern (1740), the 15th challenge pattern (1750), the 16th challenge pattern (1760), and the 17th challenge pattern (1810) may have an isolated shape on a plane.

[0116] The 11th conductive pattern (1710) may be a connection electrode connecting the data line (DL, see FIG. 2) and the source region (S2) of the second transistor (T2). The 11th conductive pattern (1710) of the first pixel circuit (PC1) may be connected to the 1-1 semiconductor pattern (1210a) through the third contact hole (CP3) and to the first data line (DL1) through the fourteenth contact hole (CP14). The 11th conductive pattern (1710) of the second pixel circuit (PC2) may be connected to the 1-2 semiconductor pattern (1210b) through the third contact hole (CP3) and to the second data line (DL2) through the fourteenth contact hole (CP14). The 11th conductive pattern (1710) of the 3rd pixel circuit (PC3) can be connected to the 1st-3rd semiconductor pattern (1210c) through the 3rd contact hole (CP3) and to the 3rd data line (DL3) through the 14th contact hole (CP14).

[0117] The 12th conductive pattern (1720) may be a connection electrode connecting the first gate electrode (G1) of the first transistor (T1), the source region (S3) of the third transistor (T3), and the drain region (D4) of the fourth transistor (T4). The 12th conductive pattern (1720) may be connected to the second semiconductor pattern (1510) through the 5-1 contact hole (CP5a), and may be connected to the second conductive pattern (1310) through the first hole (1410h) and the 5-2 contact hole (CP5b).

[0118] The 13th conductive pattern (1730) may be a connecting electrode connecting the drain region (D1) of the first transistor (T1) and the drain region (D3) of the third transistor (T3). The 13th conductive pattern (1730) may be connected to the second semiconductor pattern (1510) through the 6-1 contact hole (CP6a) and to the first semiconductor pattern (1210) through the 6-2 contact hole (CP6b).

[0119] The 14th conductive pattern (1740) and the 17th conductive pattern (1810) may be connection electrodes connecting the drain region (D6) of the 6th transistor (T6), the drain region (D7) of the 7th transistor (T7), and the pixel electrode (210). For convenience of explanation, the 17th conductive pattern (1810) disposed in the first circuit region (PCA1) may be referred to as the 17-1st conductive pattern (1810a), the 17th conductive pattern (1810) disposed in the second circuit region (PCA2) may be referred to as the 17-2nd conductive pattern (1810b), and the 17th conductive pattern (1810) disposed in the third circuit region (PCA3) may be referred to as the 17-3rd conductive pattern (1810c).

[0120] The 14th conductive pattern (1740) of the 1st pixel circuit (PC1) may be connected to the 1-1st semiconductor pattern (1210a) through the 9th contact hole (CP9) and to the 17-1st conductive pattern (1810a) through the 16th contact hole (CP16). The 14th conductive pattern (1740) of the 2nd pixel circuit (PC2) may be connected to the 1-2nd semiconductor pattern (1210b) through the 9th contact hole (CP9) and to the 17-2nd conductive pattern (1810b) through the 16th contact hole (CP16). The 14th conductive pattern (1740) of the 3rd pixel circuit (PC3) may be connected to the 1-3rd semiconductor pattern (1210c) through the 9th contact hole (CP9) and to the 17-3rd conductive pattern (1810c) through the 16th contact hole (CP16). The 17-1st conductive pattern (1810a) may be connected to the 1st pixel electrode (210a) through the 18th contact hole (CP18), the 17-2nd conductive pattern (1810b) may be connected to the 2nd pixel electrode (210b) through the 18th contact hole (CP18), and the 17-3rd conductive pattern (1810c) may be connected to the 3rd pixel electrode (210c) through the 18th contact hole (CP18).

[0121] The 15th conductive pattern (1750) may be a connecting electrode connecting the source region (S7) of the 7th transistor (T7) to the 2-1st initialization voltage line (VL2a) or the 2-2nd initialization voltage line (VL2b). The 15th conductive pattern (1750) of the 1st pixel circuit (PC1) may be connected to the 1-1st semiconductor pattern (1210a) through the 11-1st contact hole (CP11a) and to the 2-1st initialization voltage line (VL2a) through the 11-2nd contact hole (CP11b). The 15th conductive pattern (1750) of the 2nd pixel circuit (PC2) can be connected to the 1st-2nd semiconductor pattern (1210b) through the 11-1st contact hole (CP11a) and to the 2nd-2nd initialization voltage line (VL2b) through the 11-2nd contact hole (CP11b). The 15th conductive pattern (1750) of the 3rd pixel circuit (PC3) can be connected to the 1st-3rd semiconductor pattern (1210c) through the 11-1st contact hole (CP11a) and to the 2nd-2nd initialization voltage line (VL2b) through the 11-2nd contact hole (CP11b).

[0122] The 16th conductive pattern (1760) is arranged in the wiring area (WA) and may be a connecting electrode that connects the auxiliary voltage line (VLa) to any one of the first initialization voltage line (VL1), the second initialization voltage line (VL2), and the bias voltage line (VL3). Referring to Fig. 14, the 16th conductive pattern (1760) may be connected to the 2-1 initialization voltage line (VL2a) through the 13th contact hole (CP13) and to the auxiliary voltage line (VLa) through the 17th contact hole (CP17).

[0123] The first gate line (GWL), the second gate line (GCL), the third gate line (GIL), the emission control line (EML), the first initialization voltage line (VL1), the bias voltage line (VL3), and the horizontal driving voltage line (PLa) can be arranged to extend in the first direction (x direction) and pass through the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0124] The first gate line (GWL) can be connected to the third conductive pattern (1320) through the fourth contact hole (CP4). The first gate line (GWL) can transmit a first gate signal (GW, see FIG. 2) to the second gate electrode (G2) of the second transistor (T2).

[0125] The second gate line (GCL) can be connected to the ninth conductive pattern (1610) through the second-first contact hole (CP2a) and to the seventh conductive pattern (1420) through the second-second contact hole (CP2b). The second gate line (GCL) can transmit a second gate signal (GC, see FIG. 2) to the upper gate electrode (G3) and the lower gate electrode of the third transistor (T3).

[0126] The third gate line (GIL) can be connected to the tenth conductive pattern (1620) through the first-first contact hole (CP1a) and to the eighth conductive pattern (1430) through the first-second contact hole (CP1b). The third gate line (GIL) can transmit a third gate signal (GI, see FIG. 2) to the upper gate electrode (G4) and the lower gate electrode of the fourth transistor (T4).

[0127] The emission control line (EML) can be connected to the fourth conductive pattern (1330) through the 8-1 contact hole (CP8a) and to the fifth conductive pattern (1340) through the 8-2 contact hole (CP8b). The emission control line (EML) can transmit an emission control signal (EM, see FIG. 2) to the fifth gate electrode (G5) of the fifth transistor (T5) and the sixth gate electrode (G6) of the sixth transistor (T6).

[0128] The first initialization voltage line (VL1) can be connected to the second semiconductor pattern (1510) through the 12th contact hole (CP12). The first initialization voltage line (VL1) can transmit the first initialization voltage (VINT, see FIG. 2) to the source region (S4) of the fourth transistor (T4).

[0129] The bias voltage line (VL3) can be connected to the first semiconductor pattern (1210) through the tenth contact hole (CP10). The bias voltage line (VL3) can transmit a bias voltage (VOBS, see FIG. 2) to the source region (S8) of the eighth transistor (T8).

[0130] The horizontal driving voltage line (PLa) may be connected to the first semiconductor pattern (1210) through the 7-1 contact hole (CP7a), to the first conductive pattern (1110) through the 7-2 contact hole (CP7b), and to the sixth conductive pattern (1410) through the 7-3 contact hole (CP7c). The 7-1 contact hole (CP7a) may be arranged in the first circuit area (PCA1), and the 7-2 contact holes (CP7b) may be arranged at the boundary between the first circuit area (PCA1) and the second circuit area (PCA2), and at the boundary between the second circuit area (PCA2) and the third circuit area (PCA3).

[0131] The horizontal driving voltage line (PLa) may be connected to the first driving voltage line (PL1) through the fifteenth contact hole (CP15) arranged between the first circuit area (PCA1) and the second circuit area (PCA2), and may be connected to the second driving voltage line (PL2) through the fifteenth contact hole (CP15) arranged in the third circuit area (PCA3). The horizontal driving voltage line (PLa) may be connected to the first driving voltage line (PL1) and the second driving voltage line (PL2) to form a mesh structure in the display area (DA, see FIG. 1). The horizontal driving voltage line (PLa) may transmit a driving voltage (ELVDD, see FIG. 2) to the second capacitor electrode (CE2) of the storage capacitor (Cst) and the source area (S5) of the fifth transistor (T5).

[0132] Each of the first data line (DL1), the second data line (DL2), and the third data line (DL3) may extend in the second direction (y direction). The first data line (DL1) may be arranged on the left side (-x direction) of the first pixel circuit (PC1), and the second data line (DL2) may be arranged on the right side (+x direction) of the second pixel circuit (PC2). The third data line (DL3) may be arranged on the right side (+x direction) of the third pixel circuit (PC3).

[0133] A first transistor (T1) of a first pixel circuit (PC1) and a first transistor (T1) of a second pixel circuit (PC2) may be arranged between a first data line (DL1) and a second data line (DL2). A third transistor (T3) of a third pixel circuit (PC3) may be arranged between a second data line (DL2) and a third data line (DL3).

[0134] Each of the first driving voltage line (PL1) and the second driving voltage line (PL2) may extend in the second direction (y direction). The first driving voltage line (PL1) may be arranged between the first data line (DL1) and the second data line (DL2), and the second driving voltage line (PL2) may be arranged between the second data line (DL2) and the third data line (DL3).

[0135] The first driving voltage line (PL1) overlaps the first transistor (T1) of the first pixel circuit (PC1) and the first transistor (T1) of the second pixel circuit (PC2), so as to shield the first transistor (T1) of the first pixel circuit (PC1) and the first transistor (T1) of the second pixel circuit (PC2) from the electrical influence of the components located above the first driving voltage line (PL1). The first driving voltage line (PL1) may overlap the 13th conductive pattern (1730) of the first pixel circuit (PC1) and the 13th conductive pattern (1730) of the second pixel circuit (PC2). Since the first pixel circuit (PC1) and the second pixel circuit (PC2) share one first driving voltage line (PL1), the total area of ​​the pixel circuit can be reduced.

[0136] The second driving voltage line (PL2) overlaps with the first transistor (T1) of the third pixel circuit (PC3), so that the first transistor (T1) of the third pixel circuit (PC3) can be shielded from the electrical influence of components located above the second driving voltage line (PL2).

[0137] An auxiliary voltage line (VLa) may be arranged between the second data line (DL2) and the second driving voltage line (PL2). The auxiliary voltage line (VLa) may be symmetrical with the third data line (DL3) based on an imaginary straight line passing through the center of the third pixel electrode (210c). Accordingly, the third organic light-emitting diode including the third pixel electrode (210c) may have the same luminance when viewed from the left (-x direction) and the right (+x direction).

[0138] The auxiliary voltage line (VLa) may be arranged between the second data line (DL2) and the first transistor (T1) of the third pixel circuit (PC3). The 13th conductive pattern (1730) of the first pixel circuit (PC1) and the 13th conductive pattern (1730) of the second pixel circuit (PC2) may be arranged close to the boundary between the first circuit area (PCA1) and the second circuit area (PCA2), so as to be sufficiently spaced apart from the first data line (DL1) and the second data line (DL2) in the first direction (x direction). On the other hand, the 13th conductive pattern (1730) of the third pixel circuit (PC3) may be arranged relatively adjacent to the second data line (DL2). The auxiliary voltage line (VLa) is arranged between the 13th conductive pattern (1730) of the third pixel circuit (PC3) and the second data line (DL2), so as to reduce the parasitic capacitance between the 13th conductive pattern (1730) and the second data line (DL2).

[0139] Referring to FIG. 16, the seventh conductive layer (1900) may be disposed on the sixth conductive layer (1800). The seventh conductive layer (1900) may include a first pixel electrode (210a), a second pixel electrode (210b), and a third pixel electrode (210c). The first pixel electrode (210a), the second pixel electrode (210b), and the third pixel electrode (210c) may be disposed in a stripe arrangement. For example, the first pixel electrode (210a) and the second pixel electrode (210b) may be disposed to be spaced apart from each other in the second direction (y direction), and the third pixel electrode (210c) may be disposed to be spaced apart from the first pixel electrode (210a) and the second pixel electrode (210b) in the first direction (x direction). A first light-emitting area (EA1) that emits red light may be defined in the first pixel electrode (210a), a second light-emitting area (EA2) that emits green light may be defined in the second pixel electrode (210b), and a third light-emitting area (EA3) that emits blue light may be defined in the third pixel electrode (210c). The first pixel electrode (210a), the second pixel electrode (210b), and the third pixel electrode (210c) may have an approximately rectangular shape on a plane. However, the present invention is not limited thereto. Each of the first pixel electrode (210a), the second pixel electrode (210b), and the third pixel electrode (210c) may be a pentile. TM It can be arranged in various forms such as an array, a mosaic array, etc., and can have various shapes such as different polygonal shapes, circles, and ovals on a plane.

[0140] Fig. 17 is a layout diagram schematically illustrating a portion of a display panel according to one embodiment of the present invention. Fig. 18 is a cross-sectional view schematically illustrating a cross-section along line Ⅰ-Ⅰ' of the display panel illustrated in Fig. 17.

[0141] Referring to FIGS. 17 and 18 together, the display panel (1, see FIG. 1) may include a substrate (100). The substrate (100) may include glass, metal, or a polymer resin. The substrate (100) may have flexible or bendable characteristics. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one embodiment, the substrate (100) may have a multilayer structure including two layers comprising a polymer resin and a barrier layer comprising an inorganic material (such as silicon nitride, silicon oxide, or silicon oxynitride) interposed between the layers, and various modifications are possible.

[0142] A first pixel circuit (PC1), a second pixel circuit (PC2), and a third pixel circuit (PC3) may be arranged on a substrate (100). The first pixel circuit (PC1) and the second pixel circuit (PC2) may be symmetrical with respect to an imaginary straight line extending in the second direction (y direction) along the boundary between the first circuit area (PCA1) and the second circuit area (PCA2). Hereinafter, corresponding components that form symmetrical lines will be described based on the first pixel circuit (PC1).

[0143] A first conductive layer (1100, see FIG. 6) may be disposed on a substrate (100). The first conductive layer (1100) may include a first conductive pattern (1110, see FIG. 6). A first body portion (1111) of the first conductive pattern (1110) may overlap a first channel region (A1, see FIG. 7) of a first transistor (T1).

[0144] A first insulating layer (101) may be disposed on a first conductive layer (1100), and a first semiconductor layer (1200, see FIG. 7) may be disposed on the first insulating layer (101). The first semiconductor layer (1200) may include a first semiconductor pattern (1210). The first semiconductor pattern (1210) may include a first channel region (A1) of a first transistor (T1) and a second channel region (A2) of a second transistor (T2). The source region (S1) of the first transistor (T1) may be disposed between the first channel region (A1) of the first transistor (T1) and the second channel region (A2) of the second transistor (T2). The drain region (D1) of the first transistor (T1) can be arranged to face the source region (S1) of the first transistor (T1) with the first channel region (A1) interposed therebetween.

[0145] A second insulating layer (103) may be disposed on a first semiconductor layer (1200), and a second conductive layer (1300, see FIG. 8) may be disposed on the second insulating layer (103). The second conductive layer (1300) may include a second conductive pattern (1310) and a third conductive pattern (1320). The second conductive pattern (1310) may be disposed to overlap with the first body portion (1111) and the first channel region (A1) of the first transistor (T1). The second conductive pattern (1310) may be a first gate electrode (G1, see FIG. 9) of the first transistor (T1). The third conductive pattern (1320) may be disposed to overlap with the second channel region (A2) of the second transistor (T2). The third challenge pattern (1320) may be a second gate electrode (G2, see FIG. 9) of the second transistor (T2).

[0146] A third insulating layer (105) may be disposed on a second conductive layer (1300), and a third conductive layer (1400, see FIG. 10) may be disposed on the third insulating layer (105). The third conductive layer (1400) may include a sixth conductive pattern (1410, see FIG. 10). The sixth conductive pattern (1410) may include a second body portion (1411), a second horizontal connecting portion (1412, see FIG. 10) connecting neighboring second body portions (1411) in the first direction (x direction), and a shielding portion (1413).

[0147] The second body portion (1411) may overlap with the second conductive pattern (1310) to form a storage capacitor (Cst). For example, the second conductive pattern (1310) may be a first capacitor electrode (CE1) of the storage capacitor (Cst), and the second body portion (1411) may be a second capacitor electrode (CE2) of the storage capacitor (Cst). The second body portion (1411) may define a first hole (1410h) that overlaps with the second conductive pattern (1310) on a plane.

[0148] As illustrated in FIG. 17, the source region (S1) of the first transistor (T1) on a plane may protrude in the first direction (x direction) from the first body portion (1111) of the first conductive pattern (1110), the second body portion (1411) of the second conductive pattern (1310), and the sixth conductive pattern (1410). In other words, the first conductive pattern, the second conductive pattern (1310), and the sixth conductive pattern (1410) may define an opening area (OA) that exposes the source region (S1) of the first transistor (T1) so as not to overlap with the source region (S1) of the first transistor (T1).

[0149] The shielding portions (1413) may extend in the second direction (y direction) to overlap the first data line (DL1), the second data line (DL2), and the third data line (DL3) on a plane. The shielding portions (1413) may shield a portion of the first semiconductor pattern (1210) (e.g., a drain region of the second transistor (T2)) to reduce parasitic capacitance between the first data line (DL1), the second data line (DL2), and the third data line (DL3) and the first semiconductor pattern (1210).

[0150] A fourth insulating layer (106), a fifth insulating layer (107), and a sixth insulating layer (108) may be sequentially stacked on a third conductive layer (1400). Although not shown in FIG. 18, a second semiconductor layer (1500, see FIG. 11) may be disposed between the fourth insulating layer (106) and the fifth insulating layer (107), and a fourth conductive layer (1600, see FIG. 12) may be disposed between the fifth insulating layer (107) and the sixth insulating layer (108).

[0151] A fifth conductive layer (1700, see FIG. 14) may be disposed on the sixth insulating layer (108). The fifth conductive layer (1700) may include an eleventh conductive pattern (1710), a twelfth conductive pattern (1720), and a first gate line (GWL). The eleventh conductive pattern (1710) may be connected to the first semiconductor pattern (1210) through a third contact hole (CP3). The 11th conductive pattern (1710) of the first circuit area (PCA1) may connect the first data line (DL1) and the second transistor (T2) of the first pixel circuit (PC1), the 11th conductive pattern (1710) of the second circuit area (PCA2) may connect the second data line (DL2) and the second transistor (T2) of the second pixel circuit (PC2), and the 11th conductive pattern (1710) of the third circuit area (PCA3) may connect the third data line (DL3) and the third transistor (T3) of the third pixel circuit (PC3). The 12th conductive pattern (1720) may be connected to the second conductive pattern (1310) through the first hole (1410h) and the 5-2 contact hole (CP5b).

[0152] A seventh insulating layer (109) may be disposed on a fifth conductive layer (1700), and a sixth conductive layer (1800, see FIG. 15) may be disposed on the seventh insulating layer (109). The sixth conductive layer (1800) may include a first data line (DL1), a second data line (DL2), a third data line (DL3), a first driving voltage line (PL1), a second driving voltage line (PL2), and an auxiliary voltage line (VLa).

[0153] A first transistor (T1) of a first pixel circuit (PC1) and a first transistor (T1) of a second pixel circuit (PC2) may be arranged between a first data line (DL1) and a second data line (DL2). A third transistor (T3) of a third pixel circuit (PC3) may be arranged between a second data line (DL2) and a third data line (DL3).

[0154] As illustrated in FIG. 17, the first driving voltage line (PL1) may be arranged to overlap the first transistor (T1) of the first pixel circuit (PC1) and the first transistor (T1) of the second pixel circuit (PC2). Since the first pixel circuit (PC1) and the second pixel circuit (PC2) share one first driving voltage line (PL1), the total area of ​​the pixel circuit can be reduced. The second driving voltage line (PL2) may be arranged to overlap the first transistor (T1) of the third pixel circuit (PC3).

[0155] An auxiliary voltage line (VLa) may be arranged between the second data line (DL2) and the second driving voltage line (PL2). The auxiliary voltage line (VLa) may be arranged between the second data line (DL2) and the first transistor (T1) of the third pixel circuit (PC3). The auxiliary voltage line (VLa) may reduce or prevent a change in the luminance of an organic light-emitting diode connected to the third pixel circuit (PC3) due to a data signal applied to the second data line (DL2).

[0156] An eighth insulating layer (111) may be disposed on a sixth conductive layer (1800), and a second organic light-emitting diode (OLED2) may be disposed on the eighth insulating layer (111). The second organic light-emitting diode (OLED2) may include a second pixel electrode (210b), a light-emitting layer (220), and a counter electrode (230). The second organic light-emitting diode (OLED2) may be connected to a second pixel circuit (PC2). The first organic light-emitting diode connected to the first pixel circuit (PC1) and the third organic light-emitting diode connected to the third pixel circuit (PC3) may have a structure similar to that of the second organic light-emitting diode (OLED2). Hereinafter, the second organic light-emitting diode (OLED2) will be described.

[0157] The second pixel electrode (210b) may be a (semi)transparent electrode or a reflective electrode. In one embodiment, the second pixel electrode (210b) may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In one embodiment, the second pixel electrode (210b) may be formed of ITO / Ag / ITO.

[0158] A bank layer (BNK) may be arranged on the eighth insulating layer (111) to cover the edge of the second pixel electrode (210b). The bank layer (BNK) may define a pixel opening (OP) that exposes the center of the second pixel electrode (210b). A second light-emitting area (EA2) of the second organic light-emitting diode (OLED2) may be defined by the pixel opening (OP) of the bank layer (BNK).

[0159] The bank layer (BNK) can prevent arcs or the like from occurring at the edge of the second pixel electrode (210b) by increasing the distance between the edge of the second pixel electrode (210b) and the counter electrode (230). The bank layer (BNK) can include one or more organic materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

[0160] The light-emitting layer (220) may be disposed on the second pixel electrode (210b). The light-emitting layer (220) may include a polymer or low-molecular organic material that emits light of a predetermined color. The light-emitting layer (220) may further include a metal-containing compound such as an organometallic compound, an inorganic material such as a quantum dot, etc. In one embodiment, the light-emitting layer (220) may be patterned to correspond to the second pixel electrode (210b).

[0161] A first functional layer may be disposed between the light-emitting layer (220) and the second pixel electrode (210b), and a second functional layer may be disposed between the light-emitting layer (220) and the counter electrode (230). The first functional layer may be a hole transport layer. Alternatively, the first functional layer may include a hole injection layer and a hole transport layer. The second functional layer may include an electron transport layer and / or an electron injection layer. The first functional layer and the second functional layer may be formed integrally to correspond to a plurality of organic light-emitting diodes. The first functional layer or the second functional layer may be omitted.

[0162] In one embodiment, the second organic light-emitting diode (OLED2) may be a tandem light-emitting element including two or more light-emitting units and a charge generation layer. The second organic light-emitting diode (OLED2) may have a stacked structure of multiple light-emitting units, thereby improving color purity and light-emitting efficiency.

[0163] The counter electrode (230) may be disposed on the light-emitting layer (220). The counter electrode (230) may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), indium tin oxide (ITO), indium zinc oxide (IZO), or any combination thereof. The counter electrode (230) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The counter electrode (230) may be integrally formed to correspond to a plurality of organic light-emitting diodes.

[0164] The first to sixth conductive layers (1100, 1300, 1400, 1600, 1700, 1800) and the second semiconductor layer (1500) described with reference to FIGS. 6 to 15 may not overlap the aperture areas (OA). Accordingly, the source area (S1) of the first transistor (T1) is exposed to the internal light reflected from the lower portion of the counter electrode (230), and the threshold voltage and the driving range (DR range) of the first transistor (T1) may transition. Accordingly, when a white gradation block pattern and a black gradation block pattern are simultaneously displayed for a certain period of time and then a gray gradation is displayed over the entire display area (DA, see FIG. 2), the afterimage phenomenon in which a difference in brightness occurs between the area where the white gradation block pattern was displayed and the area where the black gradation block pattern was displayed can be reduced. Therefore, the display panel (1) can display high-quality images.

[0165] FIG. 19 is a layout diagram schematically illustrating a portion of a display panel according to one embodiment of the present invention, and FIG. 20 is a diagram schematically explaining the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0166] Referring to FIG. 19, the display panel (1) may include a first pixel electrode (210a) connected to a first pixel circuit (PC1), a second pixel electrode (210b) connected to a second pixel circuit (PC2), and a third pixel electrode (210c) connected to a third pixel circuit (PC3). The first pixel electrode (210a) may define a first light-emitting area (EA1), the second pixel electrode (210b) may define a second light-emitting area (EA2), and the third pixel electrode (210c) may define a third light-emitting area (EA3).

[0167] A first data line (DL1) may be connected to a first pixel circuit (PC1), a second data line (DL2) may be connected to a second pixel circuit (PC2), and a third data line (DL3) may be connected to a third pixel circuit (PC3). The first data line (DL1) may be arranged on the left side (-x direction) of the first pixel circuit (PC1), the second data line (DL2) may be arranged on the right side (+x direction) of the second pixel circuit (PC2), and the third data line (DL3) may be arranged on the right side (+x direction) of the third pixel circuit (PC3). A first transistor (T1) (or a first gate electrode of the first transistor) of a first pixel circuit (PC1) and a first transistor (T1) of a second pixel circuit (PC2) may be arranged between a first data line (DL1) and a second data line (DL2). A first transistor (T1) of a third pixel circuit (PC3) may be arranged between a second data line (DL2) and a third data line (DL3). The first pixel circuit (PC1) and the second pixel circuit (PC2) may be symmetrical with respect to an imaginary straight line extending in the second direction (y direction) along a boundary between the first circuit area (PCA1) and the second circuit area (PCA2).

[0168] The first driving voltage line (PL1) may be arranged between the first data line (DL1) and the second data line (DL2), and the second driving voltage line (PL2) may be arranged between the second data line (DL2) and the third data line (DL3). The first driving voltage line (PL1) may overlap the first transistor (T1) (or the gate electrode of the first transistor) of the first pixel circuit (PC1) and the first transistor (T1) of the second pixel circuit (PC2). The second driving voltage line (PL2) may overlap the first transistor (T1) of the third pixel circuit (PC3).

[0169] The first pixel electrode (210a) and the second pixel electrode (210b) may be arranged between the first data line (DL1) and the second data line (DL2), and the third pixel electrode (210c) may be arranged between the second data line (DL2) and the third data line (DL3). The first pixel electrode (210a) and the second pixel electrode (210b) may overlap the first driving voltage line (PL1) in a plane, and the third pixel electrode (210c) may overlap the second pixel circuit (PC2) in a plane. The first pixel electrode (210a) and the second pixel electrode (210b) may be arranged alternately along the second direction (y direction).

[0170] On a plane, the first data line (DL1) and the second data line (DL2) may be arranged to be spaced apart from the first pixel electrode (210a), the second pixel electrode (210b), and the third pixel electrode (210c). On a plane, the third pixel electrode (210c) may be arranged to be spaced apart from the second data line (DL2) and may partially overlap with the third data line (DL3). The first data line (DL1) and the second data line (DL2) may not overlap with the first pixel electrode (210a), the second pixel electrode (210b), and the third pixel electrode (210c). The third data line (DL3) may partially overlap with the third pixel electrode (210c), but the remaining portion may be arranged on the outside of the third pixel electrode (210c) on a plane.

[0171] According to embodiments of the present invention, by minimizing the overlapping area between pixel electrodes (210a, 210b, 210c) and adjacent data lines (DL1, DL2, DL3), the parasitic capacitance between pixel electrodes (210a, 210b, 210c) and adjacent data lines (DL1, DL2, DL3) can be minimized. Accordingly, it is possible to prevent or reduce a change in the luminance of an adjacent organic light-emitting diode (OLED, see FIG. 2) due to a data signal (Dm, see FIG. 2) applied to the data lines (DL1, DL2, DL3).

[0172] Fig. 20 is a drawing for explaining a stripe arrangement, and the pixel (P) illustrated in Fig. 20 may represent a light-emitting region of an organic light-emitting diode included in the pixel. Referring to Fig. 20, the pixels (P) may be arranged to form an mХL matrix in a first direction (x direction) and a second direction (y direction). Here, m and L may be natural numbers greater than or equal to 1. The pixels (P) arranged along the first direction (x direction) form a pixel row, and the pixels (P) arranged along the second direction (y direction) form a pixel column.

[0173] Each of the pixels (P) may include a pixel circuit (PC) and an organic light-emitting diode (OLED, see FIG. 2). In one embodiment, the pixels (P) may include red pixels (Pr), green pixels (Pg), and blue pixels (Pb).

[0174] Pixel circuits (PCs) can be arranged in an m×n matrix in a first direction (x direction) and a second direction (y direction). Here, m and n can be natural numbers greater than or equal to 1. Pixel circuits (PCs) arranged along the first direction (x direction) form a pixel circuit row, and pixel circuits (PCs) arranged along the second direction (y direction) form a pixel circuit column.

[0175] For convenience of explanation, Fig. 20 illustrates a pixel (P) matrix forming a 3×4 matrix and a pixel circuit (PC) matrix forming a 3Х6 matrix, but this is merely an example and the display panel may include a larger number of pixels.

[0176] Data lines (DL) may be arranged in each pixel circuit column. Pixel circuits (PC) arranged in the same pixel circuit column may be connected to the same data line. Pixel circuits (PC) connected to the same data line may be pixel circuits (PC) of pixels (P) that emit light of the same color. Each of the pixel circuits (PC11, PC14, PC21, PC24, PC31, PC34) connected to the first data line (DL1) and the fourth data line (DL4) can form a red pixel (Pr), each of the pixel circuits (PC12, PC15, PC22, PC25, PC32, PC35) connected to the second data line (DL2) and the fifth data line (DL5) can form a green pixel (Pg), and each of the pixel circuits (PC13, PC16, PC23, PC26, PC33, PC36) connected to the third data line (DL3) and the sixth data line (DL6) can form a blue pixel (Pb).

[0177] The pixel circuits (PC11, PC21, PC31) arranged in the first pixel circuit column (n1) and the pixel circuits (PC12, PC22, PC32) arranged in the second pixel circuit column (n2) may have a flipped structure. The pixel circuits (PC14, PC24, PC34) arranged in the fourth pixel circuit column (n4) and the pixel circuits (PC15, PC25, PC35) arranged in the fifth pixel circuit column (n5) may have a flipped structure.

[0178] The first data line (DL1) may be arranged on the left side (-x direction) of the pixel circuits (PC11, PC21, PC31) arranged in the first pixel circuit column (n1), and the second data line (DL2) may be arranged on the right side (+x direction) of the pixel circuits (PC12, PC22, PC32) arranged in the second pixel circuit column (n2). The third data line (DL3) may be arranged on the right side (+x direction) of the pixel circuits (PC13, PC23, PC33) arranged in the third pixel circuit column (n3). The fourth data line (DL4) may be arranged on the left side (-x direction) of the pixel circuits (PC14, PC24, PC34) arranged in the fourth pixel circuit column (n4), and the fifth data line (DL5) may be arranged on the right side (+x direction) of the pixel circuits (PC15, PC25, PC35) arranged in the fifth pixel circuit column (n5). The sixth data line (DL6) may be arranged on the right side (+x direction) of the pixel circuits (PC16, PC26, PC36) arranged in the sixth pixel circuit column (n6).

[0179] In odd-numbered pixel columns (L1, L3), red pixels (Pr) and green pixels (Pg) may be arranged alternately in the second direction (y direction). In even-numbered pixel columns (L2, L4), blue pixels (Pb) may be arranged repeatedly in the second direction (y direction). Red pixels (Pr) and green pixels (Pg) arranged in the first pixel column (L1) may be arranged between the first data line (DL1) and the second data line (DL2), blue pixels (Pb) arranged in the second pixel column (L2) may be arranged between the second data line (DL2) and the third data line (DL3), red pixels (Pr) and green pixels (Pg) arranged in the third pixel column (L3) may be arranged between the fourth data line (DL4) and the fifth data line (DL5), and blue pixels (Pb) arranged in the fourth pixel column (L4) may be arranged between the fifth data line (DL5) and the sixth data line (DL6).

[0180] The pixels (P) are arranged between the data lines (DL1, DL2, ... DL6), so that the pixel electrodes and the data lines (DL1, DL2, ... DL6) do not overlap, or the overlapping area can be minimized. Accordingly, the display panel (1) according to the embodiments of the present invention can display high-quality images by preventing or reducing the luminance of the pixels (P) from changing due to the data signal applied to the adjacent data lines (DL1, DL2, ... DL6).

[0181] FIG. 21 is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention.

[0182] Referring to FIG. 21, a display panel (1) is provided in an electronic device (2) to display moving images or still images or to input and output data. For example, the display panel (1) may be accommodated in a housing (3) of the electronic device (2). The housing (3) may be configured to protect components of the electronic device (2) and to secure the display panel (1).

[0183] Although FIG. 21 illustrates that the electronic device (2) is a mobile phone, the present invention is not limited thereto. The electronic device (2) may be a portable electronic device such as a laptop, a tablet personal computer (PC), a mobile phone, a smart phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc.

[0184] Alternatively, the electronic device (2) may be an electronic device for a television, a monitor, a billboard, an Internet of Things (IOT), or a wearable electronic device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the electronic device (2) according to one embodiment may be an electronic device for a display placed on the back of a front seat, such as an instrument panel of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, or an entertainment device for the rear seats of a vehicle.

[0185] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and equivalent alternative embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. Includes a first pixel circuit, a second pixel circuit, and a third pixel circuit arranged side by side along a first direction on a substrate; Each of the first pixel circuit, the second pixel circuit and the third pixel circuit, A first transistor including a first channel region, a first source region adjacent to the first channel region, and a first gate electrode disposed on the first channel region; A second transistor including a second channel region and a second gate electrode disposed on the second channel region; A first conductive pattern disposed below the first channel region; and A second conductive pattern disposed on the first gate electrode; The first source region is disposed between the first channel region and the second channel region, and protrudes in the first direction from the first conductive pattern and the second conductive pattern on a plane, A display panel in which the first pixel circuit and the second pixel circuit are substantially line-symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction.

2. In paragraph 1, A first data line electrically connected to the first pixel circuit; A second data line electrically connected to the second pixel circuit; and Further comprising a third data line electrically connected to the third pixel circuit; A display panel, in which a first transistor of the first pixel circuit and a first transistor of the second pixel circuit are arranged between the first data line and the second data line.

3. In paragraph 2, A first pixel electrode electrically connected to the first pixel circuit; a second pixel electrode electrically connected to the second pixel circuit; and Further comprising a third pixel electrode electrically connected to the third pixel circuit; A display panel, wherein the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line, and the third pixel electrode is disposed between the second data line and the third data line.

4. In paragraph 3, A display panel in which the first pixel electrode and the second pixel electrode are alternately arranged along the second direction.

5. In paragraph 3, A display panel, wherein the first data line and the second data line are spaced apart from the first pixel electrode, the second pixel electrode, and the third pixel electrode on a plane.

6. In paragraph 3, A first voltage line arranged to overlap the first transistor of the first pixel circuit and the first transistor of the second pixel circuit; and A display panel including a second voltage line arranged to overlap with the first transistor of the third pixel circuit.

7. In paragraph 6, The first pixel electrode and the second pixel electrode overlap with the first voltage line, A display panel in which the third pixel electrode overlaps the second voltage line.

8. In paragraph 6, Further comprising a third voltage line extending in the first direction and electrically connected to the first voltage line and the second voltage line, A display panel in which the third voltage line is electrically connected to the first conductive pattern and the second conductive pattern.

9. In paragraph 3, A display panel further comprising an auxiliary voltage line extending in the second direction and arranged between the second data line and the first transistor of the third pixel circuit.

10. In paragraph 9, A display panel in which the auxiliary voltage line is substantially symmetrical with the third data line based on an imaginary straight line passing through the center of the third pixel electrode.

11. Includes a first pixel circuit, a second pixel circuit, and a third pixel circuit arranged side by side along a first direction on a substrate; Each of the first pixel circuit, the second pixel circuit and the third pixel circuit, A first conductive layer disposed on a substrate and including a first conductive pattern; A first semiconductor layer disposed on the first conductive layer and including a first channel region, a second channel region, and a first source region between the first channel region and the second channel region; A second conductive layer disposed on the first semiconductor layer and including a first gate electrode overlapping the first channel region and a second gate electrode overlapping the second channel region; and A third conductive layer including a second conductive pattern disposed on the second conductive layer and overlapping the first gate electrode; The first conductive layer, the second conductive layer, and the third conductive layer define an opening region that exposes the first source region on a plane, A display panel in which the first pixel circuit and the second pixel circuit are substantially line-symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction.

12. In paragraph 11, A fourth conductive layer disposed on the third conductive layer, including a first voltage line extending in the first direction and electrically connected to the second conductive pattern; and Further comprising a fifth conductive layer, which is disposed on the fourth conductive layer and includes a first data line electrically connected to the first pixel circuit, a second data line electrically connected to the second pixel circuit, and a third data line electrically connected to the third pixel circuit; A display panel, wherein a first gate electrode of the first pixel circuit and a first gate electrode of the second pixel circuit are arranged between the first data line and the second data line.

13. In paragraph 12, The fifth conductive layer further includes a second voltage line overlapping the first gate electrode of the first pixel circuit and the first gate electrode of the second pixel circuit, and a third voltage line extending in the second direction and overlapping the first gate electrode of the third pixel circuit. A display panel, wherein the first voltage line is electrically connected to the second voltage line and the third voltage line.

14. In paragraph 12, A display panel, wherein the first voltage line is electrically connected to the first conductive pattern of the first pixel circuit.

15. In paragraph 12, A sixth conductive layer is further included, which is disposed on the fifth conductive layer and includes a first pixel electrode electrically connected to the first pixel circuit, a second pixel electrode electrically connected to the second pixel circuit, and a third pixel electrode electrically connected to the third pixel circuit; A display panel, wherein the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line, and the third pixel electrode is disposed between the second data line and the third data line.

16. In paragraph 15, A display panel in which the first pixel electrode and the second pixel electrode are alternately arranged along the second direction.

17. In paragraph 15, A display panel, wherein the first data line and the second data line are spaced apart from the first pixel electrode, the second pixel electrode, and the third pixel electrode on a plane.

18. In paragraph 15, A display panel, wherein the fifth conductive layer further includes an auxiliary voltage line extending in the second direction and arranged between the second data line and the first gate electrode of the third pixel circuit.

19. In paragraph 18, A display panel in which the auxiliary voltage line is substantially symmetrical with the third data line based on an imaginary straight line passing through the center of the third pixel electrode.

20. A display panel in which a plurality of pixels are arranged; The above display panel, A first pixel circuit, a second pixel circuit, and a third pixel circuit arranged side by side in a first direction on a substrate; Each of the first pixel circuit, the second pixel circuit and the third pixel circuit, A first transistor including a first channel region, a first source region and a first drain region facing each other with the first channel region interposed therebetween, and a first gate electrode disposed on the first channel region; A second transistor including a second channel region and a second gate electrode disposed on the second channel region; A first conductive pattern disposed below the first channel region; and A second conductive pattern disposed on the first gate electrode; The first source region is disposed between the first channel region and the second channel region, and protrudes in the first direction from the first conductive pattern and the second conductive pattern on a plane, An electronic device in which the first pixel circuit and the second pixel circuit are substantially line-symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction.

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