Thermal management for integrated memory and compute circuits

Abstract

Methods, systems, and apparatus, including computational instructions / programs are disclosed for implementing thermal management techniques using leakage attributes of semiconductor circuit die. The system determines a respective leakage attribute for multiple first circuit die on a first semiconductor wafer and a respective leakage attribute for multiple second circuit die on a second semiconductor wafer. The system generates a leakage distribution profile for: i) the first semiconductor wafer based on the respective leakage attribute for each first circuit die; and ii) the second semiconductor wafer based on the respective leakage attribute for each second circuit die. The system computes, from the leakage distribution profile, leakage percentile categories corresponding to different subsets of the first circuit die and the second circuit die. The system determines a grouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned.

Description

THERMAL MANAGEMENT FOR INTEGRATED MEMORY AND COMPUTE CIRCUITSBACKGROUND

[0001] This specification generally relates to memory devices used to execute computations.

[0002] Modem computing systems often incorporate a wide variety of compute processing units that each offer different computing capabilities and trade-offs. Efficient execution of a given compute job often involves parsing computations into meaningful subtasks or workloads that are mapped to available processor cores of a computing system. The computations may be parsed and mapped based on suitability criteria, such as processor capability', performance, and power. Generally, this overall process of allocating portions of a computation to appropriate processor resources is referred to as heterogeneous compute.

[0003] At least one processor core of the computing system can be an Intellectual Property block (“IP block") that executes a respective portion of a computational operation for different multimedia workloads. Example use cases can involve processing image or speech data captured respectively by a camera or microphone on the mobile device as well as performing computations for generative artificial intelligence (“GenAF) applications. The SoC can use a heterogeneous computing operation to process input samples derived from image data, speech data, a text corpus, or a combination of these. An example step in the heterogeneous computation can include processing data associated with the input samples using a memory device that provides in-memory processing or computing capabilities.SUMMARY

[0004] This specification describes manufacturing, hardware, and software techniques for thermal management of an integrated memory and compute circuit (“integrated memory' circuit”).

[0005] At least two thermal management techniques are described for enhancing manufacturing and design aspects of an integrated memory circuit. A first technique minimizes thermal / heat densities or hot spots between dies of the integrated memory circuit by uniquely combining memory and compute die based on complementary part-to-part variations in the leakage attributes of each die. A second technique computes and uses PiM proximity values to manage data storage locations and memory cell usages to minimize theheat density and temperature at nodes between distinct compute die and memory die in an integrated memory circuit.

[0006] The integrated memory' circuit includes a memory unit(s) and a compute unit(s) that are each implemented and configured on different and / or separate semiconductor circuit die. The integrated memory circuit can be a random-access memory7(RAM) device that couples to, and receives requests / commands from, an example System-on-Chip (“SoC’). For example, the SoC can generate data and control signaling that are used to communicate with compute circuitry of the memory' device. The data and control signaling can be generated by a host processor of the SoC, a memory7controller of the SoC, or both. The memory' controller passes the data and control signaling to compute circuitry in the memory device, which uses the control signaling to execute computations for an example inference or data processing workload.

[0007] In some implementations, the integrated memory device can be configured as a three-dimensional integrated circuit (3DIC). For example, circuitry for a memory7unit and a compute unit of the device can be arranged in a stacked configuration and combined in a single integrated circuit package. More specifically, the integrated memory circuit can be a dynamic random-access memory' (DRAM) memory' device that includes a Processing-in- Memory (“PiM”) architecture. The PiM architecture defines one or more PiM blocks of the memory device. Each PiM block includes the compute circuitry (or compute elements), such as a processor unit, mode registers, and one or more computational units, e.g., arithmetic logic units (ALUs) or related addition and multiplication circuitry7. For example, the PiM block can include discrete processors, processor units, register devices, buffers, multiply accumulate cells (MACs), etc. that cooperate to form one or more PiM compute elements.

[0008] One aspect of the subject matter described in this specification can be embodied in a computer-implemented method. The method includes determining, by a leakage detection engine, a respective leakage attribute for each of one or more first circuit die on a first semiconductor wafer and determining, by the leakage detection engine, a respective leakage attribute for each of one or more second circuit die on a second semiconductor wafer. The method also includes generating a leakage distribution profile for: i) the first semiconductor wafer based on the respective leakage attributes for each of the one or more first circuit die; and ii) the second semiconductor wafer based on the respective leakage attributes for each of the one or more second circuit die. The method also includes computing, from the leakage distribution profile, leakage percentile categories corresponding to different subsets of the one or more first circuit die and the one or more second circuit die and determining agrouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned.

[0009] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, the determined grouping of the first and second circuit die are for an integrated circuit package and when arranged in an integrated circuit package, the respective leakage attributes for the first and second circuit minimizes thermal conduction between circuit die of the integrated circuit. In some implementations, the method further includes, for each first circuit die of the one or more first circuit die: storing the respective leakage attribute for the first circuit die in anon-volatile memory of the first circuit die. and for each second circuit die of the one or more second circuit die: storing the respective leakage attribute for the second circuit die in a non-volatile memory of the second circuit die.

[0010] In some implementations, determining the grouping includes determining an allocation of circuit die pairs based on a respective leakage percentile category for each circuit die in the circuit die pair, each circuit die pair comprising a first circuit die and a second circuit. In some implementations, computing the leakage percentile categories includes determining different percentile categorizations of the one or more first circuit die based on the respective leakage attribute for each first circuit die and determining different percentile categorizations of the one or more second circuit die based on the respective leakage attribute for each second circuit die.

[0011] In some implementations, generating the leakage distribution profile includes generating the leakage distribution profile based on: i) a respective location of each first circuit die on the first semiconductor wafer, and ii) a respective location of each second circuit die on the second semiconductor wafer. In some implementations, each first circuit die includes a memory unit and each second circuit die includes a compute unit. In some implementations, determining the respective leakage attribute for each first circuit die on the first semiconductor wafer includes applying a voltage signal to a first circuit die on the first semiconductor wafer, measuring a current signal generated at the first circuit die based on the applied voltage signal and based on the current signal, determining the respective leakage attribute for the first circuit die with reference to a temperature of the first circuit die.

[0012] In some implementations, determining the respective leakage attribute for each second circuit die on the second semiconductor wafer includes applying a voltage signal to a second circuit die on the second semiconductor wafer, measuring a current signal generated at the second circuit die based on the applied voltage signal, and based on the current signal.determining the respective leakage attribute for the second circuit die with reference to a temperature of the second circuit die.

[0013] Another aspect of the subject matter described in this specification can be embodied in a system including, a processor and non-transi lory machine-readable storage medium storing instructions that are executable by the processor to cause performance of operations. The operations include determining, by a leakage detection engine, a respective leakage attribute for each of one or more first circuit die on a first semiconductor wafer and determining, by the leakage detection engine, a respective leakage attribute for each of one or more second circuit die on a second semiconductor wafer. The operations further include generating a leakage distribution profile for: i) the first semiconductor wafer based on the respective leakage attributes for each of the plurality of first circuit die. and ii) the second semiconductor wafer based on the respective leakage attributes for each of the plurality of second circuit die. The operations further include computing, from the leakage distribution profile, leakage percentile categories corresponding to different subsets of the one or more first circuit die and the one or more second circuit die and determining a grouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned.

[0014] Another aspect of the subject matter described in this specification can be embodied in a method implemented using an integrated circuit comprising a System-on-Chip (“SoC”) and a memory device coupled to the SoC. The method includes for each memory die of the memory device, determining a proximity value that characterizes a proximity of the memoiy die to a Processing-in-Memory (PiM) block of a compute die of the memory device, computing a leakage score that indicates a thermal output of the memory die and for each bank of the memory die, computing a bank preference score based on the proximity value and the leakage score. The method further includes selecting a particular memory die and a particular bank on the memoi ' die based on a determined weighting of the bank preference score, proximity value, and leakage score, determining, for the particular bank, memoi ' addresses used to access operands for a machine-learning (“ML”) computation and executing the ML computation at the PiM block using the operands accessed from the preferred memory addresses.

[0015] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, determining a bank preference score includes for each memoiy die: determining a memory address preference score basedon the proximity value and the leakage score, where the memory address preference score is determined for an address space of a bank on the memory die.

[0016] In some implementations, the method further includes determining an allocation of frequently accessed data to memory cells of a memory die based on a proximity value for the memory' die that indicates the memory die is outside a threshold proximity of the PiM block. In some implementations, the method further includes determining an allocation of frequently accessed data to one or more memory die of the memory device to minimize heat density in the memory device. For example, the allocations are determined such that frequently accessed data is stored in a memory bank at a location that exceeds the threshold proximity of the PiM block and non-frequently accessed data is stored in a memory' bank that is within a threshold proximity of the PiM block.

[0017] Another aspect of the subject matter described in this specification can be embodied in an integrated circuit including a System-on-Chip (“SoC”), a memory device coupled to the SoC, and a processor and a non-transitory machine-readable storage medium of the SoC for storing instructions that are executable by the processor to cause performance of operations. The operations include for each memory die of the memory device, determining a proximity value that characterizes a proximity of the memory die to a Processing-in-Memory (PiM) block of a compute die of the memory device, computing a leakage score that indicates a thermal output of the memory die, and for each bank of the memory die, computing a bank preference score based on the proximity value and the leakage score. The operations further include selecting a particular memory die and a particular bank on the memory' die based on a determined yveighting of the bank preference score, proximity value, and leakage score, determining, for the particular bank, memoryaddresses used to access operands for a machine-learning ("ML") computation, and executing the ML computation at the PiM block using the operands accessed from the memory addresses.

[0018] Another aspect of the subject matter described in this specification can be embodied in a method. The method includes determining, for memory dies produced from one or more wafers, first quality bins that categorize the memory dies into low. medium, and high quality and determining, for compute logic dies, second quality bins that categorize the compute logic dies into low, medium, and high quality. The method further includes selecting, for combining into an integrated circuit package, memory dies and compute logic dies so that an overall quality of the integrated circuit package is within a pre-determined range.

[0019] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, selecting a memory die and a compute logic die includes selecting a memory die of medium qualify and a compute logic die of medium or greater qualify, selecting a memory die of high qualify and a compute logic die of low qualify, or selecting a memory die of low qualify and a compute logic die of high qualify.

[0020] As described, each of the preceding different aspects of the subject matter described in this specification include a corresponding set of optional features. Each optional feature of one aspect applies similarly to, and can be included in, each of the other aspects described above. For example, determining a grouping of first and second circuit die from the different subsets can include selecting, for combining into an integrated circuit package, memory dies and compute logic dies so that an overall qualify of the integrated circuit package is within a pre-determined range.

[0021] Additionally, computing, from the leakage distribution profile, leakage percentile categories corresponding to different subsets of the plurality of first circuit die and the plurality of second circuit die can include: i) determining, for each of the first circuit dies, first qualify’ bins that categorize the first circuit dies into low, medium, and high qualify; and ii) determining, for each of the second circuit dies, second qualify bins that categorize the second circuit dies into low, medium, and high quality.

[0022] Other implementations of this and other aspects include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. A system of one or more computers can be so configured by virtue of software, firmware, hardware, or a combination of them installed on the system that in operation causes the system to perform the actions. One or more computer programs can be so configured by virtue of having instructions that, when executed by a data processing apparatus, cause the apparatus to perform the actions.

[0023] The subject matter described in this specification can be implemented in particular embodiments to realize one or more of the following advantages.

[0024] Localized occurrences of hot spots from wide variations in leakage current causes thermal management challenges when manufacturing mixed die integrated circuits. The present disclosure provides multiple solutions for addressing these challenges. The proposed techniques include combining circuit die from different silicon / semi conductor wafers to minimize part-to-part variations in thermal / heat densify between memory and compute circuit die of an integrated memory circuit. An example fabrication process to produce theintegrated memory circuit involves combining memory dies and compute dies in an integrated circuit package. The disclosed techniques for minimizing thermal conduction between memory and compute dies provides a more uniform heat density profile of the die circuitry, which reduces occurrences of hot spots and improves production.

[0025] The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other potential features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Fig. 1 is an example wafer / die processing system that identifies and combines circuit die from different leakage bins.

[0027] Fig. 2 illustrates example graphical data showing reductions in part-to-part variation for different circuit die of an integrated memory circuit.

[0028] Fig. 3A shows example leakage percentile categories for different subsets of circuit die.

[0029] Fig. 3B shows an example of alleviating hot spots at a memory bank by reallocating frequently accessed data to a low-leakage region of a circuit die to minimize heat density7.

[0030] Fig. 4 illustrates an example approach for managing heat density7locations at an integrated memory circuit.

[0031] Fig. 5 is an example device manufacturing process for combining circuit die from different leakage bins in the same integrated circuit package.

[0032] Fig. 6 is an example process for managing locations of memory cell usage in an integrated memory circuit to minimize discrete, localized heat densities across the circuit.

[0033] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0034] Prior approaches for manufacturing semiconductor devices often lead to integrated circuit products with die combinations, where each exhibits worst-case attributes for leakage and thermal performance. Combining worst-case circuit dies in the same package widens part-to-part variations in thermal conduction and power consumption, which often leads to low7production yields and degraded part performance. These aspects represent oneor more semiconductor device design and manufacturing problems. Accordingly, the present disclosure describes techniques for solving or substantially addressing these problems.

[0035] More specifically, this specification describes techniques for combining a compute logic die and a memory die from different leakage bins in a complementary way, for example, by grouping one or more high-leakage memory7die with one or more low-leakage compute die. For example, the technique can be used to combine one or more high-leakage, lower-quality die with one or more low-leakage, higher-quality die to improve overall production volumes and yield higher quantities of integrated emory circuits that operate within specifications and constraints for thermal design power and thermal design cost.

[0036] Fig. 1 shows an example computing system 100 for identifying and combining circuit dies from different leakage bins. System 100 includes a wafer / die processing system 102, a signal / power generator 104, and a leakage detection engine 106.

[0037] The signal / power generator 104 is configured to generate signal communications for processing wafers at the system 100. The semiconductor wafers can be silicon or bulk silicon, however other semiconductor materials or wafers can be used, such as germanium, selenium, gallium, etc. The signal communications can include voltage signals 110 and clock signals 112. In addition to clock signals 112, the signal / power generator 104 may also be configured to generate other ty pes of frequency-based control or processor signals. Aspects of the signal / po er generator 104 can be implemented in hard are, soft are, or both.

[0038] The wafer / die processing system 102 uses signals generated by the signal / power generator 104 to evaluate attributes of different circuit die formed on semiconductor wafers 114, 116. The semiconductor wafers 114, 116 include multiple circuit die. In the example of Fig. 1, a first semiconductor wafer 114 includes multiple compute circuit die. whereas a second semiconductor wafer 116 includes multiple memory circuit die. In other examples, a single wafer can include a mix of compute logic die and memory circuit die.

[0039] Integrated circuitry7for an example PiM architecture or PiM block can be fabricated on a single compute die or across multiple compute die. Similarly, integrated circuitry for a memory bank, bank groups, or a grouping of DRAM cells can be fabricated on a single memory die or across multiple memory die. The compute die is described alternatively as a compute unit, compute circuit, or compute logic die. Regardless of the term used, a compute unit (or portions thereof) may be fabricated on a single circuit die or across multiple circuit die. In general, a circuit die is a piece or section of a wafer, such as semiconductor wafer 114. The wafer is cut (or diced) into many circuit die pieces or sections.

[0040] In some implementations, a compute unit corresponds to a PiM architecture, a PiM block, or both. In some other implementations, a compute unit corresponds to arithmetic circuitry of a PiM architecture, a processor / processing unit of the PiM architecture, or both. The arithmetic circuitry can be an arithmetic logic unit (ALU), MACs, a matrix unit, a vector math operator, or a combination of these.

[0041] The leakage detection engine 106 includes die location & sorting logic 108. Each of the leakage detection engine 106 and die location & sorting logic 108 can be implemented in hardware, software, or both. The leakage detection engine 106 determines respective leakage attributes for multiple first circuit die of first semiconductor wafer 114 and respective leakage attributes for multiple second circuit die of second semiconductor wafer 116.

[0042] Leakage attributes for the first circuit die are passed to the leakage detection engine 106 as data signals 118, whereas leakage attributes for the second circuit die are passed to the leakage detection engine 106 as data signals 120. In some implementations, the leakage detection engine 106 captures all measured current values for signals 118, 120, associates all received cunent values with a corresponding voltage and / or clock signal 110, 112, and associates all received current values with a corresponding semiconductor wafer 114, 116.

[0043] The die location & sorting logic 108 can associate the captured current and / or leakage values with a corresponding quadrant of a wafer as well as higher resolutions than quadrant level. For example, each semiconductor wafer 114, 116 can include 4 quadrants (e.g., NE, SE, NW, SW). The die location & sorting logic 108 can determine to associate certain current and / or leakage data values with a corresponding wafer quadrant. For example, the die location & sorting logic 108 can make these determinations and associations using metadata tags that indicate the quadrant, die, or circuit grouping from which a current and / or leakage data value was obtained or measured. In some examples the metadata tags are generated using the signal / power generator 104.

[0044] Additionally, the die location & sorting logic 108 can determine or identify the relative locations of the corresponding circuit die from which the current values were measured or obtained. For example, the signal / power generator 104 and leakage detection engine 106 can interact with various hardware control systems that dynamically cause various control signal generators to traverse a surface of the semiconductor wafers 114, 116 to apply corresponding signals to the circuit die. In some implementations, die location & sorting logic 108 computes or otherwise determines correlations among the current signal values or other leakage attributes of the circuit dies.

[0045] In some implementations, system 102 is configured such that leakage attributes are captured, metadata tagged, and stored for relative locations that are more fine-grained than at a wafer quadrant level (e.g. per-die). For example, the leakage attributes can be determined for: i) different compute or memory dies obtained from a wafer quadrant; ii) different sections of circuitry' within circuit die obtain from a wafer quadrant; iii) different groupings of transistors and hardware logic gates within a section of circuitry; or iv) a combination of these. Relatedly, each of the signal / power generator 104. leakage detection engine 106, and die location & sorting logic 108 is configured to generate and read data signals for obtaining leakage attributes higher resolutions than per-quadrant levels.

[0046] The wafer / die processing system 102 can generate leakage distribution profile(s) 122 for: i) the first semiconductor wafer based on the respective leakage attribute for each first circuit die; and ii) the second semiconductor wafer based on the respective leakage attribute for each second circuit die. The die location & sorting logic 108 can generate the leakage distribution profile 122 from the computed correlations among the current signal values coupled with other leakage attributes such as operating speed and responsiveness to certain input signals.

[0047] In some implementations, the leakage profiles are clusters of current values, such as , 10-20 micro Amps (pA) or 80-90 pA, that represent part-to-part variations in thermal and power densities. The leakage distribution profiles 122 can be stored in an example database or storage bank(s) that is accessible by wafer / die processing system 102. In some implementations, the wafer / die processing system 102 generates different leakage profile ty pes 124. For example, the wafer / die processing system 102 can generate leakage distribution profiles 122 that characterize circuit die leakage using parameters / units other than current, such as operating frequency and speed (or latency).

[0048] The die location & sorting logic 108 computes leakage percentile categories 126, 128, 130 corresponding to different subsets of the first circuit die and the second circuit die. For example, the die location & sorting logic 108 can encode one or more percentile functions. The die location & sorting logic 108 can compute the leakage percentile categories 126, 128. 130 in response to applying one or more of its percentile functions to the distribution of leakage data or current values. In some implementations, a center portion 115 of the semiconductor wafers 114, 116 can represent an area of the wafer that normally exhibits lower leakage current. The die location & sorting logic 108 can determine and apply a corresponding weighting for circuit die at center portion 115 when computing the leakage percentile categories 126, 128, 130. For example, die location & sorting logic 108 canreference a metadata tag indicating a relative location of a die as being associated w ith center portion 115 and apply a corresponding weighting to its leakage attributes (e.g., leakage data or current values).

[0049] The wafer / die processing system 102 determines a grouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned. For example, the die location & sorting logic 108 can determine allocations 135 of circuit die pairs based on a respective leakage percentile category for each circuit die in the circuit die pair. Each circuit die pair includes a memory die and a compute die. The respective leakage attributes for a first circuit die (e.g., memory die) and a second circuit die (e.g., compute die) allow for minimizing thermal conduction between circuit die of an integrated memory circuit.

[0050] For example, the leakage distribution profiles 122 for different circuit die can be referenced during production to obtain the respective leakage attributes for the first and second circuit die. The first and second circuit die can be arranged to minimize thermal conduction between the circuit dies of the integrated circuit based on the respective leakage attributes for the first and second circuit die. For example, a high-leakage compute die is paired with a low-leakage memory' die to manage thermal conduction intermediate these distinct circuit die, which allows for managing overall thermal conduction in the integrated circuit package. In some implementations, selection of different memory and compute dies is performed in a complementary way so as to reduce the overall leakage distribution across an integrated memory device. Relatedly, corresponding memory' bank allocations can be performed in view of the thermal conduction between these adjacent parts.

[0051] The system 100 further includes a client / user device 103. In the example of Fig. 1, the client device 103 can be any known computing device / system, such as a desktop computer, a laptop computer, a tablet device, a mobile device, a smartphone, or a combination of these. In general, the user device 103 can be any related computing device that receives inputs and that processes, transmits, transfers, or otherwise provides data and input commands to devices of system 100.

[0052] Each device of system 100 can be optionally coupled to another device of the system. For example, the client device 103 couples to the signal / power generator 104 via a wired or wireless connection. In some implementations, client device 103 is coupled to, or communicates with, an example computing server 103-1, which may be local or remote relative to the client device 104. For example, the computing server 103-1 can be a cloudbased computing asset.

[0053] Fig. 2 illustrates example graphical data showing reductions in part-to-part variation for different circuit die of an integrated memory circuit. For example, the part-to- part variations can correspond to leakage attributes such as leakage current and device speed. In some examples the graphical data can represent a reduction (e.g., 20%-30%) in part-to-part variation of leakage current and operating speed for memory7devices that combine memory7dies and compute logic dies. These reductions can provide a corresponding improvement to (e.g.. by lowering) product power constraints / limits defined by relevant device specifications.

[0054] For example, reducing the width or range in part-to-part variation can translate to lower (or reduced) power limits / constraints for corresponding memory products. The adjusted constraints can improve device yields for memory or circuit products that must operate within those power specification limits. The power limits that are adjusted (or reduced) can be power specification limits for Thermal Design Power (TDP), e.g., maximum sustainable power consumption or threshold voltage before experiencing a device malfunction, and Thermal Design Cost (TDC), e.g., additional costs that can be required to ensure device can satisfy higher, or more stringent, limits on thermal conduction and heat density.

[0055] The graphical data in the example of Fig. 2 includes a memory die quality7graph 202 that shows a part-to-part variation of quality7of produced memory7dies. The distribution of the quality variation is represented by a bell curve 204 showing, on a y-axis, a count 206 of the parts having a particular quality. In the case of the memory die quality graph 202, the quality is characterized by leakage attribute 208, which can be leakage current or a corresponding device speed, as indicated on the x-axis of the memory7die quality7graph 202. Similarly, a compute logic die quality graph 210 includes a bell curve 212 that shows the count 206 of the parts having a particular quality. In the case of the compute die quality graph 210, the quality can also be characterized by leakage attribute 214, which can be leakage current or a corresponding device speed.

[0056] An integral compute+memory package quality graph 216 shows a part-to-part variation of quality of produced compute+memory package. The distribution of the quality variation is represented by a bell curve 218 showing, on a y-axis. the count 206 of the parts having a particular quality. In the case of the integral compute+memory package quality graph 216, the quality7is compute+memory7220, as indicated on the x-axis of the integral compute+memory package quality graph 216. The shape of the bell curve 218 for the compute+memory packages is taller and narrower than would be expected if dies of different ty pes are combined without considering the qualities of the separate dies. Further, asindicated by the lines 222, integral compute+memory packages do not incur low-quality specifications, e.g., which have been eliminated by not combining low-quality dies of each type. As a result, a part-to-part variation 224 of the integral compute+memory packages is reduced, and the part-to-part variation 224 defines a limit in the product specifications.

[0057] In general, hot spots can be a region of non-uniform heat density' that exists between a memory die and a compute die due to less thermal conduction between the dies. Problems that result from the hot spots can be solved (e.g., reduced or eliminated) by storing more frequently accessed data in memory locations that are farther from high heat density that is caused by conduction of the compute die. At the same time, less frequently accessed data can be stored closer to the high-heat density' areas.

[0058] Fig. 3A shows example leakage percentile categories 330. 335 for different subsets of memory circuit die (330) and compute circuit die (335).

[0059] The yvafer / die processing system 102 obtains leakage attributes of circuit die on wafers 114, 116. The leakage attributes include current signal values that are analyzed and correlated using a percentile function. The results of the percentile function are used to categorize various subsets of memory and compute die into different bins of low-, medium-, and high-quality dies, as rated according to leakage or speed distribution. For example, 10 percent of each type of die can be categorized as loyv quality', 80 percent as medium quality', and 10 percent as high quality. Dies of different qualities are combined into an integrated memory circuit, represented by the integral compute+memory package.

[0060] The result is to create and use production part bins (leakage or speed distribution) that divide the dies into the different quality categories. While the categories in this example are 10, 80, and 10 percent, other thresholds can be used, and percentile categories can number more than three. If the quality of the individual dies is considered yvhen combining the dies, as is a feature of the present disclosure, then the quality of the integral compute+memory package can be controlled. This can be done by combining medium-quality dies together, or combining a low-quality die with a high-quality die of the different type.

[0061] In some examples of combinations 350 (referring to Fig. 3A), high-leakage, faster parts 352 can be combined with low-leakage, slower parts 354. In another example, low- leakage, slow parts 354 can be combined with high leakage, fast parts 352. In yet another example, median leakage, median parts 356 can be combined yvith median leakage, median parts 356. Each combination 350 includes an example memory die / circuit 332 and a corresponding compute die / circuit 334.

[0062] Fig. 3B shows an example of alleviating hot spots at a memory bank by reallocating frequently accessed data to a low-leakage region of a circuit die to minimize heat density.

[0063] In the example of Fig. 3B, an initial data allocation scheme 303 results in frequently accessed data being stored in memory cells or locations that coincide with high- leakage regions of a memoiy circuit die. This results in high heat density 305 at those regions, which can degrade performance of a memory circuit. The high heat density 305 can occur due to conduction from an adjacent compute die (not shown). As shown in allocation scheme 303, existing systems may store the more frequently accessed data 314 and the less frequently accessed data 316 in a randomized manner, which results in the data being scattered throughout memory 302 resulting in frequently accessed data 314 being stored in high leakage regions of the memory circuit die.

[0064] In contrast, the data storage scheme 300 is used to address, prevent, or reduce these (and other) occurrences of high heat density. Using data storage scheme 300, an example computing system can determine and provide a memory layout that minimizes read / write access to DRAM cells that are close to certain areas of the compute die that either also have high leakage or just generally emit high heat due to computations that are executed at the compute die. Data to be stored in (or accessed from) storage passes through data buffers 306. Address bits in memory are divided between the two decoders. A row decoder 308 is used to select word lines for storage in memory 302. Word lines are used to select a row for reading or writing. A column decoder 310 is used to select one or more columns for input / output of data. Additionally, a sense amplifier circuit 312 can read and amplify weak signals stored in memory' cells of memory 302.

[0065] The data storage scheme 300 can be used to manage the locations of DRAM cell usage to minimize the heat density and temperature in compute + memory device. The management of the memory locations can be based on information of data read / write counts from the compiler / simulation. More frequently accessed data 314 can be allocated to the DRAM cells in a low-leakage region 315, that is also far (in proximity) from the high-heat regions of the compute die, whereas less frequently accessed data 316 can be allocated to the DRAM cells that maybe closer (or slightly closer) to the high-heat regions 304 of the compute die. The low-leakage region 315 can be represented by one or more memory die, or portions or sections of circuitry' within a memory die, that exhibited low-leakage attributes when assessed by the system 102. For example, the low-leakage region 315 can be defined based on leakage data and / or current values obtained at sub-quadrant or sub-die resolutions.

[0066] In some implementations, addresses in memory can be assigned a memory7address preference score, which may be referred to alternatively as a rating score. Such assigned values can be based on a distance from a compute die, where a greater distance can have a higher address preference / rating score and can be reserved (or preferred) for high-frequency memory7accesses. In some implementations, rating scores indicating preferred address locations in memory can be based on particular qualities of the circuit dies (e.g., memorydies). For example, locations in memory die with a higher-leakage value can have a lower rating score than locations in memory die exhibited higher greater quality7(e.g., lower leakage).

[0067] Fig. 4 illustrates an example approach for managing heat density7locations at an integrated memory circuit. Fig. 4 shows an example of how managing storage based on heat density locations can more evenly distribute heat and eliminate hot spots. In the example of storage 402 that does not use the techniques of the present disclosure, heat is not considered in the organization of data on memory. As a result, memory7406 and compute space 408 provide concentrated heat 410 in certain areas of storage since locations of frequently accessed data are scattered throughout memory.

[0068] As an example, there can be a concentration of heat 410 at a central location of the storage 402 in the compute unit, which was generated from computations executed by the compute unit and from the close proximity of the frequently accessed data on both sides of the compute unit. In the example storage and compute device 404 using techniques of the present disclosure, heat 410 is more spread out (compared to the storage 402), since the locations of frequently accessed data are farther away from the location of the computations.

[0069] In the example of Fig. 4, example heat density7indicators 414 and high-density7memory read / write access indicators 416 (based on addresses used) are included in key 418. As described herein, the disclosed thermal management technique computes and uses PiM proximity values to manage data storage locations and memory^ cell usage to minimize overall heat density7and temperatures at nodes between compute and memory7die in an integrated memory circuit. This reduces the hot spots in the integrated compute + memory package by spreading memory access workloads (e.g., dynamic power density) across the package. The techniques also reduce max junction temperatures in both the compute unit and memory units. A reduction in the DRAM refresh rate can also contribute to overall power reduction and increased performance.

[0070] As shown at Fig. 4. device 402 includes an example high-heat density area 420, whereas design 404 includes an example solution for managing these high-heat density7locations. The solution results in an example area 425 where heat from memory accesses and computes are distributed more evenly across device 404. Design approaches for integrated circuitry include thermal solutions that are crafted for the hot spot locations of a circuit die, which generally correspond to the worst-case temperature on the die. Hence, a thermal management solution that distributes memory access workloads in a manner that reduces overall package (and junction) temperatures will also lead to a significant reduction in Thermal Design Power (TDP) and Thermal Design Cost. In some implementations, the junction temperature can be obtained and monitored through temperature sensors located in the integrated circuit.

[0071] In some implementations, the approach for managing heat density locations at an integrated memory circuit (described with reference to Fig. 4) can be achieved using a storage management method. The storage management method can be implemented using an integrated circuit that comprises a System-on-Chip (“SoC”) and a memory device coupled to the SoC. In some examples, the storage management method can be used to manage the device 404, providing improved management of high-heat density’ location as compared to device 402.

[0072] The storage management method can include the following steps for each memory die of the memory device. Referring to Fig. 3B, a proximity’ value 318 is determined that characterizes a proximity 320 of the memory die (or memory banks) to an example PiM block 322 of a compute die of the memory’ device. A leakage score 324 is calculated that indicates a thermal output of the memory die. In some implementations, the leakage score 324 is computed at a particular resolution based on a structure or partitioning of memory’ banks among different memory' dies of an integrated memory device. For example, the leakage score can be computed for a memory die, a portion of circuitry on a memory die, or both. In some other implementations, the leakage score 324 is computed at a particular resolution based generally on design preference.

[0073] For each bank of the memory' die, a memory address preference score 326 is computed based on the proximity value 318 and the leakage score 324. A corresponding bank preference score 328 is computed based on the memory address preference score 326. In some implementations, determining the bank preference score 328 includes determining, for each memory’ space, a memory’ address preference score 326 that is computed based on the proximity' value and the leakage score. Each memory address preference score 326 is determined for an address space of a bank on the memory die. In some implementations, each memory' die has a particular chip density that corresponds to the number of memory'banks implemented on the die. For example, each memory die can have a density defined by N banks, where TV is an integer greater than or equal to one. The PiM proximity value 318. leakage score 324, and memory address preference score 326 can be computed with reference to each of the N banks.

[0074] Once the bank preference scores are computed, the following steps of storage management method can proceed. A particular memory’ die and a particular bank on the memory die are selected based on the bank preference score. In some implementations, the particular bank on the memory' die is selected from a determined weighting of the bank preference score, the proximity value, the leakage score, or combination of these. For the particular bank, an allocation of memory' addresses used to access operands for a machinelearning (“ML’?) computation is determined. The ML computation is executed at the PiM block using the operands accessed from the allocation of memory' addresses.

[0075] When determining the allocation of memory addresses, in some implementations, the allocation of frequently accessed data to memory' cells of a memory die is determined to be outside a threshold proximity 321 of the PiM block. That is, to manage heat density, frequently accessed data is allocated to memory cells on a bank of the memory die that is a particular distance, e.g., far enough, away from the PiM block 322 to minimize temperature and heat density between the memory' die and PiM block 322.

[0076] For example, the temperature and heat density are minimized by leveraging the threshold proximity 321 to spread out and place the heat from the frequently accessed data at a particular distance aware from the heat generated because of computations executed at the PiM block 322. For less frequently accessed data, the allocation of memory' addresses can be determined to be within a particular distance of the PiM block 322. For example, data that is accessed less frequently can be allocated to memory’ cells on a bank of the memory die that are closer than a particular distance to the PiM block to manage heat density.

[0077] More specifically, relative to the compute block (e.g., PiM block 322), less frequently accessed data can be allocated to memory' cells of banks that are located at a distance within the threshold proximity, whereas more frequently accessed data can be allocated to memory cells of banks that are located at a distance that exceeds the threshold proximity. In some implementations, the threshold proximity is determined as a minimum distance required to minimize temperature increases and heat densities from the respective heat output of the computes at the compute block and corresponding memory accesses at the memory banks.

[0078] Fig. 5 is an example device manufacturing process 500 for combining circuit die from different leakage bins in the same integrated circuit package. Process 500 is implemented or executed at system 100 using at least the wafer / die processing system 102 described above with reference to Fig. 1. Hence, descriptions of process 500 will reference the above-mentioned computing resources of system 102. In some examples, the steps or actions of process 500 are enabled by programmed software instructions, firmware instructions, or both. Each type of instruction may be stored in a non-transitory machine- readable storage device and is executable by one or more of the processors or other resources described in this specification.

[0079] Referring again to process 500, the wafer / die processing system 102 determines a respective leakage attribute for each of multiple first circuit die on a first semiconductor wafer (502). Relatedly, the wafer / die processing system 102 also determines a respective leakage attribute for each of multiple second circuit die on a second semiconductor wafer (504). For each of the first and second semiconductor wafers 114, 116. the respective leakage attributes for the corresponding first and second circuit die are determined by the leakage detection engine 106 based on signals 1 13 generated by the signal / power generator 104.

[0080] The signals 113 can be voltage signals 110 that are applied to some (or all) of the circuit die of the semiconductor wafers 114, 116. For example, the signal / power generator 104 can apply a voltage signal 110 to each first circuit die on the first semiconductor wafer 1 14 and measure a corresponding current signal 1 18 generated at each first circuit die based on the applied voltage signal 110. Similarly, the signal / power generator 104 can apply a voltage signal 110 to each second circuit die on the second semiconductor wafer 116 and measure a corresponding current signal 120 generated at each second circuit die based on the applied voltage signal 110.

[0081] The leakage detection engine 106 determines the respective leakage attribute for each of the first circuit die based at least on the corresponding current signal 118, 120 generated for that circuit die. In some implementations, voltage signals 110 and current signals 1 18, 120 are applied and measured at a circuit die with reference to a temperature of that circuit die. In some implementations, the applied signals 113 are a combination of voltage signals 110 and clock signals 113 that have a corresponding frequency.

[0082] The wafer / die processing system 102 generates a die leakage distribution profile (506). For example, wafer / die processing system 102 generates a leakage distribution profile for the first semiconductor wafer 114 based on the respective leakage attributes for each ofthe multiple first circuit die. Further, the wafer / die processing system 102 generates a leakage distribution profile for the second semiconductor wafer 116 based on the respective leakage attributes for each of the multiple second circuit die. In some implementations, the leakage distribution profile for the first semiconductor wafer 114 and the second semiconductor wafer 116 are the same profiles.

[0083] The wafer / die processing system 102 computes or otherwise determines leakage percentile categories from the leakage distribution profile (508). The leakage percentile categories correspond to different subsets of the multiple first circuit die and the multiple second circuit die. The wafer / die processing system 102 determines a grouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned (510)

[0084] Fig. 6 is an example process 600 for managing locations of memory cell usage in a random-access memory device to minimize occurrences of hotspots and / or localized heat densities across the memory circuit. Process 600 can be implemented or executed using computing resources described herein. For example, some aspects of process 600 can be implemented using a compiler that determines address spaces for read / write operations at the memory device.

[0085] In other examples, aspects of process 600 can be implemented using a host device on an SoC, a memory controller of an SoC, or both. Some steps or actions of process 600 are enabled by programmed software instructions, firmware instructions, or both. Each type of instruction may be stored in a non-transitory machine-readable storage device and is executable by one or more of the processors or other resources described in this specification.

[0086] Referring again to process 600, for each memory die of the memory device, the system 100 (e.g.. the SoC or compiler) determines a proximity value that characterizes a proximity of the memory' die to a PiM block of a compute die in the memory device (602). In these and other examples, the memory' device is an integrated memory circuit that includes one or more memory die that are coupled to one or more compute die. For each memory die of the integrated memory’ circuit: the system computes a leakage score that indicates a thermal output of the memory die (604).

[0087] For each bank of the memory' die, the system computes a bank preference score based on the proximity' value and the leakage score (606). The system selects a particular memory die and a particular bank on the memory die based on a determined weighting of the bank preference score, proximity’ value, and leakage score. For the particular bank, the system determines an allocation of memory addresses used to access operands for a machine-leaming (“ML"’) computation (608). The system executes the ML computation at the PiM block using the operands accessed from the allocation of memory addresses (610).

[0088] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non transitory program carrier for execution by, or to control the operation of, data processing apparatus.

[0089] Alternatively, or in addition, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0090] The term “computing system” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0091] A computer program (which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0092] A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0093] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as. special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a GPGPU (General purpose graphics processing unit).

[0094] Computers suitable for the execution of a computer program include, by way of example, can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read only memory or a random-access memory7or both. Some elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0095] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memorydevices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory7can be supplemented by, or incorporated in, special purpose logic circuitry7.

[0096] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can bereceived in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s client device in response to requests received from the web browser.

[0097] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g., the Internet.

[0098] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0099] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0100] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in theembodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0101] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

What is claimed is:

1. A computer-implemented method comprising: determining, by a leakage detection engine, a respective leakage attribute for each of a plurality of first circuit die on a first semiconductor wafer; determining, by the leakage detection engine, a respective leakage attribute for each of a plurality of second circuit die on a second semiconductor wafer; generating a leakage distribution profile for: i) the first semiconductor wafer based on the respective leakage attributes for each of the plurality7of first circuit die; and ii) the second semiconductor wafer based on the respective leakage attributes for each of the plurality of second circuit die; computing, from the leakage distribution profile, leakage percentile categories corresponding to different subsets of the plurality of first circuit die and the plurality of second circuit die; and determining a grouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned.

2. The method of claim 1, wherein: the determined grouping of the first and second circuit die are for an integrated circuit package; and when arranged in an integrated circuit package, the respective leakage attributes for the first circuit die and the second circuit die minimizes thermal conduction between circuit die of the integrated circuit.

3. The method of claim 1 or 2, further comprising: for each first circuit die of the plurality of first circuit die: storing the respective leakage attribute for the first circuit die in a non-volatile memory of the first circuit die; and for each second circuit die of the plurality of second circuit die: storing the respective leakage attribute for the second circuit die in a non-volatile memory of the second circuit die.

4. The method of any one of claims 1 to 3, wherein determining the grouping comprises:determining an allocation of circuit die pairs based on a respective leakage percentile category for each circuit die in the circuit die pair, each circuit die pair comprising a first circuit die and a second circuit.

5. The method of claim 4, wherein computing the leakage percentile categories comprises: determining different percentile categorizations of the plurality of first circuit die based on the respective leakage attribute for each first circuit die; and determining different percentile categorizations of the plurality of second circuit die based on the respective leakage attribute for each second circuit die.

6. The method of claim 5, wherein generating the leakage distribution profile comprises: generating the leakage distribution profile based on: i) a respective location of each first circuit die on the first semiconductor wafer, and ii) a respective location of each second circuit die on the second semiconductor wafer.

7. The method of any preceding claim, wherein: each first circuit die comprises a memory unit; and each second circuit die comprises a compute unit.

8. The method of any preceding claim, wherein determining the respective leakage attribute for each first circuit die on the first semiconductor wafer comprises: applying a voltage signal to a first circuit die on the first semiconductor wafer; measuring a current signal generated at the first circuit die based on the applied voltage signal; and based on the current signal, determining the respective leakage attribute for the first circuit die with reference to a temperature of the first circuit die.

9. The method of any preceding claim, wherein determining the respective leakage attribute for each second circuit die on the second semiconductor wafer comprises: applying a voltage signal to a second circuit die on the second semiconductor wafer; measuring a current signal generated at the second circuit die based on the applied voltage signal; andbased on the current signal, determining the respective leakage attribute for the second circuit die with reference to a temperature of the second circuit die.

10. A system comprising: a processor; and a non-transitory machine-readable storage medium storing instructions that are executable by the processor to cause performance of operations comprising: determining, by a leakage detection engine, a respective leakage attribute for each of a plurality7of first circuit die on a first semiconductor wafer; determining, by the leakage detection engine, a respective leakage attribute for each of a plurality of second circuit die on a second semiconductor wafer; generating a leakage distribution profile for: i) the first semiconductor wafer based on the respective leakage attributes for each of the plurality of first circuit die; and ii) the second semiconductor wafer based on the respective leakage attributes for each of the plurality of second circuit die; computing, from the leakage distribution profile, leakage percentile categories corresponding to different subsets of the plurality of first circuit die and the plurality of second circuit die; and determining a grouping of first and second circuit die from the different subsets based on a respective leakage percentile category to which each of the different subsets is assigned.

11. A method implemented using an integrated circuit comprising a System-on-Chip C’SoC”) and a memory- device coupled to the SoC, the method comprising: for each memory die of the memory device: determining a proximity value that characterizes a proximity of the memory die to a Processing-in-Memory (PiM) block of a compute die of the memory device; computing a leakage score that indicates a thermal output of the memory die; and for each bank of the memory- die, computing a bank preference score based on the proximity value and the leakage score; selecting a particular memory die and a particular bank on the memory die based on a determined weighting of the bank preference score, proximity- value, and leakage score;determining, for the particular bank, memory addresses used to access operands for a machine-learning (“ML”) computation; and executing the ML computation at the PiM block using the operands accessed from the memory addresses.

12. The method of claim 11, wherein determining a bank preference score comprises: for each memory die: determining a memory' address preference score based on the proximity value and the leakage score, wherein the memory address preference score is determined for an address space of a bank on the memory die.

13. The method of claim 1 1 or 12, further comprising: determining an allocation of frequently accessed data to memory cells of a memory' die based on a proximity value for the memory' die that indicates the memory die is outside a threshold proximity of the PiM block.

14. The method of any one of claims 11 to 13, further comprising: determining an allocation of frequently accessed data to one or more memory' die of the memory device, such that frequently accessed data is stored in a memory bank at a location that exceeds the threshold proximity of the PiM block and other data is stored in a memory bank that is within a threshold proximity of the PiM block. .

15. An integrated circuit comprising: a System-on-Chip (“SoC”); a memory' device coupled to the SoC; and a processor and a non-transitory machine-readable storage medium of the SoC for storing instructions that are executable by the processor to cause performance of operations comprising: for each memory die of the memory device: determining a proximity value that characterizes a proximity' of the memory' die to a Processing-in-Memory (PiM) block of a compute die of the memory' device; computing a leakage score that indicates a thermal output of the memory' die; andfor each bank of the memory die, computing a bank preference score based on the proximity value and the leakage score; selecting a particular memory die and a particular bank on the memory die based on a determined weighting of the bank preference score, proximity value, and leakage score; determining, for the particular bank, memory’ addresses used to access operands for a machine-learning (“ML”) computation; and executing the ML computation at the PiM block using the operands accessed from the memory' addresses.

16. A method comprising: determining, for memory' dies produced from one or more wafers, first quality bins that categorize the memory dies into low, medium, and high quality; determining, for compute logic dies, second quality bins that categorize the compute logic dies into low. medium, and high quality; and selecting, for combining into an integrated circuit package, memory dies and compute logic dies so that an overall quality of the integrated circuit package is within a predetermined range.

17. The method of claim 16. wherein selecting a memory die and a compute logic die comprises: selecting a memory' die of medium quality and a compute logic die of medium or greater quality; selecting a memory die of high quality and a compute logic die of low quality; or selecting a memory die of low quality and a compute logic die of high quality'.

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