Power processing circuit

Abstract

Provided in the present invention is a power processing circuit, comprising: at least one power processing circuit stage, each power processing circuit stage comprising at least one group of power processing circuit modules. Each group of power processing circuit modules comprises one first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports, wherein the power processing unit comprises N pairs of differential coupling lines, and N≥2. In the same power processing circuit stage, the positive port and the negative port of at least one second differential signal port are connected to positive coupling lines and negative coupling lines of different pairs of the differential coupling lines.

Description

A power processing circuit Technical Field

[0001] The present invention relates to the field of radio frequency and microwave technology, and in particular to a power processing circuit. Background Art

[0002] Power splitters are widely used in wireless communications. They split a single signal into two or more equal-amplitude, in-phase signals. They can also combine two or more equal-amplitude, in-phase signals into a single signal, for example, as combiners in low-orbit satellite communications or millimeter-wave communications. The bandwidth of a power splitter affects the system's operating frequency, while its in-band insertion loss affects the transmit power of wireless communication signals. Its isolation directly impacts interference between communication signals.

[0003] In modern communication systems, power splitters / combiners, as key RF components, are required to have wide bandwidth, low insertion loss, and high isolation. Commonly used power splitters / combiners are implemented in three ways: The first is using lumped components in the form of capacitors and inductors. This type of power splitter / combiner is difficult to implement at high frequencies (e.g., frequencies above 5 GHz) and has a relatively narrow bandwidth of approximately 20%. The second is using distributed transmission lines, known as Wilkinson power splitters. This type of power splitter struggles to maintain compatibility between size and broadband performance. The third is using waveguides or dielectric integrated waveguides. This type of power splitter offers good performance, but is difficult to reduce in size and achieve high integration, making it challenging to implement in practical applications.

[0004] The transmit link in modern communication systems requires high operating bandwidth, output power, and efficiency. This means that the power splitter / combiner must have high bandwidth, low insertion loss, and high isolation. The receive link must also have high operating bandwidth, low noise, and high crosstalk suppression. However, existing power splitter / combiner implementations are not compatible with both transmit and receive link requirements of modern communication systems.

[0005] In response to the above needs, the applicant proposed a Chinese patent entitled "A differential power divider, transmitting link system and receiving link system" with publication number "CN116632488B" on July 21, 2023. The length of the coupling line used in the circuit implemented can be much less than a quarter wavelength, which not only reduces the size of the power divider, but also reduces the in-band insertion loss and improves isolation. Its bandwidth performance can be achieved by controlling the ratio of the fundamental mode impedance and even mode impedance of the coupling line without adding multi-stage coupling lines, ensuring that the small size of the power divider is taken into account while achieving high broadband performance, while taking into account the high integration and high broadband performance of the power divider.

[0006] However, the inventors have discovered through experiments that the isolation of the above-mentioned prior art solutions still has room for further improvement.

[0007] Summary of the Invention

[0008] The object of the present invention is to provide a power processing circuit which, compared with the prior art, can further increase the isolation while taking both the transmitting link and the receiving link into consideration.

[0009] To solve one or more of the above technical problems, the technical solutions adopted in this application are:

[0010] In a first aspect, a power processing circuit includes: at least one level of power processing circuit, each level of power processing circuit including at least one group of power processing circuit modules;

[0011] Each group of power processing circuit modules includes a first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports, wherein the power processing unit includes N pairs of differential coupled lines, where N is greater than or equal to 2;

[0012] In the same-level power processing circuit, the positive port and the negative port of at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0013] In a preferred embodiment, in the same-level power processing circuit, the positive port and the negative port in at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, which is specifically implemented as follows: the positive port and the negative port in each second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0014] In a preferred embodiment, in the same-level power processing circuit, the positive port and the negative port of at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, specifically implemented as follows:

[0015] The positive port and the negative port of the at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines in different groups of power processing circuit modules.

[0016] In a preferred embodiment, each stage of the power processing circuit further includes an isolation module, which is arranged between the same-polarity ports of different second differential signal terminals in the power processing circuit of that stage.

[0017] In a preferred embodiment, the isolation module is specifically provided between the same-polarity ports of different second differential signal terminals in the same group of power processing circuit modules.

[0018] In a preferred embodiment, the isolation module is further provided between the same-polarity ports of different second differential signal terminals in different groups of power processing circuit modules.

[0019] In a preferred embodiment, the isolation module includes an isolation resistor, or an isolation resistor and a capacitor in parallel.

[0020] In a preferred embodiment, in each group of power processing circuit modules, the positive port of the first differential signal port is connected to the positive coupling line of the first pair of differential coupling lines, the negative port of the first differential signal port is connected to the negative coupling line of the Nth pair of differential coupling lines, and the negative coupling line of the i-th pair of differential coupling lines is connected to the positive coupling line of the i+1-th pair of differential coupling lines, where 1≤i <N。

[0021] Connecting the negative coupling line of the i-th pair of differential coupling lines with the positive coupling line of the i+1-th pair of differential coupling lines is specifically achieved by connecting the negative coupling line of the i-th pair of differential coupling lines with the positive coupling line of the i+1-th pair of differential coupling lines in series.

[0022] In a preferred embodiment, the power processing circuit is a power splitter.

[0023] In a preferred embodiment, the first differential signal port in each group of power processing circuit modules serves as a differential signal input port, and the second differential signal port serves as a differential signal output port.

[0024] In a preferred embodiment, the power processing circuit is a combiner.

[0025] In a preferred embodiment, the first differential signal port in each group of power processing circuit modules serves as a differential signal output port, and the second differential signal port serves as a differential signal input port.

[0026] In a preferred embodiment, at least the first differential signal port is connected to a balun.

[0027] In a preferred embodiment, at least one second differential signal port is connected to a balun.

[0028] In a preferred embodiment, the length of the differential coupling line is less than a quarter of the wavelength of the electromagnetic wave at the working center frequency.

[0029] In a preferred embodiment, when the upper-stage power processing circuit is connected to the lower-stage power processing circuit, at least one second differential signal port of the upper-stage power processing circuit is connected to at least one first differential signal port of the lower-stage power processing circuit.

[0030] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: the isolation can be further improved compared with the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] FIG1 is a schematic structural diagram of a power processing circuit provided by one embodiment of the present invention;

[0033] FIG2 is a schematic diagram of the power processing circuit in FIG1 in a power splitter operating mode;

[0034] FIG3 is a schematic diagram of the power processing circuit in FIG1 in a combiner operating mode;

[0035] FIG4 is a schematic structural diagram of a power processing circuit provided in a second embodiment of the present invention;

[0036] FIG5 is a schematic structural diagram of a power processing circuit provided in a third embodiment of the present invention;

[0037] FIG6 is a schematic diagram of the structure of a power processing circuit provided in a fourth embodiment of the present invention;

[0038] 7 is a schematic structural diagram of a power processing circuit provided in Embodiment 5 of the present invention;

[0039] FIG8 is a schematic structural diagram of a power processing circuit provided in Example 6 of the present invention;

[0040] FIG9 is a schematic diagram of an embodiment of a multi-stage power processing circuit provided in Embodiment 7 of the present invention;

[0041] FIG10 is a schematic diagram of an embodiment of a multi-stage power processing circuit provided in Embodiment 8 of the present invention;

[0042] FIG11 is a schematic diagram of an embodiment of a multi-stage power processing circuit provided in Embodiment 9 of the present invention;

[0043] FIG12 is a circuit diagram of the prior art in an experimental example provided by the present invention;

[0044] FIG13 is a diagram showing the port isolation test results of the prior art circuit in FIG12 ;

[0045] FIG14 is a circuit diagram of an embodiment of the present invention in an experimental example provided by the present invention;

[0046] FIG15 is a diagram showing the port isolation test results of the circuit according to the embodiment of the present invention in FIG14 . DETAILED DESCRIPTION

[0047] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] An embodiment of the present invention provides a power processing circuit, comprising: at least one level of power processing circuit, each level of power processing circuit comprising at least one group of power processing circuit modules;

[0049] Each group of power processing circuit modules includes a first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports, wherein the power processing unit includes N pairs of differential coupled lines, where N is greater than or equal to 2;

[0050] In the same-level power processing circuit, the positive port and the negative port of at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0051] The inventors have found through a large number of experiments that the above improvements can further enhance the isolation of the entire power processing circuit.

[0052] The specific implementation of the present application is described in detail below through multiple embodiments with only one-stage power processing circuit and multiple embodiments with two-stage power processing circuit.

[0053] Example 1

[0054] FIG1 is a schematic diagram illustrating the structure of a power processing circuit according to a first embodiment of the present invention. In this embodiment, the number N is 2. The circuit includes a first differential signal port 101, two second differential signal ports 1021 and 1022, and a power processing unit 103 connected between the first differential signal port 101 and the two second differential signal ports 1021 and 1022.

[0055] The first differential signal port 101 includes a positive port 101a and a negative port 101b, the second differential signal port 1021 includes a positive port 1021a and a negative port 1021b, and the second differential signal port 1022 includes a positive port 1022a and a negative port 1022b.

[0056] The power processing unit 103 includes two pairs of differential coupling lines, denoted as 1031 and 1032. The first pair of differential coupling lines 1031 includes a positive coupling line 1031a and a negative coupling line 1031b, and the second pair of differential coupling lines 1032 includes a positive coupling line 1032a and a negative coupling line 1032b.

[0057] The positive port 101a of the first differential signal port 101 is connected to the positive coupled line 1031a of the first pair of differential coupled lines 1031, and the negative port 101b of the first differential signal port 101 is connected to the negative coupled line 1032b of the second pair of differential coupled lines 1032. The negative coupled line 1031b of the first pair of differential coupled lines 1031 is connected to the positive coupled line 1032a of the second pair of differential coupled lines 1032, for example, in series.

[0058] The positive port 1021 a of the second differential signal port 1021 is connected to the positive coupled line 1031 a of the first pair of differential coupled lines 1031 , and the negative port 1021 b of the second differential signal port 1021 is connected to the negative coupled line 1032 b of the second pair of differential coupled lines 1032 .

[0059] The positive port 1022 a of the second differential signal port 1022 is connected to the positive coupled line 1032 a of the second pair of differential coupled lines 1032 , while the negative port 1022 b of the second differential signal port 1022 is connected to the negative coupled line 1031 b of the first pair of differential coupled lines 1031 .

[0060] It can be seen that in this embodiment, the positive port 1021a and the negative port 1021b of the second differential signal port 1021 are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, and the positive port 1022a and the negative port 1022b of the second differential signal port 1022 are also connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0061] In addition, the power processing circuit also includes an isolation module, which is disposed between like-pole ports of different second differential signal ports. For example, in the circuit shown in FIG1 , an isolation resistor serving as the isolation module is disposed between like-pole ports of different second differential signal ports. Specifically, two isolation resistors, R112a and R112b, are provided. Isolation resistor R112a is disposed between the positive port 1021a of the second differential signal port 1021 and the positive port 1022a of the second differential signal port 1022, and isolation resistor R112b is disposed between the negative port 1021b of the second differential signal port 1021 and the negative port 1022b of the second differential signal port 1022.

[0062] Experiments have shown that by setting up the isolation module and connecting the positive port and the negative port of at least one second differential signal port to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, the isolation can be further improved compared to the existing technology.

[0063] In addition, in addition to being implemented using an isolation resistor, the above isolation module can also be implemented by connecting an isolation resistor and a capacitor in parallel.

[0064] FIG2 shows a schematic diagram of the power processing circuit in FIG1 in power splitter mode, in which the first differential signal port serves as a differential signal input port, and the second differential signal port serves as a differential signal output port. The positive port 101a and negative port 101b of the first differential signal port 101 in FIG1 are replaced in FIG2 by the positive input port I101a and negative input port I101b representing differential signal input port I101. The positive port 1021a and negative port 1021b of the second differential signal port 1021 in FIG1 are replaced in FIG2 by the positive output port O1021a and negative output port O1021b representing differential signal output port O1021. The positive port 1022a and negative port 1022b of the second differential signal port 1022 in FIG1 are represented by the positive output port O1022a and negative output port O1022b of the differential signal output port O1022 in FIG2. Other circuit elements with the same reference numerals as in FIG1 are the same elements and are not repeated here.

[0065] FIG3 shows a schematic diagram of the power processing circuit in FIG1 in combiner mode, in which the first differential signal port serves as the differential signal output port for the combined signal, and the second differential signal port serves as the differential signal input port. The positive port 101a and negative port 101b of the first differential signal port 101 in FIG1 are replaced in FIG3 by the positive output port O101a and negative output port O101b representing the differential signal output port O101. The positive port 1021a and negative port 1021b of the second differential signal port 1021 in FIG1 are replaced in FIG3 by the positive input port I1021a and negative input port I1021b representing the differential signal input port I1021. The positive port 1022a and negative port 1022b of the second differential signal port 1022 in FIG1 are represented by the positive input port I1022a and negative input port I1022b of the differential signal output port I1022 in FIG3. Other circuit elements with the same reference numerals as in FIG1 are the same elements and are not repeated here.

[0066] In the power processing circuit provided in this first embodiment, in-band insertion loss, return loss, and isolation can be optimized by varying the electrical length of the differential coupled lines, the even-mode impedance Ze, the odd-mode impedance Zo, and the isolation module. This eliminates the need for conventional quarter-wavelength coupled lines, allowing the length of the differential coupled lines in this embodiment to be less than a quarter wavelength of the operating center frequency, thereby reducing the overall circuit size, increasing integration, and improving insertion loss performance. By varying the electrical length of the differential coupled lines, the even-mode impedance Ze, and the odd-mode impedance Zo, the operating bandwidth can be controlled.

[0067] It should also be noted that in this embodiment, "positive" and "negative" are relative concepts and may simply indicate "opposite phase" or "different phase" between corresponding port signals. The circuit in this embodiment can still function normally by swapping the "positive" and "negative" positions, and this variation remains within the scope of protection of this application.

[0068] Example 2

[0069] FIG4 is a schematic diagram showing the structure of a power processing circuit according to a second embodiment of the present invention. In this embodiment, the number N is 3. The circuit includes a first differential signal port 201, three second differential signal ports 2021, 2022, and 2023, and a power processing unit 203 connected between the first differential signal port 201 and the three second differential signal ports 2021, 2022, and 2023.

[0070] The first differential signal port 201 includes a positive terminal 201a and a negative terminal 201b. The second differential signal port 2021 includes a positive terminal 2021a and a negative terminal 2021b. The second differential signal port 2022 includes a positive terminal 2022a and a negative terminal 2022b. The second differential signal port 2023 includes a positive terminal 2023a and a negative terminal 2023b.

[0071] The power processing unit 203 includes three pairs of differential coupled lines, designated 2031, 2032, and 2033. The first pair of differential coupled lines 2031 includes a positive coupled line 2031a and a negative coupled line 2031b. The second pair of differential coupled lines 2032 includes a positive coupled line 2032a and a negative coupled line 2032b. The third pair of differential coupled lines 2033 includes a positive coupled line 2033a and a negative coupled line 2033b.

[0072] The positive port 201a of the first differential signal port 201 is connected to the positive coupled line 2031a of the first pair of differential coupled lines 2031, and the negative port 201b of the first differential signal port 201 is connected to the negative coupled line 2033b of the third pair of differential coupled lines 2033. The negative coupled line 2031b of the first pair of differential coupled lines 2031 is connected to the positive coupled line 2032a of the second pair of differential coupled lines 2032, for example, in series. The negative coupled line 2032b of the second pair of differential coupled lines 2032 is connected to the positive coupled line 2033a of the third pair of differential coupled lines 2033, for example, in series.

[0073] The positive terminal 2021a of the second differential signal port 2021 is connected to the positive coupled line 2031a of the first pair of differential coupled lines 2031 , while the negative terminal 2021b of the second differential signal port 2021 is connected to the negative coupled line 2032b of the second pair of differential coupled lines 2032 .

[0074] The positive terminal 2022a of the second differential signal port 2022 is connected to the positive coupled line 2032a of the second pair of differential coupled lines 2032 , while the negative terminal 2022b of the second differential signal port 2022 is connected to the negative coupled line 2033b of the third pair of differential coupled lines 2033 .

[0075] The positive terminal 2023a of the second differential signal port 2023 is connected to the positive coupled line 2033a of the third pair of differential coupled lines 2033 , while the negative terminal 2023b of the second differential signal port 2023 is connected to the negative coupled line 2031b of the first pair of differential coupled lines 2031 .

[0076] It can be seen that, in this embodiment, the positive port and the negative port in each second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0077] In addition, the power processing circuit also includes an isolation module, which is arranged between the same-pole ports of different second differential signal ports. For example, in the circuit shown in Figure 4, the isolation resistor serving as the isolation module is arranged between the same-pole ports of different second differential signal ports. Specifically, a total of six isolation resistors R212a, R212b, R223a, R223b, R213a, and R213b are provided. The isolation resistor R212a is arranged between the positive port 2021a of the second differential signal port 2021 and the positive port 2022a of the second differential signal port 2022, and the isolation resistor R223b is arranged between the negative port 2021b of the second differential signal port 2021 and the negative port 2022b of the second differential signal port 2022. The isolation resistor R223a is disposed between the positive terminal 2022a of the second differential signal port 2022 and the positive terminal 2023a of the second differential signal port 2023. The isolation resistor R213b is disposed between the negative terminal 2022b of the second differential signal port 2022 and the negative terminal 2023b of the second differential signal port 2023. The isolation resistor R213a is disposed between the positive terminal 2021a of the second differential signal port 2021 and the positive terminal 2023a of the second differential signal port 2023. The isolation resistor R212b is disposed between the negative terminal 2021b of the second differential signal port 2021 and the negative terminal 2023b of the second differential signal port 2023.

[0078] Experiments have shown that by setting up the isolation module and connecting the positive port and the negative port of at least one second differential signal port to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, the isolation can be further improved compared to the existing technology.

[0079] In the power processing circuit provided in the second embodiment, in-band insertion loss, return loss, and isolation can be optimized by varying the electrical length of the differential coupled lines, the even-mode impedance Ze, the odd-mode impedance Zo, and the isolation module. This eliminates the need for conventional quarter-wavelength coupled lines, allowing the length of the differential coupled lines in the present embodiment to be less than a quarter wavelength of the operating center frequency, thereby reducing the overall circuit size, increasing integration, and improving insertion loss performance. By varying the electrical length of the differential coupled lines, the even-mode impedance Ze, and the odd-mode impedance Zo, the operating bandwidth can be controlled.

[0080] It should also be noted that in this embodiment, "positive" and "negative" are relative concepts and may simply indicate "opposite phase" or "different phase" between corresponding port signals. The circuit in this embodiment can still function normally by swapping the "positive" and "negative" positions, and this variation remains within the scope of protection of this application.

[0081] In this embodiment, the first differential signal port of the circuit is used as a differential signal input port, and the second differential signal port is used as a differential signal output port. Then, the entire circuit is equivalent to a power divider.

[0082] In this embodiment, the first differential signal port of the circuit is used as a differential signal output port of the combined signal, and the second differential signal port is used as a differential signal input port. Then, the entire circuit is equivalent to a combiner.

[0083] Example 3

[0084] FIG5 is a schematic diagram illustrating the structure of a power processing circuit according to a third embodiment of the present invention. This differs from the embodiment shown in FIG4 primarily in that the positive and negative ports of each second signal port are connected to the positive and negative coupling lines of different pairs of differential coupling lines. Components in FIG5 that are numbered the same as those in FIG4 are identical and are not further described here.

[0085] The embodiment shown in FIG5 differs primarily from the embodiment shown in FIG4 in that the negative terminal 2021b of the second differential signal port 2021 is connected to the negative coupled line 2033b of the third pair of differential coupled lines 2033. The negative terminal 2022b of the second differential signal port 2022 is connected to the negative coupled line 2031b of the first pair of differential coupled lines 2031. The negative terminal 2023b of the second differential signal port 2023 is connected to the negative coupled line 2032b of the second pair of differential coupled lines 2032. Accordingly, an isolation resistor R213b is provided between the negative terminal 2021b of the second differential signal port 2021 and the negative terminal 2022b of the second differential signal port 2022. An isolation resistor R212b is provided between the negative terminal 2022b of the second differential signal port 2022 and the negative terminal 2023b of the second differential signal port 2023. The isolation resistor R223 b is disposed between the negative terminal 2021 b of the second differential signal port 2021 and the negative terminal 2023 b of the second differential signal port 2023 .

[0086] Example 4

[0087] FIG6 is a schematic diagram illustrating the structure of a power processing circuit according to a fourth embodiment of the present invention. This circuit differs from the embodiments shown in FIG4 and FIG5 primarily in that not every positive and negative port in each second differential signal port is connected to the positive and negative coupled lines of different pairs of differential coupled lines. Components in FIG6 that are numbered the same as those in FIG4 and FIG5 are identical and are not further described here.

[0088] Specifically, in this embodiment, the positive port 2021a of the second differential signal port 2021 is connected to the positive coupled line 2031a of the first pair of differential coupled lines 2031 , and the negative port 2021b of the second differential signal port 2021 is connected to the negative coupled line 2032b of the second pair of differential coupled lines 2032 .

[0089] The positive terminal 2022a of the second differential signal port 2022 is connected to the positive coupled line 2032a of the second pair of differential coupled lines 2032 , while the negative terminal 2022b of the second differential signal port 2022 is connected to the negative coupled line 2031b of the first pair of differential coupled lines 2031 .

[0090] The positive terminal 2023a of the second differential signal port 2023 is connected to the positive coupled line 2033a of the third pair of differential coupled lines 2033 , while the negative terminal 2023b of the second differential signal port 2023 is connected to the negative coupled line 2033b of the third pair of differential coupled lines 2033 .

[0091] Correspondingly, the isolation resistor R212b is disposed between the negative terminal 2021b of the second differential signal port 2021 and the negative terminal 2022b of the second differential signal port 2022. The isolation resistor R213b is disposed between the negative terminal 2022b of the second differential signal port 2022 and the negative terminal 2023b of the second differential signal port 2023. The isolation resistor R223b is disposed between the negative terminal 2021b of the second differential signal port 2021 and the negative terminal 2023b of the second differential signal port 2023.

[0092] It can be seen that the positive port and negative port of the second differential signal port 2023 are connected to the positive coupling line and negative coupling line of the same pair of differential coupling lines, while the positive port and negative port of the other two second differential signal ports are connected to the positive coupling line and negative coupling line of different pairs of differential coupling lines.

[0093] Those skilled in the art should be able to understand that the second differential signal port whose positive port and negative port are connected to the positive coupling line and negative coupling line of the same pair of differential coupling lines can be selected arbitrarily from the three second differential signal ports, while the positive port and negative port of the other two second differential signal ports are connected to the positive coupling line and negative coupling line of different pairs of differential coupling lines.

[0094] For example, in an alternative embodiment, the positive and negative ports of the second differential signal port 2021 can be connected to the positive and negative coupling lines of the same pair of differential coupling lines (e.g., the first pair of differential coupling lines), while the positive and negative ports of the other two second differential signal ports (i.e., the second differential signal ports 2022 and 2023) can be connected to the positive and negative coupling lines of different pairs of differential coupling lines. Another alternative embodiment is described in the following embodiment 5.

[0095] Example 5

[0096] In another alternative embodiment, as shown in the structural diagram of the power processing circuit of Example 5 in Figure 7, the positive port 2022a and the negative port 2022b of the second differential signal port 2022 can be connected to the positive coupling line 2032a and the negative coupling line 2032b of the same pair of differential coupling lines (such as the second pair of differential coupling lines), while the positive port and the negative port of the other two second differential signal ports (i.e., the second differential signal ports 2021 and 2023) can be connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0097] Specifically, the positive port 2021a of the second differential signal port 2021 is connected to the positive coupled line 2031a of the first pair of differential coupled lines 2031 , and the negative port 2021b of the second differential signal port 2021 is connected to the negative coupled line 2033b of the third pair of differential coupled lines 2033 .

[0098] The positive terminal 2023a of the second differential signal port 2023 is connected to the positive coupled line 2033a of the third pair of differential coupled lines 2033 , while the negative terminal 2023b of the second differential signal port 2023 is connected to the negative coupled line 2031b of the first pair of differential coupled lines 2031 .

[0099] Correspondingly, the isolation resistor R223b is disposed between the negative terminal 2023b of the second differential signal port 2021 and the negative terminal 2022b of the second differential signal port 2022. The isolation resistor R212b is disposed between the negative terminal 2022b of the second differential signal port 2022 and the negative terminal 2023b of the second differential signal port 2023. The isolation resistor R213b is disposed between the negative terminal 2021b of the second differential signal port 2021 and the negative terminal 2023b of the second differential signal port 2023.

[0100] Example 6

[0101] FIG8 is a schematic diagram of the structure of a power processing circuit according to a sixth embodiment of the present invention. This circuit increases the number of second differential signal ports and the number of pairs of differential coupled lines in the power processing unit, represented by a number N. Specifically, the circuit includes a first differential signal port 601, N second differential signal ports 6031-603N, and a power processing unit 603 connected between the first differential signal port 601 and the N second differential signal ports 6021-602N. The number N is ≥ 2 and is a positive integer.

[0102] The first differential signal port 601 includes a positive port 601a and a negative port 601b. Each second differential signal port includes a positive port and a negative port. Specifically, the second differential signal port 6021 includes a positive port 6021a and a negative port 6021b. The second differential signal port 6022 includes a positive port 6022a and a negative port 6022b. Similarly, the second differential signal port 602i includes a positive port 602ia and a negative port 602ib. The second differential signal port 602i+1 includes a positive port 602i+1a and a negative port 602i+1b. The Nth differential signal port 602N includes a positive port 602Na and a negative port 602Nb.

[0103] The power processing unit 603 includes N pairs of differential coupled lines, denoted as 6031-603N. Each pair of differential coupled lines includes a positive coupled line and a negative coupled line. For example, the first pair of differential coupled lines 6031 includes a positive coupled line 6031a and a negative coupled line 6031b, the second pair of differential coupled lines 6032 includes a positive coupled line 6032a and a negative coupled line 6032b, and so on. The i-th pair of differential coupled lines 603i includes a positive coupled line 603ia and a negative coupled line 603ib, the i+1-th pair of differential coupled lines 603i+1 includes a positive coupled line 603i+1a and a negative coupled line 603i+1b, and the N-th pair of differential coupled lines 603N includes a positive coupled line 603Na and a negative coupled line 603Nb.

[0104] The positive terminal 601a of the first differential signal port 601 is connected to the positive coupling line 6031a of the first pair of differential coupling lines 6031, and the negative terminal 601b of the first differential signal port 601 is connected to the negative coupling line 603Nb of the Nth pair of differential coupling lines 603N. The negative coupling line 603ib of the i-th pair of differential coupling lines 603i is connected to the positive coupling line 603i+1a of the i+1-th pair of differential coupling lines 603i+1, for example, in series, where 1≤i <N。

[0105] The positive and negative ports of at least one of the N second differential signal ports 6021-602N are connected to the positive and negative coupled lines of different pairs of differential coupled lines. For example, the positive and negative ports of at least two of the N second differential signal ports 6021-602N are connected to the positive and negative coupled lines of different pairs of differential coupled lines.

[0106] In a preferred embodiment, as shown in FIG. 8, the positive and negative ports of each of the N second differential signal ports 6021-602N are connected to the positive and negative coupled lines of different pairs of differential coupled lines. Specifically, the positive port 6021a and the negative port 6021b of the second differential signal port 6021 are respectively connected to the positive coupled line 6031a in the first pair of differential coupled lines 6031 and the negative coupled line 6032b of the second pair of differential coupled lines 6032, and so on. The positive port 602ia and the negative port 602ib of the second differential signal port 602i are respectively connected to the positive coupled line 603ia in the i-th pair of differential coupled lines 603i and the negative coupled line 603i+1b of the i+1-th pair of differential coupled lines 603i+1, where 1≤i<N. The positive port 602Na and the negative port 602Nb of the second differential signal port 602N are respectively connected to the positive coupled line 603Na in the N-th pair of differential coupled lines 603N and the negative coupled line 6031b in the first pair of differential coupled lines 6031.

[0107] In addition, the power processing circuit in this embodiment further includes isolation modules disposed between the same-polarity ports of different second differential signal ports. For example, an isolation module is disposed between the positive ports of the i-th second differential signal port and the j-th second differential signal port, and an isolation module is also disposed between the negative ports of the i-th second differential signal port and the j-th second differential signal port, where 1≤i<N, 1≤j<N, and i≠j. In addition to being implemented using isolation resistors, the isolation modules can also be replaced by the parallel connection of isolation resistors and capacitors.

[0108] In the power processing circuit provided in this sixth embodiment, the in-band insertion loss, return loss, and isolation can be optimized by changing the electrical length, even-mode impedance Ze, odd-mode impedance Zo, and isolation modules of the differential coupled lines. Without using traditional quarter-wave coupled lines, the length of the differential coupled lines in the embodiments of the present application can be less than a quarter wavelength of the operating center frequency, thereby reducing the size of the entire circuit, increasing the integration level, and improving the insertion loss performance. By changing the electrical length, even-mode impedance Ze, and odd-mode impedance Zo of the differential coupled lines, the operating bandwidth can be controlled.

[0109] It should also be noted that in this embodiment, "positive" and "negative" are relative concepts and may simply indicate "opposite phase" or "different phase" between corresponding port signals. The circuit in this embodiment can still function normally by swapping the "positive" and "negative" positions, and this variation remains within the scope of protection of this application.

[0110] In this embodiment, the first differential signal port of the circuit is used as a differential signal output port of the combined signal, and the second differential signal port is used as a differential signal input port. Then, the entire circuit is equivalent to a combiner.

[0111] Example 7

[0112] 9 shows a schematic diagram of an embodiment of combining the power processing circuits in the above embodiments to form a multi-stage power processing circuit. The multi-stage power processing circuit includes two stages of power processing circuits, namely a first stage power processing circuit 7001 and a second stage power processing circuit 7002.

[0113] The structure of the first-stage power processing circuit 7001 is similar to that of the power processing circuit shown in FIG1 , and the value N in the first power processing circuit 7001 is selected to be 2. The first power processing circuit 7001 includes a first differential signal port 701 and two second differential signal ports 7021 and 7022 , and a power processing unit 703 connected between the first differential signal port 701 and the two second differential signal ports 7021 and 7022 .

[0114] The first differential signal port 701 includes a positive port 701a and a negative port 701b, the second differential signal port 7021 includes a positive port 7021a and a negative port 7021b, and the second differential signal port 7022 includes a positive port 7022a and a negative port 7022b.

[0115] The power processing unit 703 includes two pairs of differential coupling lines, denoted as 7031 and 7032. The first pair of differential coupling lines 7031 includes a positive coupling line 7031a and a negative coupling line 7031b, and the second pair of differential coupling lines 7032 includes a positive coupling line 7032a and a negative coupling line 7032b.

[0116] The positive port 701a of the first differential signal port 701 is connected to the positive coupled line 7031a of the first pair of differential coupled lines 7031 in the power processing unit 703, and the negative port 701b of the first differential signal port 701 is connected to the negative coupled line 7032b of the second pair of differential coupled lines 7032 in the power processing unit 703. The negative coupled line 7031b of the first pair of differential coupled lines 7031 is connected to the positive coupled line 7032a of the second pair of differential coupled lines 7032, for example, in series.

[0117] The positive terminal 7021a of the second differential signal port 7021 is connected to the positive coupled line 7031a of the first pair of differential coupled lines 7031 , while the negative terminal 7021b of the second differential signal port 7021 is connected to the negative coupled line 7032b of the second pair of differential coupled lines 7032 .

[0118] The positive terminal 7022a of the second differential signal port 7022 is connected to the positive coupled line 7032a of the second pair of differential coupled lines 7032 , while the negative terminal 7022b of the second differential signal port 7022 is connected to the negative coupled line 7031b of the first pair of differential coupled lines 7031 .

[0119] It can be seen that in the first-stage power processing circuit, the positive port 7021a and the negative port 7021b of the second differential signal port 7021 are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, and the positive port 7022a and the negative port 7022b of the second differential signal port 7022 are also connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0120] In addition, the first-stage power processing circuit also includes an isolation module, which is disposed between like-pole ports of different second differential signal ports. For example, in the circuit shown in FIG9 , an isolation resistor serving as the isolation module is disposed between like-pole ports of different second differential signal ports. Specifically, two isolation resistors, R712a and R712b, are provided: isolation resistor R712a is disposed between the positive port 7021a of the second differential signal port 7021 and the positive port 7022a of the second differential signal port 7022; and isolation resistor R712b is disposed between the negative port 7021b of the second differential signal port 7021 and the negative port 7022b of the second differential signal port 7022.

[0121] With this design, the isolation between ports of the first-stage power processing circuit 7001 is further improved.

[0122] The following describes the detailed structure of the second-stage power processing circuit 7002. The second-stage power processing circuit 7002 is divided into two groups of power processing circuit modules, denoted as 70021 and 70022 respectively.

[0123] The value N corresponding to the first group of power processing circuit modules 70021 is selected as 2. The first group of power processing circuit modules 70021 includes a first differential signal port, which is the same port as or connected to the second differential signal port 7021 of the first-stage power processing circuit 7001. Specifically, the positive and negative ports of the first differential signal port of the first group of power processing circuit modules 70021 are the same port as or connected to the positive port 7021a and negative port 7021b of the second differential signal port 7021 of the first-stage power processing circuit 7001. Therefore, in FIG9 , for simplicity, the first differential signal port of the first group of power processing circuit modules 70021 is no longer individually labeled, but instead directly reuses the reference numerals 7021a and 7021b of the positive and negative ports of the second differential signal port 7021 of the first-stage power processing circuit 7001.

[0124] The first group of power processing circuit modules 70021 further includes two second differential signal ports 70211 and 70212 , and a power processing unit 70310 disposed between the first differential signal port 7021 and the two second differential signal ports 70211 and 70212 .

[0125] The second differential signal port 70211 includes a positive terminal 70211 a and a negative terminal 70211 b , and the second differential signal port 70212 includes a positive terminal 70212 a and a negative terminal 70212 b .

[0126] The power processing unit 70310 includes two pairs of differential coupling lines, denoted as 70311 and 70312. The first pair of differential coupling lines 70311 includes a positive coupling line 70311a and a negative coupling line 70311b, and the second pair of differential coupling lines 70312 includes a positive coupling line 70312a and a negative coupling line 70312b.

[0127] The positive port 7021a of the first differential signal port 7021 is connected to the positive coupled line 70311a of the first pair of differential coupled lines 70311 in the power processing unit 70310, and the negative port 7021b of the first differential signal port 7021 is connected to the negative coupled line 70312b of the second pair of differential coupled lines 70312 in the power processing unit 70310. The negative coupled line 70311b of the first pair of differential coupled lines 70311 is connected to the positive coupled line 70312a of the second pair of differential coupled lines 70312, for example, in series.

[0128] The value N corresponding to the second power processing circuit module 70022 is selected as 2. The second power processing circuit module 70022 includes a first differential signal port, which is the same port as or connected to the second differential signal port 7022 of the first-stage power processing circuit 7001. Specifically, the positive and negative ports of the first differential signal port of the second power processing circuit module 70022 are the same port as or connected to the positive port 7022a and negative port 7022b of the second differential signal port 7022 of the first-stage power processing circuit 7001. Therefore, in FIG9 , for simplicity, the first differential signal port of the second power processing circuit module 70022 is no longer individually labeled, but is instead directly reused with the reference numerals 7022a and 7022b of the second differential signal port 7022 of the first-stage power processing circuit 7001.

[0129] The second power processing circuit module 70022 further includes two second differential signal ports 70221 and 70222 , and a power processing unit 70320 disposed between the first differential signal port 7021 and the two second differential signal ports 70221 and 70222 .

[0130] The second differential signal port 70221 includes a positive terminal 70221 a and a negative terminal 70221 b , and the second differential signal port 70222 includes a positive terminal 70222 a and a negative terminal 70222 b .

[0131] The power processing unit 70320 includes two pairs of differential coupling lines, denoted as 70321 and 70322. The first pair of differential coupling lines 70321 includes a positive coupling line 70321a and a negative coupling line 70321b, and the second pair of differential coupling lines 70322 includes a positive coupling line 70322a and a negative coupling line 70322b.

[0132] The positive port 7022a of the first differential signal port 7022 is connected to the positive coupled line 70321a of the first pair of differential coupled lines 70321 in the power processing unit 70320, and the negative port 7022b of the first differential signal port 7022 is connected to the negative coupled line 70322b of the second pair of differential coupled lines 70322 in the power processing unit 70320. The negative coupled line 70321b of the first pair of differential coupled lines 70321 is connected to the positive coupled line 70322a of the second pair of differential coupled lines 70322, for example, in series.

[0133] The following describes the connection relationship between the second differential signal ports 70211 , 70212 , 70221 , and 70222 in the two groups of power processing circuit modules 70021 and 70022 and the power processing units 70310 and 70320 .

[0134] In this embodiment, the positive ports and negative ports of the second differential signal ports 70211, 70212, 70221 and 70222 in the two groups of power processing circuit modules 70021 and 70022 are all connected to the positive coupling lines and negative coupling lines of different pairs of differential coupling lines. The positive port and negative port of the second differential signal port located in one group of power processing circuit modules can be respectively connected to the positive port and negative port of the differential coupling lines in the group of power processing circuit modules and the differential coupling lines in another group of power processing circuit modules. That is to say, when the second differential signal port is connected to the positive coupling lines and negative coupling lines of different pairs of differential coupling lines, it can cross different groups of power processing circuit modules.

[0135] Specifically, in this embodiment, the positive port 70211a of the second differential signal port 70211 in the first group of power processing circuit modules 70021 is connected to the positive coupling line 70311a in the first pair of differential coupling lines 70311 in the first group of power processing circuit modules 70021, and the negative port 70211b of the second differential signal port 70211 in the first group of power processing circuit modules 70021 is connected to the negative coupling line 70322b in the second pair of differential coupling lines 70322 in the second group of power processing circuit modules 70022.

[0136] The positive port 70212a of the second differential signal port 70212 in the first group of power processing circuit modules 70021 is connected to the positive coupling line 70312a of the second pair of differential coupling lines 70312 in the first group of power processing circuit modules 70021, and the negative port 70212b of the second differential signal port 70212 in the first group of power processing circuit modules 70021 is connected to the negative coupling line 70311b of the first pair of differential coupling lines 70311 in the first group of power processing circuit modules 70021.

[0137] The positive port 70221a of the second differential signal port 70221 in the second group of power processing circuit modules 70022 is connected to the positive coupling line 70321a of the first pair of differential coupling lines 70321 in the second group of power processing circuit modules 70022, and the negative port 70221b of the second differential signal port 70221 in the second group of power processing circuit modules 70022 is connected to the negative coupling line 70312b of the second pair of differential coupling lines 70312 in the first group of power processing circuit modules 70021.

[0138] The positive port 70222a of the second differential signal port 70222 in the second group of power processing circuit modules 70022 is connected to the positive coupling line 70322a of the second pair of differential coupling lines 70322 in the second group of power processing circuit modules 70022, and the negative port 70222b of the second differential signal port 70222 in the second group of power processing circuit modules 70022 is connected to the negative coupling line 70321b of the first pair of differential coupling lines 70321 in the second group of power processing circuit modules 70022.

[0139] In addition, the power processing circuit further includes an isolation module, which is disposed between like-pole ports of different second differential signal ports. In this embodiment, the isolation module is not only disposed between like-pole ports of different second differential signal ports within the same group of power processing circuit modules, but can also be disposed between like-pole ports of second differential signal ports within different groups of power processing circuit modules. To this end, the isolation module can also span different groups of power processing circuit modules. In this embodiment, the isolation module is an isolation resistor. For example, isolation resistor R7112a is disposed between the positive port 70211a of the second differential signal port 70211 and the positive port 70212a of the second differential signal port 70212; isolation resistor R7112b is disposed between the negative port 70212b of the second differential signal port 70212 and the negative port 70221b of the second differential signal port 70221.

[0140] In the power processing circuit provided in this embodiment, in-band insertion loss, return loss, and isolation can be optimized by varying the electrical length of the differential coupled lines, the even-mode impedance Ze, the odd-mode impedance Zo, and the isolation module. This eliminates the need for conventional quarter-wavelength coupled lines, allowing the length of the differential coupled lines in this embodiment to be less than a quarter wavelength of the operating center frequency, thereby reducing the overall circuit size, increasing integration, and improving insertion loss performance. By varying the electrical length of the differential coupled lines, the even-mode impedance Ze, and the odd-mode impedance Zo, the operating bandwidth can be controlled.

[0141] It should also be noted that in this embodiment, "positive" and "negative" are relative concepts and may simply indicate "opposite phase" or "different phase" between corresponding port signals. The circuit in this embodiment can still function normally by swapping the "positive" and "negative" positions, and this variation remains within the scope of protection of this application.

[0142] In this embodiment, the first differential signal port of the circuit is used as a differential signal input port, and the second differential signal port is used as a differential signal output port. Then, the entire circuit is equivalent to a power divider.

[0143] In this embodiment, the first differential signal port of the circuit is used as a differential signal output port of the combined signal, and the second differential signal port is used as a differential signal input port. Then, the entire circuit is equivalent to a combiner.

[0144] Example 8

[0145] FIG10 is a schematic diagram of another embodiment of a multi-stage power processing circuit. This differs from the embodiment shown in FIG9 primarily in that, in this embodiment, when the positive and negative ports of the second differential signal port are connected to the positive and negative coupled lines of different pairs of differential coupled lines, they are connected only to the positive and negative coupled lines of different pairs of differential coupled lines within the power processing circuit module in the group in which the second differential signal port is located, i.e., they do not cross different groups of power processing circuit modules.

[0146] Therefore, in this embodiment, only the connection relationship between the second differential signal ports 70211 , 70212 , 70221 and 70222 in the two groups of power processing circuit modules 70021 and 70022 and the power processing units 70310 and 70320 is specifically described.

[0147] In this embodiment, the positive port 70211a of the second differential signal port 70211 in the first group of power processing circuit modules 70021 is connected to the positive coupling line 70311a of the first pair of differential coupling lines 70311 in the first group of power processing circuit modules 70021, and the negative port 70211b of the second differential signal port 70211 in the first group of power processing circuit modules 70021 is connected to the negative coupling line 70312b of the second pair of differential coupling lines 70312 in the first group of power processing circuit modules 70021.

[0148] The positive port 70212a of the second differential signal port 70212 in the first group of power processing circuit modules 70021 is connected to the positive coupling line 70312a of the second pair of differential coupling lines 70312 in the first group of power processing circuit modules 70021, and the negative port 70212b of the second differential signal port 70212 in the first group of power processing circuit modules 70021 is connected to the negative coupling line 70311b of the first pair of differential coupling lines 70311 in the first group of power processing circuit modules 70021.

[0149] The positive port 70221a of the second differential signal port 70221 in the second group of power processing circuit modules 70022 is connected to the positive coupling line 70321a in the first pair of differential coupling lines 70321 in the second group of power processing circuit modules 70022, and the negative port 70221b of the second differential signal port 70221 in the second group of power processing circuit modules 70022 is connected to the negative coupling line 70322b in the second pair of differential coupling lines 70322 in the second group of power processing circuit modules 70022.

[0150] The positive port 70222a of the second differential signal port 70222 in the second group of power processing circuit modules 70022 is connected to the positive coupling line 70322a of the second pair of differential coupling lines 70322 in the second group of power processing circuit modules 70022, and the negative port 70222b of the second differential signal port 70222 in the second group of power processing circuit modules 70022 is connected to the negative coupling line 70321b of the first pair of differential coupling lines 70321 in the second group of power processing circuit modules 70022.

[0151] It should be noted that in this embodiment, the two groups of power processing circuit modules contain the same number of pairs of differential coupled lines and the same number of second differential signal ports. From this perspective, the structures of the two groups of power processing circuit modules have a certain degree of symmetry. In alternative embodiments, the two groups of power processing circuit modules can also be designed to contain different numbers of pairs of differential coupled lines. For example, the second group of power processing circuit modules can be designed to contain three pairs of differential coupled lines, and accordingly, this group of power processing circuit modules can be provided with three second differential signal ports. In other words, when the same level of power processing circuit includes multiple groups of power processing circuit modules, the value N (i.e., the number of second differential signal ports and the number of pairs of differential coupled lines) can be set to be different for at least two of the groups of power processing circuit modules.

[0152] Embodiment 9

[0153] FIG11 shows a schematic diagram of another embodiment of a multi-stage power processing circuit, which differs from the embodiment shown in FIG10 mainly in that only one second differential signal port in the first-stage power processing circuit 8001 is further connected to the second-stage power processing circuit 8002 .

[0154] Specifically, the multi-stage power processing circuit includes two stages of power processing circuits, namely a first stage power processing circuit 8001 and a second stage power processing circuit 8002 .

[0155] The structure of the first-stage power processing circuit 8001 is similar to that of the first-stage power processing circuit shown in FIG10 , and the corresponding value N is selected as 2. The first-stage power processing circuit 8001 includes a first differential signal port 801 and two second differential signal ports 8021 and 8022 , and a power processing unit 803 connected between the first differential signal port 801 and the two second differential signal ports 8021 and 8022 .

[0156] The first differential signal port 801 includes a positive port 801a and a negative port 801b, the second differential signal port 8021 includes a positive port 8021a and a negative port 8021b, and the second differential signal port 8022 includes a positive port 8022a and a negative port 8022b.

[0157] The power processing unit 803 includes two pairs of differential coupling lines, denoted as 8031 ​​and 8032. The first pair of differential coupling lines 8031 ​​includes a positive coupling line 8031a and a negative coupling line 8031b, and the second pair of differential coupling lines 8032 includes a positive coupling line 8032a and a negative coupling line 8032b.

[0158] The positive port 801a of the first differential signal port 801 is connected to the positive coupled line 8031a of the first pair of differential coupled lines 8031 ​​in the power processing unit 803, and the negative port 801b of the first differential signal port 801 is connected to the negative coupled line 8032b of the second pair of differential coupled lines 8032 in the power processing unit 803. The negative coupled line 8031b of the first pair of differential coupled lines 8031 ​​is connected to the positive coupled line 8032a of the second pair of differential coupled lines 8032, for example, in series.

[0159] The positive port 8021a of the second differential signal port 8021 is connected to the positive coupled line 8031a of the first pair of differential coupled lines 8031 ​​, while the negative port 8021b of the second differential signal port 8021 is connected to the negative coupled line 8032b of the second pair of differential coupled lines 8032 .

[0160] The positive port 8022a of the second differential signal port 8022 is connected to the positive coupled line 8032a of the second pair of differential coupled lines 8032 , while the negative port 8022b of the second differential signal port 8022 is connected to the negative coupled line 8031b of the first pair of differential coupled lines 8031 ​​.

[0161] It can be seen that in the first-stage power processing circuit, the positive port 8021a and the negative port 8021b of the second differential signal port 8021 are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, and the positive port 8022a and the negative port 8022b of the second differential signal port 8022 are also connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

[0162] In addition, the first-stage power processing circuit also includes an isolation module, which is disposed between like-pole ports of different second differential signal ports. For example, in the circuit shown in FIG11 , an isolation resistor serving as the isolation module is disposed between like-pole ports of different second differential signal ports. Specifically, two isolation resistors, R812a and R812b, are provided: isolation resistor R812a is disposed between the positive port 8021a of the second differential signal port 8021 and the positive port 8022a of the second differential signal port 8022; and isolation resistor R812b is disposed between the negative port 8021b of the second differential signal port 8021 and the negative port 8022b of the second differential signal port 8022.

[0163] With this design, the isolation between ports of the first-stage power processing circuit 8001 is further improved.

[0164] The following describes the detailed structure of the second-stage power processing circuit 8002. In this embodiment, the power processing circuit 8002 has only one set of power processing circuit modules, denoted as 80021.

[0165] The value N corresponding to the power processing circuit module 80021 is selected as 2.

[0166] The power processing circuit module 80021 includes a first differential signal port, which is the same port as or connected to the second differential signal port 8021 of the first-stage power processing circuit 8001. Specifically, the positive and negative ports of the first differential signal ports of the first group of power processing circuit modules 80021 are the same port as or connected to the positive port 8021a and negative port 8021b of the second differential signal port 8021 of the first-stage power processing circuit 8001. Therefore, in FIG11 , for simplicity, the first differential signal ports of the first group of power processing circuit modules 80021 are no longer individually labeled, but instead directly reuse the reference numerals 8021a and 8021b of the positive and negative ports of the second differential signal port 8021 of the first-stage power processing circuit 8001.

[0167] The power processing circuit module 80021 further includes two second differential signal ports 80211 and 80212 , and a power processing unit 80310 disposed between the first differential signal port 8021 and the two second differential signal ports 80211 and 80212 .

[0168] The second differential signal port 80211 includes a positive terminal 80211 a and a negative terminal 80211 b , and the second differential signal port 80212 includes a positive terminal 80212 a and a negative terminal 80212 b .

[0169] The power processing unit 80310 includes two pairs of differential coupled lines, denoted as 80311 and 80312. The first pair of differential coupled lines 80311 includes a positive coupled line 80311a and a negative coupled line 80311b, and the second pair of differential coupled lines 80312 includes a positive coupled line 80312a and a negative coupled line 80312b.

[0170] The positive port 8021a of the first differential signal port 8021 is connected to the positive coupled line 80311a of the first pair of differential coupled lines 80311 in the power processing unit 80310, and the negative port 8021b of the first differential signal port 8021 is connected to the negative coupled line 80312b of the second pair of differential coupled lines 80312 in the power processing unit 80310. The negative coupled line 80311b of the first pair of differential coupled lines 80311 is connected to the positive coupled line 80312a of the second pair of differential coupled lines 80312, for example, in series.

[0171] The following describes the connection relationship between the second differential signal ports 800211 and 80212 in the power processing circuit module 80021 and the power processing unit 80310.

[0172] In this embodiment, the positive port 80211a of the second differential signal port 80211 in the power processing circuit module 80021 is connected to the positive coupling line 80311a of the first pair of differential coupling lines 80311 in the power processing circuit module 80021, and the negative port 80211b of the second differential signal port 80211 in the power processing circuit module 80021 is connected to the negative coupling line 80312b of the second pair of differential coupling lines 80312 in the power processing circuit module 80021.

[0173] The positive port 80212a of the second differential signal port 80212 in the power processing circuit module 80021 is connected to the positive coupling line 80312a of the second pair of differential coupling lines 80312 in the power processing circuit module 80021, and the negative port 80212b of the second differential signal port 80212 in the power processing circuit module 80021 is connected to the negative coupling line 80311b of the first pair of differential coupling lines 80311 in the power processing circuit module 80021.

[0174] In addition, the second-stage power processing circuit 8002 further includes an isolation module, which is disposed between like-polarity ports of different second differential signal ports in the second-stage power processing circuit 8002. In this embodiment, the isolation module is implemented using isolation resistors. Specifically, an isolation resistor R8121a is disposed between the positive port 80211a of the second differential signal port 80211 and the positive port 80212a of the second differential signal port 80212, and an isolation resistor R8121b is disposed between the negative port 80211b of the second differential signal port 80211 and the negative port 80212b of the second differential signal port 80212.

[0175] In each of the above embodiments, based on the actual needs of the interface, at least the first differential signal port can be connected to a balun to achieve conversion between single-ended signals and differential signals; or at least one second differential signal port can be connected to a balun to achieve conversion between single-ended signals and differential signals.

[0176] Experimental Example 1

[0177] Figure 12 shows a circuit schematic and device parameter selection results for a prior art solution (Chinese patent application number CN116632488B, entitled "A Differential Power Splitter, Transmitter Link System, and Receiver Link System"). As shown in Figure 12, the positive and negative coupling lines of the first pair of differential coupling lines TL6 in this prior art solution are directly connected to the positive and negative ports P2 and P3 of the same second differential signal port, while the positive and negative coupling lines of the second pair of differential coupling lines TL7 are directly connected to the positive and negative ports P4 and P5 of the same second differential signal port.

[0178] The parameters of the various devices shown in Figure 12 are selected as follows:

[0179] The even-mode impedance of the first pair of differential coupled lines TL6 is Ze = 500 ohms, the odd-mode impedance is Zo = 12 ohms, and the electrical length is E = 25 degrees (relative to a 1 GHz electromagnetic wave). The isolation resistors R1 and R2 are both 25 ohms. The operating frequency is 1 GHz.

[0180] The scattering coefficient curve between the actual measurement ports is shown in FIG13 , which can reflect the isolation between the positive port and the negative port of the same second differential port.

[0181] FIG14 shows a circuit schematic diagram of a power processing circuit according to the first embodiment of the present invention and the device parameter selection results thereof. As shown in FIG14 , the positive port P2 and the negative port P3 correspond to the positive port 1021a and the negative port 1021b of the second differential signal port 1021 in the first embodiment of the present application; the positive port P4 and the negative port P5 correspond to the positive port 1022a and the negative port 1022b of the second differential signal port 1022 in FIG1 according to the first embodiment of the present application. The positive coupling line and the negative coupling line in the differential coupling line TL6 correspond to the positive coupling line 1031a and the negative coupling line 1031b of the first pair of differential coupling lines 1031 in FIG1 , respectively; the positive coupling line and the negative coupling line in the differential coupling line TL7 correspond to the positive coupling line 1032a and the negative coupling line 1032b of the second pair of differential coupling lines 1032 in FIG1 , respectively. The isolation resistor R1 corresponds to the isolation resistor R112 a in FIG. 1 , and the isolation resistor R2 corresponds to the isolation resistor R112 b in FIG. 1 .

[0182] The scattering coefficient curve between the actual measurement ports is shown in FIG15 , which can reflect the isolation between the positive port and the negative port of the same second differential port.

[0183] By comparing the two actual measurement results in FIG13 and FIG15 , it can be clearly seen that the isolation can be further improved by adopting the solution provided in the embodiment of the present application.

[0184] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without expending creative work.

[0185] The technical solutions provided by the present invention have been described in detail above. Specific examples have been used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is intended only to help understand the method and core concept of the present invention. At the same time, those skilled in the art will appreciate that the specific implementation methods and application scopes may vary based on the concepts of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A power processing circuit, characterized in that: include: At least one level of power processing circuit, each level of power processing circuit including at least one group of power processing circuit modules; Each group of power processing circuit modules includes a first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports, wherein the power processing unit includes N pairs of differential coupled lines, where N is greater than or equal to 2; In the same-level power processing circuit, the positive port and the negative port of at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

2. The power processing circuit according to claim 1, wherein: In the same-level power processing circuit, the positive port and the negative port in at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines. This is specifically implemented as follows: the positive port and the negative port in each second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines.

3. The power processing circuit according to claim 1, wherein: In the same-level power processing circuit, the positive port and the negative port of at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, specifically implemented as follows: The positive port and the negative port of the at least one second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines in different groups of power processing circuit modules.

4. The power processing circuit according to claim 1, wherein: Each stage of the power processing circuit further includes an isolation module, which is arranged between the same-polarity ports of different second differential signal terminals in the power processing circuit of this stage.

5. The power processing circuit according to claim 4, wherein: The isolation module is specifically provided between the same-polarity ports of different second differential signal terminals in the same group of power processing circuit modules.

6. The power processing circuit according to claim 5, wherein: The isolation module is further provided between the same-polarity ports of different second differential signal terminals in different groups of power processing circuit modules.

7. The power processing circuit according to claim 4, wherein: The isolation module includes an isolation resistor, or an isolation resistor and a capacitor in parallel.

8. The power processing circuit according to claim 1, wherein: In each power processing circuit module, the positive port of the first differential signal port is connected to the positive coupling line of the first pair of differential coupling lines, the negative port of the first differential signal port is connected to the negative coupling line of the Nth pair of differential coupling lines, and the negative coupling line of the i-th pair of differential coupling lines is connected to the positive coupling line of the i+1-th pair of differential coupling lines, where 1≤i <N。 9. The power processing circuit according to claim 1, wherein: The connection of the negative coupling line of the i-th pair of differential coupling lines with the positive coupling line of the (i+1)-th pair of differential coupling lines is specifically implemented as follows: The negative coupling line of the i-th pair of differential coupling lines is connected in series with the positive coupling line of the (i+1)-th pair of differential coupling lines.

10. The power processing circuit according to claim 1, wherein: The power processing circuit is a power divider.

11. The power processing circuit according to claim 10, wherein: The first differential signal port in each group of power processing circuit modules serves as a differential signal input port, and the second differential signal port serves as a differential signal output port.

12. The power processing circuit according to claim 1, wherein: The power processing circuit is a combiner.

13. The power processing circuit according to claim 12, wherein: The first differential signal port in each group of power processing circuit modules serves as a differential signal output port, and the second differential signal port serves as a differential signal input port.

14. The power processing circuit according to claim 1, wherein: At least the first differential signal port is connected to the balun.

15. The power processing circuit according to claim 1, wherein: At least one second differential signal port is connected to a balun.

16. The power processing circuit according to claim 1, wherein: The length of the differential coupling line is less than a quarter of the wavelength of the electromagnetic wave at the working center frequency.

17. The power processing circuit according to claim 1, wherein: When the upper-stage power processing circuit is connected to the lower-stage power processing circuit, at least one second differential signal port of the upper-stage power processing circuit is connected to at least one first differential signal port of the lower-stage power processing circuit.

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