Light-emitting device and image display apparatus

Abstract

A light-emitting device according to an embodiment of the present disclosure comprises: a first substrate that includes a first circuit; a second substrate that is laminated on the first substrate, includes a second circuit having a function different from that of the first circuit, and is electrically connected to the first substrate; and a third substrate that is laminated on the second substrate, includes a plurality of light-emitting elements arranged in an array, and is electrically connected to the second substrate.

Description

Light-emitting device and image display device

[0001] The present disclosure relates to a light-emitting device and an image display device including the same.

[0002] For example, Patent Document 1 discloses an image display element in which a nitride semiconductor layer constituting an LED is bonded to a drive circuit board.

[0003] Japanese Patent Application Laid-Open No. 2019-129226

[0004] In an image display element in which a nitride semiconductor layer constituting an LED is bonded to a drive circuit board, mounting various functional elements to enhance functionality increases the area of ​​the drive circuit board, leading to an increase in device size, which poses a problem in terms of commercial viability for wearable applications, for example.

[0005] It is desirable to provide a light emitting device and an image display device that can achieve both miniaturization and high functionality.

[0006] A light emitting device according to one embodiment of the present disclosure comprises a first substrate including a first circuit, a second substrate stacked on the first substrate, including a second circuit having a function different from that of the first circuit and electrically connected to the first substrate, and a third substrate stacked on the second substrate, including a plurality of light emitting elements arranged in an array and electrically connected to the second substrate.

[0007] An image display device according to an embodiment of the present disclosure includes a light-emitting device, and includes the light-emitting device according to the embodiment of the present disclosure as the light-emitting device.

[0008] In a light-emitting device and an image display device according to an embodiment of the present disclosure, a first circuit and a second circuit having different functions are formed separately on a first substrate and a second substrate, respectively. Furthermore, the first substrate, the second substrate, and a third substrate including a plurality of light-emitting elements arranged in an array are stacked and electrically connected to each other. This reduces the area of ​​the drive circuit substrate compared to the image display device described in the above-mentioned Cited Document 1, which stacks a drive circuit substrate having different circuits mounted on a single substrate and a nitride semiconductor layer constituting a plurality of micro LEDs.

[0009] FIG. 1 is a cross-sectional view illustrating an example of a configuration of a light-emitting device according to an embodiment of the present disclosure. FIG. 2 is a functional block diagram illustrating an example of a configuration of a light-emitting device. FIG. 3A is a cross-sectional view illustrating an example of a planar configuration of an element substrate of the light-emitting device illustrated in FIG. 1. FIG. 3B is a cross-sectional view illustrating an example of a planar configuration of an analog substrate of the light-emitting device illustrated in FIG. 1. FIG. 3C is a cross-sectional view illustrating an example of a planar configuration of a logic substrate of the light-emitting device illustrated in FIG. 1. FIG. 4 is a cross-sectional view illustrating an enlarged portion of the planar configuration of the light-emitting device illustrated in FIG. 1. FIG. 5A is a cross-sectional view illustrating an example of a manufacturing process for the light-emitting device illustrated in FIG. 1. FIG. 5B is a cross-sectional view illustrating a process subsequent to FIG. 5A. FIG. 5C is a cross-sectional view illustrating a process subsequent to FIG. 5B. FIG. 5D is a cross-sectional view illustrating a process subsequent to FIG. 5C. FIG. 5E is a cross-sectional view illustrating a process subsequent to FIG. 5D. FIG. 5F is a cross-sectional view illustrating a process subsequent to FIG. 5E. FIG. 5G is a cross-sectional view illustrating a process subsequent to FIG. 5F. FIG. 5H is a cross-sectional view illustrating a process subsequent to FIG. 5G. FIG. 6A is a schematic cross-sectional view showing a step subsequent to FIG. 5H. FIG. 6B is a schematic cross-sectional view showing a step subsequent to FIG. 6A. FIG. 6C is a schematic cross-sectional view showing a step subsequent to FIG. 6B. FIG. 6D is a schematic cross-sectional view showing a step subsequent to FIG. 6C. FIG. 6E is a schematic cross-sectional view showing a step subsequent to FIG. 6D. FIG. 6F is a schematic cross-sectional view showing a step subsequent to FIG. 6E. FIG. 6G is a schematic cross-sectional view showing a step subsequent to FIG. 6F. FIG. 6H is a schematic cross-sectional view showing a step subsequent to FIG. 6G. FIG. 6I is a schematic cross-sectional view showing a step subsequent to FIG. 6H. FIG. 7A is a schematic cross-sectional view showing a step subsequent to FIG. 6I. FIG. 7B is a schematic cross-sectional view showing a step subsequent to FIG. 7A. FIG. 7C is a schematic cross-sectional view showing a step subsequent to FIG. 7B. FIG. 7D is a schematic cross-sectional view showing a step subsequent to FIG. 7C. FIG. 7E is a schematic cross-sectional view showing a step subsequent to FIG. 7D. FIG. 7F is a schematic cross-sectional view showing a step subsequent to FIG. 7E. Fig. 7G is a schematic cross-sectional view showing a step subsequent to Fig. 7F. Fig. 7H is a schematic cross-sectional view showing a step subsequent to Fig. 7G. Fig. 7I is a schematic cross-sectional view showing a step subsequent to Fig. 7H. Fig. 7J is a schematic cross-sectional view showing a step subsequent to Fig. 7I. Fig. 7K is a schematic cross-sectional view showing a step subsequent to Fig. 5K. Fig. 7L is a schematic cross-sectional view showing a step subsequent to Fig. 7K. Fig. 7M is a schematic cross-sectional view showing a step subsequent to Fig. 7L.FIG. 7N is a cross-sectional view schematically illustrating a step subsequent to FIG. 7M. FIG. 8 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to Modification 1 of the present disclosure. FIG. 9 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to Modification 2 of the present disclosure. FIG. 10A is a cross-sectional view schematically illustrating an example of a manufacturing process for the light-emitting device shown in FIG. 1. FIG. 10B is a cross-sectional view schematically illustrating a step subsequent to FIG. 10A. FIG. 10C is a cross-sectional view schematically illustrating a step subsequent to FIG. 10B. FIG. 10D is a cross-sectional view schematically illustrating a step subsequent to FIG. 10C. FIG. 10E is a cross-sectional view schematically illustrating a step subsequent to FIG. 10D. FIG. 11 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to Modification 3 of the present disclosure. FIG. 12 is a cross-sectional view schematically illustrating another example of the configuration of a light-emitting device according to Modification 3 of the present disclosure. FIG. 13 is a cross-sectional view schematically illustrating another example of the configuration of a light-emitting device according to Modification 3 of the present disclosure. FIG. 14 is a cross-sectional view schematically illustrating another example of the configuration of a light-emitting device according to Modification 3 of the present disclosure. FIG. 15 is a cross-sectional view schematically illustrating another example of the configuration of a light-emitting device according to Modification 3 of the present disclosure. FIG. 16 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to Modification 4 of the present disclosure. FIG. 17A is a cross-sectional view schematically illustrating an example of a manufacturing process for the light-emitting device shown in FIG. 16. FIG. 17B is a cross-sectional view schematically illustrating a process subsequent to FIG. 17A. FIG. 17C is a cross-sectional view schematically illustrating a process subsequent to FIG. 17B. FIG. 17D is a cross-sectional view schematically illustrating a process subsequent to FIG. 17C. FIG. 17E is a cross-sectional view schematically illustrating a process subsequent to FIG. 17D. FIG. 17F is a cross-sectional view schematically illustrating a process subsequent to FIG. 17E. FIG. 18 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to Modification 5 of the present disclosure. FIG. 19 is a cross-sectional view schematically illustrating another example of the configuration of a light-emitting device according to Modification 5 of the present disclosure. FIG. 20 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to Modification 6 of the present disclosure. FIG. 21 is a cross-sectional view schematically illustrating an example of the configuration of a light-emitting device according to another modification of the present disclosure. Fig. 22 is a cross-sectional view schematically illustrating a configuration example of a light-emitting device according to another modified example of the present disclosure. Fig. 23 is a cross-sectional view schematically illustrating a configuration example of a light-emitting device according to another modified example of the present disclosure. Fig. 24 is a cross-sectional view schematically illustrating a configuration example of a light-emitting device according to another modified example of the present disclosure. Fig. 25A is a front view illustrating an example of the appearance of a digital still camera as an application example of the present disclosure.Fig. 25B is a rear view illustrating an example of the appearance of the digital still camera illustrated in Fig. 24A. Fig. 26A is a perspective view illustrating the appearance of an example of a head-mounted display as an application example of the present disclosure. Fig. 26B is a perspective view illustrating the appearance of another example of a head-mounted display as an application example of the present disclosure. Fig. 27 is a perspective view illustrating an example of the appearance of a television device as an application example of the present disclosure.

[0010] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of the components shown in the drawings. The order of description is as follows: 1. Embodiment (Example in which a sapphire substrate is patterned on the light-emitting surface of a light-emitting element) 1-1. Overall configuration of a light-emitting device 1-2. Cross-sectional configuration of a light-emitting device 1-3. Method for manufacturing a light-emitting device 1-4. Actions and effects 2. Modifications 2-1. Modification 1 (Another example of a light-emitting device) 2-2. Modification 2 (Another example of a light-emitting device) 2-3. Modification 3 (Another example of a light-emitting device) 2-4. Modification 4 (Another example of a light-emitting device) 2-5. Modification 5 (Another example of a light-emitting device) 2-6. Modification 6 (Another example of a light-emitting device) 2-7. Other modifications 3. Application examples

[0011] 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-emitting device (light-emitting device 1) according to an embodiment of the present disclosure. Light-emitting device 1 is suitably applicable to image display devices known as LED displays (e.g., electronic viewfinder 1124 of digital still camera 1120, see FIG. 25B ).

[0012] (1-1. Overall Configuration of the Light-Emitting Device) The light-emitting device 1 comprises an element substrate 10, an analog substrate 20, and a logic substrate 30 electrically connected to one another by, for example, hybrid bonding. The element substrate 10 has a display area 100A in which a plurality of light-emitting elements 11 are arranged in a two-dimensional array, and a frame area 100B surrounding the display area 100A. The element substrate 10 has a surface 10S1 serving as a light-emitting surface and a surface 10S2 opposite the surface 10S1. The analog substrate 20 and the logic substrate 30 are provided with drive circuits that control the drive of the plurality of light-emitting elements 11 arranged in the display area 100A. The analog substrate 20 and the logic substrate 30 are each provided with circuits having different functions. The analog substrate 20 has opposing surfaces 20S1 and 20S2, and is stacked such that the surface 20S1 faces the surface 10S2 of the element substrate 10. The logic board 30 has opposing surfaces 30S1 and 30S2, and is stacked so that the surface 30S1 faces the surface 20S2 of the analog board 20.

[0013] Here, the element substrate 10 corresponds to a specific example of a "third substrate" in one embodiment of the present disclosure. The analog substrate 20 corresponds to a specific example of a "second substrate" in one embodiment of the present disclosure. The logic substrate 30 corresponds to a specific example of a "first substrate" in one embodiment of the present disclosure. The light-emitting element 11 corresponds to a specific example of a "light-emitting element" in one embodiment of the present disclosure.

[0014] 2 is a functional block diagram showing an example of the configuration of a light emitting device 1. The light emitting device 1 includes, for example, an interface 1001, a timing generation circuit (TCON) 1002, a memory 1003, a V-logic circuit 1004, a logic circuit 1005, a V-analog circuit 1006, an H-logic circuit 1007, and an H-analog circuit 1008.

[0015] The TCON 1002 generates various timing signals such as a start signal and a clock signal for driving the internal circuit of the light emitting device 1 .

[0016] The memory 1003 stores, for example, video signals and non-uniformity correction data.

[0017] The V-logic circuit 1004 is composed of, for example, a shift register that generates signals to drive the pixels P, an address decode circuit, and the like.

[0018] The logic circuit 1005 is composed of, for example, a video signal processing circuit, a gamma correction circuit, a brightness adjustment circuit, and a non-uniformity correction circuit.

[0019] The V-analog circuit 1006 is composed of, for example, a level shifter that converts the voltage level into a voltage suitable for driving the pixel P.

[0020] The H-logic circuit 1007 may have a built-in address decode circuit that latches the video signal for one horizontal line and supplies it to the H-analog circuit 1008, and may be configured to latch partially.

[0021] For example, in the case of a pulse amplitude modulation (PAM) system, the H-analog circuit 1008 converts the supplied digital signal into an analog signal and transmits it to the pixel P. For example, in the case of a pulse width modulation (PWM) system, the H-analog circuit 1008 pulse-width-modulates the supplied digital signal and transmits it to the pixel P.

[0022] The light emitting device 1 is connected to an external video supply device, such as a computer such as a PC (not shown) or various image players, via an interface 1001. The light emitting device 1 processes the video signal input to the interface 1001 as shown in Fig. 2. The pixel P receives the video signal that has been signal processed by the TCON 1002, memory 1003, V-logic circuit 1004, logic circuit 1005, V-analog circuit 1006, H-logic circuit 1007, and H-analog circuit 1008.

[0023] 3A to 3C are schematic diagrams showing an example of the planar configuration of the element substrate 10, analog substrate 20, and logic substrate 30 that constitute the light emitting device 1. FIG.

[0024] 3A, the element substrate 10 has a display area 100A in which a plurality of pixels P are arranged in a two-dimensional array, and a frame area 100B surrounding the display area 100A. The frame area 100B is provided with external connection terminals 61 to be connected to, for example, an external power supply.

[0025] The circuits mounted on the analog substrate 20 and the logic substrate 30 are distinguished, for example, by their drive voltages. For example, the analog substrate 20 is equipped with circuits having a higher drive voltage than the circuits mounted on the logic substrate 30. For example, the interface 1001, TCON 1002, memory 1003, V-logic circuit 1004, logic circuit 1005, V-analog circuit 1006, H-logic circuit 1007, and H-analog circuit 1008 are separately mounted on the analog substrate 20 and the logic substrate 30, for example, as shown in FIG. 3B . The analog substrate 20 further includes a drive circuit for controlling the drive of the plurality of light-emitting elements 11 at a position corresponding to the display region 100A provided on the element substrate 10, and the V-analog circuit 1006 and H-analog circuit 1008 are respectively disposed at positions corresponding to the frame region 100B provided on the element substrate 10. The logic board 30 is mounted with an interface 1001, a TCON 1002, a memory 1003, a V-logic circuit 1004, a logic circuit 1005, and an H-logic circuit 1007, as shown in FIG. 3C, for example.

[0026] (1-2. Cross-sectional Structure of the Light-Emitting Device) The element substrate 10 has a plurality of light-emitting elements 11 formed by separating a compound semiconductor layer 110 extending across the display region 100A. The light-emitting elements 11 have a generally regular hexagonal shape, as shown in FIG. 4, and are arranged in the display region 100A in, for example, a honeycomb pattern. An electrode layer 12, an insulating layer 13, and an extraction electrode 14 are formed in this order on the light extraction surface (surface 11S1) of the plurality of light-emitting elements 11. An electrode layer 114, an insulating layer 115, and a protective layer 117 are formed on each of the plurality of light-emitting elements 11 on the surface 11S2 side of the plurality of light-emitting elements 11, as well as an insulating film 118A and a reflective film 118B that are continuous with the plurality of light-emitting elements 11. The element substrate 10 further has, on the analog substrate 20 side, an embedding layer 119 that embeds the plurality of light-emitting elements 11 from the surface 10S2 side, and a wiring layer that forms the bonding surface (surface 10S2) with the analog substrate 20.

[0027] The light-emitting element 11 corresponds to a specific example of a "light-emitting element" in an embodiment of the present disclosure. The light-emitting element 11 is a solid-state light-emitting element that emits light in a predetermined wavelength band from a surface 11S1, and is, for example, an LED (Light Emitting Diode) chip. The LED chip refers to an element cut from a wafer used for crystal growth, and is not a packaged type covered with molded resin or the like. The LED chip has a size of, for example, 0.5 μm or more and 100 μm or less, and is a so-called micro LED.

[0028] The light emitting element 11 has a first conductivity type layer 111, an active layer 112, and a second conductivity type layer 113 stacked in this order, and the upper surface of the second conductivity type layer 113 is a surface 11S1.

[0029] The first conductivity type layer 111 is formed of, for example, a p-type GaN-based semiconductor material. The active layer 112 has, for example, a multiple quantum well structure in which InGaN and GaN are alternately stacked, and has a light-emitting region within the layer. Light in the blue band of, for example, 430 nm to 500 nm is extracted from the active layer 112. In addition, light with a wavelength corresponding to, for example, the ultraviolet region (ultraviolet light) may also be extracted from the active layer 112. The second conductivity type layer 113 is formed of, for example, an n-type GaN-based semiconductor material. Note that the conductivity types of the first conductivity type layer 111 and the second conductivity type layer 113 are not limited to those described above. For example, the first conductivity type layer 111 may be formed of an n-type GaN-based semiconductor material, and the second conductivity type layer 113 may be formed of a p-type GaN-based semiconductor material.

[0030] The electrode layer 12 is formed continuously on the surface 11S1 of each of the light-emitting elements 11 as a common electrode for the light-emitting elements 11. The electrode layer 12 is in ohmic contact with the second conductivity type layer 113 and is formed of a transparent electrode material such as zinc oxide (ZnO), ITO, indium zinc oxide (IZO), tin oxide (SnO), or TiO.

[0031] The insulating layer 13 fills the irregularities formed above the plurality of light emitting elements 11. The insulating layer 13 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0032] The extraction electrode 14 applies a voltage to the second conductivity type layer 113 of each of the plurality of light-emitting elements 11, and is electrically connected to the electrode layer 12, for example, through an opening (opening 13H, see FIG. 7G ) provided in the insulating layer 13 between adjacent light-emitting elements 11. In the display region 100A, the extraction electrode 14 is formed continuously between adjacent light-emitting elements 11 so as to avoid the surfaces 11S1 of the plurality of light-emitting elements 11 arranged in a honeycomb pattern, for example, and extends to a part of the frame region 100B. The extraction electrode 14 formed in the frame region 100B is electrically connected to the pad portion 16 through an opening H1 that penetrates the insulating layer 13, the embedded layer 119, and the protective layer 117. The extraction electrode 14 is formed using, for example, a single layer film of palladium (Pd), chromium (Cr), titanium (Ti), aluminum (Al), platinum (Pt), silver (Ag), nickel (Ni), gold (Au), or the like, a multilayer film of Ti and Al (Ti / Al), or a multilayer film of Cr and Au (Cr / Au).

[0033] The electrode layer 12 and the extraction electrode 14 correspond to a specific example of a "cathode electrode" in an embodiment of the present disclosure. The pad portion 16 to which the extraction electrode 14 is connected is not electrically connected to the analog substrate 20, and the extraction electrode 14 is routed on the element substrate 10 without passing through the analog substrate 20, and is connected to an external power supply.

[0034] An electrode layer 114 is formed on the lower surface (surface 11S2) of the first conductivity type layer 111 of the light emitting element 11. The electrode layer 114 corresponds to a specific example of an "anode electrode" in an embodiment of the present disclosure. The electrode layer 114 is in ohmic contact with the first conductivity type layer 111 and is formed using a transparent conductive material such as a multilayer film (Ni / Au) of nickel (Ni) and gold (Au) or ITO.

[0035] The insulating layer 115 is provided on the electrode layer 114. The insulating layer 115 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0036] The light emitting element 11 has a mesa shape on the analog substrate 20 side, including the first conductivity type layer 111, the active layer 112, and a part of the second conductivity type layer 113. A surface 11S2 of the light emitting element 11 processed into a mesa shape and the side surfaces of the first conductivity type layer 111, the active layer 112, and a part of the second conductivity type layer 113 are covered with a protective layer 117. The protective layer 117 is made of, for example, silicon oxide (SiO), silicon nitride (SiN), or aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), or the like, or a laminated film thereof.

[0037] Furthermore, the protective layer 117 and the side surfaces of the second conductivity type layer 113 exposed from the protective layer 117 are covered with a laminated film made of an insulating film 118A and a reflective film 118B. The laminated film is continuously formed on the plurality of light emitting elements 11. The laminated film has an opening 118H on the surface 11S2 side of the light emitting element 11, and a plug 15 is formed in the opening 118H.

[0038] The plugs 15 apply a voltage to the first conductivity type layers 111 of the plurality of light emitting elements 11. The plugs 15 are formed using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof.

[0039] The embedded layer 119 embeds the plurality of light-emitting elements 11 and has an embedded layer 119 on the analog substrate 20 side that forms a flat layered surface across the display region 100A and the frame region 100B. The embedded layer 119 further forms a flat surface in the frame region 100B that is continuous with the surfaces 11S1 of the plurality of light-emitting elements 11. The embedded layer 119 is formed of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0040] An insulating layer 17 is provided on the analog substrate 20 side of the embedded layer 119. A plurality of pads 16 and vias connected to the pads 16 are formed within the insulating layer 17. A plurality of pads 16 are provided for each light-emitting element 11 in the display region 100A. An opening H1 penetrating the insulating layer 13, the embedded layer 119, and the protective layer 117, and an opening H2 penetrating the optical unit 40 (described later), the insulating layer 13, the embedded layer 119, and the protective layer 117, are provided in the frame region 100B. The pads 16 are exposed at the bottoms of the openings H1 and H2. The pads 16 exposed at the bottom of the opening H1 are connected to the extraction electrodes 14 as described above. The pads 16 exposed at the bottom of the opening H2 are used as external connection terminals 61. The insulating layer 17 is formed of, for example, silicon oxide (SiO) or silicon nitride (SiN). The pad portion 16 and the via are formed using, for example, copper (Cu), tantalum (Ta), cobalt (Co), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof, etc. Alternatively, the pad portion 16 and the via can be formed using, for example, tantalum nitride (TaN) or titanium nitride (TiN).

[0041] Further provided on the analog substrate 20 side of the insulating layer 17 are an insulating layer 18 that forms a bonding surface (surface 10S2) with the analog substrate 20, and a plurality of pads 19 embedded in the insulating layer 18. The insulating layer 18 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN). The plurality of pads 19 electrically and physically bond the element substrate 10 and the analog substrate 20 together. The pads 19 are made of, for example, copper (Cu) or gold (Au).

[0042] The insulating layer 17 including the plurality of pads 16 and vias, and the insulating layer 18 in which the plurality of pads 19 are embedded correspond to the wiring layer. The plurality of pads 19 correspond to a specific example of a "fourth pad" in an embodiment of the present disclosure.

[0043] As described above, the analog substrate 20 is provided with the V-analog circuit 1006, the H-analog circuit 1008, and a drive circuit that controls the drive of the plurality of light-emitting elements 11 arranged in the display region 100A. The analog substrate 20 has a semiconductor layer 21 made of, for example, silicon (Si). The semiconductor layer 21 has a surface 21S1 that faces the element substrate 10 and a surface 21S2 that faces the logic substrate 30 on the opposite side of surface 21S1. An interlayer insulating layer 22 including a plurality of wiring layers (e.g., wiring layer 23) is provided on the surface 21S1 side, and an insulating layer 24 that forms a bonding surface (surface 20S1) with the element substrate 10 and a plurality of pad portions 25 embedded in the insulating layer 24 is provided on the interlayer insulating layer 22. An interlayer insulating layer 26 including a plurality of wiring layers (e.g., wiring layer 27) is provided on the surface 21S2 side, and a plurality of pad portions 25 are embedded in the bonding surface (surface 20S2) of the interlayer insulating layer 26 with the logic substrate 30.

[0044] The interlayer insulating layers 22 and 26 and the insulating layer 24 are formed of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0045] The wiring layers 23, 27 and the vias electrically connecting the respective wiring layers are formed using, for example, copper (Cu), tantalum (Ta), cobalt (Co), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. Alternatively, the wiring layers 23, 27 and the vias electrically connecting the respective wiring layers can be formed using, for example, tantalum nitride (TaN) or titanium nitride (TiN). The pads 25, 28 are formed using, for example, copper (Cu) or gold (Au).

[0046] As described above, the logic substrate 30 is provided with the interface 1001, the TCON 1002, the memory 1003, the V-logic circuit 1004, the logic circuit 1005, and the H-logic circuit 1007. The logic substrate 30 has a support substrate 31 made of, for example, silicon (Si). An interlayer insulating layer 32 including a plurality of wiring layers (for example, wiring layer 33) is provided on the support substrate 31, and a plurality of pad portions 34 are embedded in the bonding surface (surface 30S1) of the interlayer insulating layer 32 that is bonded to the analog substrate 20.

[0047] The interlayer insulating layer 32 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0048] The wiring layer 33 and the vias electrically connecting the wiring layers are formed using, for example, copper (Cu), tantalum (Ta), cobalt (Co), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. Alternatively, the wirings M1, ..., Mn and the vias electrically connecting the wirings can be formed using, for example, tantalum nitride (TaN) or titanium nitride (TiN). The pads 34 are formed using, for example, copper (Cu) or gold (Au).

[0049] As described above, the element substrate 10, the analog substrate 20, and the logic substrate 30 are electrically connected to one another by hybrid bonding. Specifically, the element substrate 10 and the analog substrate 20 are electrically connected by bonding together a plurality of pads 19 and a plurality of pads 25 provided on the opposing bonding surfaces (surfaces 10S2 and 20S1). The analog substrate 20 and the logic substrate 30 are electrically connected by bonding together a plurality of pads 28 and a plurality of pads 34 provided on the opposing bonding surfaces (surfaces 20S2 and 30S1). As described above, the plurality of pads 19, 25, 28, and 34 are formed using, for example, copper (Cu). That is, the element substrate 10, the analog substrate 20, and the logic substrate 30 are electrically connected to one another by Cu-Cu bonding.

[0050] An optical unit 40 is provided on the surface 10S1 side of the element substrate 10. The optical unit 40 includes a planarizing layer 41, a partition layer 42 having openings 42H for each light-emitting element 11, and a wavelength conversion layer 43 formed in the openings 42H. A reflective film 44 is further provided between the partition layer 42 and the wavelength conversion layer 43. A protective layer 45 is further provided on the light-emitting surface S1 side of the wavelength conversion layer 43, and a wavelength selection layer 46 is provided within the protective layer 45. A lens layer 47 is further provided on the protective layer 45.

[0051] The planarization layer 41 is intended to planarize the light extraction surface (surface 11S1) of the display region 100A in which a plurality of light-emitting elements 11 are arranged in an array. The planarization layer 41 is formed of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0052] The partition layer 42 is intended to prevent color mixing due to light leakage between adjacent RGB subpixels (red pixel Pr, green pixel Pg, and blue pixel Pb) when the light-emitting device 1 is applied to the image display device 100. The partition layer 42 has, for example, a honeycomb structure. Specifically, as shown in FIG. 4 , the partition layer 42 has, for example, a substantially regular hexagonal opening 42H for each of the plurality of light-emitting elements 11 arranged in an array. In cross-sectional view, the opening 42H has, for example, a surface inclined at an angle of less than 90° with respect to the surface facing the element substrate 10. In other words, in cross-sectional view, the partition layer 42 has a forward tapered shape between adjacent color pixels Pr, Pg, and Pb. The partition layer 42 is preferably formed using a material with high thermal conductivity and electrical conductivity, such as a metal material such as copper (Cu), aluminum (Al), gold (Au), nickel (Ni), or platinum (Pt).

[0053] The wavelength conversion layer 43 is for converting light emitted from the plurality of light-emitting elements 11 into a desired wavelength (for example, red (R) / green (G) / blue (B)) and emitting the light, and is formed in an opening 42H provided above each light-emitting element 11. Specifically, the red pixel Pr is provided with a red wavelength conversion layer 43R that converts light emitted from the light-emitting element 11 into light in a red band (red light), the green pixel Pg is provided with a green wavelength conversion layer 43G that converts light emitted from the light-emitting element 11 into light in a green band (green light), and the blue pixel Pb is provided with a blue wavelength conversion layer 43B that converts light emitted from the light-emitting element 11 into light in a blue band (blue light).

[0054] Each wavelength conversion layer 43R, 23G, 23B can be formed using quantum dots corresponding to each color. Specifically, when red light is obtained, the quantum dots can be selected from, for example, InP, GaInP, InAsP, CdSe, CdZnSe, CdTeSe, or CdTe. When green light is obtained, the quantum dots can be selected from, for example, InP, GaInP, ZnSeTe, ZnTe, CdSe, CdZnSe, CdS, or CdSeS. When blue light is obtained, the quantum dots can be selected from, for example, ZnSe, ZnTe, ZnSeTe, CdSe, CdZnSe, CdS, CdZnS, and CdSeS. Note that when blue light is emitted from the light-emitting element 11 as described above, the blue wavelength conversion layer 43B may be formed from a light-transmitting resin layer.

[0055] The reflective film 44 is provided on the side surface of the opening 42H to efficiently extract the color light emitted from the light-emitting element 11 and converted in the wavelength conversion layers 43R, 23G, and 23B from the light extraction surface (surface 22S1) of the wavelength conversion layer 43. The reflective film 44 is formed using a metal material with optical reflectivity. Examples of the metal material for the reflective film 44 include metals with high reflectivity in the visible light range. Specific examples of the material include silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys thereof.

[0056] It should be noted that the reflective film 44 does not necessarily have to be formed when the partition wall layer 42 is formed using the above-mentioned metal material having light reflectivity.

[0057] The protective layer 45 is for protecting the surface of the light emitting device 1 and is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0058] A wavelength selection layer 46 is provided across the red pixel Pr and the green pixel Pg within the protective layer 45. The wavelength selection layer 46 selectively reflects, for example, light in the blue wavelength band (blue light), thereby improving the color purity of the red light and green light extracted from the red pixel Pr and the green pixel Pg, respectively.

[0059] The lens layer 47 is provided to cover the entire display area 100A and the frame area 100B. The lens layer 47 is made of a light-transmitting material, and is, for example, a single-layer film made of any of inorganic materials such as silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiCN), or a laminated film made of two or more of these materials. Alternatively, the lens layer 47 may be made of an organic material.

[0060] (1-3. Manufacturing Method of Light-Emitting Device) The light-emitting device 1 of the present embodiment can be manufactured, for example, as follows. Figures 5A to 5H, 6A to 6I, and 7A to 7N show an example of a manufacturing process for the light-emitting device 1.

[0061] 5A, a compound semiconductor layer 110 is formed on a growth substrate 50 made of, for example, a sapphire substrate or a silicon substrate by epitaxial crystal growth using a method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Subsequently, an electrode layer 114 is formed on the compound semiconductor layer 110 by, for example, sputtering, and an insulating layer 115 is formed on the compound semiconductor layer 110 by, for example, chemical vapor deposition (CVD).

[0062] Next, as shown in Fig. 5B, the insulating layer 115, the electrode layer 114, and the compound semiconductor layer 110 are etched and patterned using, for example, photolithography. Subsequently, as shown in Fig. 5C, the growth substrate 50 is transferred to the support substrate 51 so that the insulating layer 115 faces the support substrate 51, and then the growth substrate 50 is cut into individual pieces. Next, as shown in Fig. 5D, each of the individual growth substrates 50 is bonded to the support substrate 52 so that the insulating layer 115 faces the support substrate 52.

[0063] Next, as shown in Fig. 5E, the growth substrate 50 is removed by, for example, grinding and polishing, and the surface of the compound semiconductor layer 110 is planarized. Next, as shown in Fig. 5F, a buried layer 119 is formed on the support substrate 52 by, for example, a CVD method, and then planarized. Next, as shown in Fig. 5G, the buried layer 119 is bonded to the support substrate 53 by, for example, plasma bonding, and then the support substrate 52 is peeled off as shown in Fig. 5H. The area within the frame X shown in Fig. 5H will be explained in an enlarged manner below.

[0064] 6A, the insulating layer 115 and the electrode layer 114 are etched and patterned using, for example, photolithography. Then, as shown in FIG. 6A, a mesa structure including the first conductivity type layer 111, the active layer 112, and a part of the second conductivity type layer 113 is formed by etching a part of the compound semiconductor layer using, for example, photolithography.

[0065] Next, for example, by atomic layer deposition (ALD), an AlO film is formed on the top surface of the insulating layer 115 and on the side and bottom surfaces of the insulating layer 115, the electrode layer 114, and the first conductivity type layer 111, the active layer 112, and the second conductivity type layer 113 that constitute the mesa structure. Then, for example, by CVD, an SiO ２ Then, a SiO film is formed by using, for example, a photolithography technique. ２ The film is etched to form a protective layer 117 as sidewalls on the top and sides of the mesa structure, as shown in FIG. 6B.

[0066] 6C , for example, photolithography is used to separate the second conductivity type layer 113 exposed from the protective layer 117, thereby forming a plurality of light emitting elements 11. Next, as shown in Fig. 6D , an AlO film is formed by, for example, ALD to cover the upper surface of the protective layer 117 and the exposed side surfaces of the light emitting elements 11. Next, as shown in Fig. 6D , an insulating film 118A and a reflective film 118B are formed in this order by, for example, CVD, and then an opening 118H is formed in the upper surface of the mesa structure.

[0067] Next, as shown in Fig. 6E, a buried layer 119 is formed again by, for example, a CVD method and planarized, and then, as shown in Fig. 6F, an insulating layer 17 in which a plug 15 and a plurality of pad portions 16 are buried is formed for each light-emitting element 11. Subsequently, as shown in Fig. 6G, the insulating layer 17 is thickened and an insulating layer 18 is formed on the insulating layer 17.

[0068] Next, as shown in Fig. 6H, openings 18H are formed on the pads 16. Subsequently, as shown in Fig. 6I, the openings 18H are filled with, for example, Cu to form a plurality of pads 19. Thereafter, the surfaces of the insulating layer 18 and the plurality of pads 19 are polished by, for example, CMP to flatten the bonding surfaces with the analog substrate 20.

[0069] Next, as shown in Fig. 7A, an analog substrate 20 is separately fabricated, which includes an interlayer insulating layer 26 including a wiring layer 27 on the surface 21S2 side of the semiconductor layer 21 and with a plurality of pads 28 embedded in its surface, and a logic substrate 30 is separately fabricated, which includes a wiring layer 33 on a support substrate 31 and with a plurality of pads 34 embedded in its surface. Subsequently, as shown in Fig. 7B, the separately fabricated plurality of pads 28 of the analog substrate 20 and the plurality of pads 34 of the logic substrate 30 are bonded together by hybrid bonding. Next, as shown in Fig. 7C, after thinning the semiconductor layer 21, an interlayer insulating layer 22 including a wiring layer 23 and an insulating layer 24 with a plurality of pads 25 embedded in its surface are sequentially formed on the surface 21S1 side of the semiconductor layer 21.

[0070] Next, as shown in FIG. 7D , the plurality of pad portions 25 and the plurality of pad portions 19 of the element substrate 10 are bonded together by hybrid bonding. Next, as shown in FIG. 7E , the support substrate 53 is peeled off. Next, as shown in FIG. 7F , an ITO film is formed by, for example, sputtering, and then the ITO film is patterned using, for example, photolithography to form an electrode layer 12. Next, as shown in FIG. 7G , an insulating layer 13 is formed by, for example, CVD, and then openings 13H penetrating the insulating layer 13 between adjacent light-emitting elements 11 are formed using, for example, photolithography, and then openings H1 reaching the pad portions 16 are formed as shown in FIG.

[0071] Next, as shown in FIG. 7I , a stacked film of, for example, Ti / W is formed by, for example, CVD, and then the stacked film is patterned by, for example, photolithography to form the extraction electrode 14. Subsequently, as shown in FIG. 7J , a planarization layer 41 and a partition layer 42 are formed in sequence by, for example, CVD. Subsequently, as shown in FIG. 7K , openings 42H are formed in the partition layer 42 above each light-emitting element 11 by, for example, photolithography. Next, as shown in FIG. 7L , an Al film is formed by, for example, CVD on the top surface of the partition layer 42 and on the side and bottom surfaces of the openings 42H, and then the Al film formed on the top surface of the partition layer 42 and on the bottom surface of the openings 42H is removed by etch-back to form a reflective film 44 on the side surfaces of the openings 42H.

[0072] Next, as shown in Fig. 7M, wavelength conversion layers 43 of each color are formed in openings 42H using a coating method such as an inkjet method. Thereafter, as shown in Fig. 7N, a protective layer 45 including a wavelength selection layer 46 is formed on the partition layer 42 and the wavelength conversion layer 43, and then a lens layer 47 is formed. Then, outside opening H1, opening H2 is formed by, for example, etching, penetrating the embedded layer 119 below protective layer 117 to expose pad portion 16. This completes the light-emitting device 1 shown in Fig. 1.

[0073] (1-4. Actions and Effects) In the light emitting device 1 of the present embodiment, for example, analog circuits (e.g., V-analog circuit 1006 and H-analog circuit 1008) are mounted on the analog substrate 20, and logic circuits (e.g., V-logic circuit 1004, logic circuit 1005, and V-analog circuit 1006) are mounted separately on the logic substrate 30, and the element substrate 10 on which a plurality of light emitting elements 11 are arranged in a two-dimensional array, the analog substrate 20, and the logic substrate 30 are stacked. This reduces the area of ​​the substrates (analog substrate 20 and logic substrate 30) on which the element substrate 10 is stacked, compared to when analog circuits and logic circuits are mounted together on a single substrate. This is described below.

[0074] In recent years, high-definition image display devices using light-emitting devices with micro LEDs using gallium nitride (GaN) as light sources have become widespread. Light-emitting devices generally have a structure in which a substrate on which LEDs are mounted and a drive circuit board are hybrid-bonded. However, when various functional elements are mounted to enhance functionality, as mentioned above, the area of ​​the drive circuit board becomes larger than, for example, the display area, leading to an increase in device size. Furthermore, even when a drive IC such as a display driver IC (DDIC) is connected to the mounting board separately from the light-emitting device, the area of ​​the image display device becomes large, which poses a problem in terms of commercial viability, for example, in wearable applications.

[0075] In contrast to this, in the present embodiment, as described above, for example, an analog circuit and a logic circuit are mounted separately on separate substrates, and an element substrate 10 on which a plurality of light-emitting elements 11 are arranged in a two-dimensional array, a substrate on which an analog circuit is mounted (for example, analog substrate 20), and a substrate on which a logic circuit is mounted (for example, logic substrate 30) are stacked. This makes it possible to mount, for example, a circuit for correcting brightness unevenness, a memory, a timing control circuit that selectively drives only a part of the circuit to achieve small electrodes, an AI chip that can be applied to optical computing, and the like, without increasing the device size.

[0076] As described above, the light emitting device 1 of this embodiment can provide a light emitting device that is both compact and highly functional, and an image display device including the same.

[0077] Furthermore, in the light emitting device 1 of the present embodiment, the substrates to be mounted can be separated according to, for example, the drive voltage. For example, a circuit with a relatively high drive voltage can be mounted on the analog substrate 20, and a circuit with a relatively low drive voltage can be mounted on the logic substrate 30, thereby reducing the substrate cost, for example.

[0078] Next, modified examples 1 to 6 and application examples of the present disclosure will be described. Note that components corresponding to those of the light emitting device 1 of the above embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0079] 8 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-emitting device (light-emitting device 1A) according to Modification 1 of the present disclosure. As in the above embodiment, light-emitting device 1A is suitably applicable to image display devices known as LED displays (for example, electronic viewfinder 1124 of digital still camera 1120).

[0080] In the above embodiment, an example in which the plurality of light-emitting elements 11 are separated from one another has been shown, but this is not limiting. In the light-emitting device 1A of this modification, for example, the second conductivity type layer 113 extends into the display region 100A as a common layer for the plurality of light-emitting elements 11. Even with this configuration, the same effects as those of the light-emitting device 1 of the above embodiment can be obtained.

[0081] 9 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-emitting device (light-emitting device 1B) according to Modification 2 of the present disclosure. Similar to the above embodiment, light-emitting device 1B is suitable for use in image display devices known as LED displays (for example, electronic viewfinder 1124 of digital still camera 1120).

[0082] In the above embodiment, an example was shown in which a plurality of light-emitting elements 11 are embedded in the frame region 100B, and an embedding layer 119 that forms a flat layered surface across the display region 100A and the frame region 100B extends on the analog substrate 20 side, but this is not limiting. In the light-emitting device 1B of this modification, for example, an insulating layer 120 different from the embedding layer 119 is embedded around the periphery of the frame region 100B.

[0083] The light emitting device 1B can be manufactured, for example, as follows.

[0084] First, as in the above embodiment, as shown in Fig. 10A, a plurality of pads 19 are formed by filling, for example, Cu into the openings 18H above the pads 16. Thereafter, the surfaces of the insulating layer 18 and the plurality of pads 19 are polished by, for example, CMP to flatten the bonding surfaces with the analog substrate 20, and then the element substrate 10 is singulated together with the support substrate 53 as shown in Fig. 10B.

[0085] 10C, the pads 25 exposed on the bonding surface (surface 20S1) of the analog substrate 20, which has been separately bonded to the logic substrate 30, are bonded by hybrid bonding to the pads 19 exposed on the bonding surface (surface 10S2) of the element substrate 10. Subsequently, the support substrate 53 is peeled off as shown in FIG.

[0086] 10E , an insulating layer 120 is formed by, for example, CVD to bury the element substrate 10 and its surroundings, and then the insulating layer 120 formed on the element substrate 10 is removed by polishing, for example, CMP, to expose the buried layer 119. Thereafter, similarly to the above embodiment, the electrode layer 12, the insulating layer 13, the extraction electrode 14, the planarization layer 41, the partition layer 42, the wavelength conversion layer 43, the reflective film 44, the protective layer 45 including the wavelength selection layer 46, and the lens layer 47 are sequentially formed. This completes the light-emitting device 1B shown in FIG. 9 .

[0087] In this way, in the light emitting device 1B of this modified example, the insulating layer 120 different from the embedding layer 119 is embedded in the outer periphery of the frame region 100B. Even with this configuration, the same effects as those of the light emitting device 1 of the above embodiment can be obtained.

[0088] (2-3. Modification 3) FIG. 11 is a schematic diagram showing an example of a cross-sectional configuration of a light-emitting device according to Modification 3 of the present disclosure (light-emitting device 1C). FIG. 12 is a schematic diagram showing another example of a cross-sectional configuration of a light-emitting device according to Modification 3 of the present disclosure (light-emitting device 1D). FIG. 13 is a schematic diagram showing another example of a cross-sectional configuration of a light-emitting device according to Modification 3 of the present disclosure (light-emitting device 1E). FIG. 14 is a schematic diagram showing another example of a cross-sectional configuration of a light-emitting device according to Modification 3 of the present disclosure (light-emitting device 1F). As with the above-described embodiment, light-emitting devices 1C to 1F are suitably applicable to image display devices known as LED displays (for example, electronic viewfinder 1124 of digital still camera 1120).

[0089] In the above embodiment, an example has been shown in which the pad portions 16 provided on the element substrate 10 are used as the external connection terminals 61, but this is not limiting. A light emitting device 1C of this modified example uses the wiring layer 23 provided on the surface 21S1 side of the semiconductor layer 21 of the analog substrate 20 as the external connection terminals 61. A light emitting device 1D of this modified example uses the wiring layer 27 provided on the surface 22S1 side of the semiconductor layer 21 of the analog substrate 20 as the external connection terminals 61. A light emitting device 1E of this modified example uses the wiring layer 33 provided on the support substrate 31 of the logic substrate 30 of the analog substrate 20 as the external connection terminals 61. In the light emitting device 1F of this modified example, a recessed portion is provided in the frame region 100B that penetrates the lens layer 47, the protective layer 45, the partition layer 42, the planarizing layer 41, the insulating layer 13, and the protective layer 117, leaving a portion of the embedded layer 119, and further, an opening H2 is provided in the remaining embedded layer 119, and the pad portion 16 is used as an external connection terminal 61.

[0090] In this way, the external connection terminals 61 may be provided not only on the element substrate 10 but also on the analog substrate 20 or logic substrate 30. Even with such a configuration, the same effects as those of the light emitting device 1 of the above embodiment can be obtained.

[0091] Furthermore, in light emitting device 1F, a recessed portion is provided in frame region 100B that penetrates lens layer 47, protective layer 45, partition layer 42, planarizing layer 41, insulating layer 13, and protective layer 117, leaving a portion of embedded layer 119, and furthermore, an opening H2 is provided in the remaining embedded layer 119 to expose pad portion 16 that serves as external connection terminal 61. This reduces the aspect ratio of opening H2, thereby making it easier to mount compared to the above embodiment.

[0092] Furthermore, in the light emitting devices 1D and 1E, an example was shown in which the opening H2 penetrates the semiconductor layer 21 together with the insulating layer including the embedded layer 119, but this is not limiting. In the light emitting device 1G shown in Fig. 15, an opening 21H is formed in the semiconductor layer 21 in advance, and then the opening H2 is formed within this opening 21H. This makes it possible to form the opening H2 in one step.

[0093] 16 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-emitting device (light-emitting device 1H) according to Modification 4 of the present disclosure. Similar to the above embodiment, light-emitting device 1H is suitably applicable to image display devices known as LED displays (for example, electronic viewfinder 1124 of digital still camera 1120).

[0094] In the above embodiment, an example has been shown in which the first conductivity type layer 111, the active layer 112, and the second conductivity type layer 113 constituting the light emitting element 11 are laminated in this order from the analog substrate 20 side, but this is not limiting. The light emitting device 1H of this modified example uses a light emitting element 11A in which the first conductivity type layer 111, the active layer 112, and the second conductivity type layer 113 are laminated from the optical unit 40 side, opposite the analog substrate 20 side.

[0095] The light emitting device 1H can be manufactured, for example, as follows.

[0096] First, as in the above-described embodiment, compound semiconductor layer 110, electrode layer 114, and insulating layer 115, each of which is formed by stacking individualized second-conductivity-type layer 113 and first-conductivity-type layer 111 in order from the growth substrate 116 side, are bonded to support substrate 52 as shown in Fig. 5D, and then growth substrate 116 is removed by, for example, grinding and polishing as shown in Fig. 5E. Next, as shown in Fig. 17A, buried layer 119 is formed on support substrate 52 by, for example, CVD and planarized. The area within frame X shown in Fig. 17A will be explained below by enlarging it.

[0097] Subsequently, as shown in FIG. 17B, an ITO film is formed on the second conductivity type layer 113 by, for example, CVD, and then the ITO film is patterned by, for example, photolithography to form the electrode layer 12.

[0098] Next, as shown in FIG. 17C , a buried layer 119 is further formed by, for example, CVD. After that, the buried layer 119 is planarized, and then an insulating layer 17 is formed for each light-emitting element 11A, in which a plug 15, a plurality of pad portions 16A, and a pad electrode 16B are embedded. Subsequently, as shown in FIG. 17C , the insulating layer 17 is thickened, and an insulating layer 18 is formed on the insulating layer 17. Next, as shown in FIG. 17C , a plurality of pad portions 19 are formed on each pad portion 16A and pad electrode 16B. Thereafter, the surfaces of the insulating layer 18 and the plurality of pad portions 19 are polished by, for example, CMP, to planarize the bonding surface (surface 10S2) with the analog substrate 20.

[0099] 17D, the pads 25 exposed on the bonding surface (surface 20S1) of the analog substrate 20, which has been separately bonded to the logic substrate 30, are bonded by hybrid bonding to the pads 19 exposed on the bonding surface (surface 10S2) of the element substrate 10. Next, as shown in FIG. 17E, the support substrate 52 is peeled off.

[0100] 17F, the insulating layer 115, the electrode layer 114, the first conductivity type layer 111, the active layer 112, and the second conductivity type layer 113 are etched using, for example, photolithography to separate the light emitting elements 11A. Then, a protective layer 117 is formed on the top surface of the insulating layer 115, on the side surfaces of the light emitting elements 11A including the insulating layer 115, the electrode layer 114, the first conductivity type layer 111, the active layer 112, and the second conductivity type layer 113, and across the spaces between adjacent light emitting elements 11A, for example, by ALD. Furthermore, a reflective film (not shown) is formed, and an opening is formed on the top surface of each light emitting element 11A. Then, a buried layer 119 is further formed by, for example, CVD.

[0101] Thereafter, after planarizing the embedded layer 119, the extraction electrodes 14 connected via plugs are formed for each light emitting element 11A using, for example, photolithography and CVD, and then, in the same manner as in the above embodiment, the planarizing layer 41, the partition layer 42, the wavelength conversion layer 43, the reflective film 44, the protective layer 45 including the wavelength selection layer 46, and the lens layer 47 are sequentially formed. In this manner, the light emitting device 1H shown in FIG. 16 is completed.

[0102] In this way, the light emitting device 1H of this modified example uses the light emitting element 11A in which the first conductivity type layer 111, the active layer 112, and the second conductivity type layer 113 are stacked from the optical unit 40 side. Even with this configuration, the same effects as those of the light emitting device 1 of the above embodiment can be obtained.

[0103] (2-5. Modification 5) Fig. 18 is a schematic representation of an example cross-sectional configuration of a light-emitting device according to Modification 5 of the present disclosure (light-emitting device 1I). Fig. 19 is a schematic representation of another example cross-sectional configuration of a light-emitting device according to Modification 5 of the present disclosure (light-emitting device 1J). As with the above embodiment, light-emitting device 1I is suitably applicable to image display devices known as LED displays (for example, electronic viewfinder 1124 of digital still camera 1120).

[0104] In the above embodiment, the external connection terminals 61 are taken out from the light emitting surface side, but this is not limiting. In the light emitting device 1I and the light emitting device 1J of this modification, the external connection terminals 61 are taken out from the surface 20S2 side of the logic substrate 30, which is the side opposite to the light emitting surface.

[0105] The light emitting device 1I is provided with an opening H3 that penetrates the support substrate 31 and reaches the wiring layer 33. The wiring layer 33 is exposed at the bottom of the opening H3. A metal film 62 is formed on the side and bottom of the opening H3, and this metal film 62 is used as an external connection terminal 61. The metal film 62 formed on the support substrate 31 is provided with a bump 63 that is connected to an external power supply or the like.

[0106] The light emitting device 1J has an opening H3 that penetrates the support substrate 31 and reaches the wiring layer 33, and a through electrode 64 is formed in the opening H3 and is used as an external connection terminal 61. The via 3 has a larger diameter than the through electrode 29 that penetrates the semiconductor layer 21 of the analog substrate 20.

[0107] The metal film 62 and the through electrode 64 are formed using, for example, copper (Cu), tantalum (Ta), cobalt (Co), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. Alternatively, the metal film 62 and the through electrode 64 can be formed using, for example, tantalum nitride (TaN) or titanium nitride (TiN). The bump 63 is formed using, for example, copper (Cu), tin-silver (SnAg), or gold (Au).

[0108] In this way, in the light emitting devices 1I and 1J of the present modified example, the external connection terminals 61 are taken out from the surface 20S2 of the logic substrate 30, which is the side opposite to the light emitting surface. Even with this configuration, the same effects as those of the light emitting device 1 of the above embodiment can be obtained.

[0109] 20 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-emitting device (light-emitting device 1K) according to Modification 6 of the present disclosure. Similar to the above embodiment, light-emitting device 1K is suitably applicable to image display devices known as LED displays (for example, electronic viewfinder 1124 of digital still camera 1120).

[0110] As in the above-mentioned variant example 5, when the external connection terminal 61 is taken out from the surface 20S2 of the logic substrate 30 opposite the light emission surface, a glass substrate 49 may be further laminated on the lens layer 47 via a resin layer 48.

[0111] (2-7. Other Modifications) FIGS. 21 to 24 show the stacking modes of the element substrate 10, the analog substrate 20, and the logic substrate 30. FIG.

[0112] 21 is formed by stacking a wafer-shaped element substrate 10, an analog substrate 20, and a logic substrate 30. The stacking configuration in FIG. 21 corresponds to the light emitting devices 1, 1A, and 1C to 1K of the above-described embodiments.

[0113] The light emitting device 1M shown in Fig. 22 is formed by stacking wafer-shaped analog substrates 20 and logic substrates 30 and a plurality of chip-shaped element substrates 10. The embodiment of Fig. 22 corresponds to, for example, the light emitting device 1B of the above-described modified example 2.

[0114] The light emitting device 1N shown in Fig. 23 is formed by stacking a wafer-shaped element substrate 10 and logic substrate 30, and a plurality of chip-shaped analog substrates 20. Fig. 24 shows a light emitting device 1N formed by stacking a wafer-shaped logic substrate 30, a plurality of chip-shaped element substrates 10, and a plurality of chip-shaped analog substrates 20.

[0115] In either case, the same effects as those of the above embodiment can be obtained.

[0116] 3. Application Examples Application Example 1 Fig. 25A is a front view showing an example of the appearance of a digital still camera (electronic device) 1120. Fig. 25B is a rear view showing an example of the appearance of the digital still camera 1120. The digital still camera 1120 is an interchangeable lens single-lens reflex camera. The digital still camera 1120 has an interchangeable taking lens unit (interchangeable lens) 1121 located approximately in the center of the front of a camera main body (camera body) 1122, and a grip part 1123 on the left side of the front for the photographer to hold.

[0117] A monitor 1126 is provided at a position shifted to the left from the center of the back of the camera body 1122. An electronic viewfinder (eyepiece window) 1124 is provided above the monitor 1126. By looking through the electronic viewfinder 1124, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 1121 and determine the composition. The electronic viewfinder 1124 is equipped with a light-emitting device 1.

[0118] (Application Example 2) The light-emitting device (e.g., the light-emitting device 1) of the present disclosure can also be applied to a head-mounted display (hereinafter referred to as an HMD). The head-mounted display 1130A can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), or the like.

[0119] 26A is a perspective view showing the appearance of a head-mounted display (electronic device) 1130A. The head-mounted display 1130A has, for example, ear hooks 1131 on both sides of a glasses-shaped display unit 1132 for wearing on the user's head. The display unit 1132 is equipped with a light-emitting device 1.

[0120] FIG. 26B is a perspective view showing the appearance of another head-mounted display (electronic device). The head-mounted display is smart glasses 1130B that display various information on glasses 1133. The smart glasses 1130B include a main body, an arm 1135, and a lens barrel 1136. The main body 1134 is connected to the arm 1135. The main body 1134 is detachable from the glasses 1133. The main body 1134 incorporates a control board and a display unit for controlling the operation of the smart glasses 1130B. The main body 1134 and the lens barrel 1136 are connected to each other via the arm 1135. The lens barrel 1136 emits image light emitted from the main body 1134 via the arm 1135 toward the lenses 1137 of the glasses 1133. This image light enters the human eye through the lens 1137. 28B, a wearer of the smart glasses 1130B can visually recognize not only the surrounding situation but also various pieces of information emitted from the lens barrel 1136, as with normal glasses. The main body 1134 includes the light-emitting device 1.

[0121] 27 is a perspective view showing an example of the appearance of a television device (electronic device) 1140. This television device 1140 has, for example, an image display screen unit 1141 including a front panel 1142 and a filter glass 1143. The image display screen unit 1141 is equipped with the light-emitting device 1.

[0122] Although the present technology has been described above with reference to the embodiment, modifications 1 to 6, and other modifications and application examples, the present technology is not limited to the above-described embodiment, etc., and various modifications are possible. For example, the element substrate 10 and the logic substrate 30 may be electrically connected via a through electrode.

[0123] In the above-described embodiment, the light emitted from the light-emitting element 11 is blue light or ultraviolet light, but the present invention is not limited to this. For example, the light-emitting device 1 may use a light-emitting element that emits two or more types of light, such as blue light and green light, or ultraviolet light and green light.

[0124] Furthermore, in the above-described embodiment, the light-emitting element (e.g., light-emitting element 11) has a substantially regular hexagonal planar shape, but this is not limiting. The planar shape of light-emitting element 11 may be, for example, a polygonal shape including a square, rectangle, and trapezoid, or a circular shape including an ellipse.

[0125] Furthermore, in the above embodiments, each component constituting the light emitting device 1 etc. has been specifically listed and described, but it is not necessary to include all components, and other components may also be included.

[0126] The effects described in this specification are merely examples and are not limited to those described, and other effects may also be obtained.

[0127] The present technology can also be configured as follows. According to the present technology configured as follows, the area of ​​the drive circuit board is reduced compared to when a drive circuit board having different circuits mounted thereon and nitride semiconductor layers constituting multiple micro LEDs are stacked on a single substrate. This makes it possible to achieve both miniaturization and high functionality. (1) A light-emitting device comprising: a first substrate including a first circuit; a second substrate stacked on the first substrate, including a second circuit having a function different from that of the first circuit and electrically connected to the first substrate; and a third substrate stacked on the second substrate, including a plurality of light-emitting elements arranged in an array and electrically connected to the second substrate. (2) The light-emitting device according to (1), in which the first substrate, the second substrate, and the third substrate are electrically connected to each other. (3) The light-emitting device according to (1) or (2), in which the first substrate, the second substrate, and the third substrate are electrically connected to each other by hybrid bonding. (4) The light-emitting device according to any one of (1) to (3), wherein the first substrate, the second substrate, and the third substrate are stacked in this order, the first substrate further having one or more first pad portions on a first bonding surface facing the second substrate, the second substrate further having one or more second pad portions on a second bonding surface facing the first substrate and one or more third pad portions on a third bonding surface facing the third substrate, the third substrate further having one or more fourth pad portions on a fourth bonding surface facing the second substrate, the first substrate and the second substrate are electrically connected to each other by bonding the one or more first pad portions and the one or more second pad portions together, and the second substrate and the third substrate are electrically connected to each other by bonding the one or more third pad portions and the one or more fourth pad portions together. (5) The light-emitting device according to (4), wherein the one or more first pad portions, the one or more second pad portions, the one or more third pad portions, and the one or more fourth pad portions are each formed using copper (Cu), and the first substrate, the second substrate, and the third substrate are electrically connected to each other by CuCu bonding.(6) The light-emitting device according to any one of (1) to (5), wherein the first substrate, the second substrate, and the third substrate are stacked in this order, the second substrate further includes a semiconductor layer having a first surface and a second surface opposite to each other, and a first through-electrode penetrating between the first surface and the second surface of the semiconductor layer, and the second substrate is electrically connected to the first substrate and the third substrate, respectively, via the first through-electrode. (7) The light-emitting device according to any one of (1) to (6), wherein the first substrate, the second substrate, and the third substrate are stacked in this order, and the first substrate and the third substrate are electrically connected via the through-electrode. (8) The light-emitting device according to any one of (1) to (7), wherein the first circuit and the second circuit have different driving voltages. (9) The light-emitting device according to any one of (1) to (8), wherein the first circuit is a logic circuit. (10) The light emitting device according to any one of (1) to (9), wherein the second circuit is an analog circuit. (11) The light emitting device according to any one of (1) to (10), wherein the third substrate further includes a compound semiconductor layer forming the plurality of light emitting elements, a first insulating layer that embeds the plurality of light emitting elements from the second substrate side, and a second insulating layer provided around the first insulating layer. (12) The light emitting device according to any one of (1) to (11), wherein the third substrate has a fourth bonding surface facing the second substrate and a light emitting surface opposite to the fourth bonding surface, and a microlens is further provided on the light emitting surface side of the third substrate. (13) The light emitting device according to any one of (1) to (12), wherein the third substrate has a fourth bonding surface facing the second substrate and a light emitting surface opposite to the fourth bonding surface, and a wavelength conversion layer that converts the wavelength of light emitted from the plurality of light emitting elements is further provided on the light emitting surface side of the third substrate. (14) The light emitting device according to any one of (1) to (13), wherein the third substrate has a fourth bonding surface facing the second substrate and a light emitting surface opposite to the fourth bonding surface, and a glass substrate is further laminated on the light emitting surface side of the third substrate via a resin layer.(15) The light-emitting device according to any one of (1) to (14), wherein the first substrate, the second substrate, and the third substrate are stacked in this order, and the first substrate further has an external connection terminal on a surface opposite to a first bonding surface facing the second substrate. (16) The light-emitting device according to (15), wherein the first substrate further includes a support substrate having opposing third and fourth surfaces, and the first circuit is provided on the third surface side of the support substrate, and the external connection terminal is provided on the fourth surface side of the support substrate. (17) The light-emitting device according to (16), wherein the first substrate further has an opening penetrating between the third and fourth surfaces of the support substrate, and the external connection terminal is electrically connected to the first circuit via a second through-electrode formed in the opening. (18) The light-emitting device according to (17), wherein the first substrate, the second substrate, and the third substrate are stacked in this order, the second substrate further includes a semiconductor layer having a first surface and a second surface opposing each other, and a first through electrode that penetrates between the first surface and the second surface of the semiconductor layer, and the second through electrode has a diameter larger than that of the first through electrode. (19) The light-emitting device according to any one of (15) to (18), wherein the external connection terminal is connected to an external power supply via a bump. (20) An image display device comprising a light-emitting device, the light-emitting device having: a first substrate including a first circuit; a second substrate stacked on the first substrate, including a second circuit having a function different from the first circuit and electrically connected to the first substrate; and a third substrate stacked on the second substrate, including a plurality of light-emitting elements arranged in an array and electrically connected to the second substrate.

[0128] This application claims priority based on Japanese Patent Application No. 2024-040748, filed on March 15, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0129] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A light emitting device comprising: a first substrate including a first circuit; a second substrate stacked on the first substrate, including a second circuit having a function different from that of the first circuit and electrically connected to the first substrate; and a third substrate stacked on the second substrate, including a plurality of light emitting elements arranged in an array and electrically connected to the second substrate.

2. The light emitting device according to claim 1, wherein the first substrate, the second substrate, and the third substrate are electrically connected to each other.

3. The light emitting device according to claim 1, wherein the first substrate, the second substrate, and the third substrate are electrically connected to one another by hybrid bonding.

4. The light-emitting device described in claim 1, wherein the first substrate, the second substrate, and the third substrate are stacked in this order, the first substrate further having one or more first pad portions on a first bonding surface facing the second substrate, the second substrate further having one or more second pad portions on a second bonding surface facing the first substrate and one or more third pad portions on a third bonding surface facing the third substrate, the third substrate further having one or more fourth pad portions on a fourth bonding surface facing the second substrate, the first substrate and the second substrate are electrically connected to each other by bonding the one or more first pad portions and the one or more second pad portions together, and the second substrate and the third substrate are electrically connected to each other by bonding the one or more third pad portions and the one or more fourth pad portions together.

5. The light-emitting device described in claim 4, wherein the one or more first pad portions, the one or more second pad portions, the one or more third pad portions, and the one or more fourth pad portions are each formed using copper (Cu), and the first substrate, the second substrate, and the third substrate are electrically connected to each other by CuCu bonding.

6. The light-emitting device described in claim 1, wherein the first substrate, the second substrate, and the third substrate are stacked in this order, the second substrate further includes a semiconductor layer having opposing first and second surfaces, and a first through-electrode that penetrates between the first and second surfaces of the semiconductor layer, and the second substrate is electrically connected to the first substrate and the third substrate, respectively, via the first through-electrode.

7. The light-emitting device according to claim 1, wherein the first substrate, the second substrate, and the third substrate are stacked in this order, and the first substrate and the third substrate are electrically connected via a through electrode.

8. The light emitting device according to claim 1, wherein the first circuit and the second circuit have different driving voltages.

9. The light emitting device according to claim 1, wherein the first circuit is a logic circuit.

10. The light emitting device according to claim 1, wherein the second circuit is an analog circuit.

11. The light-emitting device described in claim 1, wherein the third substrate further has a compound semiconductor layer forming the plurality of light-emitting elements, a first insulating layer that embeds the plurality of light-emitting elements from the second substrate side, and a second insulating layer provided around the first insulating layer.

12. The light-emitting device according to claim 1, wherein the third substrate has a fourth bonding surface facing the second substrate and a light-emitting surface opposite the fourth bonding surface, and a microlens is further provided on the light-emitting surface side of the third substrate.

13. The light-emitting device according to claim 1, wherein the third substrate has a fourth bonding surface facing the second substrate and a light-emitting surface opposite the fourth bonding surface, and a wavelength conversion layer that converts the wavelength of light emitted from the plurality of light-emitting elements is further provided on the light-emitting surface side of the third substrate.

14. The light-emitting device according to claim 1, wherein the third substrate has a fourth bonding surface facing the second substrate and a light-emitting surface opposite the fourth bonding surface, and a glass substrate is further laminated on the light-emitting surface side of the third substrate via a resin layer.

15. The light-emitting device described in claim 1, wherein the first substrate, the second substrate, and the third substrate are stacked in this order, and the first substrate further has an external connection terminal on the surface opposite to the first bonding surface facing the second substrate.

16. The light-emitting device described in claim 15, wherein the first substrate further includes a support substrate having opposing third and fourth surfaces, the first circuit is provided on the third surface side of the support substrate, and the external connection terminal is provided on the fourth surface side of the support substrate.

17. The light-emitting device described in claim 16, wherein the first substrate further has an opening penetrating between the third surface and the fourth surface of the support substrate, and the external connection terminal is electrically connected to the first circuit via a second penetrating electrode formed in the opening.

18. The light-emitting device described in claim 17, wherein the first substrate, the second substrate, and the third substrate are stacked in this order, the second substrate further includes a semiconductor layer having opposing first and second surfaces, and a first through electrode that penetrates between the first and second surfaces of the semiconductor layer, and the second through electrode has a larger diameter than the first through electrode.

19. The light emitting device according to claim 15, wherein the external connection terminal is connected to an external power supply via a bump.

20. An image display device comprising a light-emitting device, the light-emitting device having: a first substrate including a first circuit; a second substrate stacked on the first substrate, including a second circuit having a function different from that of the first circuit and electrically connected to the first substrate; and a third substrate stacked on the second substrate, including a plurality of light-emitting elements arranged in an array and electrically connected to the second substrate.

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