Display substrate

Abstract

The present disclosure provides a display substrate, comprising a base and a transistor located on one side of the base, the transistor comprising a gate, an active layer, and a first insulating layer, which is located on the side of the active layer facing away from the base and covering the active layer. The first insulating layer comprises a first insulating sub-layer close to the active layer and a second insulating sub-layer away from the active layer, and the oxygen content of the second insulating sub-layer is higher than the oxygen content of the first insulating sub-layer.

Description

Display substrate TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display substrate. BACKGROUND

[0002] With the increasing demand for high-resolution, high-refresh rate, low power consumption, narrow frame and other high-performance displays, the demand for high-mobility oxide transistors is more and more obvious. Using high-mobility oxide material as the active layer is the main method to improve the performance of oxide transistors. However, the improvement of the mobility of high-mobility oxide transistors is prone to reduce the stability, and the stability is the key to restrict the performance improvement of oxide products.

[0003] SUMMARY

[0004] The present disclosure provides a display substrate, comprising a substrate and a transistor located on one side of the substrate, the transistor comprising a gate, an active layer, and

[0005] A first insulating layer is located on the side of the active layer away from the substrate and covers the active layer; wherein the first insulating layer comprises a first insulating sub-layer close to the active layer and a second insulating sub-layer away from the active layer, and the oxygen content of the second insulating sub-layer is higher than that of the first insulating sub-layer.

[0006] In some embodiments, the difference between the oxygen contents of the first insulating sub-layer and the second insulating sub-layer ranges from 1-15%.

[0007] In some embodiments, the ratio of the difference between the oxygen contents of the first insulating sub-layer and the second insulating sub-layer to the oxygen content of the first insulating sub-layer ranges from 3-10%.

[0008] In some embodiments, the thickness of the first insulating sub-layer is The thickness of the second insulating sub-layer is

[0009] In some embodiments, the sum of the thickness of the first insulating sub-layer and the thickness of the second insulating sub-layer is

[0010] In some embodiments, the oxygen content of the first insulating sub-layer is less than 65%, and the oxygen content of the second insulating sub-layer is greater than 70%.

[0011] In some embodiments, the first insulating layer comprises silicon and oxygen elements, and the Si-O peak positions of the first insulating sub-layer and the second insulating sub-layer are different.

[0012] In some embodiments, the transistor further comprises a second insulating layer between the gate and the active layer, wherein the second insulating layer comprises silicon element and oxygen element.

[0013] In some embodiments, the oxygen content of the second insulating layer is greater than the oxygen content of the first insulating sub-layer and less than the oxygen content of the second insulating sub-layer.

[0014] In some embodiments, the Si-O peak position of the first insulating sub-layer is less than the Si-O peak position of the second insulating layer, and the Si-O peak position of the second insulating layer is less than the Si-O peak position of the second insulating sub-layer.

[0015] In some embodiments, the second insulating layer comprises a third insulating sub-layer close to the active layer and a fourth insulating sub-layer away from the active layer, and the oxygen content of the fourth insulating sub-layer is higher than the oxygen content of the third insulating sub-layer.

[0016] In some embodiments, the thickness of the third insulating sub-layer is the thickness of the fourth insulating sub-layer is

[0017] In some embodiments, the oxygen content of the fourth insulating sub-layer is greater than 70%, and the oxygen content of the third insulating sub-layer is less than 65%.

[0018] In some embodiments, the Si-O peak position of the fourth insulating sub-layer is different from the Si-O peak position of the third sub-layer.

[0019] In some embodiments, the oxygen content of the first insulating sub-layer and the third insulating sub-layer is less than the oxygen content of the second insulating sub-layer and the fourth insulating sub-layer.

[0020] In some embodiments, the Si-O peak position of the first insulating sub-layer and the third insulating sub-layer is less than the Si-O peak position of the second insulating sub-layer and the fourth insulating sub-layer.

[0021] In some embodiments, the transistor further comprises a first source-drain electrode layer and a second source-drain electrode layer, and the second source-drain electrode layer is consistent with the pattern of the first source-drain electrode layer and completely covers the first source-drain electrode layer.

[0022] In some embodiments, the material of the second source-drain electrode layer is an oxidation-resistant metal.

[0023] In some embodiments, the width of the sidewall of the second source-drain electrode layer in the direction parallel to the substrate is greater than 0.5 μm.

[0024] In some embodiments, the thickness of the metal oxide material between the second source-drain electrode layer and the first source-drain electrode layer is less than 0.1 μm.

[0025] In some embodiments, the active layer is located on the side of the gate electrode closer to the substrate, and the first insulating layer is located on the side of the gate electrode farther from the substrate.

[0026] In some embodiments, the difference in oxygen content between the first insulating sub-layer and the second insulating sub-layer ranges from 1-15%.

[0027] In some embodiments, the ratio of the difference in oxygen content between the first insulating sub-layer and the second insulating sub-layer to the oxygen content of the first insulating sub-layer ranges from 3-10%.

[0028] In some embodiments, the thickness of the first insulating sub-layer is the thickness of the second insulating sub-layer is

[0029] In some embodiments, the oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

[0030] In some embodiments, the first insulating layer includes silicon and oxygen elements, and the Si-O peak positions of the first insulating sub-layer and the second insulating sub-layer are different.

[0031] In some embodiments, the active layer includes a channel region and first and second end portions located on opposite sides of the channel region, the first and second end portions are conductorized, and the transistor further includes source and drain electrodes disposed above the active layer, one of the source and drain electrodes is in contact with the first end portion, and the other of the source and drain electrodes is in contact with the second end portion.

[0032] In some embodiments, the active layer includes a metal oxide material, and includes a first metal oxide layer and a second metal oxide layer, the second metal oxide layer is located on at least one of the side facing the substrate or the side facing away from the substrate of the first metal oxide layer, the carrier concentration of the second metal oxide layer is lower than the carrier concentration of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than the band gap of the first metal oxide layer.

[0033] In some embodiments, the material of the second metal oxide layer is the same type of material as the material of the first metal oxide layer.

[0034] In some embodiments, the active layer comprises indium element and at least one of gallium element, zinc element and tin element, the oxygen content of the first metal oxide layer is less than the oxygen content of the second metal oxide layer, and the indium content of the first metal oxide layer is 1-8% higher than the indium content of the second metal oxide layer.

[0035] In some embodiments, the active layer comprises zinc element, gallium element and rare earth element, and the contents of zinc element, gallium element and rare earth element in the first metal oxide layer are respectively lower than the contents of zinc element, gallium element and rare earth element in the second metal oxide layer.

[0036] In some embodiments, the material of the second metal oxide layer is different from the material of the first metal oxide layer.

[0037] In some embodiments, the second metal oxide layer is located on the side of the first metal oxide layer facing the substrate and the side of the first metal oxide layer facing away from the substrate, the first metal oxide layer comprises a rare earth doped metal oxide material, the second metal oxide layer located on the side of the first metal oxide layer facing the substrate comprises a non-rare earth doped metal oxide material, and the indium content of the second metal oxide layer located on the side of the first metal oxide layer facing away from the substrate is lower than the indium content of the first metal oxide layer. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative effort based on these drawings.

[0039] FIG. 1 shows a schematic diagram of a cross-sectional structure of a transistor according to an embodiment of the present disclosure;

[0040] FIG. 2 shows a schematic diagram in which a low-oxygen-content first silicon oxide layer in a first passivation layer protects an active layer;

[0041] FIG. 3 shows a schematic diagram in which a high-oxygen-content second silicon oxide layer in a first passivation layer supplements oxygen for an active layer;

[0042] FIG. 4(a) shows an SEM cross-sectional view of a transistor with a first passivation layer using a silicon oxide stack;

[0043] FIG. 4(b) shows an SEM cross-sectional view of a transistor with a first passivation layer using only high-oxygen-content silicon oxide;

[0044] Figure 5(a) shows the transfer characteristic curve of a transistor with a low-oxygen-content silicon oxide layer as the first passivation layer;

[0045] Figure 5(b) shows the transfer characteristic curve of a transistor with a high-oxygen-content silicon oxide layer as the first passivation layer;

[0046] Figure 5(c) shows the transfer characteristic curve of a transistor with a low-oxygen-content / high-oxygen-content silicon oxide stack as the first passivation layer;

[0047] Figure 6 shows the FT-IR test curve of a low-oxygen-content silicon oxide layer and a high-oxygen-content silicon oxide layer;

[0048] Figure 7 shows a cross-sectional structure schematic diagram of a transistor according to one embodiment of the present disclosure;

[0049] Figure 8 shows a cross-sectional structure schematic diagram of a transistor according to one embodiment of the present disclosure;

[0050] Figure 9 shows a cross-sectional structure schematic diagram of a transistor according to one embodiment of the present disclosure;

[0051] Figure 10 is a schematic diagram of channel defect states and channel trap centers of a rare earth element-doped oxide material in the related art;

[0052] Figure 11 is a transistor PBTS test result graph in the related art;

[0053] Figure 12 shows a cross-sectional structure schematic diagram of a transistor according to one embodiment of the present disclosure;

[0054] Figure 13 shows a cross-sectional structure schematic diagram of a transistor according to one embodiment of the present disclosure;

[0055] Figure 14 shows a cross-sectional structure schematic diagram of a transistor according to one embodiment of the present disclosure;

[0056] Figure 15 is a transistor PBTS test result graph according to one embodiment of the present disclosure;

[0057] Figure 16 is a transistor NBTIS test result graph with a single-layer oxide and a stack oxide as the active layer, respectively;

[0058] Figure 17 is a TEM cross-sectional view of a stack oxide structure of an active layer;

[0059] Figures 18(a)-18(f) show cross-sectional schematic diagrams of a transistor fabrication process according to embodiments of the present disclosure;

[0060] Figure 19 shows a cross-sectional schematic diagram of a transistor fabrication process according to embodiments of the present disclosure;

[0061] FIG. 20 shows a cross-sectional schematic view of a transistor fabrication process according to an embodiment of the present disclosure;

[0062] FIG. 21 shows a cross-sectional schematic view of a transistor fabrication process according to an embodiment of the present disclosure;

[0063] FIG. 22 shows a cross-sectional schematic view of a transistor fabrication process according to an embodiment of the present disclosure;

[0064] FIG. 23 shows a cross-sectional schematic view of a transistor fabrication process according to an embodiment of the present disclosure.

[0065] It should be understood that the appended drawings are not necessarily to scale, present a simplified representation of illustrative embodiments of the present disclosure, and form no part of the present disclosure, and the limitation thereof should not be implied by the inclusion thereof in the detailed description. In addition, elements common between various drawings are denoted by like reference numerals. DETAILED DESCRIPTION

[0066] At present, using high mobility oxide material as an active layer is the mainstream method for improving the performance of oxide transistors. In order to improve the problem of deterioration of characteristics such as negative bias caused by high mobility oxide material, it is usually necessary to supplement oxygen to the active layer through a high oxygen content dielectric layer, in which the insulating layer adjacent to the active layer is a key film layer affecting the characteristics. However, the high power used in depositing the high oxygen content insulating layer will cause damage to the channel, and in addition, the high oxygen content insulating layer is also prone to cause serious oxidation of the source-drain metal layer, resulting in damage to the device structure. The structure of the oxide transistor in the related art is contradictory in terms of channel oxygen supplementation and avoiding channel damage and avoiding oxidation of the source-drain metal layer, and it is difficult to take both into account.

[0067] Meanwhile, the inventors also realized that when high mobility (20-40 cm 2 / Vs) oxide transistors and ultrahigh mobility (greater than 40 cm 2 / Vs mobility) oxide transistors use a single layer of high mobility oxide material as an active layer, they are easily affected by impurity elements such as H in the passivation layer or etching liquid in the source-drain patterning process, forming a large number of defects in the back channel or a large number of defect states in the channel, resulting in a significant reduction in stability and seriously affecting the device characteristics.

[0068] The inventors of the present application propose a transistor display substrate, comprising a substrate and a transistor located on one side of the substrate, characterized in that: the insulating layer adjacent to the active layer is arranged in a low-oxygen-content / high-oxygen-content laminated structure, wherein the side close to the active layer adopts a low-oxygen-content insulating layer, and the side away from the active layer adopts a high-oxygen-content insulating layer. On the one hand, such a structure can avoid plasma damage caused by high-power deposition and protect the active layer; on the other hand, such a structure can weaken the oxidation of the metal of the source-drain electrode layer and avoid structural damage caused by serious oxidation of the metal of the source-drain electrode layer; moreover, the high-oxygen-content insulating layer can supplement oxygen to the active layer through diffusion after the annealing process, which can improve the negative bias characteristic problem of high-mobility oxide transistors and ensure the high-performance device characteristics.

[0069] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0070] It can be understood that the drawings in the embodiments of the present disclosure are only used for illustratively showing the connection relationship between the components, the sizes of the components in the drawings are not drawn according to the proportion, and their relative position relationship does not necessarily correspond to the actual position completely. In the drawings, the proportion of some regions and layers may be exaggerated for clarity.

[0071] Generally, a transistor includes a gate, an active layer, a source and a drain. The embodiments of the present disclosure provide a display substrate, comprising a substrate and a transistor located on one side of the substrate. FIG. 1 shows a cross-sectional schematic view of a transistor according to an embodiment of the present disclosure. As shown in FIG. 1, the transistor includes a gate 12, a gate insulating layer 13 / 14, an active layer 15, a drain 16, a first passivation layer 171 / 172, a second passivation layer 18, etc. arranged in sequence on a substrate 11. The transistor shown in FIG. 1 is a bottom gate structure, i.e. the active layer 15 is located on the side of the gate 12 away from the substrate 11, and the active layer 15 can include a high-mobility metal oxide material, wherein the first passivation layer includes a first insulating layer, the first insulating layer includes a first insulating sub-layer 171 close to the active layer and a second insulating sub-layer 172 away from the active layer, and the oxygen content of the second insulating sub-layer 172 is higher than that of the first insulating sub-layer 171.

[0072] It should be noted that the first insulating layer can include multiple sub-layers, which can refer to a layer structure with a clear interface between each other in a micro view, or a layer structure with different materials or containing the same element but different element contents without a clear interface.

[0073] In the embodiment of the transistor as shown in Fig. 1, the first passivation layer adopts a stacked structure of the first insulating layer, in which the first silicon oxide layer 171 close to the active layer 15 adopts low-oxygen-content silicon oxide, and the second silicon oxide layer 172 away from the active layer 15 adopts high-oxygen-content silicon oxide. On the one hand, such a structure can avoid plasma damage caused by high power used for directly depositing high-oxygen-content silicon oxide on the active layer, and protect the active layer. On the other hand, such a structure can weaken the oxidation of the metal of the source-drain electrode layer, avoid structural damage caused by serious oxidation of the metal of the source-drain electrode layer, and, through diffusion, the high-oxygen-content silicon oxide layer can supplement oxygen to the active layer through an annealing process, improve the negative bias characteristic problem prone to occur in high-mobility oxide transistors, and ensure high-performance device characteristics.

[0074] Figure 2 shows a schematic diagram of a low-oxygen-content first silicon oxide layer in the first passivation layer protecting the active layer. Figure 3 shows a schematic diagram of a high-oxygen-content second silicon oxide layer in the first passivation layer oxygenating the active layer. After the device is soaked in hydrofluoric acid, scanning electron microscope detection can clearly distinguish the various film layers. Figure 4(a) shows an SEM cross-sectional view of a transistor with a first passivation layer using a low-oxygen-content / high-oxygen-content silicon oxide stack; the film layer indicated by PVX1-1 Bottom SiO corresponds to the low-oxygen-content first silicon oxide layer 171 in the first passivation layer in Figure 1, the film layer indicated by PVX1-1 Top SiO corresponds to the high-oxygen-content second silicon oxide layer 172 in the first passivation layer in Figure 1, the film layer indicated by PVX1-2 SiN corresponds to the second passivation layer 18 in Figure 1, and the structure indicated by SD corresponds to the source-drain metal layer 16 in Figure 1. Figure 4(b) shows an SEM cross-sectional view of a transistor with a first passivation layer using only high-oxygen-content silicon oxide; the film layer indicated by PVX1-1 SiO corresponds to the first passivation layer using only high-oxygen-content silicon oxide, the film layer indicated by PVX1-2 SiN corresponds to the second passivation layer, and the structure indicated by SD corresponds to the source-drain metal layer. It should be understood that the thickness of the oxide layer of the source-drain metal layer is not significantly related to the thickness of the source-drain metal layer itself, and the metal oxidation of the source-drain electrode layer is mainly determined by the chamber atmosphere during deposition, rather than the oxygen content in the thin film after deposition is completed. The high power, high N2O ratio, and high temperature used in the deposition process of high-oxygen-content silicon oxide are prone to cause metal oxidation of the source-drain electrode layer, and the metal oxide layer of the source-drain electrode layer mainly appears on the sidewall of the source-drain electrode layer metal, as indicated by the arrow in Figure 4(b). The metal oxidation of the source-drain electrode layer may cause the rupture of the first passivation layer, so it is necessary to avoid the metal oxidation of the source-drain electrode layer as much as possible. However, as shown in Figure 4(a), the use of a low-oxygen-content silicon oxide layer as the first passivation layer can effectively prevent the sidewall of the source-drain electrode layer metal from being oxidized, thereby avoiding the risk of rupture of the first passivation layer.

[0075] Figure 5(a) shows the transfer characteristic curve of a transistor using a low-oxygen-content silicon oxide layer as the first passivation layer; Figure 5(b) shows the transfer characteristic curve of a transistor using a high-oxygen-content silicon oxide layer as the first passivation layer; and Figure 5(c) shows the transfer characteristic curve of a transistor using a low-oxygen-content / high-oxygen-content silicon oxide stack as the first passivation layer. As can be seen from Figures 5(a)-5(c), the Id-Vg characteristic of the transistor using a low-oxygen-content / high-oxygen-content silicon oxide stack as the first passivation layer is significantly better than that of the transistor using only a low-oxygen-content silicon oxide layer or only a high-oxygen-content silicon oxide layer as the first passivation layer.

[0076] In some embodiments, the difference in oxygen content between the first insulating sub-layer and the second insulating sub-layer is in the range of 1-15%. Optionally, the difference in oxygen content between the first insulating sub-layer and the second insulating sub-layer is in the range of 2-5%.

[0077] In some embodiments, the ratio of the difference in oxygen content between the first insulating sub-layer and the second insulating sub-layer to the oxygen content of the first insulating sub-layer is in the range of 3-10%.

[0078] In the present disclosure, the oxygen content refers to the atomic percentage of oxygen element in a target film layer or a target region obtained by a certain testing method, including but not limited to EDX, DSIMS or Tof-SIM.

[0079] In some embodiments, the thickness of the first insulating sub-layer 171 can be in the range of 0.5-2 nm. The thickness of the second insulating sub-layer 172 can be in the range of 0.5-2 nm. Optionally, the sum of the thickness of the first insulating sub-layer and the thickness of the second insulating sub-layer is in the range of 1-4 nm.

[0080] In some embodiments, the first insulating layer comprises silicon element and oxygen element, and the Si-O peak positions of the first insulating sub-layer and the second insulating sub-layer are different. FIG. 6 shows the FT-IR test curves of a low-oxygen-content silicon oxide layer and a high-oxygen-content silicon oxide layer, in which arrow 1 indicates the FT-IR test curve of the first silicon oxide layer with low oxygen content, and arrow 2 indicates the FT-IR test curve of the second silicon oxide layer with low oxygen content. In some embodiments, the Si-O peak position of the first silicon oxide layer is less than 1062 cm -1 , and the Si-O peak position of the second silicon oxide layer is greater than 1064 cm -1 .

[0081] The oxygen content of the first silicon oxide layer and the second silicon oxide layer can also be tested by EDS, and in some embodiments, the oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

[0082] In some embodiments, as shown in FIG. 1, the gate insulating layer of the transistor can include a silicon nitride layer 13 on the gate 12 and a second insulating layer 14 on the side of the silicon nitride layer away from the gate. Optionally, the oxygen content of the first silicon oxide layer 171 is less than the oxygen content of the second insulating layer 14, and the oxygen content of the second insulating layer 14 is less than the oxygen content of the second silicon oxide layer 172. Optionally, the Si-O peak of the first silicon oxide layer 171 is less than the Si-O peak of the second insulating layer 14, and the Si-O peak of the third silicon oxide layer 14 is less than the Si-O peak of the second silicon oxide layer 142.

[0083] In some embodiments, as shown in FIG. 7, the second insulating layer in the gate insulating layer includes a stacked structure 141 / 142, i.e., the second insulating layer includes a third insulating sublayer 142 close to the active layer 15 and a fourth insulating sublayer 141 away from the active layer 15, and the oxygen content of the fourth insulating sublayer 141 is higher than the oxygen content of the third insulating sublayer 142.

[0084] The embodiment shown in FIG. 7 employs a stacked structure of silicon oxide layers in the gate insulating layer, which can block the hydrogen diffusion of the silicon nitride layer 13 of the gate insulating layer during the annealing process by employing a high-oxygen-content silicon oxide layer in the fourth insulating sublayer 141 away from the active layer 15, and can reduce the interface defects between the silicon oxide layer of the gate insulating layer and the active layer by employing a low-oxygen-content silicon oxide layer in the third insulating sublayer 142 close to the active layer 15, thereby ensuring high-performance device characteristics.

[0085] In some embodiments, the thickness of the third insulating sublayer 142 is 0.5-2 nm. The thickness of the fourth insulating sublayer 141 is 0.5-2 nm.

[0086] In some embodiments, the oxygen content of the fourth insulating sublayer 141 is greater than 70%, and the oxygen content of the third insulating sublayer 142 is less than 65%.

[0087] In some embodiments, the Si-O peak of the fourth insulating sublayer is different from that of the third insulating sublayer. Optionally, the Si-O peak of the fourth insulating sublayer 141 is greater than 1060 cm-1, and the Si-O peak of the third insulating sublayer 142 is less than 1055 cm-1. - 1 -1 .

[0088] In some embodiments, the oxygen content of the first insulating sublayer 171 and the third insulating sublayer 142 is less than the oxygen content of the second insulating sublayer 172 and the fourth insulating sublayer 141.

[0089] ​In some embodiments, the Si-O peak position of the first insulating sub-layer 171 and the third insulating sub-layer 142 is less than the Si-O peak position of the second insulating sub-layer 172 and the fourth insulating sub-layer 141.

[0090] The embodiment shown in FIG. 7 is that the stacked silicon oxide structure is provided in both the first passivation layer and the gate insulating layer, which is not necessarily required. Those skilled in the art can understand that in fact, the silicon oxide stacked structure can also be provided only in the gate insulating layer, a high-oxygen-content silicon oxide layer is arranged on the side far from the active layer to block the hydrogen diffusion of the silicon nitride layer of the gate insulating layer in the annealing process, and a low-oxygen-content silicon oxide layer is arranged on the side close to the active layer to reduce the interface defects between the silicon oxide layer of the gate insulating layer and the active layer, and to ensure high-performance device characteristics.

[0091] FIG. 8 shows a schematic diagram of a cross-sectional structure of a transistor according to an embodiment of the present disclosure, in which the source-drain electrode layer of the transistor is a double-layer structure. As shown in FIG. 8, the transistor includes a first source-drain electrode layer 161 and a second source-drain electrode layer 162, which is consistent with the pattern of the first source-drain electrode layer 161 and completely covers the first source-drain electrode layer 161.

[0092] By depositing the second source-drain electrode layer 162 on the first source-drain electrode layer 161, the sidewall of the first source-drain electrode layer 161 can be protected from oxidation.

[0093] In some embodiments, the material of the second source-drain electrode layer can be an oxidation-resistant metal. Here, the oxidation-resistant metal can refer to a metal that is chemically stable and has low electrochemical activity, and is difficult to react with water and oxygen, so it can prevent the diffusion and penetration of other metals. For example, the material of the second source-drain electrode layer can be an alloy material such as MO, MoNb, MoNi, MoNiTi, etc.

[0094] In some embodiments, the thickness of the sidewall of the second source-drain electrode layer in the direction parallel to the substrate (the width shown as W in FIG. 8) is greater than 0.5 μm.

[0095] The transistors shown in FIGS. 1, 7, and 8 are bottom-gate structures, and the inventive concept of the present disclosure is also applicable to top-gate structure transistors.

[0096] FIG. 9 shows a schematic diagram of a cross-sectional structure of a transistor in a top-gate structure according to an embodiment of the present disclosure. As shown in FIG. 9, the transistor includes, in sequence on a substrate 11, a light-shielding layer 23, a buffer layer 24 / 25, an active layer 26 / 261 / 262, a gate insulating layer 27, a gate 28, an interlayer dielectric layer 301 / 302, a source-drain electrode layer 31, a passivation layer 32, etc., wherein the interlayer dielectric layer adopts a stacked structure of first insulating layers including a first insulating sub-layer 301 close to the active layer and a second insulating sub-layer 302 away from the active layer, and the oxygen content of the second insulating sub-layer 302 is higher than that of the first insulating sub-layer 301. In the embodiment shown in FIG. 9, the first insulating sub-layer 301 can adopt a first silicon oxide layer 301 with low oxygen content, and the second insulating sub-layer 302 can adopt a second silicon oxide layer 302 with high oxygen content.

[0097] In some embodiments, the active layer includes a channel region 26 and first and second end portions 261 and 262 respectively located on both sides of the channel region 26, the first and second end portions 261 and 262 are subjected to conductorization treatment, and the transistor further includes source and drain electrodes disposed above the active layer, one of the source and drain electrodes is in contact with the first end portion 261, and the other of the source and drain electrodes is in contact with the second end portion 262.

[0098] The interlayer dielectric layer of the transistor shown in FIG. 9 adopts a stacked silicon oxide structure, wherein the first silicon oxide layer 301 close to the active layer 26 / 261 / 262 adopts a silicon oxide layer with low oxygen content, which on one hand avoids the increase of resistance of the conductorized region caused by oxygen deposition of the interlayer dielectric layer, and on the other hand avoids the oxidation of the side surface of the gate 28 caused by deposition of the interlayer dielectric layer, thereby preventing structural damage. The second silicon oxide layer 302 away from the active layer 26 / 261 / 262 adopts a silicon oxide layer with high oxygen content, which blocks the diffusion of hydrogen in the passivation layer and other film layers and supplies oxygen to the channel during subsequent annealing, thereby ensuring the characteristics of the device.

[0099] In some embodiments, the thickness of the first silicon oxide layer is 1-10 nm. The thickness of the second silicon oxide layer is 1-10 nm.

[0100] In some embodiments, the oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

[0101] In some embodiments, the Si-O peak of the first silicon oxide layer is different from the Si-O peak of the second silicon oxide layer. Optionally, the Si-O peak of the first silicon oxide layer is less than 1062 cm-1, and the Si-O peak of the second silicon oxide layer is greater than 1064 cm-1. -1 -1 ​.

[0102] In the above embodiments, a single layer of high mobility oxide material is used as the active layer. In the related art, high mobility (20-40 cm 2 / Vs) oxide transistors and ultra-high mobility (more than 40 cm 2 / Vs mobility) oxide transistors typically use a small amount of element-doped oxide material as the active layer, such as rare earth element and Ta, W, etc. doped oxides. Rare earth elements include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y) and scandium (Sc), and the main elements are In, Ga, Zn, Sn, and two or more elements formed by the material, such as IZO+rare earth, ITO+rare earth, IZO+rare earth, IGZO+rare earth, ITZO+rare earth, etc. By adding rare earth materials to the main material, high / ultra-high mobility oxide transistors can be achieved, and the light stability of the transistor is significantly improved. However, the inventors have realized that this type of oxide material has significantly improved sensitivity to defects (acceptor state defects), and is extremely susceptible to voltage resistance, current resistance, and high temperature stability problems, such as applying a bias voltage to the gate at high temperature, which can cause a significant positive shift in the threshold voltage V th . Figure 10 is a schematic diagram of the channel defect state and channel trap center of the rare earth element-doped oxide material in the related art. Figure 11 is a transistor PBTS test result graph in the related art. In the presence of defects as shown in Figure 10, the threshold voltage V th continuously shifts positively, as shown in Figure 11, which will seriously affect the normal operation of the device. In addition, when the rare earth-doped oxide is applied to a back channel etching type device, if the back channel is damaged significantly, it can cause the threshold voltage V th continuously shifts negatively in the NBTIS (negative gate-bias thermal stress with illumination) test.

[0103] The present disclosure proposes a multi-layer oxide structure active layer, which can solve the above problems of insufficient bias stability and insufficient light stability, and effectively improve the stability of the device.

[0104] In embodiments of the present disclosure, wherein the active layer comprises a metal oxide material, and comprises a first metal oxide layer and a second metal oxide layer, the second metal oxide layer is located on at least one of the side of the first metal oxide layer facing the substrate or the side of the first metal oxide layer facing away from the substrate, the first metal oxide layer is composed of a small element doped oxide material with high carrier concentration, the carrier concentration of the second metal oxide layer is lower than the carrier concentration of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than the band gap of the first metal oxide layer.

[0105] Figure 12 shows a schematic diagram of the cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the active layer comprises a first metal oxide layer 151 and a second metal oxide layer 152, the second metal oxide layer 152 is located on the side of the first metal oxide layer 151 facing away from the substrate 11, the first metal oxide layer 151 is composed of a small element doped oxide material with high carrier concentration, the carrier concentration of the second metal oxide layer 152 is lower than the carrier concentration of the first metal oxide layer 151, and the band gap of the second metal oxide layer 152 is wider than the band gap of the first metal oxide layer 151.

[0106] Figure 13 shows a schematic diagram of the cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the active layer comprises a first metal oxide layer 151 and two second metal oxide layers 152, the second metal oxide layers 152 are respectively located on the side of the first metal oxide layer 151 facing the substrate and the side of the first metal oxide layer 151 facing away from the substrate 11, the first metal oxide layer 151 is composed of a small element doped oxide material with high carrier concentration, the carrier concentration of the second metal oxide layers 152 is lower than the carrier concentration of the first metal oxide layer 151, and the band gap of the second metal oxide layers 152 is wider than the band gap of the first metal oxide layer 151.

[0107] Figures 12 and 13 show the arrangement of the active layer in a bottom gate structure transistor, wherein the first passivation layer is shown as the first insulating layer of the stack structure, however this does not represent a limitation of the present disclosure, and those skilled in the art can understand that the improvement scheme proposed in the present disclosure can be applied to both the active layer and the passivation layer, or only to the active layer, and the scheme of improving only the active layer also falls within the protection scope of the present disclosure.

[0108] The improved active layer scheme proposed in the present application is also applicable to transistors of top-gate structure. FIG. 14 shows a schematic diagram of a cross-sectional structure of a transistor according to an embodiment of the present disclosure, wherein the transistor is of top-gate structure, and the active layer includes a first metal oxide layer 261 and a second metal oxide layer 262, the second metal oxide layer 262 is located on the side of the first metal oxide layer 261 facing the substrate 11, the first metal oxide layer 261 is composed of a small amount of element-doped oxide material with high carrier concentration, the carrier concentration of the second metal oxide layer 262 is lower than that of the first metal oxide layer 261, and the band gap of the second metal oxide layer 262 is wider than that of the first metal oxide layer 261.

[0109] In embodiments of the present disclosure, the material of the first metal oxide layer may, for example, be a small amount of element-doped IGZO, ITZO, IZO, IGO, ITO, etc. oxide material, the small amount of elements including lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y), and scandium (Sc), tungsten (W), tantalum (Ta), and may be a doping body composed of one or more than two elements of the above, for example, Pr-doped IGZO material.

[0110] In some embodiments, the material of the second metal oxide layer 152 / 262 and the material of the first metal oxide layer 151 / 261 can be the same type of material. In the present disclosure, the same type of material refers to the same type of metal elements in the formed thin film. The oxygen content of the first metal oxide layer 151 / 261 can be made less than that of the second metal oxide layer 152 / 262 by changing the film forming conditions or by post-processing.

[0111] In some embodiments, the active layer contains indium elements and at least one of gallium elements, zinc elements, and tin elements, the oxygen content of the first metal oxide layer is less than that of the second metal oxide layer, and the indium content of the first metal oxide layer is 1%-8% higher than that of the second metal oxide layer.

[0112] In some embodiments, the active layer contains zinc elements, gallium elements, and rare earth elements, and the contents of zinc elements, gallium elements, and rare earth elements in the first metal oxide layer are respectively lower than those in the second metal oxide layer.

[0113] Optionally, the material of the second metal oxide layer 152 / 262 and the material of the first metal oxide layer 151 / 261 can both be rare earth doped IGZO, the oxygen content of the first metal oxide layer 151 / 261 is less than the oxygen content of the second metal oxide layer 152 / 261, the In content of the first metal oxide layer 151 / 261 is higher than the In content of the second metal oxide layer 152 / 262, and the content of Zn, Ga, rare earth elements of the first metal oxide layer 151 / 261 is respectively lower than the content of Zn, Ga, rare earth elements of the second metal oxide layer 152 / 262.

[0114] In some embodiments, the material of the second metal oxide layer 152 / 262 and the material of the first metal oxide layer 151 / 261 can be different types of materials. In the present disclosure, different types of materials refer to the inconsistency of the type of metal elements in the formed thin film.

[0115] In some embodiments, the material of the first metal oxide layer 151 / 261 can be any one selected from rare earth doped IGZO, ITZO, IZO, IGO, ITO, the material of the second metal oxide layer 152 / 262 is different from the In-containing material of the first metal oxide layer, and the In content of the first metal oxide layer 151 / 261 is higher than the In content of the second metal oxide layer 152 / 262. For example, the second metal oxide layer 152 / 262 can be, for example, IGZO(136), IGZO(423), IGZO(111).

[0116] In the embodiment as shown in FIG. 13, wherein the active layer includes a first metal oxide layer 151 and two second metal oxide layers 152, the second metal oxide layers 152 are respectively located on the side of the first metal oxide layer 151 facing the substrate and the side of the first metal oxide layer 151 facing away from the substrate 11, the first metal oxide layer 151 includes a rare earth doped metal oxide material, the second metal oxide layer 152 located on the side of the first metal oxide layer 151 facing the substrate includes a non-rare earth doped metal oxide material, and the In content of the second metal oxide layer 152 located on the side of the first metal oxide layer 151 facing away from the substrate is lower than the In content of the first metal oxide layer 151.

[0117] The arrangement of the multilayer oxide as the active layer in the present disclosure, wherein the second metal oxide layer is an oxide with relatively low carrier concentration, mainly serving as a channel protection, which can be a polycrystalline oxide or an amorphous oxide; the first metal oxide layer is an oxide material with relatively high carrier concentration, a carrier providing layer, mainly serving as a carrier providing, which can be a polycrystalline oxide or an amorphous oxide. Through the material selection and structure design,

[0118] Channel defects caused by exposure of the channel region to the etching and patterning of the source-drain electrode layer or other film deposition processes can be avoided, and the stability and mobility of the oxide transistor can be significantly improved. Moreover, when the multilayer oxide film is made of the same material, the deposition of the multilayer oxide film does not involve the increase of the mask and etching processes. FIG. 15 is a transistor PBTS test result graph according to an embodiment of the present disclosure. As can be seen, when the multilayer metal oxide proposed in the present disclosure is used as the active layer, the positive shift of the threshold voltage V th of the oxide transistor is significantly reduced (compared to the related art shown in FIG. 11), and the positive voltage stability of the oxide transistor is significantly improved.

[0119] FIG. 16 is a transistor NBTIS test result graph with single-layer oxide and stacked oxide as the active layer, respectively. When the NBTIS test is 1 h, the V th shift of the transistor with single-layer oxide as the active layer is -3 V (the column chart corresponding to sample 1 in FIG. 16), and the V th shift of the transistor with stacked oxide as the active layer is only -1.5 V (the column chart corresponding to sample 2 in FIG. 16). As can be seen, when the multilayer metal oxide proposed in the present disclosure is used as the active layer, the negative voltage stability of the oxide transistor is also significantly improved.

[0120] FIG. 17 is a TEM cross-sectional view of the stacked oxide structure of the active layer.

[0121] According to another aspect of the present disclosure, a method for manufacturing a transistor is provided. FIGS. 18(a)-18(f) show cross-sectional schematic diagrams of a transistor manufacturing process according to embodiments of the present disclosure. As shown in FIGS. 18(a)-18(f), the transistor manufacturing process according to embodiments of the present disclosure includes: forming a gate metal layer on a substrate 11, and patterning to form a gate 12, to obtain a structure as shown in FIG. 18(a); forming a gate insulating layer 13 / 14 on the substrate 11 on which the gate 12 is formed; forming a metal oxide layer on the substrate 11 on which the gate insulating layer 13 / 14 is formed, and patterning to form an active layer 15, to obtain a structure as shown in FIG. 18(b); forming a metal on the substrate 11 on which the active layer 15 is formed, and patterning to form a source-drain metal layer 16, to obtain a structure as shown in FIG. 18(c); forming a passivation layer on the substrate on which the source-drain metal layer 16 is formed, wherein forming a passivation layer on the substrate on which the source-drain metal layer 16 is formed includes: forming a first silicon oxide layer 171 on the substrate 11 on which the source-drain metal layer 16 is formed, to obtain a structure as shown in FIG. 18(d); forming a second silicon oxide layer 172 on the substrate 11 on which the first silicon oxide layer 171 is formed, to obtain a structure as shown in FIG. 18(e); wherein the oxygen content of the second silicon oxide layer 172 is higher than the oxygen content of the first silicon oxide layer 171. Next, a second passivation layer 18 and a resin layer 19 are formed and patterned, to obtain a structure as shown in FIG. 18(f); then, a first transparent conductive layer is formed and patterned to form a first transparent electrode layer 20, a third passivation layer 21 is formed and patterned, a second transparent conductive layer is formed and patterned to form a second transparent electrode layer 22, to obtain a transistor structure as shown in FIG. 1.

[0122] In some embodiments, forming a gate insulating layer 13 / 14 on the substrate 11 on which the gate 12 is formed includes: forming a third silicon oxide layer 14 on the substrate 11 on which the gate 12 is formed, wherein the oxygen content of the first silicon oxide layer 171 is less than the oxygen content of the third silicon oxide layer 14, and the oxygen content of the third silicon oxide layer 14 is less than the oxygen content of the second silicon oxide layer 172.

[0123] In some embodiments, as shown in FIG. 19, forming a gate insulating layer on the substrate 11 on which the gate 12 is formed includes: forming a fifth silicon oxide layer 141 on the substrate 11 on which the gate 12 is formed; forming a fourth silicon oxide layer 142 on the substrate on which the fifth silicon oxide layer is formed; wherein the oxygen content of the fifth silicon oxide layer 141 is higher than the oxygen content of the fourth silicon oxide layer 142.

[0124] According to another aspect of the present disclosure, a method for manufacturing a transistor is provided. FIGS. 20(a)-20(d) show cross-sectional schematic diagrams of a transistor manufacturing process according to an embodiment of the present disclosure. As shown in FIGS. 20(a)-20(d), the transistor manufacturing process according to an embodiment of the present disclosure includes: depositing and patterning a metal on a substrate 11 to form a light shielding layer 23; forming a buffer layer 24 / 25 on the substrate on which the light shielding layer 23 is formed; forming a metal oxide layer on the substrate 11 on which the buffer layer 24 / 25 is formed, and patterning to form an active layer 26, to obtain a structure as shown in FIG. 20(a); forming a gate insulating layer 27 on the substrate 11 on which the active layer 26 is formed; forming a gate metal layer on the substrate on which the gate insulating layer 27 is formed, and patterning to form a gate 28, to obtain a structure as shown in FIG. 20(b); forming an interlayer dielectric layer on the substrate 11 on which the gate 28 is formed, wherein forming an interlayer dielectric layer on the substrate on which the gate is formed includes: forming a first silicon oxide layer 301 on the substrate on which the gate is formed, to obtain a structure as shown in FIG. 20(c); forming a second silicon oxide layer 302 on the substrate on which the first silicon oxide layer 301 is formed, to obtain a structure as shown in FIG. 20(d); wherein the oxygen content of the second silicon oxide layer 302 is higher than the oxygen content of the first silicon oxide layer 301. Next, a metal layer is formed and patterned to obtain a source-drain electrode layer 31, then a passivation layer 32 and a resin layer 19 are formed and patterned; then, a first transparent conductive layer is formed and patterned to form a first transparent electrode layer 20, a third passivation layer 21 is formed and patterned, a second transparent conductive layer is formed and patterned to form a second transparent electrode layer 22, to obtain a transistor structure as shown in FIG. 9.

[0125] In the above embodiment of preparing the transistor, forming the metal oxide layer can include forming a first metal oxide layer 151 on the substrate as shown in FIG. 21, and forming a second metal oxide layer 152 after forming the first metal oxide layer 151. Alternatively, forming the metal oxide layer can include forming a first metal oxide layer 161 on the substrate as shown in FIG. 22, and forming a second metal oxide layer 162 before forming the first metal oxide layer. Alternatively, forming the metal oxide layer can include forming a first metal oxide layer 151 on the substrate as shown in FIG. 23, and forming a second metal oxide layer 152 both before and after forming the first metal oxide layer 151. The second metal oxide layer is located at least one of a side of the first metal oxide layer facing the substrate or a side of the first metal oxide layer facing away from the substrate, the first metal oxide layer is composed of a small amount of element-doped oxide material having a high carrier concentration, the carrier concentration of the second metal oxide layer is lower than the carrier concentration of the first metal oxide layer, and the band gap of the second metal oxide layer is wider than the band gap of the first metal oxide layer.

[0126] In the drawings, the thickness of certain regions and layers can be exaggerated for clarity. Like reference numerals in different drawings denote like or similar elements, and detailed descriptions of them will be omitted. Described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the description of the disclosure, numerous specific details are provided, such as examples of components and / or methods, to provide a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the technology can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the present disclosure.

[0127] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed above could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0128] Spatially relative terms such as "row," "column," "below," "above," "left," "right," and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that the term "between" when used in relation to two layers means that there can be only those two layers, or there can also be one or more intervening layers.

[0129] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of the specification, the description of the terms "one embodiment," "another embodiment," and the like means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment of the disclosure. The illustrative appearances of the above-mentioned terms in the description are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Additionally, the disclosure can include a plurality of embodiments or examples that are not necessarily mutually exclusive. Furthermore, the description of a particular feature, structure, material, or characteristic does not imply that the particular feature, structure, material, or characteristic is required in all embodiments or examples.

[0130] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent to" another element or layer, it can be directly on, connected, coupled or adjacent to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to", or "directly adjacent to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when a layer is referred to as being "between" two elements or layers, it can be disposed directly between or directly contact the two elements or layers, or intervening elements or layers can also be present. In addition, it will be understood that "on" or "directly on" should not be interpreted as requiring a layer to completely cover a below layer.

[0131] Embodiments of the disclosure are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the disclosure.

[0132] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0133] As will be understood by those skilled in the art, although the various steps of the methods in the disclosure are described in a particular order in the drawings, this is not required or implied as the particular order, unless the context explicitly so indicates. Additionally or alternatively, multiple steps can be combined into one step, and / or one step can be broken up into multiple steps. Furthermore, other method steps can be interposed. The interposed steps can represent improvements to the method as described herein, or can be unrelated to the method. Furthermore, a given step can not have completed before the next step is started.

[0134] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising a substrate and a transistor located on one side of the substrate, the transistor comprising a gate electrode, an active layer, and A first insulating layer is located on the side of the active layer away from the substrate and covers the active layer; wherein The first insulating layer comprises a first insulating sub-layer close to the active layer and a second insulating sub-layer away from the active layer, and the oxygen content of the second insulating sub-layer is higher than that of the first insulating sub-layer. 2.The display substrate of claim 1, wherein the difference between the oxygen content of the first insulating sub-layer and the second insulating sub-layer ranges from 1% to 15%. 3.The display substrate of claim 1, wherein the ratio of the difference between the oxygen content of the first insulating sub-layer and the second insulating sub-layer to the oxygen content of the first insulating sub-layer ranges from 3% to 10%. 4.The display substrate of claim 1, wherein, The thickness of the first insulating sub-layer is The thickness of the second insulating sub-layer is 5.The display substrate of claim 4, wherein, The sum of the thickness of the first insulating sub-layer and the thickness of the second insulating sub-layer is 6.The display substrate of claim 1, wherein, The oxygen content of the first insulating sub-layer is less than 65%, and the oxygen content of the second insulating sub-layer is greater than 70%. 7.The display substrate of claim 1, wherein, The first insulating layer comprises silicon and oxygen elements, and the Si-O peak positions of the first insulating sub-layer and the second insulating sub-layer are different. 8.The display substrate according to any one of claims 2-7, the transistor further comprising a second insulating layer between the gate and the active layer, wherein, The second insulating layer comprises silicon and oxygen elements. 9.The display substrate of claim 8, wherein, The oxygen content of the second insulating layer is greater than that of the first insulating sub-layer and less than that of the second insulating sub-layer. 10.The display substrate of claim 8, wherein, The Si-O peak position of the first insulating sub-layer is less than that of the second insulating layer, and the Si-O peak position of the second insulating layer is less than that of the second insulating sub-layer. 11.The display substrate of claim 8, wherein the transistor is a thin film transistor. The second insulating layer comprises a third insulating sub-layer close to the active layer and a fourth insulating sub-layer away from the active layer, and the oxygen content of the fourth insulating sub-layer is higher than that of the third insulating sub-layer. 12.The display substrate of claim 11, wherein, The third insulating sub-layer has a thickness of The fourth insulating sub-layer has a thickness of 13.The display substrate of claim 11, wherein, The oxygen content of the fourth insulating sub-layer is greater than 70%, and the oxygen content of the third insulating sub-layer is less than 65%. 14.The display substrate of claim 11, wherein, The Si-O peak position of the fourth insulating sub-layer is different from that of the third insulating sub-layer. 15.The display substrate according to any one of claims 11-14, wherein, The oxygen content of the first insulating sub-layer and the third insulating sub-layer is less than that of the second insulating sub-layer and the fourth insulating sub-layer. 16.The display substrate of any one of claims 11-14, wherein, The Si-O peak position of the first insulating sub-layer and the third insulating sub-layer is less than that of the second insulating sub-layer and the fourth insulating sub-layer. 17.The display substrate of any one of claims 1-16, wherein the transistor further comprises a first source-drain electrode layer and a second source-drain electrode layer, the second source-drain electrode layer is consistent with the pattern of the first source-drain electrode layer and completely covers the first source-drain electrode layer. 18.The display substrate of claim 17, wherein, The material of the second source-drain electrode layer is an oxidation-resistant metal.

19. The display substrate of claim 18, wherein, The width of the sidewall of the second source-drain electrode layer in the direction parallel to the substrate is greater than 0.5μm. 20.The display substrate of claim 18, wherein, The thickness of the metal oxide material between the second source-drain electrode layer and the first source-drain electrode layer is less than 0.1μm. 21.The display substrate of claim 1, wherein, The active layer is located on the side of the gate electrode close to the substrate, and the first insulating layer is located on the side of the gate electrode away from the substrate. 22.The display substrate of claim 21, wherein the difference between the oxygen content of the first insulating sub-layer and the second insulating sub-layer ranges from 1% to 15%.

23. The display substrate of claim 21, wherein a ratio of a difference between the oxygen content of the first insulating sub-layer and the second insulating sub-layer to the oxygen content of the first insulating sub-layer ranges from 3-10%.

24. The display substrate of claim 21, wherein, The thickness of the first insulating sub-layer is The thickness of the second insulating sub-layer is 25.The display substrate of claim 21, wherein, The oxygen content of the first silicon oxide layer is less than 65%, and the oxygen content of the second silicon oxide layer is greater than 70%.

26. The display substrate of claim 21, wherein, The first insulating layer includes silicon and oxygen elements, and the Si-O peak positions of the first insulating sub-layer and the second insulating sub-layer are different.

27. The display substrate of claim 21, wherein, The active layer includes a channel region and a first end portion and a second end portion located on two sides of the channel region, respectively, the first end portion and the second end portion are subjected to a conductorization treatment, the transistor further includes a source electrode and a drain electrode disposed above the active layer, one of the source electrode and the drain electrode is in contact with the first end portion, and the other of the source electrode and the drain electrode is in contact with the second end portion.

28. The display substrate of any one of claims 1-27, wherein the active layer includes a metal oxide material, and includes a first metal oxide layer and a second metal oxide layer, the second metal oxide layer is located on at least one of a side facing the substrate or a side facing away from the substrate of the first metal oxide layer, a carrier concentration of the second metal oxide layer is lower than a carrier concentration of the first metal oxide layer, and a band gap of the second metal oxide layer is wider than a band gap of the first metal oxide layer. 29.The display substrate of claim 28, wherein, The material of the second metal oxide layer and the material of the first metal oxide layer are the same type of material. 30.The display substrate of claim 29, wherein, The active layer contains an indium element and at least one of a gallium element, a zinc element, and a tin element, an oxygen content of the first metal oxide layer is less than an oxygen content of the second metal oxide layer, and an indium content of the first metal oxide layer is 1-8% higher than an indium content of the second metal oxide layer. 31.The display substrate of claim 30, wherein, The active layer contains a zinc element, a gallium element, and a rare earth element, and contents of the zinc element, the gallium element, and the rare earth element of the first metal oxide layer are lower than contents of the zinc element, the gallium element, and the rare earth element of the second metal oxide layer, respectively. 32.The display substrate of claim 28, wherein, The material of the second metal oxide layer and the material of the first metal oxide layer are different types of material.

33. The display substrate of claim 28, wherein the second metal oxide layer is located on a side facing the substrate and a side facing away from the substrate of the first metal oxide layer, the first metal oxide layer includes a rare earth doped metal oxide material, the second metal oxide layer located on the side of the first metal oxide layer facing the substrate includes a non-rare earth doped metal oxide material, and an indium content of the second metal oxide layer located on the side of the first metal oxide layer facing away from the substrate is lower than an indium content of the first metal oxide layer.

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