Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises: a base and multiple light-emitting pixels located on the base. Each light-emitting pixel comprises multiple light-emitting sub-pixels; each light-emitting sub-pixel comprises a micro light-emitting device located in a corresponding region and a pixel driving circuit coupled to the micro light-emitting device by means of a circuit output point; and in a same light-emitting sub-pixel, the orthographic projections of the circuit output point and the micro light-emitting device on the base entirely fall within the range of the orthographic projection of the corresponding light-emitting sub-pixel on the base.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Micro Light-Emitting Diode (Micro LED) display products have developed rapidly in recent years due to their excellent picture quality and wide application scenarios.

[0003] When Micro LED is used for active driving display, in order to achieve higher screen brightness uniformity, the power signal, such as VDD, usually adopts two layers of metal, and the two layers of metal are distributed in a mesh shape. In this way, how to reduce the power consumption of the wire while ensuring high pixel density becomes a technical problem that needs to be solved urgently.

[0004] SUMMARY

[0005] The present disclosure provides a display substrate and a display device, and the specific solutions are as follows:

[0006] The present disclosure provides a display substrate, which comprises:

[0007] a substrate and a plurality of light-emitting pixels on the substrate;

[0008] Each of the light-emitting pixels comprises a plurality of light-emitting sub-pixels; each of the light-emitting sub-pixels comprises a micro light-emitting device in a corresponding region and a pixel driving circuit coupled with the micro light-emitting device through a circuit output point; in the same light-emitting sub-pixel, the circuit output point and the micro light-emitting device are orthographically projected on the substrate and completely fall within the orthographic projection area of the corresponding light-emitting sub-pixel on the substrate.

[0009] Optionally, in the present disclosure, a first high-potential wire extending along the direction perpendicular to the long axis of each of the light-emitting sub-pixels is further included, and a plurality of second high-potential wires extending along the direction parallel to the long axis of each of the light-emitting sub-pixels are further included; each of the second high-potential wires is coupled with the first high-potential wire through a corresponding first node, and the orthographic projection of the first node on the substrate completely falls within the orthographic projection area of the corresponding light-emitting sub-pixel on the substrate.

[0010] Optionally, in the embodiments of the present disclosure, the display substrate further comprises a first lap joint and a second lap joint in the same light-emitting sub-pixel, the pixel driving circuit is coupled with one end of the first lap joint through the circuit output point, the other end of the first lap joint is coupled with the anode of the corresponding micro light-emitting device through a second node and the second lap joint, and a projection of the second node on the substrate completely falls within a projection range of the corresponding light-emitting sub-pixel on the substrate.

[0011] Optionally, in the embodiments of the present disclosure, the pixel driving circuit comprises an active layer, a first metal layer, a second metal layer and a third metal layer arranged in sequence away from the substrate, the first high-potential wire and the second lap joint are arranged in the same layer and of the same material as the third metal layer, and the second high-potential wire and the first lap joint are arranged in the same layer and of the same material as the second metal layer.

[0012] Optionally, in the embodiments of the present disclosure, a low-potential wire arranged in a direction perpendicular to the long axis direction of each light-emitting sub-pixel is further included, the low-potential wire is arranged in the same layer and of the same material as the third metal layer, and the low-potential wire is coupled with the cathode of each micro light-emitting device in the light-emitting pixel.

[0013] Optionally, in the embodiments of the present disclosure, a third high-potential wire arranged in a direction perpendicular to the long axis direction of each light-emitting sub-pixel is further included, a projection of the third high-potential wire on the substrate completely falls within a projection range of the first high-potential wire on the substrate, and the third high-potential wire is coupled with the corresponding second high-potential wire through a third node, and a projection of the third node on the substrate completely falls within a projection range of the corresponding light-emitting sub-pixel on the substrate.

[0014] Optionally, in the embodiments of the present disclosure, a fourth metal layer between the first metal layer and the second metal layer is further included, and the third high-potential wire is arranged in the same layer and of the same material as the fourth metal layer.

[0015] Optionally, in the embodiments of the present disclosure, in each light-emitting pixel, the long axis direction of each micro light-emitting device is parallel to the long axis direction of each light-emitting sub-pixel, and each micro light-emitting device is arranged in a direction perpendicular to the long axis direction of each light-emitting sub-pixel.

[0016] Optionally, in the embodiments of the present disclosure, a flat layer and a first passivation layer are arranged between the second metal layer and the third metal layer, and a second passivation layer is arranged on the side of the third metal layer away from the substrate; the flat layer, the first passivation layer and the second passivation layer are arranged in sequence away from the substrate; a plurality of exhaust holes are arranged along the thickness direction of the first passivation layer and the second passivation layer.

[0017] Optionally, in the embodiments of the present disclosure, in the display area, the orthogonal projection of each exhaust hole on the substrate does not overlap with the orthogonal projection of the third metal layer on the substrate.

[0018] Optionally, in the embodiments of the present disclosure, in the display area, the arrangement period of the plurality of exhaust holes is the same as the arrangement period of the plurality of light-emitting sub-pixels.

[0019] Optionally, in the embodiments of the present disclosure, a display area and a peripheral area surrounding the display area are further included; in the peripheral area, the display substrate further includes a first lead and a second lead, the first lead includes a first part arranged along the direction parallel to the long axis of the light-emitting sub-pixel, the second lead includes a second part arranged along the direction parallel to the long axis of the light-emitting sub-pixel, the first part is coupled with the first high-potential wire, the second part is coupled with the low-potential wire, the first part is coupled with a first constant power supply end, and the second part is coupled with a second constant power supply end.

[0020] Optionally, in the embodiments of the present disclosure, on the same side of the display substrate, the second part is arranged on the side of the first part away from the display area.

[0021] Optionally, in the embodiments of the present disclosure, along the direction parallel to the short axis of each light-emitting sub-pixel, the extension length of the first part and the second part is greater than the extension length of each light-emitting sub-pixel.

[0022] Optionally, in the embodiments of the present disclosure, a flat layer is arranged between the first part and the substrate, the orthogonal projection of the second part on the substrate does not overlap with the orthogonal projection of the flat layer on the substrate, the orthogonal projection of the first part on the substrate falls within the area range of the orthogonal projection of the flat layer on the substrate, the first part is provided with at least one hollow structure, and an inorganic layer on the side of the flat layer away from the substrate is provided with an exhaust hole corresponding to the at least one hollow structure.

[0023] Optionally, in the embodiments of the present disclosure, a flat layer is arranged between the first part and the low-potential wire, and in the peripheral area, the flat layer is located in the overlapping area of the first part and the low-potential wire.

[0024] Optionally, in the embodiments of the present disclosure, a flat layer extending from the display region to the peripheral region is further included, and the orthographic projections of the first part and the second part on the substrate completely fall within the area range of the orthographic projection of the flat layer on the substrate, the first part and the second part are both provided with at least one hollow structure, an inorganic layer on the side of the flat layer away from the substrate is provided with exhaust holes corresponding to the at least one hollow structure.

[0025] Correspondingly, the present disclosure provides a display device, which comprises:

[0026] The display substrate as claimed in any one of the preceding items. BRIEF DESCRIPTION OF DRAWINGS

[0027] FIG. 1 is a schematic diagram of one of the arrangements of micro LEDs in a pixel in the related art;

[0028] FIG. 2 is a schematic diagram of one of the arrangements of micro LEDs in a pixel in the related art;

[0029] FIG. 3a is a schematic diagram of one of the settings of sub-pixels in the related art;

[0030] FIG. 3b is a schematic diagram of one of the settings of micro LEDs in the related art;

[0031] FIG. 4 is a typical circuit at a current channel in a pixel driving circuit in the related art;

[0032] FIG. 5 is a schematic diagram of one of the power signal designs when micro LEDs adopt the arrangement shown in FIG. 1 in the related art;

[0033] FIG. 6 is a schematic diagram of one of the power signal designs when multiple micro LEDs share VSS in the exemplary embodiment shown in FIG. 5;

[0034] FIG. 7 is a schematic diagram of one of the layout structures based on the same power signal design idea as FIG. 5 and FIG. 6;

[0035] FIG. 8 is an enlarged layout of the part not showing the third metal pattern in FIG. 7;

[0036] FIG. 9 is an enlarged layout of the first connection point and the second connection point showing the third metal pattern in FIG. 7;

[0037] FIG. 10 is a schematic diagram of one of the top view structures of the display substrate provided by the embodiments of the present disclosure;

[0038] FIG. 11 is a schematic diagram of the design of the power signal of any one of the light-emitting pixels in FIG. 10;

[0039] FIG. 12 is a schematic view of a cross-sectional structure of one of the structures in FIG. 11;

[0040] FIG. 13 is a schematic view of one of the power supply signal designs of any of the light emitting pixels in FIG. 10;

[0041] FIG. 14 is a schematic view of a cross-sectional structure of one of the structures in FIG. 13;

[0042] FIG. 15 is a simplified layout corresponding to FIG. 13;

[0043] FIG. 16 is a complete layout corresponding to FIG. 13;

[0044] FIG. 17 is a schematic view of a partial structure in FIG. 16;

[0045] FIG. 18 is a layout of the fourth metal layer in FIG. 16;

[0046] FIG. 19 is a layout after the third node is set based on FIG. 18;

[0047] FIG. 20 is a layout after the second metal layer is set based on FIG. 19;

[0048] FIG. 21 is a layout after the first node and the second node are set based on FIG. 20;

[0049] FIG. 22 is a layout after the third metal layer is set based on FIG. 21;

[0050] FIG. 23 is a layout of the third metal layer in FIG. 22;

[0051] FIG. 24 is a windowing diagram of PVX2 on the third metal layer in FIG. 23;

[0052] FIG. 25 is a schematic view of one of the signal line designs in the peripheral region of a display substrate according to embodiments of the present disclosure;

[0053] FIG. 26 is a schematic view of one of the signal line designs in the peripheral region of a display substrate according to embodiments of the present disclosure;

[0054] FIG. 27 is a schematic view of a structure in which the signal line in the peripheral region of a display substrate is made of a third metal layer and has a hollow pattern according to embodiments of the present disclosure;

[0055] FIG. 28 is a schematic view of one of the designs of the corresponding positions of the first portion and the second portion of the peripheral region of a display substrate according to embodiments of the present disclosure;

[0056] FIG. 29 is a schematic view of one of the designs of the corresponding positions of the first portion and the second portion of the peripheral region of a display substrate according to embodiments of the present disclosure;

[0057] Fig. 30 is a schematic view of one of the designs of the first and second portions of the peripheral region of Fig. 26. DETAILED DESCRIPTION

[0058] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other under the condition of no conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0059] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "inner", "outer", "upper", "lower", and the like only represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0060] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout.

[0061] In the related art, as shown in FIG. 1 and FIG. 2, when the micro LED is used for active driving display, the micro LED 01 of R, G and B colors can be arranged longitudinally as shown in FIG. 1, or horizontally as shown in FIG. 2. It should be noted that in the arrangement shown in FIG. 1, the long axis direction of the micro LED 01 is perpendicular to the long axis direction of the sub-pixel 02; in the arrangement shown in FIG. 2, the long axis direction of the micro LED 01 is parallel to the long axis direction of the sub-pixel 02. The long axis direction of the sub-pixel 02 and the long axis direction of the micro LED 01 are explained and described in combination with FIG. 3a and FIG. 3b, wherein in the example embodiment shown in FIG. 3a, the direction parallel to the long axis of the sub-pixel 02 is shown by the arrow x; in the example embodiment shown in FIG. 3b, the direction parallel to the long axis of the micro LED 01 is shown by the arrow y.

[0062] In the implementation process, in order to ensure the display performance of the micro LED 01 display product, it is usually necessary to drive and control the corresponding micro LED 01 through a pixel driving circuit. As shown in FIG. 4, a typical circuit at the current channel of the pixel driving circuit, on which circuit, at least includes a drive control transistor M1, light emitting control transistors M2 and M3, wherein the light emitting control transistor M2 is controlled to be turned on by the control end S1, and the light emitting control transistor M3 is controlled to be turned on by the control end S2; and the circuit further includes a light emitting device micro LED 01 and corresponding power signals VDD and VSS. Among them, the pixel circuit output point 03 is connected with the anode 09 of the micro LED 01, and the label 010 represents the cathode of the micro LED 01.

[0063] In order to realize higher screen brightness uniformity, the power signal line in the micro LED 01 display, such as the signal line for transmitting the VDD signal (simplified as the VDD signal line for ease of description), usually adopts two layers of metal, and the two layers of metal are distributed in a mesh shape. In order to realize the loading of the external power signal to the inside of the pixel, when the micro LED 01 adopts the arrangement mode shown in FIG. 1 and the power signal is designed as shown in FIG. 5, each pixel includes three sub-pixels 02 of SP-1, SP-2 and SP-3, and the pixel circuit output points 03 in each sub-pixel 02 are relatively consistent in position in the sub-pixel 02, and a plurality of micro LED 01s are relatively arranged in a specific sub-pixel 02. The pixel circuit output point 03 and the corresponding micro LED 01 anode 09 need to be connected through multiple changes of the lead wire, and there are a plurality of first connection points 04, the connection mode is relatively complex and the connection mode is different, the lead wire between the pixel circuit output point 03 and the corresponding anode 09 consumes a lot of power consumption, and the voltage is reduced, and too many lead wires and vias between the two are not conducive to realizing higher pixel density.

[0064] Still in combination with the example embodiment shown in FIG. 5, the first connection point 04 is used to realize the conduction of the first metal 06 and the second metal 07, and the second connection point 05 is used to realize the conduction of the second metal 07 and the third metal 08. It should be noted that the first metal 06, the second metal 07 and the third metal 08 are arranged in turn away from the substrate. In addition, in the specific implementation process, the second connection point 05 includes a first type of second connection point 051 and a second type of second connection point 052; for the VDD signal line, the first type of second connection point 051 is used to realize the conduction between the VDD signal line prepared by the third metal 08 and the VDD signal line prepared by the second metal 07; and the second type of second connection point 052 is used to realize the conduction of the second metal 07 and the third metal 08 at the position of the micro LED 01 anode 09. In the example embodiment shown in FIG. 5, a plurality of micro LED 01s can share the signal line for transmitting the VSS signal (simplified as the VSS signal line for ease of description), and accordingly, the power signal design schematic diagram is shown in FIG. 6.

[0065] Still in combination with the exemplary embodiment shown in FIG. 6, the VSS signal line formed by the third metal 08 runs through the pixel along the long axis direction of the sub-pixel 02, and the VDD signal line formed by the third metal 08 also runs through the pixel along the long axis direction of the sub-pixel 02; at this time, the VDD signal line and the VSS signal line formed by the third metal 08 are usually concentrated above some but not all sub-pixels 02 inside the pixel. For example, the VDD signal line formed by the third metal 08 is concentrated above the sub-pixel 02 (SP-1) inside the pixel, and the VSS signal line formed by the third metal 08 is concentrated above the sub-pixels 02 (SP-2 and SP-3) inside the pixel; when the VDD signal line forms a mesh structure with the first metal 06 and the third metal 08, the VDD power signal inside the sub-pixel 02 (SP-2 and SP-3) other than the sub-pixel 02 (SP-1) where the VDD signal line formed by the third metal 08 is concentrated can only use the first metal 06 and the second metal 07 to layout the VDD signal line, and since the resistance of the first metal 06 and the second metal 07 is usually relatively large, there is a lot of power loss and voltage drop inside.

[0066] Still in combination with the exemplary embodiments shown in FIG. 5 and FIG. 6, FIG. 7 shows one of the layout structure schematic diagrams based on the same power signal design idea. Still in combination with FIG. 7, the first connection point 04 is covered by the third metal 08. FIG. 8 is an enlarged layout based on the part of FIG. 7 where the third metal 08 pattern is not shown, wherein the first connection point 04 can realize the conduction of the first metal 06 and the second metal 07. In FIG. 8, the second metal 07 pointed by the arrow is connected to the pixel circuit output point 03. FIG. 9 is an enlarged layout of the first connection point 04 and the second connection point 05 based on the third metal 08 pattern shown in FIG. 7. In the exemplary embodiment shown in FIG. 9, between the anode 09 of the micro LED 01 and the pixel circuit output point 03, there are at least two first connection points 04 and one second connection point 05. It should be noted that in the exemplary embodiment shown in FIG. 6, the micro LED 01 of RGB three colors shares the third metal 08 VSS signal line; in the exemplary embodiment shown in FIG. 7, there are two third metal 08 VSS signal lines, namely VSS1 and VSS2.

[0067] In the exemplary embodiment shown in FIG. 6, when the long axis direction of the micro LED 01 is perpendicular to the long axis direction of the sub-pixel 02, in order to realize the loading of the external power supply signal to the inside of the pixel, the VDD signal line formed by the third metal 08 needs to pass through the horizontal VDD signal line formed by the first metal 06 for transfer and finally connect with the VDD signal line formed by the second metal 07 inside each sub-pixel 02. In this way, the current for transmitting the VDD signal flows through the third metal 08, the second metal 07 and the first metal 06, and the VDD signal formed by the third metal 08 is mainly concentrated above one sub-pixel 02 (i.e. SP-1), and for the other two sub-pixels 02 (SP-2 and SP-3), the current transmission path is far away, and the wire power consumption is large. Moreover, when the arrangement mode of the micro LED 01 shown in FIG. 1 is used, a plurality of micro LEDs 01 are relatively concentrated in a specific sub-pixel 02 (i.e. SP-2), the lead between the pixel circuit output point 03 of each sub-pixel 02 and the anode 09 of the corresponding micro LED 01 is transformed multiple times, and the conduction mode is complex, which is not conducive to realizing a high pixel density.

[0068] Therefore, the display substrate and the display device are provided to realize a high pixel density while taking into account the low power consumption design of the wire.

[0069] In combination with FIG. 10 and FIG. 11, wherein FIG. 10 is a schematic top view of one of the display substrates provided by the embodiments of the present disclosure, and FIG. 11 is a design schematic of the power supply signal of any one of the light-emitting pixels 20 in FIG. 10. Specifically, the display substrate provided by the embodiments of the present disclosure includes:

[0070] a substrate 10 and a plurality of light-emitting pixels 20 located on the substrate 10;

[0071] Each of the light-emitting pixels 20 includes a plurality of light-emitting sub-pixels 200; each of the light-emitting sub-pixels 200 includes a micro light-emitting device 201 located in a corresponding region and a pixel driving circuit 202 coupled with the micro light-emitting device 201 through a circuit output point N; and the circuit output point N and the micro light-emitting device 201 in the same light-emitting sub-pixel 200 are orthographically projected on the substrate 10 and completely fall within the range of the orthographic projection of the corresponding light-emitting sub-pixel 20 on the substrate 10.

[0072] In the implementation process, the display substrate includes a substrate 10 and a plurality of light-emitting pixels 20 on the substrate 10. For example, the substrate 10 can be a rigid substrate, and can also be a flexible substrate, which is not limited here. For example, when the substrate 10 is a flexible substrate, the material of the flexible substrate can be a polyimide film (PI), and can also be a polyethylene terephthalate (PET), etc., which is not limited here. The flexible substrate can be a structure including a single flexible substrate layer, and can also be a structure including a plurality of flexible substrate layers, such as a two-layer flexible substrate layer structure, and for example, a three-layer flexible substrate layer structure, which is not limited here. In addition, a support layer can be arranged between two adjacent flexible substrate layers. Of course, the substrate 10 can also be arranged according to actual application needs, which is not limited here. In addition, the plurality of light-emitting pixels 20 on the substrate 10 can be arranged in an array, and the specific number and arrangement of the plurality of light-emitting pixels 20 can be arranged according to actual application needs, which is not limited here.

[0073] In addition, each light-emitting pixel 20 includes a plurality of light-emitting sub-pixels 200. For example, each light-emitting pixel 20 includes a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), thereby ensuring color display of the display substrate. Of course, the composition of a single light-emitting pixel 20 can also be arranged according to actual application needs, which is not limited here. Each light-emitting sub-pixel 200 includes a micro light-emitting device 201 in a corresponding region and a pixel driving circuit 202 (not shown in FIG. 11) coupled to the micro light-emitting device 201 through a circuit output point N. For example, the micro light-emitting device 201 can be a Micro LED, and can also be a Mini LED, which is not limited here. It should be noted that all light-emitting pixels 20 are not shown in the figure.

[0074] In addition, in the same light-emitting sub-pixel 200, the circuit output point N and the micro light-emitting device 201 are completely within the projection area of the corresponding light-emitting sub-pixel 200 on the substrate 10. In this way, the circuit output point N and the micro light-emitting device 201 corresponding to each light-emitting sub-pixel 200 can realize effective connection between the pixel driving circuit 202 and the micro light-emitting device 201 through fewer leads and vias. The connection mode is relatively simple, and the connection mode can be approximately the same, which reduces power consumption and provides a guarantee for higher pixel density.

[0075] In the implementation process, in the same light-emitting pixel 20, the positions of the circuit output points corresponding to each light-emitting sub-pixel 200 in the corresponding light-emitting sub-pixel 200 can be set to be substantially the same, and each micro light-emitting device 201 can be uniformly distributed in each light-emitting sub-pixel 200. In this way, it provides a guarantee for subsequent simplification of the connection mode between the pixel driving circuit 202 and the micro light-emitting device 201.

[0076] It should be noted that the pixel driving circuit 202 can be any one of a plurality of forms such as low temperature polysilicon (Low Temperature Poly-silicon, LTPS), oxide (Oxide), low temperature polysilicon oxide (Low Temperature Polycrystalline Oxide, LTPO), and the like. Of course, the specific structure of the pixel driving circuit 202 can also be set according to actual application needs, which is not limited here. In the embodiment of the present disclosure, the display substrate further comprises a first high potential wire 61 (i.e. VDD made of the third metal layer) extending along the direction perpendicular to the long axis of each light-emitting sub-pixel 200, and a plurality of second high potential wires 51 (i.e. VDD made of the second metal layer) extending along the direction parallel to the long axis of each light-emitting sub-pixel 200; each second high potential wire 51 is coupled to the first high potential wire 61 through a corresponding first node n1 (i.e. the first type of second connection point 051), and the orthographic projection of the first node n1 on the substrate 10 falls completely within the area range of the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10.

[0077] Still in combination with the exemplary embodiment shown in FIG. 11, the display panel further comprises a first high potential wire 61 and a plurality of second high potential wires 51, wherein the first high potential wire 61 is arranged to extend along a direction perpendicular to the long axis direction of each light emitting sub-pixel 200, and each second high potential wire 51 is arranged to extend along a direction parallel to the long axis direction of each light emitting sub-pixel 200. In actual applications, the first high potential wire 61 and each second high potential wire 51 can transmit the same high potential signal (for example, a VDD signal). Moreover, each second high potential wire 51 is coupled to the first high potential wire 61 through a corresponding first node n1, thereby ensuring the effectiveness of the high potential signal transmission. In addition, the orthographic projection of each first node n1 on the substrate 10 falls completely within the area range of the orthographic projection of the corresponding light emitting sub-pixel 200 on the substrate 10. In this way, the effective connection between the first node n1 and the micro light emitting device 201 of each light emitting sub-pixel 200 can be achieved through fewer leads and vias; the entire connection mode is relatively simple, and each first node n1 can be arranged at approximately the same position of the corresponding light emitting sub-pixel 200, and the corresponding connection mode can be approximately the same, so as to reduce power consumption while ensuring a higher pixel density.

[0078] It should be noted that the length direction of the pattern corresponding to the light emitting sub-pixel 200 in the plan view can be regarded as the long axis direction of the light emitting sub-pixel 200, and correspondingly, the width direction of the pattern corresponding to the light emitting sub-pixel 200 in the plan view can be regarded as the short axis direction of the light emitting sub-pixel 200. In addition, the length direction of the pattern corresponding to the micro light emitting device 201 in the plan view can be regarded as the long axis direction of the micro light emitting device 201, and correspondingly, the width direction of the pattern corresponding to the micro light emitting device 201 in the plan view can be regarded as the short axis direction of the micro light emitting device 201.

[0079] In the embodiments of the present disclosure, in the same light emitting sub-pixel 200, the display substrate further comprises a first lap joint 203 and a second lap joint 204, the pixel driving circuit 202 is coupled to one end of the first lap joint 203 through the circuit output point N, the other end of the first lap joint 203 is coupled to the anode 205 of the corresponding micro light emitting device 201 through a second node n2 and the second lap joint 204, and the orthographic projection of the second node n2 on the substrate 10 completely falls within the area range of the orthographic projection of the corresponding light emitting sub-pixel 200 on the substrate 10.

[0080] Still in combination with the exemplary embodiment shown in FIG. 11, in the same light-emitting sub-pixel 200, the display substrate further comprises a first bonding portion 203 and a second bonding portion 204, wherein the pixel driving circuit 202 is coupled with one end of the first bonding portion 203 through the circuit output point N, and the other end of the first bonding portion 203 is coupled with the anode 205 of the corresponding micro light-emitting device 201 through the second node n2 and the second bonding portion 204. In this way, the effective driving of the micro light-emitting device 201 by the pixel driving circuit 202 is ensured. Exemplarily, the first bonding portion 203 can be arranged in the same layer and of the same material as the second high-potential wire 51, and the second bonding portion 204 can be arranged in the same layer and of the same material as the first high-potential wire 61. Moreover, the orthographic projection of the second node n2 on the base 10 completely falls within the area range of the orthographic projection of the corresponding light-emitting sub-pixel 200 on the base 10. In this way, in the same light-emitting pixel 200, the effective connection between the pixel driving circuit 202 and the anode 205 of the micro light-emitting device 201 can be realized through fewer leads and vias between the second node n2 corresponding to each light-emitting sub-pixel 200 and the anode 205 of the micro light-emitting device 201; the second node n2 corresponding to each light-emitting sub-pixel 200 and the anode 205 of the micro light-emitting device 201 can also be arranged at substantially the same position, and the entire connection mode is relatively simple, and the connection mode can be substantially the same, thereby reducing power consumption while ensuring a higher pixel density.

[0081] In the embodiments of the present disclosure, the pixel driving circuit 202 comprises an active layer 30, a first metal layer 40, a second metal layer 50 and a third metal layer 60 arranged in sequence away from the base 10; the first high-potential wire 61 and the second bonding portion 204 are arranged in the same layer and of the same material as the third metal layer 60, and the second high-potential wire 51 and the first bonding portion 203 are arranged in the same layer and of the same material as the second metal layer 50.

[0082] Still based on the exemplary embodiment shown in FIG. 11, FIG. 12 shows a schematic diagram of one of the cross-sectional structures of FIG. 11, without showing the micro light emitting device 201. Specifically, the pixel driving circuit 202 includes, in sequence away from the substrate 10, the active layer 30, the first metal layer 40, the second metal layer 50, and the third metal layer 60. Exemplarily, the material of the first metal layer 40 can be Mo; the material of the second metal layer 50 can be an alloy material containing aluminum with relatively low resistivity, or a laminated metal containing aluminum, such as titanium-aluminum-titanium; and the material of the third metal layer 60 can be Cu. Of course, the materials of the first metal layer 40, the second metal layer 50, and the third metal layer 60 can also be selected according to actual application needs, which are not limited herein. Moreover, the first high-potential wire 61 and the second lap joint 204 are disposed in the same layer and of the same material as the third metal layer 60, and the second high-potential wire 51 and the first lap joint 203 are disposed in the same layer and of the same material as the second metal layer 50. In the actual preparation process, the third metal layer 60 can be used to prepare the first high-potential wire 61 and the second lap joint 204, and the second metal layer 50 can be used to prepare the second high-potential wire 51 and the first lap joint 203, thereby improving the preparation efficiency of the display substrate. It should be noted that in the exemplary embodiment shown in FIG. 12, the specific arrangement of the active layer 30, the first metal layer 40, the second metal layer 50, and the third metal layer 60, as well as other film layer structures, can be referred to the description of the related part below, which is not described in detail herein.

[0083] In the embodiments of the present disclosure, the display substrate further includes a low-potential wire 206 disposed along a direction perpendicular to the long axis direction of each of the light emitting sub-pixels 200; the low-potential wire 206 is disposed in the same layer and of the same material as the third metal layer 60, and the low-potential wire 206 is respectively coupled to the cathode 207 of each of the micro light emitting devices 201 in the light emitting pixel 20.

[0084] Still in combination with the exemplary embodiment shown in FIG. 11, the display substrate further comprises a low potential trace 206 arranged along a direction perpendicular to the long axis of each light emitting sub-pixel 200. Exemplarily, the low potential trace 206 is configured to transmit a low potential signal (e.g., a VSS signal). Moreover, the low potential trace 206 is arranged in the same layer and made of the same material as the third metal layer 60, i.e., the low potential trace 206 can be made of the third metal layer 60, thereby improving the manufacturing efficiency of the low potential trace. In addition, the low potential trace 206 is coupled to the cathode 207 of each micro light emitting device 201 in the light emitting pixel 20, respectively. In this way, each micro light emitting device 201 can be designed with a common low potential trace 204, thereby reducing the number of trace designs and lowering the power consumption of the trace. In this way, in each light emitting pixel 20, the low potential trace 206 can pass through each light emitting sub-pixel 200 along a direction perpendicular to the long axis of each light emitting sub-pixel 200. For the low potential trace 204, the current can flow through each light emitting sub-pixel 200 easily, the entire current propagation path is short, the number of traces and vias to be opened is small, a high pixel density can be achieved, and the power consumption of the signal line is significantly reduced.

[0085] In the embodiments of the present disclosure, the display substrate further comprises a third high potential trace 71 arranged along a direction perpendicular to the long axis of each light emitting sub-pixel 200. The orthogonal projection of the third high potential trace 71 on the substrate 10 completely falls within the area range of the orthogonal projection of the first high potential trace 61 on the substrate 10, and the third high potential trace 71 is coupled to the corresponding second high potential trace 51 through a third node n3, respectively. The orthogonal projection of the third node n3 on the substrate 10 completely falls within the area range of the orthogonal projection of the corresponding light emitting sub-pixel 200 on the substrate 10.

[0086] In one exemplary embodiment, as shown in FIG. 13, is one of the design schematic diagrams of the power supply signal of the light emitting pixel 20 in the embodiments of the present disclosure. Specifically, the trace for transmitting a high potential signal (e.g., a VDD signal) in the display substrate not only includes the first high potential trace 61 and the second high potential trace 51, but also includes a third high potential trace 71 arranged along a direction perpendicular to the long axis of each light emitting sub-pixel 200. In this way, in each light emitting pixel 20, the third high potential trace 71 can pass through each light emitting sub-pixel 200 along a direction perpendicular to the long axis of each light emitting sub-pixel 200. For the high potential signal, the current propagation path is increased, the voltage drop is reduced, and the power consumption of the trace is reduced. In addition, the storage capacitance is also taken into account.

[0087] Moreover, the orthographic projection of the third high-potential wire 71 on the base 10 falls completely within the area range of the orthographic projection of the first high-potential wire 61 on the base 10, which facilitates the conduction and connection between the third high-potential wire 71 and the first high-potential wire 61; the third high-potential wire 71 is coupled with the corresponding second high-potential wire 51 through the third node n3, and the orthographic projection of the third node n3 on the base 10 falls completely within the area range of the orthographic projection of the corresponding light-emitting sub-pixel 200 on the base 10. In this way, the effective connection between the third node n3 corresponding to each light-emitting sub-pixel 200 and the micro light-emitting device 201 in the same light-emitting sub-pixel 200 can be achieved through fewer leads and vias; the third node n3 corresponding to each light-emitting sub-pixel 200 can be arranged at substantially the same position, and the entire connection mode is relatively simple and can be substantially the same, thereby reducing power consumption and providing a guarantee for higher pixel density. It should be noted that in the example embodiment shown in FIG. 13, the third node n3 can be a connection point for the conduction between the third high-potential wire 71 formed by the fourth metal layer 70 and the second high-potential wire 51 formed by the second metal layer 50.

[0088] In the embodiments of the present disclosure, the display substrate further comprises a fourth metal layer 70 between the first metal layer 40 and the second metal layer 50, and the third high-potential wire 71 is arranged in the same layer and made of the same material as the fourth metal layer 70.

[0089] Still in combination with the example embodiment shown in FIG. 13, FIG. 14 shows one of the cross-sectional structure schematic diagrams of FIG. 13. Specifically, the display substrate further comprises a fourth metal layer 70 between the first metal layer 40 and the second metal layer 50; accordingly, the first metal layer 40, the fourth metal layer 70, the second metal layer 50 and the third metal layer 60 are arranged in sequence away from the base 10. In the actual preparation process, the third high-potential wire 71 can be arranged in the same layer and made of the same material as the fourth metal layer 70, thereby improving the preparation efficiency of the third high-potential wire 71.

[0090] In the embodiments of the present disclosure, in each light-emitting pixel 20, the long axis direction of each micro light-emitting device 201 is parallel to the long axis direction of each light-emitting sub-pixel 200, and each micro light-emitting device 201 is arranged to extend in a direction perpendicular to the long axis direction of each light-emitting sub-pixel 200.

[0091] Still in combination with the exemplary embodiment shown in FIG. 11 and FIG. 13, in each light emitting pixel 20, the long axis direction of each micro light emitting device 201 is parallel to the long axis direction of each light emitting sub-pixel 200, and each micro light emitting device 201 is arranged along the direction perpendicular to the long axis direction of each light emitting sub-pixel 200. Accordingly, in each light emitting pixel 20, the arrangement of the micro light emitting device 201 can be arranged according to the arrangement shown in FIG. 2. In actual application, in each light emitting pixel 20, each micro light emitting device 201 is uniformly distributed in each light emitting sub-pixel 200, and there is only one micro light emitting device 201 in each light emitting sub-pixel 200. In this way, in subsequent processes, there is only one kind of metal (exemplarily, the second metal layer 50) between the circuit output point N and the anode 205 of the corresponding micro light emitting device 201, and the first metal layer 40 and the first connection point 04 are not needed, the whole connection mode is relatively simple and consistent, the lead consumption and voltage drop between the circuit output point N and the anode 205 of the corresponding micro light emitting device 201 are less, which is beneficial to realize higher pixel density.

[0092] It should be noted that in the aforementioned related power signal design schematic diagram, in addition to the first high potential wire 61 and the low potential wire 204 prepared by the third metal layer 60, other signal lines are drawn by lines, and in fact, all signal lines have a certain width in space. As shown in FIG. 15, it is a simplified layout corresponding to FIG. 13, and as shown in FIG. 16, it is a complete layout corresponding to FIG. 13. Still in combination with the exemplary embodiment shown in FIG. 16, there is only the second metal layer 50 between the circuit output point N and the corresponding anode 205, and the connection mode is relatively simple. As shown in FIG. 17, it is a partial structure schematic diagram of FIG. 16, wherein the third high potential wire 71 is connected with the corresponding second high potential wire 51 through the third node n3, the second high potential wire 51 is connected with the first high potential wire 61 through the first node n1, and the third high potential wire 71 is entirely located at the bottom of the first high potential wire 61.

[0093] Still in combination with the exemplary embodiment shown in FIG. 16, as shown in FIG. 18, it is a layout of the fourth metal layer 70, as shown in FIG. 19, it is a layout after the third node n3 is completed, as shown in FIG. 20, it is a layout after the second metal layer 50 is completed, as shown in FIG. 21, it is a layout after the first node n1 and the second node n2 are completed, as shown in FIG. 22, it is a layout after the third metal layer 60 is completed, as shown in FIG. 23, it is a layout of the third metal layer 60, and as shown in FIG. 24, it is a windowing diagram of PVX2 on the third metal layer 60, wherein the reference sign Q represents the windowing position of PVX2. It should be noted that there is no film layer material for preparing PVX2 at the windowing position of PVX2, and the specific structure of PVX2 can be referred to the description of the related part below, which is not described in detail here.

[0094] Still in combination with the exemplary embodiment shown in FIG. 14, the display substrate further comprises a planar layer 80 and a first passivation layer 90 disposed between the second metal layer 50 and the third metal layer 60, and a second passivation layer 91 disposed on the side of the third metal layer 60 away from the substrate 10; the planar layer 80, the first passivation layer 90 and the second passivation layer 91 are disposed in sequence away from the substrate 10; a plurality of exhaust holes 92 are opened along the thickness direction of the first passivation layer 90 and the second passivation layer 91.

[0095] Exemplarily, the first passivation layer 90 can be PVX1, and the second passivation layer 91 can be PVX2. The materials of the first passivation layer 90 and the second passivation layer 91 can be at least one of SiOx and SiNx, and of course, the materials of the first passivation layer 90 and the second passivation layer 91 can also be set according to actual application needs, which are not limited herein.

[0096] In the specific implementation process, the third metal layer 60 can adopt metal copper with smaller square resistance, thereby reducing the voltage drop of the power signal. In the actual preparation process of the driving backplane of the display substrate, in order to ensure the performance of the driving backplane, a post-baking (Hard Bake) process and the like need to be performed after the driving backplane is completed. The process temperature is relatively high, and the corresponding organic material of the planar layer 80 and the like can discharge gas in the post-baking process. However, the corresponding inorganic material of the first passivation layer 90 and the second passivation layer 91 on the top of the planar layer 80, and the related metal film layer are often relatively dense, which is not conducive to the discharge of gas.

[0097] In the embodiment of the present disclosure, by opening a plurality of exhaust holes 92 along the thickness direction of the first passivation layer 90 and the second passivation layer 91, the gas can be effectively discharged, thereby ensuring the use performance of the display substrate. Of course, the specific number of the plurality of exhaust holes 92 can be set according to actual application needs, which are not limited herein.

[0098] It should be noted that, in addition to the related film layers mentioned above, other film layer structures can also be provided in the embodiment of the present disclosure. Exemplarily, still in combination with FIGS. 12 and 14, the display substrate further comprises a buffer layer 93 disposed between the substrate 10 and the active layer 30, a first gate insulating layer 94 disposed between the first metal layer 40 and the active layer 30, a second gate insulating layer 95 disposed between the first metal layer 40 and the fourth metal layer 70, and an interlayer insulating layer 96 disposed between the fourth metal layer 70 and the second metal layer 50. Of course, other film layer structures can also be set according to actual application needs, which are not limited herein.

[0099] In the embodiment of the present disclosure, the exhaust holes 92 can be set in the following implementation manners, but are not limited thereto.

[0100] In one exemplary embodiment, the orthographic projection of each of the plurality of exhaust holes 92 on the substrate 10 does not overlap with the orthographic projection of the third metal layer 60 on the substrate 10 in the display area A.

[0101] Still in combination with FIGS. 15, 16, 17 and 24, in the display area A of the display substrate, the orthographic projection of each of the plurality of exhaust holes 92 on the substrate 10 does not overlap with the orthographic projection of the third metal layer 60 on the substrate 10. Exemplarily, in the interior of each of the plurality of light emitting sub-pixels 200, the exhaust hole 92 is generally disposed at the gap of the third metal layer 60, and the third metal layer 60 is not provided with a hollow design, thereby improving the uniformity of the brightness of the panel.

[0102] In one exemplary embodiment, the arrangement period of the plurality of exhaust holes 92 is the same as the arrangement period of the plurality of light emitting sub-pixels 200 in the display area A.

[0103] Still in combination with FIGS. 15, 16, 17 and 24, in the display area A, the arrangement period of the plurality of exhaust holes 92 is substantially the same as the arrangement period of the plurality of light emitting sub-pixels 200. For example, one exhaust hole 92 is disposed in one sub-pixel, and the arrangement period of the plurality of exhaust holes 92 in the display substrate is the same as the arrangement period of the corresponding plurality of light emitting sub-pixels 200. For another example, one exhaust hole 92 is disposed in one light emitting pixel 20, and the arrangement period of the plurality of exhaust holes 92 in the display substrate is the same as the arrangement period of the corresponding plurality of light emitting pixels 20. In this way, the exhaust consistency of the display substrate is ensured, and the use performance of the display substrate is improved.

[0104] In the embodiments of the present disclosure, as shown in FIG. 25 and FIG. 26, the display substrate includes a display area A and a peripheral area B surrounding the display area A. In the peripheral area B, the display substrate further includes a first lead line 97 and a second lead line 98. The first lead line 97 includes a first portion 99 extending along a direction parallel to the long axis of the light emitting sub-pixel 200. The second lead line 98 includes a second portion 100 extending along a direction parallel to the long axis of the light emitting sub-pixel 200. The first portion 99 is coupled to the first high potential wire 61. The second portion 100 is coupled to the low potential wire 206. The first portion 99 is configured to receive a signal from a first constant power supply end 101. The second portion 100 is configured to receive a signal from a second constant power supply end 102. For example, the direction shown by the arrow X is parallel to the long axis of the light emitting sub-pixel 200. The direction shown by the arrow Y is perpendicular to the long axis of the light emitting sub-pixel 200. The first constant power supply end 101 can be a constant power supply end for providing a high potential signal. The second constant power supply end 102 can be a constant power supply end for providing a low potential signal. The specific values of the high potential signal and the low potential signal can be set according to actual application requirements, which are not limited herein.

[0105] It should be noted that, unless otherwise specified, the direction shown by the arrow X is parallel to the long axis of the light emitting sub-pixel 200. The direction shown by the arrow Y is perpendicular to the long axis of the light emitting sub-pixel 200. In the embodiments of the present disclosure, since the first high potential wire 61 and the low potential wire 206 formed by the third metal layer 60 extend along a direction perpendicular to the long axis of the light emitting sub-pixel 200, VDD lead lines and VSS lead lines parallel to the long axis of the light emitting sub-pixel 200 can be arranged on the left and right sides of the display area A (i.e., the peripheral area B). The VDD lead lines can connect the first high potential wires 61 inside multiple rows of light emitting sub-pixels 200 and perpendicular to the long axis of the light emitting sub-pixel 200. The VSS lead lines can also connect the low potential wires 206 inside multiple rows of light emitting sub-pixels 200 and perpendicular to the long axis of the light emitting sub-pixel 200.

[0106] Still in combination with FIG. 25 and FIG. 26, the second portion 100 is arranged on the side of the first portion 99 away from the display area A on the same side of the display substrate.

[0107] For example, for the P-type driving backplane in the display substrate, the first constant power terminal 101 corresponding to the first high potential wire 61 can be used as the common terminal of the pixel driving circuit 202, and the second part 100 corresponding to the second lead wire 98 can be arranged on the side away from the display area A of the first part 99 corresponding to the first lead wire 97 on the same side of the display substrate. Accordingly, the first part 99 is arranged on the side close to the display area A of the second part 100. In this way, in actual production, the layer switching of the first high potential wire 61 can be reduced as much as possible, so as to ensure the uniformity of the VDD voltage and improve the use performance of the display substrate.

[0108] In an example embodiment, the extension lengths of the first part 99 and the second part 100 are greater than the extension length of the light emitting sub-pixel 200 in the direction parallel to the short axis of each light emitting sub-pixel 200. In a specific implementation, for a large-size backplane, the extension lengths of the first part 99 and the second part 100 can be greater than the extension length of the light emitting sub-pixel 200 in the direction parallel to the short axis of each light emitting sub-pixel 200, so as to realize high brightness uniformity and reduce the power consumption of the signal line. The specific extension lengths of the first part 99 and the second part 100 and the specific extension length of the light emitting sub-pixel 200 can be set according to actual application requirements, which are not limited herein.

[0109] It should be noted that in the example embodiment shown in FIG. 25, the signal lines prepared by the second metal layer 50 can be arranged. For example, the display substrate further includes a shift register (not shown in the figure) in the peripheral area B, and the signal lines corresponding to the clock signals (such as ECK signals and ECB signals) required for the operation of the shift register, the high-voltage signal VGH, and the low-voltage signal VGL. In order to reduce the coupling between the signal lines prepared by the second metal layer 50 and the signal lines prepared by the third metal layer 60, and to avoid the breakdown between different signals caused by the large voltage difference between the two metal layers, thereby causing the failure of the related circuits of the display substrate. In a specific implementation, when the signal lines prepared by the second metal layer 50 and the signal lines prepared by the third metal layer 60 have different functions and exist in the projection direction of the display substrate, a planar layer 80 is arranged between the two metal layers in addition to the first passivation layer 90. The related arrangement can be referred to FIG. 14.

[0110] In the embodiments of the present disclosure, for the exhaust hole 92 in the peripheral area B, the following implementation can be used for the related design, but it is not limited thereto.

[0111] In one of the example embodiments, when the peripheral area B of the display substrate has the planar layer 80, the exhaust hole 92 needs to be arranged on the first passivation layer 90, the second passivation layer 91 and the third metal layer 60 on top of the planar layer 80. As shown in FIG. 27, the structure schematic diagram of the signal line prepared by the third metal layer 60 with the hollow pattern. When the signal line prepared by the third metal layer 60 adopts the hollow pattern design, and the hollow pattern period is small, the resistance of the corresponding signal line will be significantly increased, and the power consumption on the signal line will be increased. In addition, the voltage drop on the signal line will also be increased, which is not conducive to achieving higher brightness uniformity. Therefore, in the specific implementation process, the planar layer 80 below the part of the signal line prepared by the third metal layer 60 can be removed, at this time, the signal line does not need to be hollowed out, and correspondingly, the corresponding exhaust hole 92 does not need to be arranged on the signal line.

[0112] In one of the example embodiments, the first portion 99 and the substrate 10 are provided with the planar layer 80, and the orthographic projection of the second portion 100 on the substrate 10 and the orthographic projection of the planar layer 80 on the substrate 10 do not overlap each other, the orthographic projection of the first portion 99 on the substrate 10 falls completely within the area range of the orthographic projection of the planar layer 80 on the substrate 10, the first portion 99 is provided with at least one hollow structure 103, and the inorganic layer on the side of the planar layer 80 away from the substrate 10 is provided with the exhaust hole 92 corresponding to the at least one hollow structure 103.

[0113] Still in combination with the example embodiment shown in FIG. 25, for the peripheral area B, the planar layer 80 below the second lead 98 prepared by the third metal layer 60 can be removed, and correspondingly, the second lead 98 does not need to be hollowed out. That is, the corresponding position of the second lead 98 does not need to be arranged with the related exhaust hole 92. In this way, the corresponding signal line of the second lead 98 has less power consumption loss, the brightness uniformity of the display substrate is improved, and the reliability of the display substrate is improved.

[0114] As shown in FIG. 28, the second lead line 98 located at the outermost side of the display substrate has no hollow design above it, and the flat layer 80 is arranged between the first portion 99 and the substrate 10. The first portion 99 corresponding to the first lead line 97 is provided with at least one hollow structure 103. Correspondingly, the first passivation layer 90 and the second passivation layer 91 located on the side of the flat layer 80 away from the substrate 10 are provided with exhaust holes 92 corresponding to the at least one hollow structure 103. The specific number and arrangement of the at least one hollow structure 103 can be set according to actual application needs, and are not limited herein. It should be noted that in the exemplary embodiment shown in FIG. 28, the VSS signal line prepared from the second metal layer 50 is under the VDD signal line prepared from the third metal layer 60, and the VSS signal line prepared from the second metal layer 50 and the VSS signal line prepared from the third metal layer 60 are connected through the second connection point (i.e., the conductive point between the second metal layer 50 and the third metal layer 60).

[0115] As shown in FIG. 29, the flat layer 80 is arranged between the first portion 99 and the low-potential trace 206, and in the peripheral area B, the flat layer 80 is only located in the region where the first portion 99 and the low-potential trace 206 overlap with each other.

[0116] Still in combination with the exemplary embodiment shown in FIG. 29, in the peripheral area B of the display substrate, the flat layer 80 is only reserved above the VSS signal line prepared from the second metal layer 50 under the VDD signal line prepared from the third metal layer 60, and the flat layer 80 in other regions is removed. In this exemplary embodiment, no hollow design is needed above the VDD signal line prepared from the third metal layer 60.

[0117] Still in combination with the exemplary embodiment shown in FIG. 26, the display substrate further comprises a flat layer 80 extending from the display area A to the peripheral area B, and the orthographic projection of the first portion 99 and the second portion 100 on the substrate 10 completely falls within the area range of the orthographic projection of the flat layer 80 on the substrate 10, the first portion 99 and the second portion 100 are both provided with at least one hollow structure 103, the inorganic layer on the side of the flat layer 80 away from the substrate 10 is provided with exhaust holes 92 corresponding to the at least one hollow structure 103. That is, compared with the exemplary embodiment shown in FIG. 25, the setting range of the flat layer 80 in the exemplary embodiment shown in FIG. 26 is relatively large. Accordingly, in the peripheral area B, the first portion 99 and the second portion 100 are both provided with at least one hollow structure 103, so that the first passivation layer 90 and the second passivation layer 91 on the side of the flat layer 80 away from the substrate 10 are provided with exhaust holes 92 corresponding to the at least one hollow structure 103. As shown in FIG. 30, it is a schematic diagram of the setting structure of the related hollow structure 103 in the peripheral area B in the exemplary embodiment shown in FIG. 26.

[0118] Based on the same disclosure concept, the embodiments of the present disclosure further provide a display device, which comprises the display substrate as claimed in any one of the preceding embodiments.

[0119] Since the display device solves problems by the same principle as the aforementioned display substrate, the implementation of the display device can refer to the implementation of the aforementioned display substrate, and the repeated parts will not be described herein.

[0120] In the implementation process, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. The other indispensable components of the display device should be understood by those skilled in the art, and will not be described herein, nor should it be regarded as a limitation on the present disclosure.

[0121] The embodiments of the present disclosure provide a display substrate and a display device, wherein the display substrate comprises a substrate 10 and a plurality of light-emitting pixels 20 on the substrate 10; each light-emitting pixel 20 comprises a plurality of light-emitting sub-pixels 200, for example, each light-emitting pixel 20 comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, thereby ensuring the color display of the display substrate; each light-emitting sub-pixel 200 comprises a micro light-emitting device 201 in a corresponding area and a pixel driving circuit 202 coupled with the micro light-emitting device 201 through a circuit output point N;

[0122] Moreover, in the same light-emitting pixel 20, the circuit output point N and the orthographic projection of the micro light-emitting device 201 on the substrate 10 completely fall within the area range of the orthographic projection of the corresponding light-emitting sub-pixel 20 on the substrate 10. In this way, the effective connection between the pixel driving circuit 202 and the micro light-emitting device 201 can be realized through fewer leads and via between the corresponding circuit output point N and the micro light-emitting device 201 of each light-emitting sub-pixel 200; the whole connection mode is relatively simple, and the connection mode can be made substantially the same, which reduces the power consumption and provides a guarantee for higher pixel density.

[0123] Although preferred embodiments of the present disclosure have been described, those skilled in the art who are familiar with the basic inventive concept can make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0124] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A display substrate, wherein, include: A substrate and multiple light-emitting pixels located on the substrate; Each of the light-emitting pixels includes multiple light-emitting sub-pixels; each of the light-emitting sub-pixels includes a micro-light-emitting device located in a corresponding region and a pixel driving circuit coupled to the micro-light-emitting device through a circuit output point; Within the same light-emitting sub-pixel, the circuit output point and the micro-light-emitting device are projected onto the substrate and fall completely within the area of ​​the corresponding light-emitting sub-pixel's projection onto the substrate.

2. The display substrate as claimed in claim 1, wherein, It also includes a first high-potential trace extending along the direction perpendicular to the long axis of each of the light-emitting sub-pixels, and a plurality of second high-potential traces extending along the direction parallel to the long axis of each of the light-emitting sub-pixels; each of the second high-potential traces is coupled to the first high-potential trace through a corresponding first node, and the orthographic projection of the first node on the substrate falls completely within the region of the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

3. The display substrate as described in claim 2, wherein, Within the same light-emitting sub-pixel, the display substrate further includes a first overlapping portion and a second overlapping portion. The pixel driving circuit is coupled to one end of the first overlapping portion through the circuit output point. The other end of the first overlapping portion is coupled to the anode of the corresponding micro-light-emitting device through a second node and the second overlapping portion. The orthographic projection of the second node on the substrate falls completely within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

4. The display substrate as described in claim 3, wherein, The pixel driving circuit includes an active layer, a first metal layer, a second metal layer, and a third metal layer disposed sequentially away from the substrate; the first high-potential trace and the second overlapping portion are both disposed in the same layer and with the same material as the third metal layer, and the second high-potential trace and the first overlapping portion are both disposed in the same layer and with the same material as the second metal layer.

5. The display substrate as claimed in claim 4, wherein, It also includes low-potential traces extending along the long axis direction perpendicular to each of the light-emitting sub-pixels; the low-potential traces are disposed in the same layer and material as the third metal layer, and the low-potential traces are respectively coupled to the cathodes of each of the micro-light-emitting devices in the light-emitting pixels.

6. The display substrate as claimed in claim 5, wherein, It also includes a third high-potential trace extending along the long axis direction perpendicular to each of the light-emitting sub-pixels; the orthographic projection of the third high-potential trace on the substrate completely falls within the area of ​​the orthographic projection of the first high-potential trace on the substrate, and the third high-potential trace is coupled to the corresponding second high-potential trace through a third node (i.e., connection point 04), and the orthographic projection of the third node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

7. The display substrate as claimed in claim 6, wherein, It also includes a fourth metal layer located between the first metal layer and the second metal layer, and the third high-potential trace is disposed in the same layer and with the same material as the fourth metal layer.

8. The display substrate according to any one of claims 1-7, wherein, Within each of the light-emitting pixels, the long axis of each of the micro-light-emitting devices is parallel to the long axis of each of the light-emitting sub-pixels, and each of the micro-light-emitting devices extends along a direction perpendicular to the long axis of each of the light-emitting sub-pixels.

9. The display substrate according to any one of claims 5-7, wherein, It also includes a planarization layer and a first passivation layer disposed between the second metal layer and the third metal layer, and a second passivation layer disposed on the side of the third metal layer away from the substrate; the planarization layer, the first passivation layer and the second passivation layer are disposed away from the substrate in sequence; a plurality of vent holes are formed along the thickness direction penetrating the first passivation layer and the second passivation layer.

10. The display substrate as claimed in claim 9, wherein, Within the display area, the orthographic projections of each of the vent holes onto the substrate and the orthographic projections of the third metal layer onto the substrate do not overlap.

11. The display substrate as claimed in claim 10, wherein, Within the display area, the arrangement period of the plurality of exhaust holes is the same as the arrangement period of the plurality of light-emitting sub-pixels.

12. The display substrate according to any one of claims 5-7, 10, and 11, wherein, It also includes a display area and a peripheral area surrounding the display area; within the peripheral area, the display substrate further includes a first lead and a second lead, the first lead including a first portion extending along a direction parallel to the long axis of the light-emitting sub-pixel, the second lead including a second portion extending along a direction parallel to the long axis of the light-emitting sub-pixel, the first portion being coupled to a first high-potential trace, the second portion being coupled to a low-potential trace, and the first portion being coupled to a first constant power supply terminal, and the second portion being coupled to a second constant power supply terminal.

13. The display substrate as claimed in claim 12, wherein, On the same side of the display substrate, the second portion is disposed on the side of the first portion opposite to the display area.

14. The display substrate as claimed in claim 13, wherein, Along the short axis direction parallel to each of the light-emitting sub-pixels, the extension lengths of both the first portion and the second portion are greater than the extension lengths of each of the light-emitting sub-pixels.

15. The display substrate as claimed in claim 12, wherein, A planarization layer is provided between the first part and the substrate, and the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the planarization layer on the substrate. The orthographic projection of the first part on the substrate falls completely within the area of ​​the orthographic projection of the planarization layer on the substrate. The first part has at least one hollow structure, and the inorganic layer located on the side of the planarization layer away from the substrate has an exhaust hole corresponding to the at least one hollow structure.

16. The display substrate as claimed in claim 12, wherein, A planarization layer is provided between the first portion and the low-potential trace, and in the peripheral area, the planarization layer is located in the area where the first portion and the low-potential trace overlap.

17. The display substrate as claimed in claim 12, wherein, It also includes a flat layer extending from the display area to the peripheral area, and the orthogonal projections of the first part and the second part on the substrate completely fall within the area of ​​the orthogonal projection of the flat layer on the substrate. The first part and the second part each have at least one hollow structure. The inorganic layer located on the side of the flat layer away from the substrate has an exhaust hole corresponding to the at least one hollow structure.

18. A display device, wherein, include: The display substrate as described in any one of claims 1-17.

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