Thin film transistor and display panel

Abstract

The present application provides a thin film transistor and a display panel. An active layer of the thin film transistor comprises at least two semiconductor layers stacked on one another. Channel regions of two adjacent semiconductor layers have the same conductivity type, and the doping concentrations of the same element in semiconductor materials of the two adjacent semiconductor layers are different, so that a homotype heterostructure is formed when the two adjacent semiconductor layers come into contact, thereby improving carrier mobility.

Description

Thin film transistors and display panels Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and a display panel. Background Art

[0002] With the continuous advancement of display technology, metal oxide thin-film transistors (TFTs), with their advantages such as good uniformity over large areas and low manufacturing temperatures, are being adopted in next-generation flat-panel displays, gradually replacing traditional amorphous silicon (a-Si) and low-temperature polysilicon (LTPS) TFTs. However, as the display industry demands increasingly higher mobility for TFT devices, the current mobility of metal oxides cannot meet these technical requirements. Therefore, improving the mobility of metal oxides has become an urgent issue for the industry. SUMMARY OF THE INVENTION

[0003] The present application provides a thin film transistor and a display panel to improve the mobility of metal oxide.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a thin film transistor, comprising:

[0006] substrate;

[0007] a source electrode, disposed on one side of the substrate;

[0008] an interlayer insulating layer, disposed on a side of the source electrode away from the substrate and exposing a portion of the source electrode;

[0009] a first gate, disposed on a side of the interlayer insulating layer away from the substrate;

[0010] a first gate insulating layer, disposed on a side of the first gate away from the substrate and covering a sidewall of the first gate;

[0011] a drain electrode, disposed on a side of the first gate insulating layer away from the substrate;

[0012] an active layer, disposed on a side of the first gate insulating layer away from the first gate electrode and covering a sidewall of the drain electrode, a sidewall of the first gate insulating layer, and the source electrode exposed by the interlayer insulating layer, the active layer comprising at least two stacked semiconductor layers;

[0013] The conductive types of the channel regions of the two adjacent semiconductor layers are the same, and the doping concentrations of the same element in the semiconductor materials of the two adjacent semiconductor layers are different.

[0014] In a second aspect, an embodiment of the present application further provides a display panel, which includes a thin film transistor, wherein the thin film transistor includes:

[0015] substrate;

[0016] a source electrode, disposed on one side of the substrate;

[0017] an interlayer insulating layer, disposed on a side of the source electrode away from the substrate and exposing a portion of the source electrode;

[0018] a first gate, disposed on a side of the interlayer insulating layer away from the substrate;

[0019] a first gate insulating layer, disposed on a side of the first gate away from the substrate and covering a sidewall of the first gate;

[0020] a drain electrode, disposed on a side of the first gate insulating layer away from the substrate;

[0021] an active layer, disposed on a side of the first gate insulating layer away from the first gate electrode and covering a sidewall of the drain electrode, a sidewall of the first gate insulating layer, and the source electrode exposed by the interlayer insulating layer, the active layer comprising at least two stacked semiconductor layers;

[0022] The conductive types of the channel regions of the two adjacent semiconductor layers are the same, and the doping concentrations of the same element in the semiconductor materials of the two adjacent semiconductor layers are different. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] FIG1 is a schematic diagram of a cross-sectional structure of a thin film transistor provided in an embodiment of the present application.

[0025] FIG2 is a schematic diagram of an energy band of the active layer in FIG1 .

[0026] FIG3 is a schematic diagram of another cross-sectional structure of a thin film transistor provided in an embodiment of the present application.

[0027] FIG4 is a schematic diagram of another cross-sectional structure of a thin film transistor provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0028] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0029] In view of the fact that the mobility of metal oxides in the prior art cannot meet the mobility requirements of thin film transistor devices in the display industry, the inventors of this application found in their research that the thin film transistor in the prior art includes a substrate and an active layer arranged on one side of the substrate, and the active layer is formed by a single layer of metal oxide. The mobility of the metal oxide in the active layer is low and cannot meet the mobility requirements of thin film transistor devices in the display industry.

[0030] To this end, the present application provides a thin film transistor and a display panel to solve the above problems.

[0031] In one embodiment, the present application provides a thin film transistor, comprising:

[0032] substrate;

[0033] a source electrode, disposed on one side of the substrate;

[0034] an interlayer insulating layer, disposed on a side of the source electrode away from the substrate and exposing a portion of the source electrode;

[0035] a first gate, disposed on a side of the interlayer insulating layer away from the substrate;

[0036] a first gate insulating layer, disposed on a side of the first gate away from the substrate and covering a sidewall of the first gate;

[0037] a drain electrode, disposed on a side of the first gate insulating layer away from the substrate;

[0038] an active layer, disposed on a side of the first gate insulating layer away from the first gate electrode and covering a sidewall of the drain electrode, a sidewall of the first gate insulating layer, and the source electrode exposed by the interlayer insulating layer, the active layer comprising at least two stacked semiconductor layers;

[0039] The conductive types of the channel regions of the two adjacent semiconductor layers are the same, and the doping concentrations of the same element in the semiconductor materials of the two adjacent semiconductor layers are different.

[0040] In one embodiment, the active layer includes a first semiconductor layer and a second semiconductor layer that are stacked, and the first semiconductor layer and the second semiconductor layer have different band gaps.

[0041] In one embodiment, the active layer includes a first semiconductor layer and a second semiconductor layer stacked together, the material of the first semiconductor layer is IZO, the material of the second semiconductor layer is IGZO, and the doping concentration of indium in the first semiconductor layer is different from the doping concentration of indium in the second semiconductor layer.

[0042] In one embodiment, the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

[0043] In one embodiment, the active layer includes a first semiconductor layer and a second semiconductor layer stacked together, the materials of the first semiconductor layer and the second semiconductor layer are both IGZO, and the doping concentration of indium in the first semiconductor layer is different from the doping concentration of indium in the second semiconductor layer.

[0044] In one embodiment, the thickness of the first semiconductor layer is smaller than the thickness of the second semiconductor layer.

[0045] In one embodiment, the active layer further includes a third semiconductor layer located on a side of the second semiconductor layer away from the first semiconductor layer, the material of the third semiconductor layer is IGZO, and the doping concentration of indium in the third semiconductor layer is different from the doping concentration of indium in the second semiconductor layer.

[0046] In one embodiment, the doping concentration of indium in the second semiconductor layer is greater than the doping concentration of indium in the third semiconductor layer.

[0047] In one embodiment, the active layer includes a first semiconductor layer and a second semiconductor layer stacked together, and a third semiconductor layer located on a side of the second semiconductor layer away from the first semiconductor layer. The third semiconductor layer and the second semiconductor layer have different band gaps, and the materials of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are ZnO, AlZnO and YZnO, respectively.

[0048] In one embodiment, the thin film transistor further comprises:

[0049] a second gate insulating layer, disposed on a side of the active layer away from the first gate insulating layer;

[0050] The second gate is arranged on a side of the second gate insulating layer away from the active layer.

[0051] In one embodiment, the drain electrode is a transparent electrode.

[0052] In one embodiment, the source electrode and the drain electrode are both made of reducing metal materials.

[0053] In one embodiment, the present application further provides a display panel comprising the thin film transistor of one of the aforementioned embodiments.

[0054] In the thin film transistor and display panel provided in the embodiments of the present application, the thin film transistor includes a substrate and an active layer arranged on one side of the substrate. The active layer includes at least two stacked semiconductor layers. The conductivity type of the channel regions of the two adjacent semiconductor layers is the same, and the doping concentration of the same element in the semiconductor materials of the two adjacent semiconductor layers is different. When the two adjacent semiconductor layers come into contact, an isotype heterostructure is formed, and an electric potential barrier is formed at the heterojunction interface, resulting in different electron and hole concentrations. The band gap width and conductivity at the heterojunction interface are different from those of the adjacent semiconductor layers, which reduces the energy required for electrons on one side of the heterojunction interface to become free electrons, thereby causing the energy band near the heterojunction interface to bend downward. At this time, a "depression" is generated where the energy band bends, and electrons gather here, thereby forming a high-concentration electron region. The electrons are less likely to be scattered by donor impurities, thereby improving the carrier mobility.

[0055] The thin film transistor and display panel of the present application will be described in detail below with reference to the accompanying drawings.

[0056] In one embodiment, please refer to Figures 1 and 2. Figure 1 is a schematic cross-sectional structure diagram of a thin film transistor provided in an embodiment of the present application, and Figure 2 is a schematic energy band diagram of the active layer in Figure 1. Referring to Figure 1, the active layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22 stacked together. The semiconductor materials of the first semiconductor layer 21 and the second semiconductor layer 22 have different energy band structures, for example, the first semiconductor layer 21 and the second semiconductor layer 22 have different band gap widths. Optionally, the material of the first semiconductor layer 21 is IZO, and the material of the second semiconductor layer 22 is IGZO. Both IZO and IGZO are N-type semiconductor layer materials, that is, the conductivity type of the channel regions of IZO and IGZO is the same; moreover, IZO and IGZO have high lattice matching and different band structures. For example, the band gap widths of IZO and IGZO are different. When IZO and IGZO are in contact, an isotype heterostructure will be formed, and an electric potential barrier will be formed at the heterojunction interface, resulting in different electron and hole concentrations. The band gap width and conductivity at the heterojunction interface are different from those of the adjacent semiconductor layer, which reduces the energy of electrons on one side near the heterojunction interface to become free electrons, thereby causing the energy band near the heterojunction interface to bend downward. At this time, a "depression" is generated where the energy band bends, and electrons will gather here, thereby forming a high-concentration electron region, reducing the scattering effect of donor impurities on electrons, thereby improving the carrier mobility.

[0057] In one embodiment, when the material of the first semiconductor layer 21 is IZO and the material of the second semiconductor layer 22 is IGZO, the doping concentration of the indium element in the first semiconductor layer 21 is different from the doping concentration of the indium element in the second semiconductor layer 22. This is beneficial to adjust the bandgap width of the first semiconductor layer 21 and the bandgap width of the second semiconductor layer 22, and can increase the adjustment space of the bandgap width of the first semiconductor layer 21 and the second semiconductor layer 22, thereby making it easier for the contact interface between the first semiconductor layer 21 and the second semiconductor layer 22 to form an isotype heterostructure, thereby further improving the carrier mobility.

[0058] Other structures of the thin film transistor 100 will be described in detail below:

[0059] Continuing with FIG1 , the thin film transistor 100 further includes a source electrode 30, a first gate electrode 40, a first gate insulating layer 13, and a drain electrode 50. The source electrode 30 is disposed on one side of the substrate 10. The first gate electrode 40 is disposed on a side of the source electrode 30 away from the substrate 10. The first gate insulating layer 13 is disposed on a side of the first gate electrode 40 away from the substrate 10 and covers the sidewalls of the first gate electrode 40. The drain electrode 50 is disposed on a side of the first gate insulating layer 13 away from the substrate 10. The active layer 20 is disposed on a side of the first gate insulating layer 13 away from the first gate electrode 40 and is connected to the source electrode 30 and the drain electrode 50.

[0060] Optionally, a buffer layer 11 is provided between the substrate 10 and the source electrode 30. The buffer layer 11 can prevent undesirable impurities or contaminants (e.g., moisture, oxygen, etc.) from diffusing from the substrate 10 into devices that may be damaged by these impurities or contaminants, while also providing a flat top surface. The buffer layer 11 can be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide.

[0061] The source electrode 30 is disposed on a side of the buffer layer 11 away from the substrate 10. Optionally, the source electrode 30 may be made of a metal conductive material with strong reducing properties. For example, the source electrode 30 may be a stack of titanium, aluminum, and titanium. Titanium has a strong reducing property and can capture oxygen atoms from the active layer 20, reducing oxygen vacancies and forming a heavily doped region on the surface of the active layer 20 to form a good ohmic contact with the source electrode 30. Of course, the source electrode 30 may also be formed of other metal conductive materials, such as copper, molybdenum, etc.

[0062] The thin film transistor 100 further includes an interlayer insulating layer 12, which covers a portion of the source electrode 30 and the buffer layer 11 and exposes a portion of the source electrode 30. The interlayer insulating layer 12 can be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide.

[0063] The first gate 40 is disposed on a side of the interlayer insulating layer 12 away from the substrate 10. The first gate 40 also exposes the source electrode 30 not covered by the interlayer insulating layer 12. That is, the sidewalls of the first gate 40 are flush with the sidewalls of the first interlayer insulating layer 12, forming an inclined surface. Optionally, the first gate 40 is a single layer or a stack of layers composed of a metal such as Mo, Al, Cu, Ti, or an alloy.

[0064] The first gate insulating layer 13 is disposed on a side of the first gate 40 away from the substrate 10 and covers the sidewalls of the first gate 40. Specifically, the first gate insulating layer 13 covers the upper surface of the first gate 40 away from the substrate 10 and extends from the upper surface of the first gate 40 to the sidewalls of the first gate 40 and the sidewalls of the interlayer insulating layer 12. The first gate insulating layer 13 can be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide.

[0065] The drain electrode 50 is disposed on a side of the first gate insulating layer 13 away from the substrate 10. The sidewalls of the drain electrode 50 are flush with the portion of the first gate insulating layer 13 covering the sidewalls of the first gate electrode 40 and the interlayer insulating layer 12. Optionally, the material of the drain electrode 50 is the same as that of the source electrode 30, that is, the material of the drain electrode 50 includes a metallic conductive material with strong reducing properties. For example, the drain electrode 50 is a stacked layer formed of titanium, aluminum, and titanium. Titanium has a strong reducing property and can capture oxygen atoms from the active layer 20, reducing oxygen vacancies and forming a heavily doped region on the surface of the active layer 20, thereby forming a good ohmic contact with the drain electrode 50.

[0066] Of course, in other embodiments, the drain electrode 50 can also be formed of other metal conductive materials, such as copper, molybdenum, etc.; or, the drain electrode 50 can also be formed of a transparent conductive material, such as ITO. Using a transparent conductive material to form the drain electrode 50 can improve the transmittance of light. When the thin film transistor 100 is applied to a display panel, the transmittance of the display panel can be improved.

[0067] The active layer 20 is disposed on a side of the first gate insulating layer 13 away from the first gate electrode 40 and is connected to the source electrode 30 and the drain electrode 50. Specifically, the active layer 20 covers the upper surface of the drain electrode 50 away from the substrate 10 and extends from the upper surface of the drain electrode 50 to the sidewalls of the drain electrode 50, the sidewalls of the first gate insulating layer 13, the upper surface of the source electrode 30 away from the substrate 10, and the sidewalls of the source electrode 30. More specifically, the active layer 20 includes a channel 201 and a source doping region 202 and a drain doping region 203 located on opposite sides of the channel 201, the source doping region 202 is connected to the source 30, the drain doping region 203 is connected to the drain 50, and the channel 201 corresponds to the side wall of the first gate 40, that is, the source doping region 202 covers the upper surface of the source 30 and the side wall of the source 30, the drain doping region 203 covers the upper surface of the drain 50 and the side wall of the drain 50, and the channel 201 covers the side wall of the first gate insulating layer 13 to form a vertical channel 201, thereby reducing the occupied area of ​​the thin film transistor 100. When the thin film transistor 100 is applied to the display panel, a high-resolution, high-pixel-density display panel can be achieved. The width of the vertical channel 201 depends on the thickness of the first gate 40 , so that the channel 201 of the thin film transistor 100 can achieve a larger width-to-length ratio.

[0068] In one embodiment, the thin film transistor 100 further includes a second gate insulating layer 14 and a second gate electrode 60. The second gate insulating layer 14 is disposed on a side of the active layer 20 away from the first gate insulating layer 13, and the second gate electrode 60 is disposed on a side of the second gate insulating layer 14 away from the active layer 20.

[0069] Specifically, the second gate insulating layer 14 sequentially covers a portion of the upper surface of the drain electrode 50, the drain doping region 203 of the active layer 20, the channel 201 of the active layer 20, the source doping region 202 of the active layer 20, and a portion of the buffer layer 11. Optionally, the second gate insulating layer 14 can be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide.

[0070] The second gate 60 is disposed on a side of the second gate insulating layer 14 away from the active layer 20 to form a dual-gate structure. Dual-gate control can provide strong gate control capabilities and is more suitable for short-channel devices 201. The dual-gate first gate 40 and the dual-gate second gate 60 can be at the same potential or at different potentials.

[0071] Optionally, with continued reference to FIG. 1 , the second semiconductor layer 22 is located on a side of the first semiconductor layer 21 away from the first gate 40, and the first semiconductor layer 21 is located on a side of the second semiconductor layer 22 away from the second gate 60. The thickness of the first semiconductor layer 21 is greater than the thickness of the second semiconductor layer 22 to ensure that the active layer 20 has better electrical performance. It should be noted that since the material of the second semiconductor layer 22 is IGZO, which has better climbing performance than IZO, a smaller thickness of IGZO can be provided, while a larger thickness of IZO can be provided, to ensure that the first semiconductor layer 21 does not suffer from defects such as breakage during climbing, thereby ensuring the electrical performance of the active layer 20 formed by the first and second semiconductor layers 21 and 22.

[0072] Next, the effect of improving carrier mobility in the embodiment of the present application is further explained by taking IZO and IGZO as the materials of the active layer 20 as an example through the energy band diagrams of IZO and IGZO:

[0073] Referring to Figure 2, in Figure 2, Ec represents the conduction band of IZO and IGZO, Ev represents the valence band of IZO and IGZO, and Ef represents the Fermi level. It can be seen from Figure 2 that when IZO and IGZO are in contact, an isotype heterostructure will be formed, and an electric potential barrier will be formed at the heterojunction interface, resulting in different electron and hole concentrations. In addition, the band gap width and conductivity at the heterojunction interface are different from those of the adjacent semiconductor layer, which reduces the energy required for electrons on one side near the heterojunction interface to become free electrons, thereby causing the energy band near the heterojunction interface to bend downward. At this time, a "depression" is generated where the energy band bends, and electrons e will gather here, thereby forming a high-concentration electron region SA. The scattering effect of donor impurities on electrons is reduced, thereby improving the carrier mobility.

[0074] In one embodiment, referring to Figures 1 to 3, Figure 3 is another schematic cross-sectional view of a thin film transistor 100 according to an embodiment of the present application. Unlike the above embodiment, the active layer 20 includes three semiconductor layers, for example, the active layer 20 includes a first semiconductor layer 21, a second semiconductor layer 22, and a third semiconductor layer 23 that are stacked.

[0075] Specifically, referring to FIG3 , the second semiconductor layer 22 is located on a side of the first semiconductor layer 21 away from the first gate electrode 40, and the third semiconductor layer 23 is located on a side of the second semiconductor layer 22 away from the first semiconductor layer 21. Optionally, the first semiconductor layer 21 and the second semiconductor layer 22 are both made of IGZO, and the indium doping concentration in the first semiconductor layer 21 is different from the indium doping concentration in the second semiconductor layer 22, resulting in different energy band structures for the first semiconductor layer 21 and the second semiconductor layer 22, thereby forming an isotype heterostructure at the interface between the first semiconductor layer 21 and the second semiconductor layer 22. The third semiconductor layer 23 is also made of IGZO, and the indium doping concentration in the third semiconductor layer 23 is different from the indium doping concentration in the second semiconductor layer 22, thereby forming a different energy band structure for the second semiconductor layer 22 and the third semiconductor layer 23, thereby forming an isotype heterostructure at the interface between the third semiconductor layer 23 and the second semiconductor layer 22. Among them, the doping concentration of indium in the first semiconductor layer 21 is lower than the doping concentration of indium in the second semiconductor layer 22, and the doping concentration of indium in the third semiconductor layer 23 is also lower than the doping concentration of indium in the second semiconductor layer 22. The energy of electrons on one side near the low-doping concentration interface turning into free electrons is reduced, the energy band is bent, and electrons gather at the interface to form a high-concentration electron region. The scattering effect of donor impurities on electrons is reduced, thereby improving the carrier mobility.

[0076] Optionally, the thickness of the first semiconductor layer 21 is smaller than the thickness of the second semiconductor layer 22, and the thickness of the third semiconductor layer 23 is also smaller than the thickness of the second semiconductor layer 22. The thicknesses of the first semiconductor layer 21 and the third semiconductor layer 23 are both in a range of 5 nanometers to 15 nanometers, and the thickness of the second semiconductor layer 22 is in a range of 20 nanometers to 30 nanometers. For example, the thickness of the first semiconductor layer 21 is 10 nanometers, the thickness of the second semiconductor layer 22 is 25 nanometers, and the thickness of the third semiconductor layer 23 is 10 nanometers. In this case, the mobility of the channel 201 of the active layer 20 is optimal.

[0077] Optionally, in some embodiments, the thin film transistor 100 in this embodiment may further include a second gate electrode 60 and a second gate insulating layer 14 as in the above embodiment to implement dual-gate driving. Similarly, the dual-gate second gate electrode 60 insulating layer is disposed on the side of the active layer 20 away from the first gate electrode 40, and the second gate electrode 60 is disposed on the side of the second gate insulating layer 14 away from the active layer 20. The second semiconductor layer 22 of the active layer 20 is located on the side of the third semiconductor layer 23 away from the second gate electrode 60.

[0078] It should be noted that, in some other embodiments, when the active layer 20 includes three semiconductor layers, the material of the first semiconductor layer 21 is IZO, the material of the second semiconductor layer 22 is IGZO, and the material of the third semiconductor layer 23 is IGZO, and the doping concentration of indium in the third semiconductor layer 23 is different from the doping concentration of indium in the second semiconductor layer 22. In this case, the purpose of improving carrier mobility in the above embodiment can also be achieved; when the active layer 20 includes two semiconductor layers, the material of the first semiconductor layer 21 is IGZO, and the material of the second semiconductor layer 22 is IGZO, and the doping concentration of indium in the first semiconductor layer 21 is different from the doping concentration of indium in the second semiconductor layer 22. In this case, the purpose of improving carrier mobility in the above embodiment can also be achieved. For other explanations, please refer to the above embodiment and will not be repeated here.

[0079] In one embodiment, referring to Figures 1 to 4, Figure 4 is another schematic cross-sectional structure diagram of a thin film transistor 100 provided in an embodiment of the present application. Unlike the above embodiment, the materials of the three semiconductor layers of the active layer 20 are different from those of the above embodiment. Specifically, the materials of the first semiconductor layer 21, the second semiconductor layer 22, and the third semiconductor layer 23 are ZnO, AlZnO, and YZnO, respectively. ZnO, AlZnO, and YZnO are all N-type semiconductor materials with high lattice matching and different band structures. For example, the band gap widths of ZnO and AlZnO are different, and the band gap widths of AlZnO and YZnO are also different. That is, the band gap widths of the first semiconductor layer 21 and the second semiconductor layer 22 are different, and the band gap widths of the third semiconductor layer 23 and the second semiconductor layer 22 are different. This makes the contact interface between the first semiconductor layer 21 and the second semiconductor layer 22 form an isotype heterostructure, and the contact interface between the third semiconductor layer 23 and the second semiconductor layer 22 also form an isotype heterostructure, thereby improving carrier mobility.

[0080] Optionally, the zinc doping concentration in the first semiconductor layer 21 is different from the zinc doping concentration in the second semiconductor layer 22. This facilitates adjusting the bandgap widths of the first semiconductor layer 21 and the second semiconductor layer 22, increasing the adjustment space for the bandgap widths of the first semiconductor layer 21 and the second semiconductor layer 22, and thereby making it easier for the first semiconductor layer 21 and the second semiconductor layer 22 to form an isotype heterostructure at the contact interface, thereby further improving carrier mobility. Accordingly, the zinc doping concentration in the third semiconductor layer 23 is different from the zinc doping concentration in the second semiconductor layer 22. This facilitates adjusting the bandgap widths of the third semiconductor layer 23 and the second semiconductor layer 22, increasing the adjustment space for the bandgap widths of the third semiconductor layer 23 and the second semiconductor layer 22, and thereby making it easier for the third semiconductor layer 23 and the second semiconductor layer 22 to form an isotype heterostructure at the contact interface, thereby further improving carrier mobility.

[0081] In addition, unlike the above embodiment, referring to FIG. 4 , the thin film transistor 100 of this embodiment includes a gate, namely a second gate 60, and the second gate 60 is located on the side of the second gate insulating layer 14 away from the active layer 20. That is, no gate is provided between the source electrode 30 and the drain electrode 50. In this case, the second semiconductor layer 22 is located on the side of the third semiconductor layer 23 away from the second gate 60, and the first semiconductor layer 21 is located on the side of the second semiconductor layer 22 away from the third semiconductor layer 23. The YZnO material of the third semiconductor layer 23 can reduce interface defects between the first semiconductor layer 21, the second semiconductor layer 22, and the second gate insulating layer 14, thereby improving the electrical stability of the thin film transistor 100.

[0082] It should be noted that, in some other embodiments, when the active layer 20 includes three semiconductor layers, and the materials of the three semiconductor layers are ZnO, AlZnO, and YZnO, respectively, the thin film transistor 100 can also adopt a dual-gate drive, that is, the thin film transistor 100 can also include the first gate 40 disposed between the source electrode 30 and the drain electrode 50 in the aforementioned embodiment; furthermore, when the thin film transistor 100 includes a single gate, the single gate can also be disposed between the source electrode 30 and the drain electrode 50, that is, the thin film transistor 100 includes the first gate 40 in the aforementioned embodiment, but in this case, the semiconductor layer formed of YZnO needs to be located between the semiconductor layers formed of ZnO and AlZnO and the first gate 40 to reduce interface defects between ZnO, AlZnO, and the gate insulating layer. For other explanations, please refer to the above embodiments and will not be repeated here.

[0083] Based on the same inventive concept, the present application further provides a display panel, which includes the thin film transistor 100 according to one of the aforementioned embodiments.

[0084] According to the above embodiments, it can be seen that:

[0085] The present application provides a thin film transistor and a display panel, wherein an active layer of the thin film transistor overlies the sidewalls of the drain electrode, the sidewalls of the first gate insulating layer, and the source electrode exposed by the interlayer insulating layer to form a vertical channel, thereby reducing the occupied area of ​​the thin film transistor and enabling the thin film transistor channel to achieve a larger width-to-length ratio. Furthermore, the active layer comprises at least two stacked semiconductor layers, wherein the channel regions of the two adjacent semiconductor layers have the same conductivity type, and the semiconductor materials of the two adjacent semiconductor layers have different doping concentrations of the same element. Thus, upon contact, the two adjacent semiconductor layers form an isotype heterostructure, forming an electric potential barrier at the heterojunction interface, resulting in different electron and hole concentrations. Furthermore, the band gap width and conductivity at the heterojunction interface differ from those of the adjacent semiconductor layers, reducing the energy required for electrons on one side of the heterojunction interface to become free electrons, thereby causing the energy band near the heterojunction interface to bend downward. At this point, a "depression" is created where the energy band bends, where electrons gather, thereby forming a high-concentration electron region. The electrons are less susceptible to donor impurity scattering, thereby improving carrier mobility.

[0086] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A thin film transistor comprising: substrate; a source electrode, disposed on one side of the substrate; an interlayer insulating layer, disposed on a side of the source electrode away from the substrate and exposing a portion of the source electrode; a first gate, disposed on a side of the interlayer insulating layer away from the substrate; a first gate insulating layer, disposed on a side of the first gate away from the substrate and covering a sidewall of the first gate; a drain electrode, disposed on a side of the first gate insulating layer away from the substrate; an active layer, disposed on a side of the first gate insulating layer away from the first gate electrode and covering a sidewall of the drain electrode, a sidewall of the first gate insulating layer, and the source electrode exposed by the interlayer insulating layer, the active layer comprising at least two stacked semiconductor layers; The conductive types of the channel regions of the two adjacent semiconductor layers are the same, and the doping concentrations of the same element in the semiconductor materials of the two adjacent semiconductor layers are different.

2. The thin film transistor according to claim 1, wherein The active layer includes a first semiconductor layer and a second semiconductor layer that are stacked, and the first semiconductor layer and the second semiconductor layer have different band gaps.

3. The thin film transistor according to claim 1, wherein The active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made of IZO, the second semiconductor layer is made of IGZO, and the doping concentration of indium in the first semiconductor layer is different from that in the second semiconductor layer. The thin film transistor according to claim 3 , wherein: The thickness of the first semiconductor layer is greater than that of the second semiconductor layer. The thin film transistor according to claim 1 , wherein: The active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The materials of the first semiconductor layer and the second semiconductor layer are both IGZO. The doping concentration of indium in the first semiconductor layer is different from that of indium in the second semiconductor layer. The thin film transistor according to claim 5 , wherein: The thickness of the first semiconductor layer is smaller than that of the second semiconductor layer.

7. The thin film transistor according to claim 5, wherein The active layer further includes a third semiconductor layer located on a side of the second semiconductor layer away from the first semiconductor layer. The material of the third semiconductor layer is IGZO, and the doping concentration of indium in the third semiconductor layer is different from the doping concentration of indium in the second semiconductor layer.

8. The thin film transistor according to claim 7, wherein: The doping concentration of indium in the second semiconductor layer is greater than the doping concentration of indium in the third semiconductor layer.

9. The thin film transistor according to claim 1, wherein The active layer includes a first semiconductor layer and a second semiconductor layer stacked together, and a third semiconductor layer located on a side of the second semiconductor layer away from the first semiconductor layer. The third semiconductor layer has a different bandgap width from the second semiconductor layer. The materials of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are ZnO, AlZnO, and YZnO, respectively.

10. The thin film transistor according to claim 1, wherein Also includes: a second gate insulating layer, disposed on a side of the active layer away from the first gate insulating layer; The second gate is arranged on a side of the second gate insulating layer away from the active layer. The thin film transistor according to claim 10 , wherein: The drain electrode is a transparent electrode.

12. The thin film transistor according to claim 10, wherein: The source electrode and the drain electrode are both made of reducing metal materials.

13. A display panel comprising a thin film transistor, wherein the thin film transistor comprises: substrate; a source electrode, disposed on one side of the substrate; an interlayer insulating layer, disposed on a side of the source electrode away from the substrate and exposing a portion of the source electrode; a first gate, disposed on a side of the interlayer insulating layer away from the substrate; a first gate insulating layer, disposed on a side of the first gate away from the substrate and covering a sidewall of the first gate; a drain electrode, disposed on a side of the first gate insulating layer away from the substrate; an active layer, disposed on a side of the first gate insulating layer away from the first gate electrode and covering a sidewall of the drain electrode, a sidewall of the first gate insulating layer, and the source electrode exposed by the interlayer insulating layer, the active layer comprising at least two stacked semiconductor layers; The conductive types of the channel regions of the two adjacent semiconductor layers are the same, and the doping concentrations of the same element in the semiconductor materials of the two adjacent semiconductor layers are different.

14. The display panel according to claim 13, wherein: The active layer includes a first semiconductor layer and a second semiconductor layer that are stacked, and the first semiconductor layer and the second semiconductor layer have different band gaps.

15. The display panel according to claim 13, wherein: The active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made of IZO, the second semiconductor layer is made of IGZO, and the doping concentration of indium in the first semiconductor layer is different from that in the second semiconductor layer.

16. The display panel according to claim 13, wherein: The active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The materials of the first semiconductor layer and the second semiconductor layer are both IGZO. The doping concentration of indium in the first semiconductor layer is different from that of indium in the second semiconductor layer.

17. The display panel according to claim 16, wherein: The thickness of the first semiconductor layer is smaller than that of the second semiconductor layer.

18. The display panel according to claim 16, wherein: The active layer further includes a third semiconductor layer located on a side of the second semiconductor layer away from the first semiconductor layer. The material of the third semiconductor layer is IGZO, and the doping concentration of indium in the third semiconductor layer is different from the doping concentration of indium in the second semiconductor layer.

19. The display panel according to claim 18, wherein: The doping concentration of indium in the second semiconductor layer is greater than the doping concentration of indium in the third semiconductor layer.

20. The display panel according to claim 13, wherein The active layer includes a first semiconductor layer and a second semiconductor layer stacked together, and a third semiconductor layer located on a side of the second semiconductor layer away from the first semiconductor layer. The third semiconductor layer has a different bandgap width from the second semiconductor layer. The materials of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are ZnO, AlZnO, and YZnO, respectively.

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