Processor and accelerator direct connection interface embedded in pipeline, and implementation method therefor

Abstract

Disclosed in the present invention are a processor and accelerator direct connection interface embedded in a pipeline, and an implementation method therefor. The interface is integrated in a memory access stage of a CPU pipeline; and after branch prediction hits, read and write operations can be immediately sent to an accelerator by means of the interface. The interface provided in the present invention constructs a random access queue and a scheduler to schedule hardware-level heterogeneous accelerator operations; the random access queue supports random access for buffering HA operations, thereby preventing physical priority inversion and allowing importance-based operation priorities; and the configurable scheduler creates a priority queue to ensure the preemptive scheduling of the HA operations, thereby ensuring both predictability and throughput. The prevent invention also prevents data hazards by means of forwarding logic. The interface provided in the present invention has relatively low latency and relatively high stability, and also ensures both the throughput and the real-time performance.

Description

A direct connection interface between a processor and an accelerator embedded in a pipeline and its implementation method Technical Field

[0001] The present invention belongs to the field of computer technology and relates to integrated circuit technology. More specifically, it relates to a direct connection interface between a processor and an accelerator embedded in a pipeline and an implementation method thereof. Background Art

[0002] In real-time systems, the complexity of systems on a chip (SoCs) has increased dramatically due to the diverse functions required for modern embedded computing (e.g., image recognition in autonomous driving) and the rapid advancement of semiconductor manufacturing processes (e.g., the ability to produce 3nm ASICs). Although modern SoCs from different vendors typically have different architectures, heterogeneity is always key. That is, SoCs combine general-purpose CPUs with heterogeneous hardware accelerators (HAs) on the same chip to achieve more functions, such as improving resource and energy efficiency.

[0003] As the "communication bridge" connecting CPUs and HAs, the Core-Accelerator (CX) interface has become the main factor determining the real-time performance (i.e., throughput and schedulability) of heterogeneous SoCs.

[0004] In traditional heterogeneous computing architectures, CX interfaces are often developed to ensure the compatibility and portability of HAS. To this end, CX interfaces are typically encapsulated as standardized memory-mapped peripherals (i.e., MM-CX) and physically connect HAS to the system interconnect, mapping HAS to specific memory addresses and allowing CPUs to access HAS using general-purpose memory write / read operations.

[0005] However, the deployment of MM-CX interfaces involves a complex HA access path, especially with the increasing complexity of hardware and architecture (for example, in interconnect-based heterogeneous SoCs, HA access must pass through multiple levels of data cache (D-Cache), system interconnect, and MM-CX interfaces). This complex path introduces significant communication delays and frequent resource contention to high-availability access, making it difficult to ensure the real-time performance of the system.

[0006] To simplify the HA access path, the Direct-Connect CX (DL-CX) interface has recently been researched and developed. Unlike the MM-CX interface, the DL-CX interface is mounted on the CPU's stream port, allowing the CPU to access HA using customized ISA extensions (ISAXes), effectively reducing the communication latency and resource contention associated with HA access. Compared to the MM-CX interface, the DL-CX interface improves the average throughput of heterogeneous systems, as demonstrated in experimental evaluations.

[0007] However, deploying the DL-CX interface still cannot guarantee system-wide schedulability because the implementation of the DL-CX interface relies on FIFO queues, which prohibits context switching at the hardware level. Effective scheduling, such as Earliest Deadline First (EDF), cannot prioritize HA operations based on their importance to ensure system schedulability. Worse, the FIFO-based design also allows low-priority HA operations to block high-priority operations, when both operations are buffered in the same FIFO queue, the low-priority operation arrives before the high-priority operation. This phenomenon, also known as physical priority inversion, further degrades the schedulability of the entire system. Therefore, in heterogeneous computing SoCs, designing a CX interface to guarantee simultaneous throughput and schedulability of HA operations is important but challenging. There is no ideal implementation solution in the existing technology.

[0008] Summary of the Invention

[0009] To address the existing challenges, this paper proposes a novel heterogeneous SOC real-time core accelerator interface and implementation method to ensure real-time HA operations. This pipeline-coupled DL-CX interface is deployed in the memory access (MA) stage of the CPU core pipeline to optimize the HA access path.

[0010] In order to achieve the above object, the technical solution adopted by the present invention is:

[0011] A pipeline-embedded processor and accelerator direct connection interface, embedded in the processor's memory access stage, includes a write channel and a read channel. The interface entrance is also provided with a mini decoder for directing HA operations to the write / read channel according to the ISAX type.

[0012] The write channel includes: a random access queue, a scheduler, and a shadow buffer; the random access queue is used to receive the payload of operations arriving at the write channel; the scheduler is used to receive timing parameters of operations arriving at the write channel, prioritize the buffered operations according to their time parameters, and map the most important operations to the shadow buffer to perform HA operations;

[0013] The read channel includes an AMBA_APB bridge, which is directly connected to the register of the accelerator; the AMBA_APB bridge is used to convert the read operation into a corresponding register index and return a value within a fixed single clock.

[0014] Furthermore, the memory access stage sets a multiplexer and demultiplexer pair for building independent paths for different types of instructions, routing HA operations to interfaces, and loading and storing instructions to load-store units, while other instructions are directly passed to the write-back pipeline stage; a parameter register is set between the multiplexer and the demultiplexer for tracking the task ID and timing information of the currently executing software task; when the HA operation reaches the memory access stage, the task ID and timing parameters inherited from the software task that issued it are combined with the HA operation and sent to the processor embedded in the pipeline and the accelerator direct connection interface.

[0015] Furthermore, the random access queue includes: a queue block, a queue controller and an optional queue mapping table;

[0016] The queue block is used to buffer HA operations for the write channel;

[0017] The queue controller is used to store / load HA operations in queue blocks;

[0018] The optional queue mapping table implements a circular table for tracking the mapping between unit index and task ID.

[0019] Furthermore, the queue block includes modular block units, which store HA operations with the same task ID; each block unit includes a load FIFO and a unit header; the load FIFO is used to store HA operations according to the order in which HA operations are issued, and the unit header is used to store the TID carried from the p register; the least significant bit of the header is used to indicate the validity of the block unit; each unit is assigned a unique index.

[0020] Furthermore, the queue controller comprises two interfaces connected to the cell header and the load FIFO respectively, including a storage controller and a load controller;

[0021] The storage controller is used to read the header of the block unit to check the status of the unit during the storage process. When a block unit has been used for the task, the storage controller pushes the operation to the same block unit that has been used for the task; otherwise, the storage controller searches for an unused block unit, then sets the LSB of the selected unit header to 1 and pushes the operation to the load FIFO;

[0022] The load controller is used to extract the contents from the load FIFO using its index during the load process, and then write the LSB of the cell header to 0.

[0023] Furthermore, a combinational logic circuit is connected between the load controller and the queue block, for converting the scheduled task ID into an index of a specific queue unit within a single clock cycle.

[0024] Further, the scheduler includes a set of task parameter blocks and a scheduling circuit;

[0025] Each task parameter block includes a register chain and a multiplexer; the register chain is used to record the task ID and timing parameters of the HA operation buffered in the random access queue block unit; the register chain in the task parameter block is routed to the scheduling circuit; the control port of the multiplexer is connected to the same configuration register;

[0026] The scheduling circuit uses a multi-level 2-to-1 multiplexer to construct a tree comparison structure. The initial level multiplexer connects the task parameter blocks and returns the scheduling results at the last level multiplexer. Each multiplexing stage is used to compare adjacent task parameter blocks using specified timing parameters, select the more important task parameter blocks and transfer them to the next multiplexing stage. The last level multiplexer is used to select the most important task parameter blocks and send them to the random access queue.

[0027] Furthermore, the mini decoder is arranged at the entrance of the direct connection interface and is composed of a multiplexer. The mini decoder selects the signal as the type of instruction and distributes the instruction to the read channel and the write channel according to the type of the instruction.

[0028] The present invention also provides a method for implementing a direct interface between a processor embedded in a pipeline and an accelerator, comprising the following steps:

[0029] A multiplexer and demultiplexer pair is set up in the memory access stage to build independent paths for different types of instructions, route HA operations to the interface, and load and store instructions to the load-store unit. Other instructions are directly passed to the write-back pipeline stage. A parameter register is set between the multiplexer and demultiplexer to track the task ID and timing information of the currently executing software task.

[0030] When an HA operation reaches the memory access stage, the TID and timing parameters inherited from the software task that issued it are combined with the operation and sent to the processor embedded in the pipeline and to the accelerator direct interface;

[0031] The mini decoder directs HA operations to the write / read channels of the processor and accelerator direct interface embedded in the pipeline according to the ISAX type;

[0032] When an HA operation arrives at the write channel, its payload and timing parameters are transmitted to the random access queue and scheduler respectively; at the same time, the scheduler prioritizes the buffered operations according to their time parameters and maps the most important operations to the shadow buffer to perform the HA operation; specifically, the queue block of the random access queue buffers HA operations for the write channel, where the load FIFO of the block unit stores them according to the order in which the HA operations are issued, and the unit header stores the task ID carried from the p register; the queue controller of the random access queue stores / loads HA operations in the queue block, and during the storage process, the storage controller first reads the header of the block unit to check the status of the unit; if a block unit has been used for the task, the storage controller will push the operation to the same block unit; otherwise, the memory controller searches for an unused block unit, then sets the LSB of the selected unit header to 1 and pushes the operation to the load FIFO; during the loading process, the load controller uses its index to extract the content from the load FIFO, then writes the LSB of the unit header to 0; the register chain in the task parameter block in the scheduler is routed to the scheduling circuit, where the task ID is bypassed and the scheduling parameters are selected using a multiplexer; the scheduling circuit in the scheduler compares adjacent task parameter blocks using specified timing parameters at each multiplexing stage, selects the task parameter block with higher importance and transfers it to the next multiplexing stage, until the most important task parameter block is selected and sent to the random access queue;

[0033] When the HA operation arrives at the read channel, the AMBA_APB bridge converts the read operation to the corresponding HA register index and returns the value within a fixed single clock.

[0034] Furthermore, the method also includes a data hazard processing step: the data read from the direct connection interface is passed back to the execution stage.

[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0036] 1. This invention proposes a new core accelerator interface, which is integrated into the memory access stage of the CPU pipeline. When a branch prediction hits, the read and write operations will be immediately sent to the accelerator through this interface.

[0037] 2. The proposed interface builds a random access queue and a scheduler to schedule heterogeneous accelerator operations at the hardware level. The random access queue supports random access buffering of HA operations, avoids physical priority inversion, and allows importance-based operation prioritization. The configurable scheduler creates a priority queue to ensure preemptive scheduling of HA operations, ensuring both predictability and throughput. The present invention also prevents data hazards through forwarding logic.

[0038] 3. The interface proposed in the present invention has lower latency and stronger stability, while ensuring throughput and real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is an overall structural diagram of a direct-connect interface between a pipeline-embedded processor and an accelerator provided by an embodiment of the present invention, including modifications to the pipeline portion of the processor and the overall structure of the interface. The left frame in the figure shows the portion for coupling the interface to the processor pipeline, and the right frame shows the portion for connecting the processor and HA using the interface.

[0040] FIG2 is a micro-architecture of a random access queue provided by an embodiment of the present invention.

[0041] FIG3 is a micro-architecture of a scheduler provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The technical solutions provided by the present invention will be described in detail below with reference to specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0043] FIG1 shows a top-level micro-architecture of a pipeline-embedded processor and an accelerator direct interface provided by the present invention, as well as a method for integrating the interface into a 5-stage pipeline CPU core.

[0044] This invention embeds a direct-connect interface into the processor's memory access phase. The interface is divided into two channels: read and write. The write channel includes a random access queue (RAQ), a scheduler, and a shadow buffer; the read channel uses an AMBA_APB bridge to directly connect to the accelerator's registers.

[0045] To integrate the interface into the memory access (MA) pipeline stage, we proposed a multiplexer and demultiplexer pair in the MA stage. They build independent paths for different types of instructions, routing HA operations to the interface and loading and storing instructions to the load store unit (LSU), while other instructions are passed directly to the write back (WB) pipeline stage. Between the multiplexer and demultiplexer, we placed a parameter register (P-Register) to track the task ID (TID) and timing information of the currently executing software task. When an HA operation reaches the MA stage, the TID and timing parameters inherited from the software task that issued it are combined with the operation and sent to the interface.

[0046] In the interface, we deployed a mini-decoder (implemented using a bidirectional multiplexer) at the entry point to direct HA operations to the write / read channel based on the ISAX type. For the write channel, we introduced a random access queue, a scheduler, and a shadow buffer. When an operation arrives at the write channel, its payload and timing parameters are transferred to the RAQ and scheduler respectively. At the same time, the scheduler prioritizes the buffered operations based on their time parameters and maps the most important operations to the shadow buffer for HA execution. For the read channel, we instantiate a standardized AMBA_APB bridge to hook the HA registers. This converts the read operation into the corresponding register index and returns the value within a fixed single clock.

[0047] Data Hazard Handling: Integrating the interface into the core pipeline can introduce runtime data hazards. This means the interface might return read data required by subsequent instructions, data that was buffered earlier in the pipeline. To optimize pipeline processing efficiency, we designed forwarding logic to pass data read from the interface back to the execute (EX) stage (the blue line in Figure 1). This forwarding logic allows instructions with data dependencies to execute directly, rather than waiting in the WB stage for read data to be stored in general-purpose registers.

[0048] Figure 2 shows the microarchitecture of the random access queue, which mainly includes the queue block, queue controller and optional queue mapping table.

[0049] Queue bank, the queue bank buffers HA operations for the write channel. Specifically, the queue bank uses modular block units, where the block unit stores HA operations with the same task ID. The block unit design has two main parts: a load FIFO and a unit header. The load FIFO stores HA operations according to the order in which they are issued, and the unit header stores the TID carried from the p register. We also use the least significant bit (LSB) of the header to indicate the validity of the block unit. When instantiating the block unit to build the queue block, we assign a unique index to each unit, starting from 0x01. We use index 0x00 to represent an invalid index. Using this design, hardware-level context switching can be implemented by loading HA operations from different queue units into the HA.

[0050] Queue controllers store and load HA operations in and out of the queue block. The queue controller contains two interfaces, one connected to the cell header and the other to the load FIFO. During a store (e.g., when an interface receives an HA operation from the CPU), the memory controller first reads the cell header to check the cell's status. If a cell is already in use for the task, the memory controller pushes the operation to the same cell. Otherwise, the controller searches for an unused cell, sets the LSB of the selected cell header to 1, and pushes the operation to the load FIFO (this search occurs only once, following a context switch by the operating system kernel). During a load (e.g., when the scheduler selects a cell for HA execution), the load controller extracts the contents from the load FIFO using its index and then writes the LSB of the cell header to 0. To achieve this, a combinational logic circuit connected to the load controller and the queue block is used to convert the scheduled task ID into the index of a specific queue cell within a single clock cycle. As shown in Figure 2, the number of combinational logic circuits corresponds to the index number. Starting from 0x01, each combinational logic circuit consists of a two-input XNOR gate and a two-input AND gate. The XNOR gate's inputs are the corresponding task ID and the block unit index. The XNOR gate's output and the block unit index are then passed through a two-input AND gate. The outputs of all two-input AND gates are then connected to an OR gate, whose output is connected to the load controller.

[0051] An optional queue mapping table, which implements a circular table to track the mapping between cell indices and task IDs, replacing much of the used combinational circuitry.

[0052] Figure 3 shows the microarchitecture of the scheduler.

[0053] The scheduler prioritizes HA operations according to their importance. To this end, we design a set of task parameter blocks (TPBs) and scheduling circuits.

[0054] Task Parameter Block (TPB),The task parameter block design consists of a register chain and a multiplexer.,The register chain records the task ID and timing parameters of,the HA operations buffered in the random access queue block unit.,To allow prioritization of the task parameter block, we,route the register chain in the task parameter block to the scheduling,circuit in the scheduling circuit, bypassing the task ID and using,a multiplexer to select the scheduling parameters.,We connect the control port of the multiplexer to the same,configuration register, ensuring that the task parameter blocks use the same,object for prioritization.

[0055] The scheduling circuit design uses a tree-like comparison logic structured by multiple levels of 2-to-1 multiplexers. The initial multiplexer connects the task parameter blocks, and the final multiplexer returns the scheduling result. At each multiplexing stage, adjacent task parameter blocks are compared using specified timing parameters. The more important task parameter blocks are selected and transferred to the next multiplexing stage, until the most important task parameter blocks are selected and sent to the random access queue. The scheduling circuit is designed using pure combinational logic.

[0056] It should be noted that the above content merely illustrates the technical idea of ​​the present invention and cannot be used to limit the scope of protection of the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications all fall within the scope of protection of the claims of the present invention.

Claims

1. A direct connection interface between a processor and an accelerator embedded in a pipeline, characterized in that: Embedded in the processor's memory access stage, it includes write and read channels. A mini decoder is also provided at the interface entrance to direct HA operations to the write / read channel based on the ISAX type. The write channel includes: a random access queue, a scheduler, and a shadow buffer; the random access queue is used to receive the payload of operations arriving at the write channel; the scheduler is used to receive timing parameters of operations arriving at the write channel, prioritize the buffered operations according to their time parameters, and map the most important operations to the shadow buffer to perform HA operations; The read channel includes an AMBA_APB bridge, which is directly connected to the register of the accelerator; the AMBA_APB bridge is used to convert the read operation into a corresponding register index and return a value within a fixed single clock.

2. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 1, characterized in that: The memory access stage sets a multiplexer and demultiplexer pair for building independent paths for different types of instructions, routing HA operations to interfaces, and loading and storing instructions to load-store units, while other instructions are directly passed to the write-back pipeline stage; A parameter register is set between the multiplexer and the demultiplexer to track the task ID and timing information of the currently executing software task; when the HA operation reaches the memory access stage, the task ID and timing parameters inherited from the software task that issued it are combined with the HA operation and sent to the processor embedded in the pipeline and the accelerator direct connection interface.

3. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 1, characterized in that: The random access queue includes: a queue block, a queue controller and an optional queue mapping table; The queue block is used to buffer HA operations for the write channel; The queue controller is used to store / load HA operations in queue blocks; The optional queue mapping table implements a circular table for tracking the mapping between unit index and task ID.

4. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 3, characterized in that: The queue block includes modular block units, which store HA operations with the same task ID; each block unit includes a load FIFO and a unit header; the load FIFO is used to store HA operations according to the order in which HA operations are issued, and the unit header is used to store the TID carried from the p register; the least significant bit of the header is used to indicate the validity of the block unit; each unit is assigned a unique index.

5. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 3, characterized in that: The queue controller comprises two interfaces connected to the cell header and the load FIFO respectively, including a storage controller and a load controller; The storage controller is used to read the header of the block unit to check the status of the unit during the storage process, and when a block unit has been used for the task, the storage controller pushes the operation to the same block unit that has been used for the task; Otherwise, the memory controller searches for an unused block cell, then sets the LSB of the selected cell header to 1 and pushes the operation to the load FIFO; The load controller is used to extract the contents from the load FIFO using its index during the load process, and then the unit header Write 0 to the LSB.

6. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 5, characterized in that: A combinational logic circuit is connected between the load controller and the queue block to convert the scheduled task ID into the index of a specific queue unit within a single clock cycle.

7. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 1, characterized in that: The scheduler includes a set of task parameter blocks and a scheduling circuit; Each task parameter block includes a register chain and a multiplexer; the register chain is used to record the task ID and timing parameters of the HA operation buffered in the random access queue block unit; the register chain in the task parameter block is routed to the scheduling circuit; the control port of the multiplexer is connected to the same configuration register; The scheduling circuit uses a multi-level 2-to-1 multiplexer to construct a tree comparison structure. The initial level multiplexer connects the task parameter blocks and returns the scheduling results at the last level multiplexer. Each multiplexing stage is used to compare adjacent task parameter blocks using specified timing parameters, select the more important task parameter blocks and transfer them to the next multiplexing stage. The last level multiplexer is used to select the most important task parameter blocks and send them to the random access queue.

8. The direct connection interface between a processor and an accelerator embedded in a pipeline according to claim 1, characterized in that: The mini decoder is arranged at the entrance of the direct connection interface and is composed of a multiplexer. The mini decoder selects the signal as the type of instruction and distributes the instruction to the read channel and the write channel according to the type of the instruction.

9. A method for implementing a direct interface between a processor embedded in a pipeline and an accelerator, characterized in that: The steps include: A multiplexer and demultiplexer pair is set in the memory access stage to build independent paths for different types of instructions, route HA operations to the interface, and load and store instructions to the load-store unit, while other instructions are directly passed to the write-back pipeline stage; A parameter register is set between the multiplexer and demultiplexer to track the task ID and timing information of the currently executing software task; When an HA operation reaches the memory access stage, the TID and timing parameters inherited from the software task that issued it are combined with the operation and sent to the processor embedded in the pipeline and to the accelerator direct interface; The mini decoder directs HA operations to the write / read channels of the processor and accelerator direct interface embedded in the pipeline according to the ISAX type; When an HA operation arrives at the write channel, its payload and timing parameters are transmitted to the random access queue and scheduler respectively. At the same time, the scheduler prioritizes the buffered operations according to their timing parameters and maps the most important operations to the shadow buffer to perform the HA operation. Specifically, the queue block of the random access queue buffers HA operations for the write channel, where the load FIFO of the block unit stores them according to the order in which the HA operations are issued, and the unit header stores the task ID carried from the p register. The queue controller of the random access queue stores / loads HA operations in the queue block. During the storage process, the storage controller first reads the header of the block unit to check the status of the unit. If a block unit has been used for the task, the storage control The controller will push the operation to the same block unit; otherwise, the memory controller will search for an unused block unit, then set the LSB of the selected unit header to 1 and push the operation to the load FIFO; during the loading process, the load controller uses its index to extract the content from the load FIFO, and then writes the LSB of the unit header to 0; the register chain in the task parameter block in the scheduler is routed to the scheduling circuit, bypassing the task ID in the scheduling circuit, and using a multiplexer to select the scheduling parameters; the scheduling circuit in the scheduler compares adjacent task parameter blocks using specified timing parameters at each multiplexing stage, selects the task parameter block with higher importance and transfers it to the next multiplexing stage, until the most important task parameter block is selected and sent to the random access queue; When the HA operation arrives at the read channel, the AMBA_APB bridge converts the read operation to the corresponding HA register index and returns the value within a fixed single clock.

10. The method for implementing a direct interface between a processor embedded in a pipeline and an accelerator according to claim 9, characterized in that: It also includes a data hazard handling step: data read from the direct connection interface is passed back to the execution stage.

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