Thread scheduling method and apparatus, processor, and computer-readable storage medium

Abstract

Embodiments of the present disclosure provide a thread scheduling method and apparatus, a processor, and a computer-readable storage medium. The thread scheduling method comprises: acquiring multiple threads to be scheduled for an object resource in a processor, and acquiring the number of the multiple threads currently occupying and the number currently reserving the object resource; and, on the basis of the number of the multiple threads currently occupying and the number currently reserving the object resource, selecting a target thread among the multiple threads which satisfies a scheduling condition, and performing scheduling. In the described thread scheduling method and apparatus, a given thread will not be starved, while ensuring the fairness of multiple threads, improving overall design robustness.

Description

Thread scheduling method and device, processor and computer-readable storage medium

[0001] This application claims priority to Chinese Patent Application No. 202410322880.8 filed on March 20, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a thread scheduling method and apparatus, a processor, and a computer-readable storage medium. Background Art

[0003] Modern, multi-issue, high-performance CPUs (Central Processing Units) include at least one processor core, each of which has multiple execution units to execute instructions. For example, the instruction execution pipeline consists of five stages: instruction fetch (IF), decode (ID), execute (EX), access memory (MEM), and write back (WB), which updates the result of instruction execution to registers.

[0004] In order to improve the parallelism of instruction execution in the processor, the processor can use simultaneous multithreading (SMT) technology, so that the pipeline structure (also referred to as "pipeline") used for instruction execution in the processor can support the simultaneous execution of two or more (hardware) threads. For example, an SMT processor can be SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads), or SMT8 (supporting up to eight concurrent threads). When a single-threaded processor is running, multiple execution units inside the processor may be idle due to stalls such as cache misses. For processors using SMT technology, even when a thread is paused, other threads can continue to use these hardware resources. This improves the utilization of hardware resources, avoids idling, and improves processor throughput and performance-power ratio.

[0005] However, as the number of threads in an SMT processor increases, competition for shared resources between threads becomes more intense. This resource competition can weaken the parallelism of multiple threads, reducing processor performance and resource utilization. Therefore, alleviating resource competition between threads and improving parallelism have become important research directions in simultaneous multithreaded processors.

[0006] Summary of the Invention

[0007] At least one embodiment of the present disclosure provides a thread scheduling method, which includes: obtaining multiple threads to be scheduled for object resources in a processor, and obtaining the current occupied quantities and reserved quantities of the object resources by the multiple threads; based on the current occupied quantities and reserved quantities of the object resources by the multiple threads, selecting a target thread that meets the scheduling conditions from the multiple threads for scheduling.

[0008] For example, in the thread scheduling method according to at least one embodiment, the scheduling condition includes that the target thread is currently active, and the object resource has a first quantity available for allocation after deducting the quantity reserved for other active threads except the target thread.

[0009] For example, in the thread scheduling method according to at least one embodiment, selecting a target thread that meets the scheduling conditions from the multiple threads for scheduling includes: performing arbitration based on a selection algorithm to select the target thread from one or more candidate threads that meet the scheduling conditions.

[0010] For example, in the thread scheduling method according to at least one embodiment, the selection algorithm includes a least recently used algorithm (LRU), a least recently used algorithm (LFU), or a round robin algorithm (RH).

[0011] For example, in a thread scheduling method according to at least one embodiment, the target thread that meets the scheduling conditions is selected from the multiple threads for scheduling, including: obtaining the target instruction to be sent by the target thread and the second number of the target instructions, and obtaining the first number of the object resources that can be allocated after excluding the number reserved for other active threads other than the target thread, wherein the first number is greater than 0; in response to the second number being less than or equal to the first number, all of the target instructions are sent to use the object resources for instruction processing, or, in response to the second number being greater than the first number, part of the first number of the target instructions is sent to use the object resources for instruction processing.

[0012] For example, according to at least one embodiment of the thread scheduling method, before obtaining the current occupation quantity and reserved quantity of the object resource by the multiple threads respectively, it also includes: determining the reserved quantity of the object resource for each thread in the multiple threads.

[0013] For example, in the thread scheduling method according to at least one embodiment, determining the reserved quantity for the object resource for each thread among the multiple threads includes: for a current thread among the multiple threads, determining whether the current thread is active; in response to the current thread being inactive, not reserving for the current thread, or, in response to the current thread being active, determining the reserved quantity for the object resource by the current thread based on the quantity of the object resource occupied by the current thread.

[0014] For example, in the thread scheduling method according to at least one embodiment, the number of the plurality of threads is greater than or equal to 4.

[0015] For example, in the thread scheduling method according to at least one embodiment, the object resources include a cache, a branch predictor storage space, an out-of-order scheduler storage space, and a data prefetcher storage space.

[0016] At least one embodiment of the present disclosure also provides a thread scheduling device, which includes: an acquisition module, configured to acquire multiple threads to be scheduled for object resources in a processor, and acquire the current occupied quantity and reserved quantity of the object resources by the multiple threads; a scheduling module, configured to select a target thread that meets the scheduling conditions from the multiple threads for scheduling based on the current occupied quantity and reserved quantity of the object resources by the multiple threads.

[0017] For example, in the thread scheduling device according to at least one embodiment, the scheduling module includes a thread selection module, and the thread selection module is configured to perform arbitration based on a selection algorithm to select the target thread from one or more candidate threads that meet all scheduling conditions.

[0018] For example, in the thread scheduling device according to at least one embodiment, the scheduling module also includes an instruction selection module, and the instruction selection module is configured to: obtain the target instructions to be sent by the target thread and the second number of the target instructions, and obtain the first number of the object resources available for allocation after excluding the number reserved for other active threads other than the target thread, wherein the first number is greater than 0; and in response to the second number being less than or equal to the first number, send all of the target instructions to use the object resources for instruction processing, or, in response to the second number being greater than the first number, send part of the first number of the target instructions to use the object resources for instruction processing.

[0019] For example, according to at least one embodiment, the thread scheduling apparatus further includes a resource reservation module, and the resource reservation module is configured to determine a reserved quantity for the object resource for each thread in the plurality of threads.

[0020] At least one embodiment of the present disclosure further provides a thread scheduling device, comprising: a processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to the processing unit; the processing unit executes the computer-readable instructions stored in the memory to implement the thread scheduling method provided in any of the above embodiments.

[0021] At least one embodiment of the present disclosure further provides a processor, and a thread scheduling device provided according to at least one embodiment of the present disclosure.

[0022] At least one embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the thread scheduling method provided by any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] FIG1 shows a schematic diagram of a pipeline of a processor core;

[0025] FIG2 shows a schematic diagram of a processor pipeline involving out-of-order execution and register renaming;

[0026] FIG3 shows a schematic diagram of a thread scheduling process of an SMT4 processor;

[0027] FIG4 is a schematic diagram showing a flow chart of a thread scheduling method provided by at least one embodiment of the present disclosure;

[0028] FIG5 shows a schematic structural diagram of a thread scheduling device provided by at least one embodiment of the present disclosure;

[0029] FIG6 shows a schematic structural diagram of another thread scheduling device provided by at least one embodiment of the present disclosure;

[0030] FIG7 shows a schematic structural diagram of another thread scheduling device provided by at least one embodiment of the present disclosure;

[0031] FIG8 is a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure; and

[0032] FIG9 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0035] In order to improve the performance of the processor core, the processor core can use a pipeline approach, that is, the entire process of an instruction from being extracted, decoded, executed, and the result written back is divided into multiple pipeline stages. In one operation cycle, an instruction can only be in one of the pipeline stages; and the processor core can run multiple instructions in different pipeline stages.

[0036] FIG1 shows a schematic diagram of a pipeline of a processor core, where the dashed line with an arrow represents a redirected instruction flow.

[0037] As shown in Figure 1, the processor cores (e.g., CPU cores) of single-core or multi-core processors utilize pipeline technology to improve instruction-level parallelism. The pipeline within the processor core consists of multiple pipeline stages. For example, after program counters (PCs) are fed into the pipeline from various sources and the next program counter (PC) is selected by a multiplexer (Mux), the instruction corresponding to that PC undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retirement. Waiting queues are set up between each pipeline stage as needed; these queues are typically first-in, first-out (FIFO) queues. For example, after the branch prediction unit, there's a branch prediction (BP) FIFO queue to store branch prediction results; after the instruction fetch unit, there's an instruction cache (IC) FIFO to cache fetched instructions; after the instruction decode unit, there's a decode (DE) FIFO to cache decoded instructions; and after the instruction dispatch and rename unit, there's a finish (RT) FIFO to cache instructions waiting for completion confirmation. The processor core's pipeline also includes an instruction queue to cache instructions waiting for execution by the instruction execution unit after dispatch and renaming.

[0038] Figure 2 shows a schematic diagram of a processor pipeline involving out-of-order execution and register renaming. As shown in Figure 2, after each instruction (e.g., a branch instruction) is fetched from the instruction cache according to the program counter (PC) ("fetch"), the fetched instruction undergoes instruction decoding ("decoding"). The decoded instruction undergoes register renaming ("renaming"). The renamed instruction is then sent for out-of-order execution to remove spurious dependencies between instructions. The instruction then enters the instruction dispatch module, which determines when to dispatch the instruction to which execution unit for execution ("out-of-order scheduling"). For example, in different operation cycles, instructions are dispatched to different execution units (e.g., arithmetic logic unit (ALU), multiplication unit (MUL), division unit (DIV), load and store unit (LSU), etc.) corresponding to different ports (e.g., port 0, port 1, port 2, port 3, etc.) for execution. While register renaming is occurring, the instruction enters the instruction commit unit, which records the original instruction fetch order of the instructions being processed in the pipeline. The instruction commit unit is used to commit the instructions in the original instruction fetch order after the instructions are executed. At the same time, it will update the actual execution information of the branch instructions to the branch prediction unit.

[0039] As mentioned above, register renaming can resolve potential pipeline conflicts associated with WAW (Write After Write) and WAR (Read After Write). This technology does not increase the number of general-purpose registers. Instead, it redefines physical registers (PRs) within the processor. Registers defined in the instruction set are called architectural registers (ARs). Physical registers are physically present within the processor, such as the physical register file (PRF). The processor dynamically maps architectural registers (ARs) to physical registers (PRs) to resolve WAW and WAR dependencies. The processor uses the architectural register mapping table and the physical register free list to perform register renaming. When the processor renames an architectural register used in the current instruction, it processes both the source and destination registers (both logical registers) in the instruction. For the source register, the processor searches the architectural register mapping table to find the corresponding PR number (PRN). For the destination register, it reads a PR number from the physical register free list, maps the PR number to the destination register, and writes it to the architectural register mapping table. If the free list is empty, the processor pipeline pauses and waits until an instruction retires, freeing up the PR. The architecture register mapping table is implemented, for example, through a hardware structure such as a storage device (eg, a cache or a register).

[0040] In addition, to increase the parallelism of instruction execution in the processor, the processor can also use simultaneous multithreading (SMT) technology. The processor's pipeline structure for instruction execution (also referred to as the "pipeline") can support the simultaneous execution of two or more (hardware) threads. For example, it can be SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads), or SMT8 (supporting up to eight concurrent threads). In the pipeline of a processor that supports simultaneous multithreading technology, the computing resources in the processor are shared by multiple threads. For example, each thread can have its own independent logical register, but the multiple physical registers within the processor are shared by multiple threads. Among the queues of various control functions in the pipeline, some can be shared by multiple threads, such as the instruction scheduling queue, and others can be statically divided between multiple threads, such as the instruction reordering queue. Simultaneous multithreading technology can use the parallelism between threads to improve pipeline resource utilization.

[0041] Furthermore, processors that utilize simultaneous multithreading (SMT) technology can operate in either SMT or single-threaded mode. For example, in SMT mode, when one thread encounters a wait state, other threads can continue executing, effectively improving hardware resource utilization and thereby enhancing the CPU core's multithreading capabilities, overall performance, and performance-per-watt ratio.

[0042] In this disclosure, an "operation cycle" can be, for example, a clock cycle or machine cycle, or any other time period in a processor's instruction pipeline that is used to complete a single operation. The execution of an instruction in each thread consists of several stages, each of which completes a basic operation (e.g., instruction fetch, memory read, memory write, etc.). The time required to complete a basic operation is called a machine cycle, also known as a CPU cycle.

[0043] Figure 3 shows a schematic diagram of the thread scheduling process of an SMT4 processor. Taking the example of an SMT4 processor that can schedule two threads in each operation cycle, as shown in Figure 3, for scheduling a queue shared by multiple threads in a certain pipeline stage, the thread numbers T0-T3 of the four threads are stored in a first-in-first-out (FIFO) queue. From the head to the tail of the FIFO queue, the priorities of the four threads are arranged from high to low. In operation cycle 0, the thread priorities stored in the FIFO queue are initially T0, T1, T2, and T3, and all four threads are in a schedulable state. When threads T0 and T1 are successfully scheduled, the status of the FIFO queue is updated to T2, T3, T0, and T1. In cycle 1, the thread priority order is T2, T3, T0, and T1. Since thread T2 is in an unschedulable state (indicated by the gray box in Figure 2), the schedulable threads are threads T3, T0, and T1. When threads T3 and T0 are successfully scheduled, the FIFO queue status is updated to T2, T1, T3, and T0. The subsequent thread scheduling process is similar and will not be further described here.

[0044] For a simultaneous multithreaded processor (hereinafter referred to as an SMT processor), when the schedulable shared resources meet the needs of all threads to be scheduled (for example, thread T0 and thread T1), the threads to be scheduled can be scheduled simultaneously; otherwise, there is a resource conflict between the threads to be scheduled, and shared resource arbitration is required to determine the target thread for scheduling.

[0045] For example, the resources shared by multiple threads in an SMT processor include, but are not limited to: cache (e.g., L1 data cache, L1 instruction cache, L2 cache, etc.), branch predictor storage space, out-of-order scheduler storage space for register renaming, data prefetcher storage space, etc.

[0046] The inventors of the present disclosure have noticed that, in existing SMT processors, for example, shared resource control for multiple threads (e.g., out-of-order scheduler storage space) is designed based on two threads at the same time. In a two-thread scenario, each thread only needs to ensure that it does not exhaust the shared resources when competing for shared resources to ensure that the other thread still has resources available, and will not cause the other thread to starve. However, for processors with more threads (e.g., four threads or more), if each thread only considers not exhausting the shared resources in the processor pipeline, then since each thread is unaware of the resource usage of the other three threads, it is very likely that the three threads will exhaust the shared resources together, resulting in the remaining thread having no resources available, causing errors (bugs) or hanging.

[0047] At least one embodiment of the present disclosure provides a thread scheduling method and apparatus, a processor, and a computer-readable storage medium.

[0048] The thread scheduling method includes: obtaining multiple threads to be scheduled for object resources in a processor, and obtaining the current occupied quantities and reserved quantities of the object resources by the multiple threads respectively; based on the current occupied quantities and reserved quantities of the object resources by the multiple threads respectively, selecting a target thread that meets the scheduling conditions from the multiple threads for scheduling.

[0049] The thread scheduling device includes an acquisition module and a scheduling module; the acquisition module is configured to acquire multiple threads to be scheduled for object resources in the processor, and to acquire the current occupied quantity and reserved quantity of the object resources by the multiple threads; the scheduling module is configured to select a target thread that meets the scheduling conditions from the multiple threads for scheduling based on the current occupied quantity and reserved quantity of the object resources by the multiple threads.

[0050] In at least one embodiment of the present disclosure, for example, in a simultaneous four-thread (SMT4) processor, for a shared resource ("object resource") of a scheduling object, each thread selected to use the shared resource, when determining how much resource it can consume, not only considers the total remaining amount of the object resource, but also the amount of resources that need to be reserved for the other three threads. Thread scheduling is only considered when sufficient resources are reserved for other threads and there are still remaining shared resources available; otherwise, waiting is required. For another example, before scheduling each thread, it is first checked whether the object resource is reserved for the thread and the amount of resources reserved.

[0051] The thread scheduling method and apparatus of the above-mentioned embodiments of the present disclosure, while ensuring fairness among multiple threads in a processor, will not starve a thread, thereby improving the overall design robustness of the processor.

[0052] The disclosed thread scheduling method and apparatus are described below in a non-limiting manner in conjunction with one or more specific embodiments.

[0053] FIG4 shows a flow chart of a thread scheduling method provided by at least one embodiment of the present disclosure. The thread scheduling method includes steps S410 to S420 .

[0054] Step S410: obtaining multiple threads to be scheduled for object resources in the processor, and obtaining the current occupied and reserved quantities of the object resources by the multiple threads respectively;

[0055] Step S420: Based on the current occupation quantity and reserved quantity of the object resource by the multiple threads, a target thread meeting the scheduling condition is selected from the multiple threads for scheduling.

[0056] For example, if the processor is an SMT processor (such as SMT4, SMT8, etc.), multiple instructions belonging to multiple threads are running in the pipeline of the processor. For the scheduling of resources ("object resources") shared by multiple threads in a certain pipeline level, it is necessary to consider the current occupation and reserved quantities of the object resources by multiple threads, and then select the target thread that meets the scheduling conditions from the multiple threads based on the occupation and reserved quantities for scheduling.

[0057] Here, for the object resources of a certain pipeline level, "occupied quantity" is used to refer to the number of object resources occupied by a certain thread in the current operation cycle and not yet released by the thread; "reserved quantity" is used to refer to the number of object resources reserved and free (therefore available for allocation) by a certain thread for the current operation cycle.

[0058] For example, in at least one example, the thread scheduling method of an embodiment of the present disclosure, before obtaining the current occupied quantity and reserved quantity of object resources by multiple threads respectively, further includes: determining the reserved quantity of object resources for each of the multiple threads.

[0059] For example, in at least one example, determining the reserved quantity for object resources for each thread among multiple threads includes: for a current thread among the multiple threads, determining whether the current thread is active; in response to the current thread being inactive, not reserving for the current thread, or, in response to the current thread being active, determining the reserved quantity for object resources for the current thread based on the quantity of object resources occupied by the current thread.

[0060] For example, taking an SMT4 processor and an out-of-order scheduler storage space as an example, the four threads being processed are threads T0 to T3. Before scheduling in the current operation cycle, the reserved quantity of object resources is determined for each of threads T0 to T3. For example, the reservation rules are as follows:

[0061] If a thread is inactive, no resources are reserved for it.

[0062] If a thread is active and has occupied 0 resources in the out-of-order scheduler storage space, 2 storage resources are reserved for the thread;

[0063] If a thread is active and the number of resources already occupied in the out-of-order scheduler storage space is 1, then 1 storage resource is reserved for the thread;

[0064] ●If a thread is active and has occupied at least 2 resources in the out-of-order scheduler storage space, there is no need to reserve storage resources for the thread.

[0065] The reservation rule may be fixed during the operation of the processor, or may be changed according to circumstances during the operation of the processor. For example, a register may be used to store the reservation rule, and the reservation rule may also be modified and adjusted accordingly.

[0066] In an example, assuming that the total amount of resources in the out-of-order scheduler storage space is 10 (e.g., 10 storage entries), the number of resources occupied and reserved by threads T0 to T3 in the out-of-order scheduler storage space before the current operation is as follows:

[0067] Thread T0: 0 occupied; 2 reserved;

[0068] Thread T1: 1 occupied; 1 reserved;

[0069] Thread T2: 3 occupied; 0 reserved;

[0070] Thread T3: 0 occupied; 2 reserved;

[0071] At this time, in the out-of-order scheduler storage space, the number of occupied resources is 4, the number of reserved resources is 5, and the number of unoccupied and non-reserved resources is 1.

[0072] For example, in at least one example, the scheduling condition includes: the target thread is currently active, and the object resource has a first quantity available for allocation excluding a quantity reserved for other active threads other than the target thread.

[0073] Here, "active" is used to refer to a thread that has not been suspended, paused, or terminated by the system, and the corresponding instruction pipeline is in a state of continuous execution, and is therefore also in a schedulable state.

[0074] For example, when performing thread scheduling in the current operation cycle, the first condition is to select an alternative thread from the active threads, that is, inactive threads will be excluded from the alternative threads; secondly, the current object resources must have free resources available for allocation after deducting the number reserved for other active threads except the target thread. The free resources available for allocation include the resources reserved for the target thread and any non-reserved free resources. Conversely, for a certain thread, if the resources reserved for the thread and any non-reserved free resources are both 0, the thread will not be selected as an alternative thread.

[0075] Assume in the above example that in the current operation cycle, threads T0-T3 are all active except thread T2, meaning only thread T2 is inactive. Therefore, threads T0, T1, and T3 may all be selected for scheduling. Furthermore, assume that threads T0-T3 all require 3 resources in the current cycle. Therefore, if threads T0, T1, and T3 are all scheduled, at least 1 idle resource will be available. In this case, threads T0, T1, and T3 can all be considered candidate threads.

[0076] For example, in at least one example, selecting a target thread that meets the scheduling condition from multiple threads for scheduling includes: performing arbitration based on a selection algorithm to select the target thread from one or more candidate threads that meet the scheduling condition.

[0077] On the other hand, the relationship between threads and their operation history also need to be considered, for example, to achieve fair scheduling among multiple threads. Thus, arbitration can be performed based on a selection algorithm to select a target thread from one or more candidate threads that meet the scheduling conditions.

[0078] For example, in at least one example, the selection algorithm includes a least recently used algorithm (LRU), a least recently used algorithm (LFU), or a round robin algorithm (RH).

[0079] For example, for the case where the above threads T0, T1 and T3 are all candidate threads, it is assumed that the number of times they were scheduled in the previous period of time from most to least are: T3, T0 and T1. Therefore, in the example of using the LRU algorithm, the thread T1 that was scheduled the least before will be selected from threads T0, T1 and T3 as the target thread for scheduling.

[0080] For example, in at least one example, a target thread that meets the scheduling conditions is selected from multiple threads for scheduling, including: obtaining a target instruction to be sent by the target thread and a second number of target instructions, and obtaining a first number of object resources available for allocation after deducting the number reserved for other active threads other than the target thread, wherein the first number is greater than 0; in response to the second number being less than or equal to the first number, all of the target instructions are sent to use the object resources for instruction processing, or, in response to the second number being greater than the first number, part of the first number of target instructions is sent to use the object resources for instruction processing.

[0081] In the above example of selecting thread T1 as the target thread for scheduling, the number of resources required by thread T1 is 3 (for example, 3 instructions require register renaming operations), the number of resources reserved for thread T1 is 1, and the number of non-reserved and idle resources is 1, that is, the number of resources currently required by thread T1 (3) is greater than the number of resources available to thread T1 (2), then 2 of the 3 instructions that require register renaming operations of thread T1 can be selected to be sent to the out-of-order scheduler storage space for register renaming operations, and the remaining 1 is left for consideration in the next operation cycle.

[0082] For example, in at least one example, the number of the multiple threads is greater than or equal to 4, for example, it can be 4, 6, 8, etc., that is, the corresponding processor is SMT4, SMT6, SMT8, etc.

[0083] For example, in at least one example, the object resources include a cache, a branch predictor storage space, an out-of-order scheduler storage space, a data prefetcher storage space, and the like.

[0084] FIG5 shows a schematic structural diagram of a thread scheduling device provided by at least one embodiment of the present disclosure.

[0085] As shown in Figure 5, the thread scheduling device 500 includes an acquisition module 510 and a scheduling module 520. The acquisition module 510 is configured to acquire multiple threads to be scheduled for an object resource in a processor, and to acquire the current occupied and reserved quantities of the object resource by the multiple threads; the scheduling module 520 is configured to select a target thread that meets the scheduling conditions from the multiple threads for scheduling based on the current occupied and reserved quantities of the object resource by the multiple threads.

[0086] For example, in at least one embodiment, the scheduling condition includes that the target thread is currently active, and the object resource has a first quantity available for allocation excluding a quantity reserved for other active threads other than the target thread.

[0087] For example, in at least one embodiment, the scheduling module includes a thread selection module configured to perform arbitration based on a selection algorithm to select a target thread from one or more candidate threads that meet all scheduling conditions.

[0088] For example, in at least one embodiment, the selection algorithm includes a least recently used algorithm (LRU), a least recently used algorithm (LFU), or a round robin algorithm (RH).

[0089] For example, in at least one embodiment, the scheduling module also includes an instruction selection module, which is configured to: obtain the target instructions to be sent by the target thread and a second number of target instructions, and obtain a first number of object resources available for allocation after excluding the number reserved for other active threads other than the target thread, wherein the first number is greater than 0; and in response to the second number being less than or equal to the first number, send all of the target instructions to use the object resources for instruction processing, or, in response to the second number being greater than the first number, send part of the first number of target instructions to use the object resources for instruction processing.

[0090] As shown in FIG. 5 , for example, in at least one embodiment, the thread scheduling apparatus further includes a resource reservation module 530 , and the resource reservation module 530 is configured to determine a reserved quantity for an object resource for each of the multiple threads.

[0091] For example, in at least one embodiment, the resource reservation module 530 is further configured to include: determining, for a current thread among multiple threads, whether the current thread is active; in response to the current thread being inactive, not reserving for the current thread, or, in response to the current thread being active, determining the number of object resources reserved for the current thread based on the number of object resources occupied by the current thread.

[0092] For example, in at least one embodiment, the number of the plurality of threads is greater than or equal to 4, such as 4, 6, 8, and the like.

[0093] For example, in at least one embodiment, the object resources may include cache, branch predictor storage space, out-of-order scheduler storage space, data prefetcher storage space, etc., and the embodiments of the present disclosure do not limit this.

[0094] FIG6 shows a schematic structural diagram of another thread scheduling device provided by at least one embodiment of the present disclosure.

[0095] The thread scheduling device 600 is used for an out-of-order scheduler in an SMT4 processor, for example, and includes an acquisition module 610 , a scheduling module 620 , four resource reservation modules 630 and an out-of-order scheduler storage space 640 , and the scheduling module 620 includes a thread selection module 621 and an instruction selection module 622 .

[0096] The acquisition module 610 is configured to acquire the four threads T0 to T3 to be scheduled for the out-of-order scheduler storage space 640 in the processor, and to acquire the current occupied quantity and reserved quantity of the out-of-order scheduler storage space 640 by the four threads T0 to T3; the scheduling module 620 is configured to select a target thread that meets the scheduling conditions from the four threads T0 to T3 for scheduling based on the current occupied quantity and reserved quantity of the out-of-order scheduler storage space 640 by the four threads T0 to T3.

[0097] As shown in Figure 6, the four resource reservation modules 630 are respectively configured to determine the reserved amount of out-of-order scheduler storage space 640 for each of the four threads T0 to T3. Here, the number of resource reservation modules 630 corresponds one-to-one to the number of threads, and each resource reservation module 630 is used for one of the threads, but the embodiments of the present disclosure do not limit this.

[0098] The thread selection module 621 is configured to arbitrate based on a selection algorithm to select a target thread from one or more alternative threads that meet all scheduling conditions. In this embodiment, the selection algorithm adopted is the RLU algorithm; the instruction selection module 622 is configured to: obtain the target instruction to be sent by the target thread and the second number of target instructions, and obtain the first number of out-of-order scheduler storage space 640 that can be used for allocation after removing the number reserved for other active threads other than the target thread, wherein the first number is greater than 0; and in response to the second number being less than or equal to the first number, send all the target instructions to use the object resources for instruction processing, or, in response to the second number being greater than the first number, send part of the first number of target instructions to use the object resources for instruction processing.

[0099] FIG7 shows a schematic structural diagram of another thread scheduling device provided by at least one embodiment of the present disclosure.

[0100] As shown in Figure 7, the thread scheduling device 700 includes a processing unit 720 and a memory 710. The memory 710 stores computer-readable instructions and is in communication with the processing unit 720. The processing unit 720 executes the computer-readable instructions stored in the memory 710 to implement the thread scheduling method provided in any embodiment of the present disclosure.

[0101] For example, the memory 710 and the processing unit 720 can communicate with each other directly or indirectly. For example, in some examples, as shown in FIG7 , the thread scheduling device 700 may further include a system bus 730, and the memory 710 and the processing unit 720 may communicate with each other via the system bus 730. For example, the processing unit 720 may access the memory 710 via the system bus 730. For example, in other examples, components such as the memory 710 and the processing unit 720 may communicate via a network on chip (NOC) connection.

[0102] For example, the processing unit 720 can control other components in the thread scheduling device to perform the desired functions. The processing unit 720 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU). It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0103] For example, the memory 710 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc.

[0104] For example, the memory 710 may store one or more computer-readable instructions, and the processing unit 720 may execute the computer-readable instructions to implement various functions. The computer-readable storage medium may also store various applications and various data, such as instruction processing code and various data used and / or generated by the application.

[0105] For example, when some computer instructions stored in the memory 710 are executed by the processing unit 720 , one or more steps in the thread scheduling method described above may be performed.

[0106] For example, as shown in FIG7 , the thread scheduling apparatus 700 may further include an input interface 740 that allows external devices to communicate with the thread scheduling apparatus 700. For example, the input interface 740 may be used to receive instructions from an external computer device, from a user, etc. The thread scheduling apparatus 700 may further include an output interface 750 that interconnects the thread scheduling apparatus 700 and one or more external devices. For example, the thread scheduling apparatus 700 may output commands to the user through the output interface 750.

[0107] It should be noted that the thread scheduling device provided in the embodiments of the present disclosure is exemplary rather than restrictive. According to actual application requirements, the thread scheduling device may also include other conventional components or structures. For example, in order to realize the necessary functions of the thread scheduling device, those skilled in the art may set other conventional components or structures according to the specific application scenarios, and the embodiments of the present disclosure do not limit this.

[0108] At least one embodiment of the present disclosure further provides a processor, such as an SMT processor, which includes the thread scheduling device provided in any embodiment of the present disclosure. The SMT processor can support a maximum number of threads of, for example, 2, 4, 8, etc., and can be a single-core or multi-core processor. For example, the processor core can adopt a microarchitecture such as X86, ARM, or RISC-V, and can include one or more levels of cache, although the embodiments of the present disclosure are not limited thereto.

[0109] At least one embodiment of the present disclosure further provides a computer-readable storage medium. FIG8 is a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.

[0110] For example, as shown in FIG8 , the computer-readable storage medium 800 stores computer-readable instructions 810 . When the computer-readable instructions 810 are executed by a computer (including a processor), the thread scheduling method provided by any embodiment of the present disclosure can be implemented.

[0111] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 800. Some of the computer-readable instructions stored on the computer-readable storage medium 800 may be, for example, instructions for implementing one or more steps in the above-mentioned thread scheduling method.

[0112] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a flash memory, or any combination thereof, or other suitable storage media. For example, the computer-readable storage medium 800 may include the memory 710 in the thread scheduling device 700.

[0113] At least some embodiments of the present disclosure further provide an electronic device, the electronic device comprising the processor of any of the above embodiments. Figure 9 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0114] The electronic devices in the embodiments of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0115] The electronic device 900 shown in FIG9 is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0116] For example, as shown in Figure 9, in some examples, the electronic device 900 includes a processor 901, which may include the processor of any of the above-mentioned embodiments, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 902 or the program loaded from the storage device 908 into the random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the computer system are also stored. The processor 901, ROM 902 and RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0117] For example, the following components may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 908 including, for example, a magnetic tape, hard disk, etc.; and a communication device 909, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 910 as needed, so that computer programs read therefrom can be installed into the storage device 908 as needed. Although FIG. 9 shows the electronic device 900 including various devices, it should be understood that implementation or inclusion of all of the devices shown is not required. More or fewer devices may alternatively be implemented or included.

[0118] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 909 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0119] In addition to the above exemplary descriptions, the following points need to be explained:

[0120] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0121] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0122] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A thread scheduling method, comprising: Acquire multiple threads to be scheduled for object resources in the processor, and acquire the current occupied quantity and reserved quantity of the object resources by the multiple threads respectively; as well as Based on the current occupation quantity and reserved quantity of the object resource by the multiple threads respectively, a target thread meeting the scheduling condition is selected from the multiple threads for scheduling.

2. The thread scheduling method according to claim 1, wherein: The scheduling condition includes: the target thread is currently active, and the object resource has a first quantity for allocation after deducting a quantity reserved for other active threads except the target thread.

3. The thread scheduling method according to claim 1, wherein: The selecting a target thread that meets the scheduling conditions from the multiple threads for scheduling includes: Arbitration is performed based on a selection algorithm to select the target thread from one or more candidate threads that meet the scheduling condition.

4. The thread scheduling method according to claim 3, wherein: The selection algorithm includes: the least recently used algorithm (LRU), the least recently used algorithm (LFU) or the round robin algorithm (RH).

5. The thread scheduling method according to claim 1, wherein: The selecting a target thread that meets the scheduling condition from the multiple threads for scheduling includes: Obtaining a target instruction to be sent by the target thread and a second number of the target instructions, and obtaining a first number of the object resource available for allocation after deducting a number reserved for other active threads except the target thread, wherein the first number is greater than 0; and In response to the second number being less than or equal to the first number, all of the target instructions are sent to use the object resources for instruction processing, or, in response to the second number being greater than the first number, part of the first number of instructions in the target instructions are sent to use the object resources for instruction processing.

6. The thread scheduling method according to claims 1 to 5, before obtaining the current occupied and reserved quantities of the object resources by the multiple threads, the thread scheduling method further comprises: A reserved quantity for the object resource is determined for each of the plurality of threads.

7. The thread scheduling method according to claim 6, wherein: The determining, for each of the plurality of threads, a reserved quantity of the object resource, includes: For a current thread among the plurality of threads, determining whether the current thread is active; and In response to the current thread being inactive, no resource is reserved for the current thread; or, in response to the current thread being active, the reserved quantity of the object resource by the current thread is determined based on the quantity of the object resource occupied by the current thread.

8. The thread scheduling method according to claim 1, wherein: The number of the multiple threads is greater than or equal to 4.

9. The thread scheduling method according to claim 1, wherein: The object resources include cache, branch predictor storage space, out-of-order scheduler storage space, and data prefetcher storage space.

10. A thread scheduling device, comprising: An acquisition module is configured to acquire a plurality of threads to be scheduled for an object resource in a processor, and to acquire the current occupied quantity and reserved quantity of the object resource by the plurality of threads respectively; as well as The scheduling module is configured to select a target thread that meets the scheduling condition from the multiple threads for scheduling based on the current occupation quantity and reserved quantity of the object resource by the multiple threads respectively.

11. The thread scheduling device according to claim 10, wherein: The scheduling module includes: The thread selection module is configured to perform arbitration based on a selection algorithm to select the target thread from one or more candidate threads that meet the scheduling condition.

12. The thread scheduling device according to claim 11, wherein: The scheduling module also includes: Instruction selection module, configured as: Obtaining a target instruction to be sent by the target thread and a second number of the target instructions, and obtaining a first number of the object resource available for allocation after deducting a number reserved for other active threads except the target thread, wherein the first number is greater than 0; and In response to the second number being less than or equal to the first number, all of the target instructions are sent to use the object resources for instruction processing, or, in response to the second number being greater than the first number, part of the first number of instructions in the target instructions are sent to use the object resources for instruction processing.

13. The thread scheduling device according to claim 10, further comprising: The resource reservation module is configured to determine a reserved quantity for the object resource for each thread in the plurality of threads.

14. A thread scheduling device, comprising at least one processing unit and a memory; wherein, The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; The at least one processing unit executes the computer-readable instructions stored in the memory to implement the thread scheduling method according to any one of claims 1 to 9.

15. A processor comprising the thread scheduling device according to any one of claims 10 to 14.

16. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the thread scheduling method according to any one of claims 1 to 9 is implemented.

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