Packaging structure, electronic device, and method for preparing packaging structure

Abstract

The embodiments of the present application relate to the technical field of electronic devices. Provided are a packaging structure, an electronic device, and a method for preparing a packaging structure. The packaging structure comprises a first chip, a first wiring layer, a second wiring layer, a first packaging layer, a first connecting portion, and a second chip, wherein the first wiring layer is arranged on the side of a first surface of the first chip and is electrically connected to the first chip; the second wiring layer is arranged on a second surface of the first chip and is in contact with the second surface; the first packaging layer is arranged around the first chip; the first connecting portion is embedded into the first packaging layer; one end of the first connecting portion is electrically connected to the first wiring layer, and the other end thereof is electrically connected to the second wiring layer; the end face of the first connecting portion that is away from the first wiring layer is closer to the first wiring layer relative to the surface of the first packaging layer that is away from the first wiring layer; and the second chip is arranged on the side of the second wiring layer that is away from the first chip, and is electrically connected to the second wiring layer. The packaging structure has a good electrical performance and a good heat dissipation effect.

Description

Packaging structure, electronic device, and method for preparing packaging structure

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 18, 2024, with application number 202410310585.0 and application name “Packaging structure, electronic device and method for preparing packaging structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of electronic equipment, and in particular to a packaging structure, an electronic device, and a method for preparing the packaging structure. Background Art

[0003] With the rapid development of wireless communications, automotive electronics, and other consumer electronics, electronic devices are becoming increasingly multifunctional. In the prior art, when manufacturing these electronic devices, chips with different functions are typically packaged separately, then integrated, and the integrated components are placed within the electronic device.

[0004] The currently used packaging and integration technology is Package on Package (POP) technology. Specifically, another matching top-level packaging structure is stacked on a lower-level packaging structure to form the above-mentioned POP packaging structure. The lower-level packaging structure can encapsulate a highly integrated logic chip, and the top-level packaging structure can encapsulate a large-capacity memory chip. Because the connection path between the logic chip and the memory chip in the POP packaging structure is short, the electrical performance is better, and the POP packaging structure occupies less space on the printed circuit board (PCB), the above-mentioned POP packaging structure has been widely used in portable electronic devices such as smartphones.

[0005] However, with the gradual increase in the functions of electronic devices and the gradual improvement in integration and sophistication, the heat dissipation capacity of the POP packaging structure has been greatly challenged. How to achieve better heat dissipation without affecting the electrical performance of the POP packaging structure has become one of the technical problems that need to be solved at present. Summary of the Invention

[0006] The embodiments of the present application provide a packaging structure, an electronic device, and a method for preparing the packaging structure, the purpose of which is to improve the heat dissipation capability of the packaging structure while avoiding performance degradation of the chip in the packaging structure.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a packaging structure is provided. The packaging structure includes a first chip, a first wiring layer, a second wiring layer, a first packaging layer, a first connecting portion, and a second chip.

[0009] The first chip includes a first surface and a second surface arranged opposite to each other. The first wiring layer is arranged on the side where the first surface of the first chip is located, and is electrically connected to the first chip. The second wiring layer is arranged on the second surface of the first chip, and is in contact with the second surface. The first packaging layer is arranged between the first wiring layer and the second wiring layer, and is arranged around at least part of the first chip. The first connecting portion is embedded in the first packaging layer and is spaced apart from the first chip; one end of the first connecting portion is electrically connected to the first wiring layer, and the other end is electrically connected to the second wiring layer; the end face of the first connecting portion away from the first wiring layer is closer to the first wiring layer than the surface of the first packaging layer away from the first wiring layer. The second chip is arranged on the side of the second wiring layer away from the first chip, and is electrically connected to the second wiring layer.

[0010] In the package structure provided in the embodiment of the present application, by setting the second surface of the first chip in contact with the second wiring layer, that is, removing the portion of the first package layer surrounding the first surface of the first chip, the heat dissipation path of the first chip is shortened, the thermal resistance of the package structure is reduced, the heat dissipation capacity of the package structure is effectively improved, and the overall thickness of the package structure is reduced, which is conducive to achieving a miniaturized design of the package structure. At the same time, in the embodiment of the present application, the end surface of the first connection portion away from the first wiring layer is set closer to the first wiring layer than the surface of the first package layer away from the first wiring layer, so that the first connection portion is retracted within the first package layer, thereby avoiding the problem that the first connection portion is exposed from the first package layer, causing the conductive particles or conductive ions (easily formed in the grinding process, etc.) to diffuse to the exposed second surface of the first chip, thereby causing the performance degradation or even failure of the first chip. That is, the package structure provided in the embodiment of the present application can improve the heat dissipation capacity and reduce the overall thickness while taking into account its electrical performance.

[0011] In a possible implementation of the first aspect, the second wiring layer includes a second dielectric layer and at least one second routing layer embedded in the second dielectric layer; the second dielectric layer contacts the second surface of the first chip. Thus, the exposed second surface of the first chip is covered by the electrically insulating second dielectric layer, thereby preventing unintended electrical connection of the first chip through the exposed second surface. The second dielectric layer also protects the second surface of the first chip from damage such as external corrosion.

[0012] In a possible implementation of the first aspect, the first packaging layer includes a first opening located on an end face of the first connection portion remote from the first wiring layer. The packaging structure further includes a contact member, one end of the contact member being electrically connected to the second wiring layer, and the other end of the contact member passing through the first opening and electrically connected to the first connection portion. The design of the contact member enables connection between the first connection portion and the second wiring layer without affecting the electrical performance of the first chip.

[0013] In a possible implementation of the first aspect, the second wiring layer includes a second dielectric layer and at least one second wiring layer embedded in the second dielectric layer; the at least one second wiring layer is integrally provided with the contact element. For example, the contact element can be prepared simultaneously with the second wiring layer, thereby improving preparation efficiency.

[0014] In a possible implementation of the first aspect, the contact member is filled in the first opening, thereby enhancing the stability of the electrical connection between the contact member and the first connecting portion; or, the contact member is arranged on the inner wall of the first opening, and the contact member deposited on the inner wall of the first opening has a smaller resistance value, thereby reducing the power consumption of the packaging structure and improving the electrical performance.

[0015] In a possible implementation of the first aspect, at least a portion of the second dielectric layer is filled in the first opening, and the contact member passes through the portion of the second dielectric layer located in the first opening and is electrically connected to the first connecting portion.

[0016] In this embodiment, by first forming the second dielectric layer and then forming the conductive contact, the exposed second surface of the first chip can be protected by the second dielectric layer before the conductive contact is formed, thereby preventing conductive particles generated during the formation of the contact from damaging the exposed second surface of the first chip, thereby improving the reliability of the first chip and making the packaging structure have better electrical performance.

[0017] In a possible implementation of the first aspect, the first encapsulation layer includes a first sub-section and a second sub-section, the first sub-section being disposed between the first chip and the first wiring layer, and the second sub-section surrounding a side surface of the first chip. The first connecting portion is embedded in the second sub-section, and at least a portion of the second sub-section is disposed between the side surface of the first chip and the first connecting portion.

[0018] The first sub-portion can prevent unexpected electrical connection between the first chip and the first wiring layer, and the second sub-portion can protect the first chip from external damage.

[0019] In a possible implementation of the first aspect, the packaging structure also includes a plurality of second connection parts, which are arranged between the first chip and the first wiring layer, and all pass through the first sub-part, and two adjacent second connection parts are arranged at intervals. The first chip and the first wiring layer are electrically connected through the plurality of second connection parts, thereby realizing independent transmission of electrical signals of multiple pins on the first chip.

[0020] In a possible implementation of the first aspect, the packaging structure also includes a plurality of third connection parts, which are arranged between the second wiring layer and the second chip, and two adjacent third connection parts are arranged at intervals. The second wiring layer and the second chip are electrically connected through the plurality of third connection parts, thereby realizing independent transmission of electrical signals of multiple pins on the second chip.

[0021] In a possible implementation of the first aspect, the package structure further includes a second package layer disposed around the second chip, and the third connection portion extends through a portion of the second package layer located between the second wiring layer and the second chip. The second package layer can protect the second chip from external damage and prevent unintended electrical connection between the second chip and external electrical devices.

[0022] In a second aspect, an electronic device is provided, comprising a circuit board and the packaging structure provided by any one of the embodiments of the first aspect, wherein the circuit board is electrically connected to the packaging structure.

[0023] In a third aspect, a method for preparing a packaging structure is provided, the method comprising:

[0024] A first wiring layer is formed, and a first connection portion is formed on the first wiring layer. A first chip and a first packaging layer are formed on the first wiring layer; the first chip includes a first surface and a second surface; the first surface of the first chip is electrically connected to the first wiring layer; the first packaging layer is disposed around at least a portion of the first chip; the first connection portion is embedded in the first packaging layer and spaced apart from the first chip; one end of the first connection portion is electrically connected to the first wiring layer; the end surface of the first connection portion away from the first wiring layer is closer to the first wiring layer than the surface of the first packaging layer away from the first wiring layer. A second wiring layer is formed on a side of the first chip and the first packaging layer away from the first wiring layer; the second wiring layer contacts the second surface of the first chip; the other end of the first connection portion is electrically connected to the second wiring layer. A second chip is formed on a side of the second wiring layer away from the first chip; the second chip is electrically connected to the second wiring layer.

[0025] The technical effects brought about by the electronic device in the second aspect and the preparation method in the third aspect can be referred to the technical effects brought about by the design of the packaging structure in the first aspect, and will not be repeated here.

[0026] In a possible implementation of the third aspect, the second wiring layer includes a second dielectric layer and at least one second routing layer embedded in the second dielectric layer. Forming the second wiring layer includes:

[0027] At least a portion of a second dielectric layer is formed on a side of the first chip and the first packaging layer that is away from the first wiring layer. At least one layer of second routing is formed on a side of at least a portion of the second dielectric layer that is away from the first chip and the first packaging layer; a portion of the second dielectric layer is provided between two adjacent layers of second routing.

[0028] The second dielectric layer contacts the second surface of the first chip, and the second dielectric layer can protect the second surface of the first chip, preventing the exposed second surface from being damaged or causing unexpected electrical connection.

[0029] In a possible implementation of the third aspect, the method further includes: providing a first opening in the first packaging layer; the first opening exposing an end surface of the first connecting portion remote from the first wiring layer; forming a contact within the first opening; and having one end of the contact extending through the first opening and electrically connecting to the end surface of the first connecting portion remote from the first wiring layer.

[0030] By preparing the contact, electrical connection between the first connection portion and the second wiring layer can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0032] FIG2 is a cross-sectional view of a packaging structure provided in an embodiment of the present application;

[0033] FIG3 is an enlarged view of a structure corresponding to the dotted box A in FIG2 ;

[0034] FIG4 is an enlarged view of another structure corresponding to the dotted box A in FIG2 ;

[0035] FIG5 is an enlarged view of another structure corresponding to the dotted box A in FIG2 ;

[0036] FIG6 is another cross-sectional view of the packaging structure provided in an embodiment of the present application;

[0037] FIG7 is a flow chart of preparing a packaging structure provided in an embodiment of the present application;

[0038] 8 to 18 are cross-sectional views corresponding to various steps of preparing the packaging structure. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0040] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0043] Connection / connected: can refer to a mechanical connection relationship or a physical connection relationship, that is, A and B are connected or A and B are connected, which can mean that there is a fastening component (such as a screw, bolt, rivet, etc.) between A and B, or A and B are in contact with each other and A and B are difficult to separate, wherein A and B can be fixedly connected, detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium.

[0044] Coupling: can be understood as direct coupling and / or indirect coupling, and "coupling connection" can be understood as direct coupling connection and / or indirect coupling connection. Direct coupling can also be called "electrical connection", which is understood as the direct or indirect physical contact and electrical conduction between components, such as the connection between different components in the circuit structure through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals; "indirect coupling" can be understood as two conductors being electrically conductive in an airless / non-contact manner. In one embodiment, indirect coupling can also be called capacitive coupling, for example, signal transmission is achieved by forming an equivalent capacitance through coupling between the gap between two conductive parts.

[0045] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0048] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] In addition, the scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art will know that with the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0050] The embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk maker, a robot vacuum), an unmanned aerial vehicle (UAV), a radar, an aerospace equipment, an on-board device, a vehicle, or other different types of user devices or terminal devices; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0051] FIG1 is a schematic diagram of the structure of an electronic device exemplarily provided in an embodiment of the present application. As shown in FIG1 , the electronic device 1000 may include a circuit board 200 .

[0052] Exemplarily, the circuit board 200 may be a printed circuit board (PCB), a flexible circuit board, or a rigid-flex circuit board.

[0053] It will be understood that the structure of the electronic device 1000 shown in FIG1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1 , or may combine some of the components shown in FIG1 , or may have a different arrangement of components than that shown in FIG1 .

[0054] For example, as shown in FIG. 1 , the electronic device 1000 may further include an integrated circuit 100 , and the integrated circuit 100 may be disposed on a circuit board 200 .

[0055] For example, as shown in FIG1 , the integrated circuit 100 may include a logic circuit 101 , an analog circuit 102 , a storage circuit 103 , an input / output circuit 104 , and the like.

[0056] It should be understood that the integrated circuit 100 includes but is not limited to a logic circuit 101, an analog circuit 102, a storage circuit 103 and an input / output circuit 104. For example, in addition to the aforementioned four circuits, the integrated circuit 100 may also include circuits of other types or functions, or discrete devices.

[0057] Furthermore, the integrated circuit 100 may include one or more of a logic circuit 101 , an analog circuit 102 , a memory circuit 103 , and an input-output circuit 104 .

[0058] Based on this, the number of logic circuits 101, analog circuits 102, memory circuits 103, and input / output circuits 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 may include one or more logic circuits 101. The integrated circuit 100 may also include one or more analog circuits 102. The integrated circuit 100 may also include one or more memory circuits 103. The integrated circuit 100 may also include one or more input / output circuits 104.

[0059] As shown in FIG. 1 , the electronic device 1000 may further include a packaging structure 300 , which is electrically connected to the circuit board 200 .

[0060] For example, referring to Figure 1, the packaging structure 300 can be integrated into the aforementioned integrated circuit 100. For example, the packaging structure 300 can be integrated into the logic circuit 101 and the storage circuit 103 at the same time, or can also be integrated into one or more other circuits. The embodiment of the present application does not limit the integration position of the packaging structure 300.

[0061] Alternatively, by way of example, the packaging structure 300 may also be directly disposed on the circuit board 200 .

[0062] The embodiment of the present application also provides a packaging structure 300 .

[0063] FIG2 is a cross-sectional view of a packaging structure 300 provided in an embodiment of the present application.

[0064] In some embodiments, as shown in FIG. 2 , the package structure 300 may include a first chip 11 , a first wiring layer 21 , a second wiring layer 22 , a first package layer 31 , a first connection portion 41 , and a second chip 12 .

[0065] The first chip 11 and the second chip 12 may have different functions. For example, the first chip 11 may be a logic chip that can implement functions such as "AND", "OR", and "NOT". For example, the second chip 12 may be a memory chip that can implement data storage.

[0066] 2 , the first chip 11 includes a first surface 1 a and a second surface 1 b opposite to each other.

[0067] The first surface 1a can serve as the front surface of the first chip 11. A signal interface can be provided on the first surface 1a to achieve electrical connection between the first chip 11 and other electrical devices, thereby facilitating the input and output of electrical signals in the first chip 11 and realizing the corresponding functions of the first chip 11. The second surface 1b can serve as the back surface of the first chip 11.

[0068] For example, referring to FIG. 2 , the lower surface of the first chip 11 may be the first surface 1 a , and the upper surface of the first chip 11 may be the second surface 1 b .

[0069] For example, the package structure 300 may include one or more first chips 11 . When the package structure 300 includes a plurality of first chips 11 , the plurality of first chips 11 may be spaced apart and arranged in a direction parallel to the first surface 1 a .

[0070] For example, the package structure 300 may also include one or more second chips 12. When the package structure 300 includes multiple second chips 12, the multiple second chips 12 may be arranged in a direction parallel to the first surface 1a, or may be stacked in a direction perpendicular to the first surface 1a. This application does not limit the number of first chips 11 and second chips 12.

[0071] Exemplarily, the first wiring layer 21 and the second wiring layer 22 may be substrates that can achieve electrical connectivity between the upper and lower surfaces of the board, such as a silicon adapter board or a redistribution layer (RDL) adapter board, which may also be called a redistribution layer RDL.

[0072] Exemplarily, referring to FIG. 2 , the first wiring layer 21 may include a first dielectric layer 211 and at least one layer of first traces 212 embedded in the first dielectric layer 211 .

[0073] Exemplarily, the first dielectric layer 211 includes multiple sublayers, which are alternately stacked with the first trace 212, so that the first trace 212 is embedded in the first dielectric layer 211, so that the first dielectric layer 211 protects the first trace 212 and prevents the first trace 212 from having unexpected electrical connections.

[0074] For example, the material of the first dielectric layer 211 may include an insulating resin material, for example, polyimide (PI).

[0075] Exemplarily, the material of the first trace 212 is a conductive material, such as copper.

[0076] For example, referring to FIG. 2 , first traces 212 on different layers may be interconnected after passing through the first dielectric layer 211 .

[0077] 2 , the second wiring layer 22 may include a second dielectric layer 221 and at least one second trace 222 embedded in the second dielectric layer 221. The material and structure of the second wiring layer 22 may refer to the aforementioned description of the first wiring layer 21 and will not be repeated here.

[0078] 2 , the first wiring layer 21 is disposed on a side of the first surface 1 a of the first chip 11 and is electrically connected to the first chip 11 .

[0079] 2 , the second wiring layer 22 is disposed on the second surface 1 b of the first chip 11 and is in contact with the second surface 1 b .

[0080] That is, the first chip 11 is sandwiched between the first wiring layer 21 and the second wiring layer 22 , and the signal interface on the front side (ie, the first surface 1 a ) of the first chip 11 is electrically connected to the first wiring layer 21 .

[0081] 2 , the first packaging layer 31 is disposed between the first wiring layer 21 and the second wiring layer 22 and surrounds at least a portion of the first chip 11 .

[0082] For example, referring to FIG2 , the first encapsulation layer 31 surrounds at least the first surface 1a of the first chip 11 and all side surfaces of the first chip 11 perpendicular to the first surface 1a. In other words, the first encapsulation layer 31 exposes the second surface 1b of the first chip 11, allowing direct contact between the second surface 1b and the second wiring layer 22. For example, referring to FIG2 , the top surface of the first encapsulation layer 31 is flush with the second surface 1b of the first chip 11.

[0083] The first packaging layer 31 is used to package the first chip 11 so as to protect the first chip 11 from external damage and prevent the first chip 11 from having unexpected electrical connections.

[0084] 2 , the first connection portion 41 is embedded in the first packaging layer 31 and spaced apart from the first chip 11 .

[0085] For example, referring to FIG. 2 , the first connection portion 41 may be provided in parallel on the left or right side of the first chip 11 , and the first connection portion 41 and the first chip 11 are insulated by a portion of the first packaging layer 31 .

[0086] 2 , one end of the first connection portion 41 is electrically connected to the first wiring layer 21 , and the other end is electrically connected to the second wiring layer 22 .

[0087] For example, referring to Figure 2, the lower end of the first connecting portion 41 is electrically connected to the exposed first trace 212 of the first wiring layer 21 close to the first chip 11, and the upper end of the first connecting portion 41 is electrically connected to the exposed second trace 222 of the second wiring layer 22 close to the first chip 11, thereby realizing communication between the first wiring layer 21 and the second wiring layer 22.

[0088] The first connecting portion 41 is conductive and is used to achieve electrical conduction between the structure disposed on the upper surface and the structure disposed on the lower surface of the first packaging layer 31 .

[0089] Exemplarily, the first connecting portion 41 may be a columnar structure, for example, a cylinder.

[0090] For example, the material of the first connection portion 41 may include at least one of metal copper, metal aluminum, metal silver, or solder.

[0091] For example, the first connection portion 41 may be formed by an electroplating process, or a solder column may be formed by reflow soldering, that is, the first connection portion 41 is formed.

[0092] It is understandable that the first connection portion 41 may also be other conductive structures that can achieve interconnection between structures provided on the upper and lower surfaces of the first packaging layer 31 , and the embodiment of the present application does not limit this.

[0093] 2 , the second chip 12 is disposed on a side of the second wiring layer 22 away from the first chip 11 and is electrically connected to the second wiring layer 22. For example, the second chip 12 is electrically connected to a second trace 222 in the second wiring layer 22 that is close to the second chip 12 ( FIG. 2 illustrates only one second trace 222 in the second wiring layer 22).

[0094] For example, referring to Figure 2, the second chip 12 can be electrically connected to the first connecting portion 41 through the second trace 222, and can be electrically connected to the first wiring layer 21 through the first connecting portion 41, so that it can be electrically connected to the first chip 11 through the first wiring layer 21, or can be electrically connected to an external device (such as a circuit board) through the first wiring layer 21.

[0095] 2 , the end surface of the first connection portion 41 away from the first wiring layer 21 is closer to the first wiring layer 21 than the surface of the first packaging layer 31 away from the first wiring layer 21 .

[0096] That is, referring to FIG2 , the upper end surface of the first connection portion 41 is retracted within the first packaging layer 31 relative to the first chip 11. Referring to FIG2 , the second surface 1 b of the first chip 11 is flush with the surface of the first packaging layer 31 that is away from the first wiring layer 21. The upper end surface of the first connection portion 41 is closer to the first wiring layer 21 relative to the second surface 1 b of the first chip 11. That is, the end surface of the first connection portion 41 that is away from the first wiring layer 21 is lower than the second surface 1 b of the first chip 11.

[0097] In other embodiments, the first encapsulation layer 31 surrounds the first chip 11. That is, in addition to surrounding the first surface 1a and the side surfaces perpendicular to the first surface 1a of the first chip 11, the first encapsulation layer 31 also surrounds the second surface 1b of the first chip 11 to protect the first chip 11. However, the heat dissipation performance of the package structure 300 in this embodiment is poor, which affects the reliability of the package structure 300. In addition, the thickness is relatively thick, which is not conducive to the miniaturization design of the package structure 300.

[0098] In the package structure 300 provided in the embodiment of the present application, by setting the second surface 1b of the first chip 11 in contact with the second wiring layer 22, that is, by removing the portion of the first package layer 31 surrounding the first surface 1a of the first chip 11, the heat dissipation path of the first chip 11 is shortened, the thermal resistance of the package structure 300 is reduced, the heat dissipation capability of the package structure 300 is effectively improved, and the overall thickness of the package structure 300 is reduced, which is conducive to achieving a miniaturized design of the package structure 300. At the same time, in the embodiment of the present application, the end surface of the first connection portion 41 away from the first wiring layer 21 is arranged closer to the first wiring layer 21 than the surface of the first package layer 31 away from the first wiring layer 21, so that the first connection portion 41 is retracted within the first package layer 31, thereby preventing the first connection portion 41 from being exposed from the first package layer 31, which would cause the conductive particles or conductive ions (easily formed during processes such as grinding) to diffuse to the exposed second surface 1b of the first chip 11, thereby causing performance degradation or even failure of the first chip 11. That is, the packaging structure 300 provided in the embodiment of the present application can improve the heat dissipation capability and reduce the overall thickness while taking into account its electrical performance.

[0099] Furthermore, in the package structure 300 provided in the embodiment of the present application, by removing the portion of the first package layer 31 located on the second surface 1b of the first chip 11, a restriction on the thickness of the first chip 11 is avoided, thereby enhancing the package strength and heat distribution capability of the package structure 300. Furthermore, in the embodiment of the present application, the first connection portion 41 is retracted within the first package layer 31, meaning that the end face of the first connection portion 41 does not need to be higher than the second surface 1b of the first chip 11. This decouples the height of the first connection portion 41 from the thickness of the first chip 11, preventing the height of the first connection portion 41 from constraining the thickness of the first chip 11, thereby further enhancing the package strength and heat distribution capability of the package structure 300.

[0100] In some embodiments, referring to FIG. 2 , the second dielectric layer 221 of the second wiring layer 22 contacts the second surface 1 b of the first chip 11, so that the exposed second surface 1 b of the first chip 11 is covered by the electrically insulating second dielectric layer 221, thereby preventing the first chip 11 from making unexpected electrical connections through the exposed second surface 1 b. At the same time, the second dielectric layer 221 can also protect the second surface 1 b of the first chip 11 from damage such as external corrosion.

[0101] Figure 3 is an enlarged view of a structure corresponding to the dotted frame A in Figure 2. Figure 4 is an enlarged view of another structure corresponding to the dotted frame A in Figure 2. Figure 5 is an enlarged view of another structure corresponding to the dotted frame A in Figure 2.

[0102] In some embodiments, referring to Figures 3, 4 and 5, the first packaging layer 31 includes a first opening K1, which is located on the end surface of the first connection portion 41 away from the first wiring layer 21, thereby exposing the end surface of the first connection portion 41 away from the first wiring layer 21, facilitating external connection of the first connection portion 41.

[0103] 3 , 4 and 5 , the package structure 300 further includes a contact member 5 , one end of which is electrically connected to the second wiring layer 22 , and the other end of which passes through the first opening K1 and is electrically connected to the first connection portion 41 , thereby achieving electrical connection between the second wiring layer 22 and the first connection portion 41 .

[0104] Exemplarily, referring to FIG. 3 , FIG. 4 and FIG. 5 , one end of the contact member 5 is electrically connected to the second trace 222 in the second wiring layer 22 .

[0105] Exemplarily, referring to FIG. 4 and FIG. 5 , at least one layer of second traces 222 may be provided integrally with the contact element 5 .

[0106] For example, the second trace 222 and the contact member 5 may be made of the same material, or for example, the second trace 222 and the contact member 5 may be integrally formed.

[0107] For example, referring to Figures 3, 4 and 5, the contact member 5 can penetrate the portion of the first packaging layer 31 located above the first connection portion 41, and penetrate the portion of the second dielectric layer 221 located between the first connection portion 41 and the second trace 222, thereby being electrically connected to the first connection portion 41.

[0108] In some embodiments, referring to FIG3 , the contact member 5 may be filled in the first opening K1 , that is, the contact member 5 may completely fill the first opening K1 , thereby enhancing the stability of the electrical connection between the contact member 5 and the first connecting portion 41 .

[0109] For example, during the manufacturing process, after forming the first encapsulation layer 31, the first encapsulation layer 31 may be opened to form a first opening K1, and the first opening K1 may be filled with a conductive material to form the contact 5. Alternatively, after forming a portion of the second dielectric layer 221 on the first encapsulation layer 31, the first encapsulation layer 31 and the second dielectric layer 221 may be opened simultaneously to form a through hole including the first opening K1, and the through hole may be filled with a conductive material to form the contact 5.

[0110] In other embodiments, referring to FIG. 4 , the contact member 5 may be disposed on the inner wall of the first opening K1 .

[0111] Exemplarily, referring to FIG. 4 , in this embodiment, at least a portion of the second dielectric layer 221 is disposed on the contact element 5 and is filled in the first opening K1 .

[0112] In this embodiment, the contact member 5 is deposited on the inner wall of the first opening K1. Compared with the case where the contact member 5 is completely filled in the first opening K1, the contact member 5 deposited on the inner wall of the first opening K1 has a smaller resistance value, thereby reducing the power consumption of the packaging structure 300 and improving the electrical performance.

[0113] Illustratively, during the preparation process, after forming a portion of the second dielectric layer 221 on the first packaging layer 31, the first packaging layer 31 and a portion of the second dielectric layer 221 can be opened at the same time to form a through hole including the first opening K1, and during the preparation of the second trace 222, a conductive material is deposited on the inner wall of the through hole to form the contact 5.

[0114] In other embodiments, referring to FIG. 5 , at least a portion of the second dielectric layer 221 is filled in the first opening K1 , and the contact member 5 passes through the portion of the second dielectric layer 221 in the first opening K1 and is electrically connected to the first connecting portion 41 .

[0115] That is, in this embodiment, the contact member 5 does not contact the hole wall of the first opening K1 .

[0116] Illustratively, during the preparation process, a first opening K1 may be first opened on the first packaging layer 31, and then a portion of the second dielectric layer 221 may be formed on the first packaging layer 31, so that the second dielectric layer 221 is formed on the second surface 1b of the first chip 11 and on the inner wall of the first opening K1. Then, the portion of the second dielectric layer 221 located on the first connecting portion 41 is opened, and a conductive material is prepared to form the contact 5 (or the contact 5 and the second trace 222 are formed at the same time).

[0117] In this embodiment, by first forming the second dielectric layer 221 and then forming the conductive contact 5, the exposed second surface 1b of the first chip 11 can be protected by the second dielectric layer 221 before the conductive contact 5 is formed, thereby preventing the conductive particles generated during the formation of the contact 5 from damaging the exposed second surface 1b of the first chip 11, thereby improving the reliability of the first chip 11 and making the packaging structure 300 have better electrical performance.

[0118] FIG6 is another cross-sectional view of the packaging structure 300 provided in an embodiment of the present application.

[0119] In some embodiments, referring to FIG. 2 and FIG. 6 , the first encapsulation layer 31 includes a first sub-portion 311 and a second sub-portion 312 .

[0120] 6 , the first sub-portion 311 is disposed between the first chip 11 and the first wiring layer 21 , thereby preventing unexpected electrical connection between the first chip 11 and the first wiring layer 21 .

[0121] For example, referring to FIG. 6 , the first sub-portion 311 may include a plurality of second openings K2 that pass through the first sub-portion 311 so that a plurality of pins on the first chip 11 can be electrically connected to the first wiring layer 21 through the plurality of second openings K2 .

[0122] Referring to Figure 6, the second sub-portion 312 surrounds the side surface of the first chip 11 perpendicular to the first surface 1a, the aforementioned first connecting portion 41 is embedded in the second sub-portion 312, and at least a portion of the second sub-portion 312 is arranged between the side surface of the first chip 11 and the first connecting portion 41, thereby avoiding unexpected electrical connection between the first connecting portion 41 and the first chip 11.

[0123] For example, the first sub-section 311 and the second sub-section 312 may be integrally provided.

[0124] Alternatively, for example, the first sub-portion 311 may be formed first, and then the second sub-portion 312 may be formed on the first sub-portion 311. For example, after the first chip 11 is disposed on the first wiring layer 21 and the plurality of pins on the first surface 1a of the first chip 11 are electrically connected to the first wiring layer 21, the first sub-portion 311 may be filled between the first wiring layer 21 and the first chip 11 by the capillary principle, and then the second sub-portion 312 may be formed around the side of the first chip 11.

[0125] In some embodiments, referring to FIG. 2 and FIG. 6 , the package structure 300 further includes a plurality of second connection portions 42 .

[0126] 6 , the plurality of second connection portions 42 are disposed between the first chip 11 and the first wiring layer 21 , and all pass through the first sub-portion 311 (for example, through the second opening K2 ), and the first chip 11 and the first wiring layer 21 are electrically connected via the plurality of second connection portions 42 .

[0127] For example, the plurality of pins on the first surface 1 a of the first chip 11 and the plurality of pads on the first wiring layer 21 are electrically connected in a one-to-one correspondence through the plurality of second connection portions 42 .

[0128] For example, referring to Figure 6, the first routing line 212 closest to the first chip 11 in at least one layer of first routing lines 212 can form multiple pads, and the first routing line 212 is electrically connected to the first chip 11 through multiple second connecting parts 42, thereby realizing independent transmission of electrical signals of multiple pins on the first chip 11.

[0129] 6 , two adjacent second connection portions 42 are spaced apart from each other, so that a plurality of pins on the first surface 1 a of the first chip 11 can be electrically connected to the first wiring layer 21 independently through the plurality of second connection portions 42 .

[0130] Exemplarily, the electrical connection between the first chip 11 and the first wiring layer 21 can be achieved by using grid array packaging technology, that is, the multiple second connection parts 42 can be multiple solder ball structures, and the array-distributed solder ball structures can correspond to the multi-pin first chip 11, so as to achieve independent external connection of multiple pins of the first chip 11.

[0131] Exemplarily, the plurality of second connection portions 42 may also be a plurality of plug-in connectors, or other conductive structures capable of achieving electrical connection between the first chip 11 and the first wiring layer 21 .

[0132] In some embodiments, referring to FIG. 6 , the package structure 300 further includes a plurality of third connection portions 43 .

[0133] 6 , the plurality of third connection portions 43 are disposed between the second wiring layer 22 and the second chip 12 . The second wiring layer 22 and the second chip 12 are electrically connected via the plurality of third connection portions 43 .

[0134] For example, a plurality of pins are provided on the surface of the second chip 12 close to the second wiring layer 22, and a plurality of pads are formed by the second trace 222 closest to the second chip 12 in the second wiring layer 22. The plurality of pins of the second chip 12 can be electrically connected to the plurality of pads of the second wiring layer 22 through a plurality of third connection parts 43.

[0135] 6 , two adjacent third connection portions 43 are spaced apart so that the plurality of pins on the second chip 12 can be electrically connected to the plurality of pads in the second wiring layer 22 independently through the plurality of third connection portions 43 , thereby realizing independent transmission of electrical signals of the plurality of pins on the second chip 12 .

[0136] For example, similar to the second connection portion 42 , the plurality of third connection portions 43 may also be a plurality of solder ball structures, or a plurality of plug-in structures or other conductive structures capable of electrically connecting the second chip 12 to the second wiring layer 22 .

[0137] For example, in other embodiments, referring to FIG2 , the second chip 12 can also be electrically connected to the second wiring layer 22 through a lead P or other means. For example, referring to FIG2 , one end of the lead P is electrically connected to the second chip 12, and the other end is electrically connected to the second trace 222 in the second wiring layer 22, thereby achieving electrical continuity between the second chip 12 and the second wiring layer 22. It is understood that in the embodiments of the present application, only the lead P connection (as shown in FIG2 ) or the third connection portion 43 connection (as shown in FIG6 ) is used as an example to illustrate the connection method between the second chip 12 and the second wiring layer 22, and this does not constitute a limitation thereto. Other methods that can achieve interconnection between the two are within the scope of protection of the present application.

[0138] In some embodiments, the second chip 12 may be an unpackaged bare chip, or may be a packaged chip.

[0139] For example, referring to FIG. 2 , the package structure 300 further includes a second package layer 32 , which is disposed around the second chip 12 .

[0140] The second packaging layer 32 is used to package the second chip 12 so as to protect the second chip 12 from external damage and prevent the second chip 12 from having unexpected electrical connections.

[0141] For example, the material of the second encapsulation layer 32 may be the same as that of the first encapsulation layer 31. For example, both may be molding materials.

[0142] For example, the aforementioned third connection portion 43 can pass through the portion of the second packaging layer 32 located between the second wiring layer 22 and the second chip 12, thereby realizing electrical connection between the second wiring layer 22 and the second chip 12 through the third connection portion 43, and two adjacent third connection portions 43 are insulated by the portion of the second packaging layer 32.

[0143] In some embodiments, referring to FIG. 6 , the package structure 300 further includes a plurality of fourth connection portions 44 . The fourth connection portions 44 are disposed on a side of the first wiring layer 21 away from the first chip 11 and are electrically connected to the first wiring layer 21 .

[0144] Exemplarily, referring to FIG. 6 , the plurality of fourth connection portions 44 are electrically connected to the first traces 212 in the first wiring layer 21 .

[0145] For example, referring to FIG. 6 , the first traces 212 in the first wiring layer 21 that are farthest from the first chip 11 form a plurality of pads, and the plurality of fourth connection portions 44 are correspondingly disposed on the plurality of pads.

[0146] Exemplarily, the fourth connection portion 44 can also be a conductive structure such as a plurality of array-distributed solder ball structures or a plug-in structure. When the packaging structure 300 needs to be electrically connected to the outside, welding with the external electrical structure can be achieved through the fourth connection portion 44.

[0147] For example, the packaging structure 300 may be soldered to the circuit board 200 through the plurality of fourth connection portions 44 , thereby achieving electrical connection between the packaging structure 300 and the circuit board 200 .

[0148] The present invention also provides a method for preparing a package structure 300. Figure 7 is a flowchart of the preparation process of the package structure 300 provided in the present invention. Figures 8 to 18 are cross-sectional views corresponding to the preparation steps of the package structure 300.

[0149] As shown in FIG. 7 to FIG. 18 , the method for preparing the package structure 300 includes steps S1 to S6:

[0150] S1 : Referring to FIG. 8 , a first wiring layer 21 is formed, and a first connecting portion 41 is formed on the first wiring layer 21 .

[0151] Exemplarily, referring to FIG. 8 , a first wiring layer 21 and subsequent structures may be fabricated on a substrate 10 .

[0152] Among them, the substrate 10 can be a separate glass substrate, etc., or the substrate 10 can also be set integrally with the first wiring layer 21. The embodiment of the present application imposes restrictions on the material and specific structure of the substrate 10. Any substrate 10 that can form a bearing function for preparing structures such as the first wiring layer 21 is within the protection scope of the embodiment of the present application.

[0153] S2 : referring to FIG. 9 , FIG. 10 , FIG. 11 and FIG. 12 , a first chip 11 and a first packaging layer 31 are formed on the first wiring layer 21 .

[0154] 9 to 12 , the first chip 11 includes a first surface 1 a and a second surface 1 b , wherein the first surface 1 a of the first chip 11 is used for electrical connection with the first wiring layer 21 .

[0155] Referring to Figure 12, the first packaging layer 31 is arranged around at least a portion of the first chip 11, the first connecting portion 41 is embedded in the first packaging layer 31 and is spaced apart from the first chip 11, and one end of the first connecting portion 41 is electrically connected to the first wiring layer 21. For example, the bottom end of the first connecting portion 41 directly abuts the first trace 212 in the first wiring layer 21.

[0156] 12 , the end surface of the first connection portion 41 away from the first wiring layer 21 is closer to the first wiring layer 21 than the surface of the first packaging layer 31 away from the first wiring layer 21 .

[0157] For example, referring to FIG9 to FIG12 , step S2 may include steps S21 to S24:

[0158] S21 : Referring to FIG. 9 , a second connection portion 42 is provided on the first surface 1 a of the unpackaged first chip 11 .

[0159] S22 : Referring to FIG. 10 , the unpackaged first chip 11 is disposed on the first wiring layer 21 , and the first chip 11 and the first wiring layer 21 are connected via the second connection portion 42 .

[0160] S23 : Referring to FIG. 11 , a first packaging layer 31 is formed to completely encapsulate the first chip 11 .

[0161] S24 : Referring to FIG. 12 , a portion of the first encapsulation layer 31 located on a side of the plane where the second surface 1 b is located and away from the substrate 10 is removed, thereby exposing the second surface 1 b .

[0162] Exemplarily, step S24 may further include: first forming a first sub-portion 311 between the first chip 11 and the first wiring layer 21, and then forming a second sub-portion 312 surrounding the first chip 11. For example, the first sub-portion 311 may be filled between the first chip 11 and the first wiring layer 21 by a capillary principle.

[0163] For example, steps S21 to S24 provided in the embodiment of the present application are merely exemplary, and other methods capable of preparing the first chip 11 and the first packaging layer 31 are also within the scope of protection of the present application. For example, the first chip 11 can be packaged first (i.e., the first packaging layer 31 is first placed around the surface of the first chip 11), and then a second opening K2 is opened (see Figure 11) and the second connection portion 42 is filled, and then the packaged first chip 11 is set on the first wiring layer 21. The embodiment of the present application does not impose any restrictions on this.

[0164] S3 : Referring to FIG. 13 , a first opening K1 is formed on the first packaging layer 31 .

[0165] 13 , the first opening K1 exposes the end surface of the first connection portion 41 away from the first wiring layer 21 , so as to subsequently realize external connection of the first connection portion 41 .

[0166] S4: Referring to FIG. 15 , a contact member 5 is formed in the first opening K1 .

[0167] 15 , one end of the contact 5 passes through the first opening K1 and is electrically connected to the end surface of the first connection portion 41 away from the first wiring layer 21 , and the other end of the contact 5 is used to electrically connect to the second wiring layer 22 described in subsequent preparation steps.

[0168] That is, the contact 5 is used to achieve electrical connection between the first connection portion 41 and the second wiring layer 22 to be described in a subsequent manufacturing step.

[0169] It is understandable that step S3 and step S4 merely exemplarily provide an electrical connection method between the first connection portion 41 and the second wiring layer 22 described in the subsequent preparation steps, and do not limit the electrical connection methods and preparation steps of the two.

[0170] S5 : referring to FIG. 14 and FIG. 15 , a second wiring layer 22 is formed on a side of the first chip 11 and the first packaging layer 31 away from the first wiring layer 21 .

[0171] 15 , the second wiring layer 22 contacts the second surface 1 b of the first chip 11 , and the other end of the first connection portion 41 is electrically connected to the second wiring layer 22 . For example, the second wiring layer 22 is electrically connected to the first connection portion 41 through the contact 5 .

[0172] It is understood that step S4 and step S5 can be performed simultaneously. For example, a portion of the second dielectric layer 221 can be formed in the first opening K1 first, and the second dielectric layer 221 located in the first opening K1 can be opened so that the portion of the second dielectric layer 221 is disposed on the inner wall of the first opening K1 and the first connecting portion 41 is exposed. Subsequently, the contact 5 can be formed simultaneously with the formation of the second trace 222. That is, the second trace 222 and the contact 5 are integrally formed.

[0173] Exemplarily, the second wiring layer 22 includes a second dielectric layer 221 and at least one layer of second traces 222 embedded in the second dielectric layer 221 .

[0174] 14 and 15 , forming the second wiring layer 22 (ie, step S5 ) may include:

[0175] S51 : referring to FIG. 14 , at least a portion of a second dielectric layer 221 is formed on a side of the first chip 11 and the first packaging layer 31 away from the first wiring layer 21 .

[0176] S52 : Referring to FIG. 15 , at least one layer of second wiring 222 is formed on at least a portion of the second dielectric layer 221 away from the first chip 11 and the first packaging layer 31 , with a portion of the second dielectric layer 221 disposed between two adjacent layers of second wiring 222 .

[0177] 14 and 15 , the second dielectric layer 221 contacts the second surface 1b of the first chip 11 . The second dielectric layer 221 can protect the second surface 1b of the first chip 11 and prevent the exposed second surface 1b from being damaged or causing unexpected electrical connections.

[0178] S6 : Referring to FIG. 18 , a second chip 12 is formed on a side of the second wiring layer 22 away from the first chip 11 . The second chip 12 is electrically connected to the second wiring layer 22 .

[0179] Exemplarily, referring to FIG. 18 , step S6 further includes: forming a third connecting portion 43 to facilitate electrical connection between the second chip 12 and the second wiring layer 22 .

[0180] For example, while or after forming the second chip 12 , a second packaging layer 32 wrapping the second chip 12 may be formed.

[0181] For example, referring to FIG. 16 and FIG. 17 , the preparation method may further include:

[0182] S7: Referring to FIG. 16 , the substrate 10 is removed.

[0183] S8: Referring to FIG. 17 , a fourth connecting portion 44 is formed.

[0184] Exemplarily, the order of step S6, step S7 and step S8 may not be fixed. For example, the formation of the third connection portion 43 may be performed simultaneously with the formation of the fourth connection portion 44, that is, step S6 and step S8 may be performed simultaneously. The embodiment of the present application does not limit the order of steps S6 to S8.

[0185] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this disclosure should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A packaging structure, characterized in that: include: A first chip includes a first surface and a second surface opposite to each other; a first wiring layer, provided on a side of the first surface of the first chip and electrically connected to the first chip; a second wiring layer, provided on the second surface of the first chip and in contact with the second surface; a first packaging layer, disposed between the first wiring layer and the second wiring layer and surrounding at least a portion of the first chip; a first connecting portion embedded in the first packaging layer and spaced apart from the first chip; one end of the first connecting portion is electrically connected to the first wiring layer, and the other end is electrically connected to the second wiring layer; an end surface of the first connecting portion away from the first wiring layer is closer to the first wiring layer than a surface of the first packaging layer away from the first wiring layer; The second chip is disposed on a side of the second wiring layer away from the first chip and is electrically connected to the second wiring layer.

2. The packaging structure according to claim 1, wherein: The second wiring layer includes a second dielectric layer and at least one layer of second traces embedded in the second dielectric layer; The second dielectric layer contacts the second surface of the first chip.

3. The packaging structure according to claim 1 or 2, characterized in that: The first packaging layer includes a first opening, and the first opening is located on an end surface of the first connecting portion away from the first wiring layer; The packaging structure further includes: A contact member has one end electrically connected to the second wiring layer, and the other end passes through the first opening and is electrically connected to the first connecting portion.

4. The packaging structure according to claim 3, wherein: The second wiring layer includes a second dielectric layer and at least one layer of second wiring embedded in the second dielectric layer; the at least one layer of second wiring is integrally provided with the contact element.

5. The packaging structure according to claim 3 or 4, characterized in that: The contact member is filled in the first opening; or, the contact member is arranged on the inner wall of the first opening.

6. The packaging structure according to claim 3 or 4, characterized in that: At least a portion of the second dielectric layer is filled in the first opening, and the contact member passes through the portion of the second dielectric layer located in the first opening and is electrically connected to the first connecting portion.

7. The packaging structure according to any one of claims 1 to 6, characterized in that: The first encapsulation layer includes a first sub-portion and a second sub-portion, the first sub-portion is arranged between the first chip and the first wiring layer, and the second sub-portion surrounds a side surface of the first chip; The first connecting portion is embedded in the second sub-portion, and at least a portion of the second sub-portion is disposed between the side surface of the first chip and the first connecting portion.

8. The packaging structure according to claim 7, wherein: Also includes: A plurality of second connection parts are arranged between the first chip and the first wiring layer and all pass through the first sub-part. Two adjacent second connection parts are arranged at intervals. The first chip and the first wiring layer are electrically connected through the plurality of second connection parts.

9. The packaging structure according to any one of claims 1 to 8, wherein: Also includes: A plurality of third connection portions are provided between the second wiring layer and the second chip, with two adjacent third connection portions spaced apart. The second wiring layer and the second chip are electrically connected via the plurality of third connection portions.

10. The packaging structure according to claim 9, wherein: Also includes: The second packaging layer is disposed around the second chip, and the third connection portion passes through a portion of the second packaging layer located between the second wiring layer and the second chip.

11. An electronic device, characterized in that: include: The packaging structure according to any one of claims 1 to 10; A circuit board is electrically connected to the packaging structure.

12. A method for preparing a packaging structure, characterized in that: include: forming a first wiring layer, and forming a first connection portion on the first wiring layer; forming a first chip and a first packaging layer on the first wiring layer; The first chip includes a first surface and a second surface; the first surface of the first chip is electrically connected to the first wiring layer; the first packaging layer is disposed around at least a portion of the first chip; the first connecting portion is embedded in the first packaging layer and spaced apart from the first chip; one end of the first connecting portion is electrically connected to the first wiring layer; an end surface of the first connecting portion away from the first wiring layer is closer to the first wiring layer than a surface of the first packaging layer away from the first wiring layer; forming a second wiring layer on a side of the first chip and the first packaging layer away from the first wiring layer; the second wiring layer is in contact with the second surface of the first chip; and the other end of the first connecting portion is electrically connected to the second wiring layer; A second chip is formed on a side of the second wiring layer away from the first chip; the second chip is electrically connected to the second wiring layer.

13. The preparation method according to claim 12, characterized in that The second wiring layer includes a second dielectric layer and at least one layer of second traces embedded in the second dielectric layer; The forming of the second wiring layer comprises: forming at least a portion of the second dielectric layer on a side of the first chip and the first packaging layer away from the first wiring layer; The at least one layer of second wiring is formed on at least a portion of the second dielectric layer on a side away from the first chip and the first packaging layer; a portion of the second dielectric layer is provided between two adjacent layers of second wiring; The second dielectric layer is in contact with the second surface of the first chip.

14. The preparation method according to claim 12 or 13, characterized in that: Also includes: opening a first opening in the first packaging layer; The first opening exposes an end surface of the first connecting portion away from the first wiring layer; forming a contact member in the first opening; One end of the contact passes through the first opening and is electrically connected to an end surface of the first connecting portion away from the first wiring layer.

Images