Optical module and optical chip

Abstract

Provided in the present disclosure are an optical module and an optical chip. The optical chip comprises a silicon platform, on which an optical coupler and an indium phosphide modulated waveguide are provided, wherein the optical coupler comprises a silicon coupled waveguide layer and an indium phosphide coupled waveguide layer, each of which comprises a gradient region, and there is an overlapping region between the gradient region of the indium phosphide coupled waveguide layer and the gradient region of the silicon coupled waveguide layer; the width of the gradient region of the silicon coupled waveguide layer gradually decreases, and the width of the gradient region of the indium phosphide coupled waveguide layer gradually increases; and the indium phosphide modulated waveguide comprises a first modulated waveguide layer, a second modulated waveguide layer and a third modulated waveguide layer, which are stacked in sequence, the second modulated waveguide layer comprises a plurality of quantum wells, a P-doping concentration of the third modulated waveguide layer falls within a first preset range, and an N-doping concentration of the first modulated waveguide layer falls within a second preset range. In the present application, the optical coupler improves the coupling efficiency, and the P-doping concentration and the N-doping concentration fall within corresponding preset ranges, so as to compensate for an increase in quantum well absorption loss.

Description

Optical modules and optical chips

[0001] This application claims priority from application number 202410308736.9 filed with the China Patent Office on March 18, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of optical communication technology, and in particular to an optical module and an optical chip. Background Art

[0003] With the development of new services and applications such as cloud computing, mobile internet, and video, advances in optical communication technology are becoming increasingly important. As a key component in optical communication equipment, optical modules enable photoelectric signal conversion. As optical communication technology evolves, the data transmission rate of these modules continues to increase. Summary of the Invention

[0004] In one aspect, the present disclosure provides an optical module, comprising:

[0005] circuit boards;

[0006] An optical chip, electrically connected to the circuit board, is used to modulate and generate optical signals;

[0007] The optical chip includes a silicon platform, on which input and output waveguides and an indium phosphide modulation waveguide are arranged. The input and output waveguides are silicon waveguides, and an optical coupler is arranged between the input and output waveguides and the indium phosphide modulation waveguide.

[0008] The optical coupler includes a silicon coupling waveguide layer and an indium phosphide coupling waveguide layer. The indium phosphide coupling waveguide layer is located above the silicon coupling waveguide layer. Both the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer include a gradient region. The gradient region of the indium phosphide coupling waveguide layer overlaps with the gradient region of the silicon coupling waveguide layer. One end of the silicon coupling waveguide layer is connected to the input and output waveguides, and one end of the indium phosphide coupling waveguide layer is connected to the indium phosphide modulation waveguide. From the input and output waveguides to the indium phosphide modulation waveguide, the width of the gradient region of the silicon coupling waveguide layer gradually decreases, while the width of the gradient region of the indium phosphide coupling waveguide layer gradually increases.

[0009] The indium phosphide modulation waveguide includes a first modulation waveguide layer, a second modulation waveguide layer, and a third modulation waveguide layer. The first modulation waveguide layer is located on a silicon platform, the second modulation waveguide layer is located above the first modulation waveguide layer, and the third modulation waveguide layer is located above the second modulation waveguide layer. The second modulation waveguide layer is in contact with and connected to the first modulation waveguide layer and the third modulation waveguide layer respectively.

[0010] The second modulation waveguide layer includes multiple quantum wells, the P doping concentration of the third modulation waveguide layer is within a first preset range, and the N doping concentration of the first modulation waveguide layer is within a second preset range to compensate for absorption loss of the quantum wells.

[0011] In another aspect, the present disclosure provides an optical chip, comprising:

[0012] A silicon platform is provided with input and output waveguides and an indium phosphide modulation waveguide; the input and output waveguides are silicon waveguides, and an optical coupler is provided between the input and output waveguides and the indium phosphide modulation waveguide;

[0013] The optical coupler includes a silicon coupling waveguide layer and an indium phosphide coupling waveguide layer, the indium phosphide coupling waveguide layer being located above the silicon coupling waveguide layer, and both the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer including a gradient region, wherein the gradient region of the indium phosphide coupling waveguide layer overlaps with the gradient region of the silicon coupling waveguide layer, one end of the silicon coupling waveguide layer is connected to the input and output waveguides, and one end of the indium phosphide coupling waveguide layer is connected to the indium phosphide modulation waveguide; the direction in which the width of the gradient region of the silicon coupling waveguide layer decreases is the same as the direction in which the width of the gradient region of the indium phosphide coupling waveguide layer increases;

[0014] The indium phosphide modulation waveguide includes a first modulation waveguide layer, a second modulation waveguide layer, and a third modulation waveguide layer. The first modulation waveguide layer is located on a silicon platform, the second modulation waveguide layer is located above the first modulation waveguide layer, the third modulation waveguide layer is located above the second modulation waveguide layer, and the second modulation waveguide layer is in contact with and connected to the first modulation waveguide layer and the third modulation waveguide layer respectively.

[0015] The second modulation waveguide layer includes multiple quantum wells, the P doping concentration of the third modulation waveguide layer is within a first preset range, and the N doping concentration of the first modulation waveguide layer is within a second preset range to compensate for absorption loss of the quantum wells. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] FIG1 is a partial structural diagram of an optical communication system according to some embodiments;

[0018] FIG2 is a partial structural diagram of a host computer according to some embodiments;

[0019] FIG3 is a structural diagram of an optical module according to some embodiments;

[0020] FIG4 is an exploded view of an optical module according to some embodiments;

[0021] FIG5 is a schematic diagram of the internal structure of an optical module according to some embodiments;

[0022] FIG6 is a schematic diagram of the layout of a hybrid InP / Si optical chip according to some embodiments;

[0023] FIG7 is a partial schematic diagram of a hybrid InP / Si optical chip according to some embodiments;

[0024] FIG8 is a first cross-sectional view of a hybrid InP / Si optical chip according to some embodiments;

[0025] FIG9 is a graph showing the relationship between quantum well absorption coefficient and wavelength according to some embodiments;

[0026] FIG10 shows the width of the depletion region of a PIN junction when the reverse bias voltage is 0V according to some embodiments;

[0027] FIG11 shows the width of the depletion region of a PIN junction when the reverse bias voltage is -3V according to some embodiments;

[0028] FIG12 is a second cross-sectional view of a hybrid InP / Si optical chip according to some embodiments;

[0029] FIG13 is a third cross-sectional view of a hybrid InP / Si optical chip according to some embodiments;

[0030] FIG14 is a top view of a first silicon-coupled waveguide layer according to some embodiments;

[0031] FIG15 is a top view of a second silicon-coupled waveguide layer according to some embodiments;

[0032] FIG16 is a top view of a quantum well coupled waveguide layer according to some embodiments;

[0033] FIG17 is a top view of a p-InP coupled waveguide layer according to some embodiments;

[0034] FIG18 is an overlapping diagram of a first silicon coupling waveguide layer, a second silicon coupling waveguide layer, a quantum coupling waveguide layer, and a p-InP coupling waveguide layer provided according to some embodiments;

[0035] FIG19 is a combined diagram of a first silicon coupling waveguide layer, a second silicon coupling waveguide layer, a quantum coupling waveguide layer, and a p-InP coupling waveguide layer according to some embodiments;

[0036] FIG20 is a diagram illustrating light distribution in an optical coupler according to some embodiments;

[0037] FIG21 is a diagram showing FDTD simulation results of an optical coupler according to some embodiments;

[0038] FIG. 22 is a schematic diagram illustrating the growth of an optical coupler according to some embodiments. DETAILED DESCRIPTION

[0039] Some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described are only some of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

[0040] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open and inclusive, that is, "including, but not limited to"; the terms "first" and "second" are not to be understood as indicating or implying relative importance or indicating an upper limit on quantity; the term "plurality" means two or more; the term "connected" is to be understood in a broad sense, for example, "connected" can be a fixed connection, a detachable connection, or an integral connection, and can be directly connected or indirectly connected through an intermediate medium; the use of the terms "suitable for" or "configured to" means open and inclusive language, which does not exclude equipment that is suitable for or configured to perform additional tasks or steps; terms such as "parallel", "perpendicular", "same", "consistent", "level" and so on are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges generated in practice, and also include differences based on the same design concept but due to manufacturing reasons.

[0041] In optical communication technology, to establish information transmission between information processing devices, it is necessary to load the information onto light and use the propagation of light to achieve information transmission. Here, the light loaded with information is an optical signal. When transmitting optical signals within information transmission equipment, they can reduce optical power loss, thereby enabling high-speed, long-distance, and low-cost information transmission. The signals that information processing equipment can recognize and process are electrical signals. Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., and information transmission equipment typically includes optical fibers and optical waveguides.

[0042] Optical modules can convert optical signals into electrical signals between information processing devices and information transmission devices. For example, at least one of the optical signal input or output ends of an optical module is connected to an optical fiber, and at least one of the electrical signal input or output ends of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber. Because multiple information processing devices can transmit information via electrical signals, at least one of the multiple information processing devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is referred to as the optical module's host computer. Furthermore, the optical signal input or output end of the optical module can be referred to as an optical port, and the electrical signal input or output end of the optical module can be referred to as an electrical port.

[0043] Figure 1 is a partial structural diagram of an optical communication system according to some embodiments. As shown in Figure 1 , the optical communication system mainly includes a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 , and a network cable 103 .

[0044] One end of optical fiber 101 extends toward remote information processing device 1000, and the other end of optical fiber 101 is connected to optical module 200 through the optical port of optical module 200. Optical signals can be totally reflected in optical fiber 101, and the propagation of the optical signal in the direction of total reflection can almost maintain the original optical power. The optical signal undergoes multiple total reflections in optical fiber 101 to transmit the optical signal from remote information processing device 1000 to optical module 200, and vice versa, thereby achieving long-distance, low-power information transmission.

[0045] The optical communication system may include one or more optical fibers 101, and the optical fibers 101 may be detachably connected or fixedly connected to the optical module 200. The host computer 100 is configured to provide data signals to the optical module 200, receive data signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0046] The host computer 100 includes a substantially rectangular housing and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to connect to the optical module 200 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0047] The host computer 100 also includes an external electrical interface that can access an electrical signal network. For example, the external electrical interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to access a network cable 103 so that the host computer 100 establishes a unidirectional or bidirectional electrical signal connection with the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so that an electrical signal connection is established between the local information processing device 2000 and the host computer 100 via the network cable 103. For example, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 via the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is then transmitted to the remote information processing device 1000 via the optical fiber 101. For example, a first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101. The first optical signal from the optical fiber 101 is transmitted to the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal. The optical module 200 transmits the first electrical signal to the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to the local information processing device 2000. It should be noted that optical modules are tools for converting optical signals into electrical signals. During this conversion process, the information does not change, but the encoding and decoding methods of the information can change.

[0048] In addition to the optical network terminal, the host computer 100 also includes an optical line terminal (OLT), an optical network device (ONT), or a data center server.

[0049] Figure 2 is a partial structural diagram of a host computer provided according to some embodiments. To clearly illustrate the connection between the optical module 200 and the host computer 100, Figure 2 only shows the structure of the host computer 100 related to the optical module 200. As shown in Figure 2, the host computer 100 also includes a PCB circuit board 105 disposed within the housing, a cage 106 disposed on the surface of the PCB circuit board 105, a heat sink 107 disposed on the cage 106, and an electrical connector disposed within the cage 106. The electrical connector is configured to connect to the electrical port of the optical module 200; the heat sink 107 has raised structures such as fins to increase the heat dissipation area.

[0050] The optical module 200 is inserted into the cage 106 of the host computer 100. The cage 106 secures the optical module 200. Heat generated by the optical module 200 is transferred to the cage 106 and then dissipated through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 connects with the electrical connector inside the cage 106, thereby establishing a bidirectional electrical signal connection between the optical module 200 and the host computer 100. Furthermore, the optical port of the optical module 200 connects to the optical fiber 101, thereby establishing a bidirectional optical signal connection between the optical module 200 and the optical fiber 101.

[0051] FIG3 is a structural diagram of an optical module provided according to some embodiments, and FIG4 is an exploded view of an optical module provided according to some embodiments. As shown in FIG3 and FIG4 , the optical module 200 includes a housing (shell), a circuit board 300 disposed within the housing, an optical chip 400, and a light source 500. Exemplarily, the optical chip 400 and the light source 500 are disposed on the circuit board 300 and electrically connected to the circuit board 300, and the light output end of the light source 500 is optically coupled to the optical chip 400. In some embodiments, the light output end of the light source 500 is connected to the optical chip 400 via an optical fiber coupling.

[0052] The housing includes an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square.

[0053] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicular to the base plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0054] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicularly to the base plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and arranged perpendicularly to the cover plate 2011. The two upper side plates are combined with the two lower side plates 2022 to achieve the upper shell 201 covering the lower shell 202.

[0055] The direction of the line connecting the two openings 204 and 205 can be consistent with the length direction of the optical module 200, or it can be inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200 (the left end in Figure 3), and opening 205 is also located at the end of the optical module 200 (the right end in Figure 3). Alternatively, opening 204 is located at the end of the optical module 200, while opening 205 is located on the side of the optical module 200. Opening 204 is an electrical port, and the gold finger 301 of the circuit board 300 extends from opening 204 and is inserted into the electrical connector of the host computer 100. Opening 205 is an optical port, configured to receive an external optical fiber 101, so that the optical fiber 101 can connect to the optical chip 400 in the optical module 200.

[0056] The combined assembly of the upper housing 201 and the lower housing 202 facilitates installation of the circuit board 300, optical chip 900, and light source 1100 within the housing, with the upper housing 201 and the lower housing 202 providing encapsulation and protection for these components. Furthermore, during assembly of the circuit board 300, optical chip 400, and light source 500, positioning components, heat dissipation components, and electromagnetic shielding components are easily positioned, facilitating automated production.

[0057] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0058] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0059] For example, the unlocking component 600 is located on the outside of the two lower side panels 2022 of the lower housing 202 and includes a snap-fit ​​component that mates with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the snap-fit ​​component of the unlocking component 600 secures the optical module 200 in the cage 106. When the unlocking component 600 is pulled, the snap-fit ​​component of the unlocking component 600 moves accordingly, thereby changing the connection between the snap-fit ​​component and the host computer, thereby releasing the optical module 200 from the cage 106 and allowing the optical module 200 to be removed from the cage 106.

[0060] The circuit board 300 includes circuit traces, electronic components, and chips. The electronic components and chips are connected according to the circuit design through the circuit traces to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include, for example, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0061] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0062] The circuit board 300 also includes a gold finger 301 formed on its end surface, and the gold finger 301 is composed of a plurality of independent pins. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is connected to the electrical connector in the cage 106. The gold finger 301 can be set only on the surface of one side of the circuit board 300 (for example, the upper surface shown in Figure 4), or it can be set on the upper and lower surfaces of the circuit board 300 to provide a larger number of pins, thereby adapting to occasions where a large number of pins are required. The gold finger 301 is configured to establish an electrical connection with the host computer to achieve power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, data signal transmission, etc. Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.

[0063] Figure 5 is a schematic diagram of the internal structure of an optical module according to some embodiments. As shown in Figure 5 , in some embodiments, a light source 500 can be disposed on the side of the optical chip 400 , and the light source 500 emits light from the side and couples it into the optical chip 400 .

[0064] The optical chip 400 itself does not have a light source. The light source 500 is used as an external light source of the optical chip 400 , and the light emitted by the light source 500 enters the optical chip 400 .

[0065] The light source 500 can be a laser box, which has a laser encapsulated inside. The laser emits light to generate a laser beam. The light source 500 is used to provide the emission laser to the optical chip 400. The laser has good single-wavelength characteristics and better wavelength tuning characteristics, making it the preferred light source for optical modules and even optical fiber transmission. Other types of light, such as LED light, are generally not used in common optical communication systems. Even if such a light source is used in a special optical communication system, the characteristics of the light source and the chip components are quite different from those of the laser, which makes the optical module using lasers and the optical module using other light sources have great technical differences. Those skilled in the art generally do not believe that these two types of optical modules can provide technical inspiration to each other.

[0066] The light emitted by the light source 500 is light that does not carry data. This light that does not carry data is the light to be modulated. The light to be modulated enters the optical chip 400, and the optical chip 400 modulates it and loads the electrical signal into the light to be modulated to obtain light carrying data, that is, generate an optical transmission signal, thereby realizing the transmission of the optical signal; external light enters the optical chip 400, and the optical chip 400 demodulates it, thereby realizing the reception of the optical signal.

[0067] In some embodiments, optical chip 400 is a silicon photonic chip. The silicon photonic chip includes a Mach-Zehnder modulator (MZM) with an integrated silicon photonic phase modulator for optical signal modulation and demodulation. Because silicon photonic chips are easily etched, other functional components such as optical splitters, combiners, mixers, and photodetectors can be integrated within them, enabling more functionality.

[0068] However, the fundamental properties of silicon materials lead to drawbacks in optical modulator implementation, such as relatively low modulation efficiency, high capacitance, limited bandwidth, and high optical loss. Consequently, because silicon photonic phase modulators operate based on carriers, current long-haul 400G optical modules can only achieve transmission rates of 50-60Gbaud per channel. However, in next-generation optical modules for 1.6-3.2T PAM short-haul transmission and 800G-3.2T coherent long-haul transmission, transmission rates per channel must exceed 100Gbaud, necessitating a silicon photonic phase modulator with a modulation rate exceeding 100Gbaud. However, when the modulation rate of a silicon photonic phase modulator approaches 100Gbaud, the driver's output voltage swing is high, resulting in high power consumption and making it unsuitable for optical modules.

[0069] In some embodiments, optical chip 400 is a thin-film lithium niobate chip. Thin-film lithium niobate exhibits properties such as the linear electro-optic effect. An applied electric field causes a linear change in its refractive index in the corresponding direction, allowing light waves transmitted through the medium to have controllable intensity, phase, and other information. Therefore, thin-film lithium niobate can be used as the material for optical modulators, achieving high modulation efficiency. However, thin-film lithium niobate is relatively hard and difficult to etch, making it difficult to integrate multiple functional devices on its surface. Furthermore, thin-film lithium niobate chips exhibit low optical loss.

[0070] In some embodiments, the optical chip 400 is a hybrid InP / Si optical chip.

[0071] FIG6 is a schematic diagram of the layout of a hybrid InP / Si optical chip provided according to some embodiments. FIG7 is a partial schematic diagram of a hybrid InP / Si optical chip provided according to some embodiments. As shown in FIG6 and FIG7, the hybrid InP / Si optical chip includes multiple channels, and each channel includes an InP phase modulator 430 and a thermal phase regulator 420. Among them, the InP phase modulator 430 is made of InP material, and the thermal phase regulator 420 is made of silicon material. The InP phase modulator 430 and the thermal phase regulator 420 are connected to each other through a silicon waveguide to form a high-traveling-wave MZM. The hybrid InP / Si optical chip provided by the present disclosure realizes the hybrid integration of Si-based chips and InP materials. The InP material provides high-speed modulation, and the Si base provides highly integrated silicon optical circuits, so that the optical chip 400 can have the high-speed modulation characteristics of the InP material, so that the optical chip 400 can meet the needs of high baud rate modulation.

[0072] In some embodiments, the InP (indium phosphide) phase modulator 430 is an InP-based MZ modulator. An MZ modulator is a modulator based on the electro-optic effect. The electro-optic effect refers to the change in the refractive index of a material caused by an applied electric field (i.e., an external power source).

[0073] In some embodiments, InP-based materials are bonded to Si-based materials, and then InP phase modulators, silicon photonic circuits, and other devices are fabricated on the bonded materials. There is a significant mismatch in the coefficient of thermal expansion (CTE) between the InP-based material platform and the silicon-based photonic material platform, which generates thermal stress. InP-based materials are brittle, and any mechanical and thermal stress can cause reliability issues over temperature and time.

[0074] In some embodiments, the hybrid InP / Si optical chip may include an InP region 410. For example, region C in FIG7 is the InP region 410. The waveguide in region C may include an InP modulation waveguide.

[0075] In some embodiments, the hybrid InP / Si optical chip may include a Si platform 440. The InP region 410 may be located in the Si platform 440 such that the Si platform 440 wraps around the InP region 410 from the front, back, left, right, and bottom.

[0076] In some embodiments, the Si platform 440 may include a region A. A waveguide may be provided on the region A. The waveguide in the region A may be a silicon waveguide 422 .

[0077] In some embodiments, the Si platform 440 may include a region B. An optical coupler 460 may be disposed on the region B.

[0078] A radio frequency pad may be provided on one side of the InP region 410. The radio frequency pad may be located on the Si platform 440. The radio frequency pad may be electrically connected to a driver to input a radio frequency signal, which is a modulated signal.

[0079] An InP phase modulator 430 is disposed within the InP region 410 . The InP phase modulator 430 may include an InP (Indium Phosphide) modulation waveguide 431 . The InP modulation waveguide 431 may be located within the InP region 410 .

[0080] A radio frequency (RF) traveling waveguide 450 can be disposed on top of the hybrid InP / Si optical chip. One end of RF traveling waveguide 450 can be connected to an RF pad. RF traveling waveguide 450 can extend above InP modulation waveguide 431 and across InP region 410 to the other side of InP region 410, coupling RF signals to InP modulation waveguide 431.

[0081] The InP phase modulator 430 may include an RF electrode 432. The RF electrode 432 may be located within the InP region 410. The RF electrode 432 may be disposed above the InP modulation waveguide 431. For example, multiple pairs of RF electrodes 432 may be disposed above the InP modulation waveguide 431, with each pair of RF electrodes 432 connected to a respective RF traveling waveguide 450.

[0082] In the InP phase modulator 430, an InP-MQW optical waveguide can have high-speed modulation efficiency with good quantum basis effect, realize high bandwidth of the InP-based traveling waveguide MZM, and thus meet the high-speed requirements of the optical module.

[0083] The InP area 410 is a prohibited area in the hybrid circuit layout of the hybrid InP / Si optical chip. No devices requiring bonding, such as pads, are set in the InP area 410 to avoid any bonding, mechanical and thermal stresses and eliminate problems caused by temperature and aging.

[0084] In some embodiments, the RF traveling waveguide 450 may include a first RF traveling waveguide 4501. The first RF traveling waveguide 4501 may extend from one side of the InP region 410 to the other side of the InP region 410. The middle of the first RF traveling waveguide 4501 may be located above one edge of the InP modulation waveguide 431.

[0085] In some embodiments, the RF traveling waveguide 450 may include a second RF traveling waveguide 4502. The second RF traveling waveguide 4502 may extend from one side of the InP region 410 to the other side of the InP region 410. The middle of the second RF traveling waveguide 4502 may be located above the other edge of the InP modulation waveguide 431.

[0086] In some embodiments, each pair of RF electrodes 433 may include a first RF electrode 4331 . The first RF electrode 4331 may be located above the InP modulation waveguide 431 . The first RF electrode 4331 may be electrically connected to the first RF traveling waveguide 4501 .

[0087] In some embodiments, each pair of RF electrodes 433 may include a second RF electrode 4332 . The second RF electrode 4332 may be located above the InP modulation waveguide 431 . The second RF electrode 4332 may be electrically connected to the second RF traveling waveguide 4502 .

[0088] The first RF electrode 4331 and the second RF electrode 4332 are spaced apart and located between the first RF traveling waveguide 4501 and the second RF traveling waveguide 4502. For example, the first RF electrode 4331 and the second RF electrode 4332 are uniform thin strips, but the present invention is not limited thereto.

[0089] Figure 8 is a first cross-sectional view of a hybrid InP / Si optical chip provided according to some embodiments. Figure 8 shows the cross-sectional structure of a hybrid InP / Si optical chip in the InP region, with the cross section intercepting the InP region. As shown in Figure 8, in some embodiments, the InP region may include a modulation waveguide. The modulation waveguide may include an InP modulation waveguide 431. A silicon modulation waveguide may be disposed below the InP modulation waveguide. The silicon modulation waveguide may couple light to the InP waveguide 431. The width of the silicon modulation waveguide is much smaller than the width of the InP modulation waveguide 431.

[0090] As shown in FIG8 , the InP modulation waveguide 431 may include a first modulation waveguide layer 4311. The first modulation waveguide layer 4311 may be primarily composed of N-type doped InP material, such that the first modulation waveguide layer 4311 is an n-InP modulation waveguide layer. A silicon modulation waveguide may be disposed below the first modulation waveguide layer 4311, but the size of the silicon modulation waveguide is much smaller than the width of the first modulation waveguide layer 4311.

[0091] An N-electrode 433 may be provided at one end above the first modulation waveguide layer 4311. The N-electrode 433 may be in contact with the upper surface of the first modulation waveguide layer 4311. The N-electrode 433 may be connected to the positive electrode of an external power source to supply power to the N-electrode 433.

[0092] The N-electrode 433 may include a first N-electrode 4331 . The first N-electrode 4331 may be located at a left end above the first modulation waveguide layer 4311 .

[0093] The N-electrode 433 may include a second N-electrode 4332 . The second N-electrode 4332 may be located at a right end above the first modulation waveguide layer 4311 .

[0094] As shown in FIG8 , the InP modulation waveguide 431 may include a second modulation waveguide layer 4312. The second modulation waveguide layer 4312 may be located above the first modulation waveguide layer 4311. The lower surface of the second modulation waveguide layer 4312 may be in contact with the upper surface of the first modulation waveguide layer 4311, so that light can be coupled between the second modulation waveguide layer 4312 and the first modulation waveguide layer 4311. The second modulation waveguide layer 4312 may be primarily made of InGaAsP or InAlGaAs multi-layer quantum well material, so that the second modulation waveguide layer 4312 is a quantum well modulation waveguide layer.

[0095] In some embodiments, the second modulation waveguide layer 4312 may include a fifth sub-modulation waveguide layer. The fifth sub-modulation waveguide layer may be located above the first modulation waveguide layer 4311. The lower surface of the fifth sub-modulation waveguide layer may be in contact with the upper surface of the first modulation waveguide layer 4311, so that light can be coupled between the fifth sub-modulation waveguide layer and the first modulation waveguide layer 4311.

[0096] In some embodiments, the second modulation waveguide layer 4312 may include a sixth sub-modulation waveguide layer. The sixth sub-modulation waveguide layer may be located above the first modulation waveguide layer 4311. The lower surface of the sixth sub-modulation waveguide layer may be in contact with the upper surface of the first modulation waveguide layer 4311, so that light can be coupled between the sixth sub-modulation waveguide layer and the first modulation waveguide layer 4311.

[0097] There may be a gap between the fifth sub-modulation waveguide layer and the sixth sub-modulation waveguide layer.

[0098] The second modulation waveguide layer 4312 may include a plurality of quantum wells. The number of quantum wells in the second modulation waveguide layer 4312 may be greater than a fifth preset value. For example, the fifth preset value may be 40, and the number of quantum wells in the second modulation waveguide layer 4312 is at least 40.

[0099] The greater the number of quantum wells, the greater the refractive index of the quantum well modulation layer. Δφ = 2πΔnL / λ, where Δφ is the phase difference between the two branches, Δn is the refractive index of the quantum well modulation layer, L is the length of the optical waveguide (i.e., the length of the InP modulation waveguide), and λ is the wavelength of light.

[0100] Since Δφ = 2πΔnL / λ, when the phase difference Δφ remains constant, the larger the refractive index Δn of the quantum well modulation waveguide layer, the smaller the length L of the InP modulation waveguide. The smaller the length L of the InP modulation waveguide, the larger the modulation bandwidth. Therefore, including multiple quantum wells in the second modulation waveguide layer 4312 can increase the refractive index of the quantum well modulation waveguide layer, thereby reducing the length of the InP modulation waveguide and increasing the modulation bandwidth.

[0101] Since the conductivity of the second modulation waveguide layer 4312 is relatively low, most of the electrical signals are concentrated in the second modulation waveguide layer 4312 .

[0102] As shown in FIG8 , the InP modulation waveguide 431 may include a third modulation waveguide layer 4313. The third modulation waveguide layer 4313 may be located above the second modulation waveguide layer 4312. The lower surface of the third modulation waveguide layer 4313 may be in contact with the upper surface of the second modulation waveguide layer 4312, so that electrical signals are transmitted to the second modulation waveguide layer 4312 via the third modulation waveguide layer 4313. The third modulation waveguide layer 4313 may be primarily composed of p-type doped InP material, such that the third modulation waveguide layer 4313 is a p-InP modulation waveguide layer.

[0103] In some embodiments, the third modulation waveguide layer 4313 may include a first sub-modulation waveguide layer 43131. The first sub-modulation waveguide layer 43131 may be located above the first sub-modulation waveguide layer. The lower surface of the first sub-modulation waveguide layer 43131 may be in contact with the lower surface of the first sub-modulation waveguide layer, so that electrical signals are transmitted through the first sub-modulation waveguide layer 43131 to the first sub-modulation waveguide layer, i.e., the second modulation waveguide layer 4312.

[0104] In some embodiments, the third modulation waveguide layer 4313 may include a second sub-modulation waveguide layer 43132. The second sub-modulation waveguide layer 43132 may be located above the second sub-modulation waveguide layer. The lower surface of the second sub-modulation waveguide layer 43132 may be in contact with the upper surface of the second sub-modulation waveguide layer, so that electrical signals are transmitted through the second sub-modulation waveguide layer 43132 to the second sub-modulation waveguide layer, i.e., the second modulation waveguide layer 4312.

[0105] A gap may be provided between the second sub-modulation waveguide layer 43132 and the first sub-modulation waveguide layer 43131 , so that electrical signals are transmitted to the second modulation waveguide layer 4312 through the first sub-modulation waveguide layer 43131 and the second sub-modulation waveguide layer 43132 , respectively.

[0106] The first modulation waveguide layer 4311, the second modulation waveguide layer 4312, and the third modulation waveguide layer 4313 form a PIN junction. The PIN junction includes a depletion region (i-region).

[0107] The depletion region may include the second modulation waveguide layer 4312 (i.e., the quantum well modulation waveguide layer), but is not limited to the second modulation waveguide layer 4312. The depletion region includes not only the second modulation waveguide layer 4312 but also a portion of the first modulation waveguide layer 4311 and a portion of the third modulation waveguide layer 4313.

[0108] As shown in FIG8 , the InP modulation waveguide 431 may include a fourth modulation waveguide layer 4314. The fourth modulation waveguide layer 4314 may be located above the third modulation waveguide layer 4313. The lower surface of the fourth modulation waveguide layer 4314 may be in contact with the upper surface of the third modulation waveguide layer 4313. The fourth modulation waveguide layer 4314 may be made of a P-type InGaAs material with a high doping concentration to achieve good contact with the RF electrode 432.

[0109] In some embodiments, the fourth modulation waveguide layer 4314 may include a third sub-modulation waveguide layer 43141. The third sub-modulation waveguide layer 43141 may be located above the first sub-modulation waveguide layer 43131. The lower surface of the third sub-modulation waveguide layer 43141 may be in contact with and connected to the upper surface of the first sub-modulation waveguide layer 43131, so that signals are transmitted to the first sub-modulation waveguide layer 43131 via the third sub-modulation waveguide layer 43141.

[0110] In some embodiments, the fourth modulation waveguide layer 4314 may include a fourth sub-modulation waveguide layer 43142. The fourth sub-modulation waveguide layer 43142 may be located above the second sub-modulation waveguide layer 43132. The lower surface of the fourth sub-modulation waveguide layer 43142 may be in contact with and connected to the upper surface of the second sub-modulation waveguide layer 43132, so that signals are transmitted to the second sub-modulation waveguide layer 43132 via the fourth sub-modulation waveguide layer 43142.

[0111] A gap may be formed between the third sub-modulation waveguide layer 43141 and the fourth sub-modulation waveguide layer 43142 , so that signals are transmitted to the third modulation waveguide layer 4313 through the third sub-modulation waveguide layer 43141 and the fourth sub-modulation waveguide layer 43142 , respectively.

[0112] 8 , an RF electrode 432 may be disposed above the fourth modulation waveguide layer 4314 . The lower surface of the RF electrode 432 may contact the upper surface of the third modulation waveguide layer 4313 , so that electrical signals can be transmitted from the RF electrode 432 to the fourth modulation waveguide layer 4314 .

[0113] Since the RF electrode 432 is also a P-electrode, which can be connected not only to the RF pad but also to the negative terminal of an external power supply, the electrical signal transmitted from the RF electrode 432 to the fourth modulation waveguide layer 4314 includes not only the modulation signal but also the reverse bias voltage.

[0114] In some embodiments, the first RF electrode 4321 (i.e., the first P-electrode) may be located above the third sub-modulation waveguide layer 43141. The first RF electrode 4321 may be in contact with the upper surface of the third sub-modulation waveguide layer 43141, so that the RF signal of the first RF electrode 4321 is transmitted to the first sub-modulation waveguide layer 43131 through the third sub-modulation waveguide layer 43141.

[0115] In some embodiments, the second RF electrode 4322 (i.e., the second P-electrode) may be located above the fourth sub-modulation waveguide layer 43142. The second RF electrode 4322 may be in contact with the upper surface of the fourth sub-modulation waveguide layer 43142, so that the RF signal of the second RF electrode 4322 is transmitted to the second sub-modulation waveguide layer 43132 through the fourth sub-modulation waveguide layer 43142.

[0116] The first P electrode and the second P electrode are respectively loaded with modulation signals. By controlling the change of the external electric field (i.e., the reverse bias voltage provided to the P electrode by the external power supply), the carriers of the PIN junction are changed, thereby changing the refractive index of the quantum well modulation layer, causing a phase difference between the first modulation waveguide and the second modulation waveguide. The output light intensity varies with the phase difference, that is, the output light intensity is modulated by the modulated electrical signal. After modulation, the modulated electrical signal becomes the output light intensity of the modulated optical signal, thereby achieving modulation. Among them, the first modulation waveguide is half of the InP modulation waveguide 431 where the first sub-modulation waveguide layer 43131 is located, and the second modulation waveguide is the other half of the InP modulation waveguide 431 where the second sub-modulation waveguide layer 43132 is located.

[0117] Figure 9 shows a graph of the relationship between the quantum well absorption coefficient and wavelength, according to some embodiments. In Figure 9 , the horizontal axis represents wavelength, and the vertical axis represents the absorption coefficient. The solid line represents the absorption coefficient curve when the reverse bias voltage is 0V, and the dashed line represents the absorption coefficient curve when the reverse bias voltage is -3V. As shown in Figure 9 , as the reverse bias voltage increases, the quantum well absorption coefficient redshifts, meaning that the quantum well absorption coefficient increases. As the quantum well absorption increases, the quantum well absorption loss of the PIN junction increases.

[0118] As shown in Figure 9, the exciton absorption peak of the quantum well is at 1382 nm, and its absorption coefficient at 1550 nm is 1 / cm. When the voltage is increased to -3 volts, its exciton absorption peak shifts to 1403 nm, and its absorption coefficient at 550 nm is 1.4 / cm.

[0119] Figure 10 shows the width of the depletion region of a PIN junction when the reverse bias voltage is 0 V, according to some embodiments. Figure 11 shows the width of the depletion region of a PIN junction when the reverse bias voltage is -3 V, according to some embodiments. As shown in Figures 10 and 11, as the reverse bias voltage increases, the width of the depletion region increases, resulting in a decrease in carrier absorption loss in the PIN junction.

[0120] If the number of quantum wells in the second modulation waveguide layer is small, changes in the reverse bias voltage of the external power supply have a small impact on the quantum well absorption coefficient, and there is no need to consider compensating for the increase in quantum well absorption loss. However, as the number of quantum wells increases, changes in the reverse bias voltage of the external power supply will affect the change in the quantum absorption coefficient, resulting in increased quantum well absorption loss in the PIN junction. Excessive quantum well absorption loss will produce residual amplitude modulation, which will be added to the phase modulation of the InP modulation waveguide, affecting the accuracy of the phase modulation of the InP modulation waveguide. To solve this problem, in some embodiments, the reduction in carrier absorption loss is adjusted by optimizing the P doping concentration of the third modulation waveguide layer 4313 and the N doping concentration of the first modulation waveguide layer 4311 to compensate for the increase in quantum well absorption loss, avoid the generation of residual amplitude modulation, and improve the accuracy of phase modulation.

[0121] Due to the same doping concentration, the absorption loss of the P-doped third modulation waveguide layer 4313 is greater than the absorption loss of the N-doped first modulation waveguide layer 4311 (approximately 10 times). Therefore, in some embodiments, the reduction in carrier absorption loss is adjusted by optimizing the P-doping concentration of the third modulation waveguide layer 4313 to compensate for the increase in quantum well absorption loss.

[0122] If the P doping concentration of the third modulation waveguide layer 4313 is too low, the reverse bias voltage will cause the depletion region to become too wide, and more of the reverse bias voltage will fall outside the quantum well modulation waveguide layer, reducing the modulation efficiency of the InP modulation waveguide 431. If the P doping concentration of the third modulation waveguide layer 4313 is too high, the high P doping concentration will reduce the depletion region width, increase carrier absorption loss, and lead to higher optical loss. Therefore, in some embodiments, the P doping concentration of the third modulation waveguide layer 4313 can be within a first preset range. The first preset range can be 2-6e17 cm-3. For example, the first preset range can be 2-4e17 cm-3. The first preset range can be 4-6e17 cm-3.

[0123] In some embodiments, the P doping concentration of the first sub-modulation waveguide layer 43131 can be in the range of 2-6e17 cm-3.

[0124] In some embodiments, the P doping concentration of the second sub-modulation waveguide layer 43132 can be in the range of 2-6e17 cm-3.

[0125] If the N-doping concentration of the first modulation waveguide layer 4311 is too low, the reverse bias voltage will cause the depletion region to become too wide, and more of the reverse bias voltage will fall outside the quantum well modulation waveguide layer, reducing the modulation efficiency of the InP modulation waveguide 431. If the N-doping concentration of the first modulation waveguide layer 431 is too high, the high N-doping concentration will reduce the depletion region width, increase carrier absorption loss, and lead to higher optical loss. Therefore, in some embodiments, the N-doping concentration of the first modulation waveguide layer 431 can be within a second preset range. The second preset range can be 1-5e18 cm-3. For example, the second preset range can be 1-3e18 cm-3. The second preset range can be 3-5e18 cm-3.

[0126] Figure 12 is a second cross-sectional view of a hybrid InP / Si optical chip according to some embodiments. Figure 12 shows the cross-sectional structure of a hybrid InP / Si optical chip outside the InP region, excluding the InP region. As shown in Figure 12 , in some embodiments, Si platform 440 may include a silicon substrate 441. Silicon substrate 441 may include a base layer 4411. A BOX layer 4412 may be disposed above base layer 4411.

[0127] As shown in FIG12 , a plurality of silicon waveguides may be provided on a silicon substrate 441. The silicon waveguides may be located above a BOX layer 4412. The silicon waveguides may include an input and output waveguide 442.

[0128] The input-output waveguide 442 may include a first input-output waveguide layer 4421 . The first input-output waveguide layer 4421 may be located above the BOX layer 4412 .

[0129] The input / output waveguide 442 may include a second input / output waveguide layer 4422. The second input / output waveguide layer 4422 may be located above the first input / output waveguide layer 4421. The width of the second input / output waveguide layer 4422 may be smaller than the length of the first input / output waveguide layer 4421.

[0130] The input-output waveguide 442 includes a first input-output waveguide and a second input-output waveguide. The first input-output waveguide and the second input-output waveguide are respectively located on both sides of the InP region. The light emitted by the light source that does not carry data is transmitted to the InP region through the first input-output waveguide. The light that does not carry data is modulated into light that carries data in the InP region. The light that carries data is transmitted out of the optical chip through the second input-output waveguide.

[0131] The first input and output waveguide is a silicon waveguide, and the first input and output waveguide and the silicon modulation waveguide are located on the same layer of the optical chip. Light can be completely transmitted from the first input and output waveguide to the silicon modulation waveguide. However, because the width of the silicon modulation waveguide is much smaller than the width of the InP modulation waveguide 431, the refractive index difference between the InP modulation waveguide 431 and the silicon modulation waveguide is large, resulting in a large difference in the effective refractive index between the silicon modulation waveguide and the InP modulation waveguide 431. The large difference in the effective refractive index between the silicon modulation waveguide and the InP modulation waveguide 431 means that the propagation constants of the silicon modulation waveguide and the InP modulation waveguide 431 differ significantly, making it difficult to couple light between the silicon modulation waveguide and the InP modulation waveguide 431, resulting in low coupling efficiency.

[0132] To address this issue, in some embodiments, an optical coupler is provided between the input and output waveguides and the modulation waveguide. The optical coupler includes a silicon coupling waveguide layer and an InP coupling waveguide layer. The InP coupling waveguide layer is located above the silicon coupling waveguide layer. Both the silicon coupling waveguide layer and the InP coupling waveguide layer include a gradient region. The gradient region of the InP coupling waveguide layer overlaps with the silicon coupling waveguide layer. From the input and output waveguides to the modulation waveguide, the gradient region of the silicon coupling waveguide layer gradually decreases in width, while the gradient region of the InP coupling waveguide layer gradually increases in width. That is, the gradient region of the silicon coupling waveguide layer decreases in width in the same direction as the gradient region of the InP coupling waveguide layer increases in width.

[0133] The width of the gradient region of the silicon coupling waveguide layer gradually decreases, and the effective refractive index of the gradient region of the silicon coupling waveguide layer gradually decreases. The width of the gradient region of the InP coupling waveguide layer gradually increases, and the effective refractive index of the gradient region of the InP coupling waveguide layer gradually increases.

[0134] There is an overlapping area between the gradient zone of the indium phosphide coupling waveguide layer and the gradient zone of the silicon coupling waveguide layer. The effective refractive index of the gradient zone of the silicon coupling waveguide layer gradually decreases, while the effective refractive index of the gradient zone of the indium phosphide coupling waveguide layer gradually increases. When the effective refractive indices of the two are similar, light is almost completely coupled from the silicon coupling waveguide layer to the InP coupling waveguide layer, or light is almost completely coupled from the InP coupling waveguide layer to the silicon coupling waveguide layer, thereby improving the optical coupling efficiency between the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer.

[0135] However, since the effective refractive index of the two layers gradually increases and decreases, respectively, once light is coupled from the coupling waveguide layer with a gradually decreasing effective refractive index to the coupling waveguide layer with a gradually increasing effective refractive index, the light will no longer be coupled from the coupling waveguide layer with a gradually increasing effective refractive index to the coupling waveguide layer with a gradually decreasing effective refractive index. For example, if the effective refractive index of the silicon coupling waveguide layer gradually decreases and the effective refractive index of the indium phosphide coupling waveguide layer gradually increases, light coupled from the silicon coupling waveguide layer to the indium phosphide coupling waveguide layer will no longer be coupled from the indium phosphide coupling waveguide layer to the silicon coupling waveguide layer.

[0136] For the optical coupler between the first input and output waveguide and the InP region, the effective refractive index of the gradient region of the silicon coupling waveguide layer gradually decreases from the first input and output waveguide to the modulation waveguide, while the effective refractive index of the gradient region of the InP coupling waveguide layer gradually increases. This allows light to be almost completely coupled from the silicon coupling waveguide layer to the InP coupling waveguide layer when their effective refractive indices are similar, thereby improving the optical coupling efficiency between the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer.

[0137] For the optical coupler between the InP region and the second input and output waveguide, the effective refractive index of the gradient region of the silicon coupling waveguide layer gradually increases from the modulation waveguide to the second input and output waveguide, while the effective refractive index of the gradient region of the InP coupling waveguide layer gradually decreases, so that when the effective refractive indices of the two are similar, light is almost completely coupled from the InP coupling waveguide layer to the silicon coupling waveguide layer, thereby improving the optical coupling efficiency between the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer.

[0138] The optical coupler is specifically described by taking the optical coupler between the first input and output waveguide and the InP region as an example.

[0139] Figure 13 is a third cross-sectional view of a hybrid InP / Si optical chip according to some embodiments. Figure 13 illustrates a cross-sectional structure of a hybrid InP / Si optical chip, with the cross section taken through an optical coupler. Figure 13 illustrates a hybrid InP / Si optical chip taken through the optical coupler. As shown in Figure 13, optical coupler 460 can be disposed on silicon substrate 441. Optical coupler 460 can extend beyond the second BOX layer 4412 of silicon substrate 441.

[0140] As shown in Figure 13, in some embodiments, the optical coupler 460 may include a silicon coupling waveguide layer. One end of the silicon coupling waveguide layer may be connected to one end of the input / output waveguide 442. The other end of the silicon coupling waveguide layer may be connected to one end of the silicon modulation waveguide.

[0141] In some embodiments, the silicon coupling waveguide layer includes a first silicon coupling waveguide layer 4601. One end of the first silicon coupling waveguide layer 4601 may be connected to one end of the first input / output waveguide layer 4421. The other end of the first silicon coupling waveguide layer 4601 may be connected to a portion of the silicon modulation waveguide.

[0142] In some embodiments, the silicon coupling waveguide layer includes a second silicon coupling waveguide layer 4602. One end of the second silicon coupling waveguide layer 4602 can be connected to one end of the second input / output waveguide layer 4422. The other end of the second silicon coupling waveguide layer 4602 can be connected to another portion of the silicon modulation waveguide. The second silicon coupling waveguide layer 4602 can be located above the first silicon coupling waveguide layer 4601. The lower surface of the second silicon coupling waveguide layer 4602 can be in contact with and connected to the upper surface of the first silicon coupling waveguide layer 4601. The width of the second silicon coupling waveguide layer 4602 is smaller than the width of the first silicon coupling waveguide layer 4601.

[0143] In some embodiments, the width of the first silicon coupling waveguide layer 4601 may be greater than the width of the second silicon coupling waveguide layer 4602 .

[0144] In some embodiments, the height of the first silicon-coupling waveguide layer 4601 may be smaller than the height of the second silicon-coupling waveguide layer 4602 .

[0145] As shown in FIG13 , in some embodiments, the optical coupler 460 may include an InP coupling waveguide layer. One end of the InP coupling waveguide layer may be suspended above the input and output waveguides, and the other end of the InP coupling waveguide layer may be connected to the InP modulation waveguide 431. The InP coupling waveguide layer may be located above the silicon coupling waveguide layer. The silicon coupling waveguide layer may couple light to the InP coupling waveguide layer.

[0146] In some embodiments, the InP coupling waveguide layer may include an n-InP coupling waveguide layer 4603. The n-InP coupling waveguide layer 4603 may be located above the second silicon coupling waveguide layer 4602. The n-InP coupling waveguide layer 4603 may be mainly composed of N-type doped InP material.

[0147] In some embodiments, the InP coupling waveguide layer may include a quantum well coupling waveguide layer 4604. The quantum well coupling waveguide layer 4604 may be located above the n-InP coupling waveguide layer 4603. The lower surface of the quantum well coupling waveguide layer 4604 may be in contact with the upper surface of the n-InP coupling waveguide layer 4603. The quantum well coupling waveguide layer 4604 may be primarily composed of InGaAsP or InAlGaAs multi-layer quantum well material.

[0148] In some embodiments, the width of the n-InP coupling waveguide layer 4603 may be greater than the width of the quantum well coupling waveguide layer 4604 .

[0149] In some embodiments, the height of the n-InP coupling waveguide layer 4603 may be smaller than the height of the quantum well coupling waveguide layer 4604 .

[0150] In some embodiments, the InP coupling waveguide layer may include a p-InP coupling waveguide layer 4605. The p-InP coupling waveguide layer 4605 may be located above the quantum well coupling waveguide layer 4604. The lower surface of the p-InP coupling waveguide layer 4605 may be in contact with the upper surface of the quantum well coupling waveguide layer 4604. The p-InP coupling waveguide layer 4605 may be mainly composed of P-type doped InP material.

[0151] In some embodiments, the width of the quantum well coupling waveguide layer 4604 may be greater than the width of the p-InP coupling waveguide layer 4605 .

[0152] In some embodiments, the height of the quantum well coupling waveguide layer 4604 may be smaller than the height of the p-InP coupling waveguide layer 4605 .

[0153] Due to the different lattice constants of the silicon-coupled waveguide layer and the InP-coupled waveguide layer, the stress between the two layers is relatively high. To relieve the stress between the two layers, a gap is provided between the two layers. Specifically, a buffer layer 4606 is provided between the two layers. Buffer layer 4606 may be a SiO2 filling layer. Buffer layer 4606 is used to relieve the stress between the two layers, thereby providing a buffering effect.

[0154] In some embodiments, the height of the buffer layer 4606 is 10-100 nm, for example, the height of the buffer layer 4606 is 10-30 nm, the height of the buffer layer 4606 is 30-70 nm, and the height of the buffer layer 4606 is 70-100 nm.

[0155] The silicon coupling waveguide layer and the InP coupling waveguide layer are embedded in SiO 2 (silicon dioxide) so that the silicon coupling waveguide layer and the InP coupling waveguide layer are surrounded by SiO 2 .

[0156] FIG14 is a top view of a first silicon-coupled waveguide layer provided in accordance with some embodiments. As shown in FIG14 and Table 1, in some embodiments, the first silicon-coupled waveguide layer 4601 may include a first gradient region. The width of the first gradient region may gradually decrease from the input and output waveguides to the modulation waveguide (i.e., from left to right). The width of the first gradient region may gradually decrease, and the effective refractive index of the first gradient region may gradually increase.

[0157] As shown in FIG14 and Table 1, the first gradient region may include a first Si slab taper. The length of the first Si slab taper is 12 μm. The width of the first Si slab taper may be changed from 5.5 μm to 4.5 μm.

[0158] The first gradient region may include a second silicon substrate gradient strip. The second silicon substrate gradient strip may have a length of 10 μm and a width changed from 4.5 μm to 3.5 μm.

[0159] The first gradient region may include a third silicon substrate gradient strip. The length of the third silicon substrate gradient strip may be 12 μm. The width of the third silicon substrate gradient strip may be changed from 3.5 μm to 2.5 μm.

[0160] The first gradient region may include a fourth silicon substrate gradient strip. The fourth silicon substrate gradient strip may have a length of 14 μm and a width changed from 2.5 μm to 1.5 μm.

[0161] The first gradient region may include a fifth silicon substrate gradient strip, the length of the fifth silicon substrate gradient strip may be 16 μm, and the width of the fifth silicon substrate gradient strip may be changed from 1.5 μm to 0.9 μm.

[0162] The first gradient region may include a sixth silicon substrate gradient strip, the length of the sixth silicon substrate gradient strip may be 16 μm, and the width of the sixth silicon substrate gradient strip may be changed from 0.9 μm to 0.6 μm.

[0163] Table 1 is the parameter table of silicon substrate gradient strip

[0164] FIG15 is a top view of a second silicon-coupled waveguide layer provided in accordance with some embodiments. As shown in FIG15 and Table 2, the second silicon-coupled waveguide layer 4602 may include a second gradient region. The width of the second gradient region gradually decreases from the input and output waveguides to the modulation waveguide (i.e., from left to right). The width of the second gradient region gradually decreases, and the effective refractive index of the second gradient region gradually increases.

[0165] As shown in FIG15 and Table 2, the second gradient region may include a first silicon ridge taper. The length of the first silicon ridge taper is 12 μm. The width of the first silicon ridge taper may be changed from 2.0 μm to 1.6 μm.

[0166] The second gradient region may include a second silicon ridge gradient strip. The second silicon ridge gradient strip may have a length of 10 μm and a width changed from 1.6 μm to 1.2 μm.

[0167] The second gradient region may include a third silicon ridge gradient strip. The third silicon ridge gradient strip may have a length of 12 μm and a width changed from 1.2 μm to 0.9 μm.

[0168] The second gradient region may include a fourth silicon ridge gradient strip. The fourth silicon ridge gradient strip may have a length of 14 μm and a width changed from 0.9 μm to 0.6 μm.

[0169] The second gradient region may include a fifth silicon ridge gradient strip. The length of the fifth silicon ridge gradient strip may be 16 μm. The width of the fifth silicon ridge gradient strip may be changed from 0.6 μm to 0.3 μm.

[0170] Table 2 is the parameter table of silicon ridge gradient strip

[0171] FIG16 is a top view of a quantum well coupling waveguide layer according to some embodiments. As shown in FIG16 and Table 3, the quantum well coupling waveguide layer 4604 may include a third gradient region. The width of the third gradient region gradually increases from the input and output waveguides to the modulation waveguide (i.e., from left to right). As the width of the third gradient region gradually increases, the effective refractive index of the third gradient region gradually increases.

[0172] As shown in FIG16 and Table 3, the third gradient region may include a first quantum well step surface gradient strip (MQWs Mesa taper). The length of the first quantum well step surface gradient strip is 10 μm. The width of the first quantum well step surface gradient strip may be changed from 0.2 μm to 0.4 μm.

[0173] The third gradient region may include a second quantum well step surface gradient strip. The length of the second quantum well step surface gradient strip may be 15 μm. The width of the second quantum well step surface gradient strip may be changed from 0.4 μm to 0.8 μm.

[0174] The third gradient region may include a third quantum well step surface gradient strip. The length of the third quantum well step surface gradient strip may be 17.5 μm. The width of the third quantum well step surface gradient strip may be changed from 0.8 μm to 1.6 μm.

[0175] The third gradient region may include a fourth quantum well step surface gradient strip. The fourth quantum well step surface gradient strip may have a length of 22.5 μm and a width changed from 1.6 μm to 2.4 μm.

[0176] The third gradient region may include a fifth quantum well step surface gradient strip. The fifth quantum well step surface gradient strip may have a length of 27.5 μm and a width changed from 2.4 μm to 3.2 μm.

[0177] The third gradient region may include a sixth quantum well step surface gradient strip. The sixth quantum well step surface gradient strip may have a length of 27.5 μm. The fifth quantum well step surface gradient strip may have a width changed from 3.2 μm to 6.2 μm.

[0178] Table 3 is the parameter table of quantum well step surface gradient strip

[0179] FIG17 is a top view of a p-InP coupled waveguide layer according to some embodiments. As shown in FIG17 and Table 4, the p-InP coupled waveguide layer 4605 may include a fourth gradient region. The width of the fourth gradient region gradually increases from the input and output waveguides to the modulation waveguide (i.e., from left to right). The width of the fourth gradient region gradually increases, and the effective refractive index of the fourth gradient region gradually increases.

[0180] As shown in FIG13 and Table 4, the fourth gradient region may include a first InP ridge waveguide gradient strip (InP ridge taper). The width of the first InP ridge waveguide gradient strip may be changed from 0.2 μm to 0.4 μm.

[0181] The third gradient region may include a second indium phosphide ridge waveguide gradient strip, and the width of the second indium phosphide ridge waveguide gradient strip may be changed from 0.4 μm to 0.8 μm.

[0182] The third gradient region may include a third indium phosphide ridge waveguide gradient strip, and the width of the third indium phosphide ridge waveguide gradient strip may be changed from 0.8 μm to 1.6 μm.

[0183] The third gradient region may include a fourth indium phosphide ridge waveguide gradient strip, and the width of the fourth indium phosphide ridge waveguide gradient strip may be changed from 1.6 μm to 2.4 μm.

[0184] Table 4 is the parameter table of the gradient strip of InP ridge waveguide

[0185] Figure 18 shows an overlapping diagram of a first silicon-coupled waveguide layer, a second silicon-coupled waveguide layer, a quantum-coupled waveguide layer, and a p-InP-coupled waveguide layer, according to some embodiments. Figure 19 shows a combined diagram of a first silicon-coupled waveguide layer, a second silicon-coupled waveguide layer, a quantum-coupled waveguide layer, and a p-InP-coupled waveguide layer, according to some embodiments. As shown in Figures 18 and 19, from left to right, the width of the gradient region of the silicon-coupled waveguide layer decreases, while the width of the gradient region of the InP-coupled waveguide layer increases. There is an overlap between the gradient regions of the silicon-coupled waveguide layer and the InP-coupled waveguide layer.

[0186] The width of the gradient zone of the silicon coupling waveguide layer gradually decreases, resulting in a gradual decrease in the effective refractive index of the gradient zone of the silicon coupling waveguide layer. The width of the gradient zone of the InP coupling waveguide layer gradually increases, resulting in an increase in the effective refractive index of the gradient zone of the InP coupling waveguide layer. The effective refractive index of the gradient zone of the silicon coupling waveguide layer gradually decreases, while the effective refractive index of the gradient zone of the InP coupling waveguide layer gradually increases. When the effective refractive indices of the two are similar, light can be coupled between the silicon coupling waveguide layer and the InP coupling waveguide layer. However, due to the increase in the effective refractive index of the InP coupling waveguide layer, after light is coupled from the silicon coupling waveguide layer to the InP coupling waveguide layer, it will no longer be coupled from the InP coupling waveguide layer to the silicon coupling waveguide layer.

[0187] As shown in FIG. 18 and FIG. 19 , in some embodiments, the starting point of the quantum well coupling waveguide layer and the starting point of the p-indium phosphide coupling waveguide layer may both be located above the first end of the silicon coupling waveguide layer.

[0188] As shown in FIG. 18 and FIG. 19 , in some embodiments, the end point of the quantum well coupling waveguide layer and the end point of the p-InP coupling waveguide layer may both be located above the second end of the silicon coupling waveguide layer.

[0189] The starting point of the quantum well coupling waveguide layer and the starting point of the p-Indium Phosphide coupling waveguide layer may both be located above the first end of the silicon coupling waveguide layer, and the ending point of the quantum well coupling waveguide layer and the ending point of the p-Indium Phosphide coupling waveguide layer may both be located above the second end of the silicon coupling waveguide layer, such that an overlapping region exists between the Indium Phosphide coupling waveguide layer and the silicon coupling waveguide layer. The width of the first end of the silicon coupling waveguide layer is greater than the width of the second end of the silicon coupling waveguide layer.

[0190] As shown in FIG. 18 and FIG. 19 , the first gradient region of the first silicon coupling waveguide layer 4601 and the second gradient region of the second silicon coupling waveguide layer 4602 have the same width reduction direction.

[0191] As shown in FIG. 18 and FIG. 19 , the width increasing direction of the third gradient region of the quantum well coupling waveguide layer 4604 and the fourth gradient region of the p-InP coupling waveguide layer 4605 are the same.

[0192] As shown in Figures 18 and 19, the direction in which the width of the first gradient zone of the first silicon coupling waveguide layer 4601 and the gradient zone of the second silicon coupling waveguide layer 4602 decreases is the same as the direction in which the width of the third gradient zone of the quantum well coupling waveguide layer 4604 and the fourth gradient zone of the p-InP coupling waveguide layer 4605 increases.

[0193] Since the height of the n-InP coupling waveguide layer 4603 is much smaller than the height of the quantum well coupling waveguide layer 4604, the shape of the n-InP coupling waveguide layer 4603 has little effect on light coupling. Therefore, in some embodiments, the shape of the n-InP coupling waveguide layer 4603 is rectangular.

[0194] In some embodiments, the width of the n-InP coupling waveguide layer 4603 gradually increases from the input and output waveguides to the modulation waveguide, so that the shape of the n-InP coupling waveguide layer 4603 is tapered.

[0195] From the input and output waveguides to the modulation waveguide, the width of the n-InP coupling waveguide layer 4603 gradually increases, that is, the width increase direction of the n-InP coupling waveguide layer 4603 is the same as the width increase direction of the third gradient zone of the quantum well coupling waveguide layer 4604 or the fourth gradient zone of the p-InP coupling waveguide layer 4605, so that the boundary surface between the n-InP coupling waveguide layer 4603 and the buffer layer 4606 is a slope to minimize the light from returning along the original path.

[0196] Figure 20 is a diagram illustrating light distribution in an optical coupler according to some embodiments. As shown in Figure 20 , after light is coupled from the silicon coupling waveguide layer to the InP coupling waveguide layer, the light is mainly distributed in the quantum well coupling waveguide layer.

[0197] Figure 21 shows the FDTD simulation results of an optical coupler according to some embodiments. The horizontal axis in Figure 21 represents wavelength, and the vertical axis represents power transmission loss. As shown in Figure 21 , the optical coupler's light loss (i.e., transmission loss) is relatively low, primarily between 0.06 and 0.08 dB, demonstrating the optical coupler's excellent coupling performance.

[0198] FIG22 is a schematic diagram of the growth of an optical coupler according to some embodiments. As shown in FIG22 , the growth process of the optical coupler is as follows: (1) After the silicon substrate 441 is bonded to the long strip of silicon coupling waveguide layer, a first silicon coupling waveguide layer 4601 is first etched on the silicon substrate 441 using an etching process, and a second silicon coupling waveguide layer 4602 is etched on the first silicon coupling waveguide layer 4601 using an etching process. (2) After the second silicon coupling waveguide layer 4602 is bonded to the long strip of indium phosphide coupling waveguide layer, an n-InP coupling waveguide layer 4603 is first etched on the second silicon coupling waveguide layer 4602 using an etching process, and a quantum well coupling waveguide layer 4604 is etched on the n-InP coupling waveguide layer 4603 using an etching process, and finally a p-InP coupling waveguide layer is etched on the quantum well coupling waveguide layer 4604 using an etching process.

[0199] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. An optical module, comprising: circuit boards; an optical chip, electrically connected to the circuit board, and configured to modulate and generate an optical signal; The optical chip includes a silicon platform, on which input and output waveguides and an indium phosphide modulation waveguide are provided. The input and output waveguides are silicon waveguides, and an optical coupler is provided between the input and output waveguides and the indium phosphide modulation waveguide. The optical coupler includes a silicon coupling waveguide layer and an indium phosphide coupling waveguide layer, the indium phosphide coupling waveguide layer being located above the silicon coupling waveguide layer. Both the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer include a gradient region, and the gradient region of the indium phosphide coupling waveguide layer overlaps with the gradient region of the silicon coupling waveguide layer. One end of the silicon coupling waveguide layer is connected to the input and output waveguides, and one end of the indium phosphide coupling waveguide layer is connected to the indium phosphide modulation waveguide. From the input and output waveguides to the indium phosphide modulation waveguide, the gradient region of the silicon coupling waveguide layer gradually decreases in width, while the gradient region of the indium phosphide coupling waveguide layer gradually increases in width. The indium phosphide modulation waveguide includes a first modulation waveguide layer, a second modulation waveguide layer, and a third modulation waveguide layer. The first modulation waveguide layer is located on the silicon platform, the second modulation waveguide layer is located above the first modulation waveguide layer, and the third modulation waveguide layer is located above the second modulation waveguide layer. The second modulation waveguide layer is in contact with and connected to the first modulation waveguide layer and the third modulation waveguide layer, respectively. The second modulation waveguide layer includes a plurality of quantum wells, the P doping concentration of the third modulation waveguide layer is within a first preset range, and the N doping concentration of the first modulation waveguide layer is within a second preset range to compensate for absorption loss of the quantum wells.

2. The optical module according to claim 1, wherein: The number of the quantum wells is at least greater than or equal to 40, the first preset range is 2-6e17 cm-3, and the second preset range is 1-5e18 cm-3.

3. The optical module according to claim 1, wherein: The indium phosphide modulation waveguide further includes a fourth modulation waveguide layer, the fourth modulation waveguide layer being located above the third modulation waveguide layer, a P electrode being provided above the fourth modulation waveguide layer, and the fourth modulation waveguide layer being in contact with and connected to the third modulation waveguide layer and the P electrode respectively; The third modulation waveguide layer includes a first sub-modulation waveguide layer and a second sub-modulation waveguide layer, wherein the first sub-modulation waveguide layer and the second sub-modulation waveguide layer are arranged in parallel, a gap is formed between the first sub-modulation waveguide layer and the second sub-modulation waveguide layer, and the first sub-modulation waveguide layer and the second sub-modulation waveguide layer are respectively in contact with and connected to the second modulation waveguide layer; The fourth modulation waveguide layer includes a third sub-modulation waveguide layer and a fourth sub-modulation waveguide layer. The third sub-modulation waveguide layer and the fourth sub-modulation waveguide layer are arranged in parallel with a gap between the third sub-modulation waveguide layer and the fourth sub-modulation waveguide layer. The third sub-modulation waveguide layer is in contact with and connected to the first sub-modulation waveguide layer, and the fourth sub-modulation waveguide layer is in contact with and connected to the second sub-modulation waveguide layer.

4. The optical module according to claim 1, wherein: The indium phosphide coupling waveguide layer includes an n-indium phosphide coupling waveguide layer, a quantum well coupling waveguide layer, and a p-indium phosphide coupling waveguide layer. The quantum well coupling waveguide layer and the p-indium phosphide coupling waveguide layer both include a gradient region. The quantum well coupling waveguide layer is located above the n-indium phosphide coupling waveguide layer. The p-indium phosphide coupling waveguide layer is located above the quantum well coupling waveguide layer. The n-indium phosphide coupling waveguide layer and the p-indium phosphide coupling waveguide layer are respectively in contact with and connected to the quantum well coupling waveguide layer. From the input and output waveguides to the indium phosphide modulation waveguide, the width of the gradient region of the quantum well coupling waveguide layer gradually increases, and the width of the gradient region of the p-indium phosphide coupling waveguide layer gradually increases.

5. The optical module according to claim 4, wherein: The silicon coupling waveguide layer includes a first silicon coupling waveguide layer and a second silicon coupling waveguide layer, wherein the first silicon coupling waveguide layer and the second silicon coupling waveguide layer both include a gradient region, the second silicon coupling waveguide layer is located above the first silicon coupling waveguide layer, and the first silicon coupling waveguide layer is in contact with and connected to the second coupling waveguide layer; From the input and output waveguides to the modulation waveguide, widths of the gradient region of the first silicon coupling waveguide layer and the gradient region of the second silicon coupling waveguide layer gradually decrease.

6. The optical module according to claim 5, wherein: The width of the first silicon coupling waveguide layer is greater than the width of the second silicon coupling waveguide layer, the width of the n-indium phosphide coupling waveguide layer is greater than the width of the quantum well coupling waveguide layer, and the width of the quantum well coupling layer is greater than the width of the p-indium phosphide coupling waveguide layer; The height of the first silicon coupling waveguide layer is smaller than the height of the second silicon coupling waveguide layer, the height of the n-indium phosphide coupling waveguide layer is smaller than the height of the quantum well coupling waveguide layer, and the height of the quantum well coupling layer is smaller than the height of the p-indium phosphide coupling waveguide layer.

7. The optical module according to claim 4, wherein: The starting points of the quantum well coupling waveguide layer and the p-indium phosphide coupling waveguide layer are located above the first end of the silicon coupling waveguide layer, and the end points of the quantum well coupling waveguide layer and the p-indium phosphide coupling waveguide layer are both located above the second end of the silicon coupling waveguide layer, so that an overlapping area exists between the indium phosphide coupling waveguide layer and the silicon coupling waveguide layer; wherein the width of the first end of the silicon coupling waveguide layer is greater than the width of the second end of the silicon coupling waveguide layer.

8. An optical chip, comprising: A silicon platform is provided with input and output waveguides and an indium phosphide modulation waveguide; the input and output waveguides are silicon waveguides, and an optical coupler is provided between the input and output waveguides and the indium phosphide modulation waveguide; The optical coupler includes a silicon coupling waveguide layer and an indium phosphide coupling waveguide layer, the indium phosphide coupling waveguide layer being located above the silicon coupling waveguide layer. Both the silicon coupling waveguide layer and the indium phosphide coupling waveguide layer include a gradient region, and the gradient region of the indium phosphide coupling waveguide layer overlaps with the gradient region of the silicon coupling waveguide layer. One end of the silicon coupling waveguide layer is connected to the input and output waveguides, and one end of the indium phosphide coupling waveguide layer is connected to the indium phosphide modulation waveguide. The direction in which the gradient region of the silicon coupling waveguide layer decreases is the same as the direction in which the gradient region of the indium phosphide coupling waveguide layer increases. The indium phosphide modulation waveguide includes a first modulation waveguide layer, a second modulation waveguide layer, and a third modulation waveguide layer. The first modulation waveguide layer is located on the silicon platform, the second modulation waveguide layer is located above the first modulation waveguide layer, and the third modulation waveguide layer is located above the second modulation waveguide layer. The second modulation waveguide layer is in contact with and connected to the first modulation waveguide layer and the third modulation waveguide layer, respectively. The second modulation waveguide layer includes a plurality of quantum wells, the P doping concentration of the third modulation waveguide layer is within a first preset range, and the N doping concentration of the first modulation waveguide layer is within a second preset range to compensate for absorption loss of the quantum wells.

9. The optical chip according to claim 8, wherein: The first preset range is 2-6e17cm -3 , the second preset range is 1-5e18cm -3 .

10. The optical chip according to claim 8, wherein: The width increasing direction of the n-InP coupling waveguide layer is the same as the width increasing direction of the quantum well coupling waveguide layer.

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