A component carrier assembly and method for manufacturing a component carrier assembly

Abstract

The invention relates to component carrier assembly (1) comprising a component carrier (2), comprising a stack (4) said stack (4) comprising at least one electrically conductive layer structure (5, 6) and at least one electrically insulating layer structure (7). It further comprises a component (10), wherein a cavity (8) is formed within the stack (4), and the component (10) is embedded within the cavity (8) by means of an embedding mass (9), wherein the embedding mass (9) is formed from solder resist material.

Description

[0001] A COMPONENT CARRIER ASSEMBLY AND METHOD FOR MANUFACTURING A COMPONENT CARRIER ASSEMBLY

[0002] The invention relates to a component carrier assembly comprising a component carrier, preferably formed as an integrated circuit substrate, comprising a stack with a preferably planar extension, said stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, and a component, preferably an electronic component. It further relates to a method for manufacturing a component carrier assembly.

[0003] According to the prior art, it is known to insert an electronic component, for example, a chip or the like, to or a component carrier. The components may be enclosed by the layers and materials of the component carrier.

[0004] The CN115064516 A discloses a composite packaging substrate structure that includes a basic packaging substrate with a plastic sealing layer on its surface, and a redistribution layer on the surface of the plastic packaging layer. The plastic packaging layer further comprises a bridge chip, a filling structure, a conductive layer metal and a plastic encapsulating compound wrapping the bridge chip, the filling structure and the conductive metal. The redistribution layer is respectively electrically connected to the basic packaging substrate and the bridge chip through the conductive metal, wherein the bridge chip and the filling structure are respectively arranged on the surface of the basic packaging substrate, and the filling structure is arranged around the bridge chip; wherein, the filling structure is used to adjust the bending state of the composite packaging substrate structure.

[0005] With reference to the prior art, the component carriers often have unsatisfactory properties with regard to their surface characteristics in the form of unevenness and / or warpage, for their further use in different fields of application.

[0006] It has been the object of the present invention to overcome the disadvantages of the prior art and to provide a component carrier assembly and method by means of which a component should be inserted into a carrier, wherein the component carrier assembly provides improved properties to prevent surface unevenness. This object is achieved by a component carrier assembly, wherein a cavity is formed within the stack, and the component is embedded within the cavity by means of an embedding mass, wherein the embedding mass is formed from solder resist material.

[0007] Preferably, the solder resist material forming the embedding mass is in direct contact with the component.

[0008] An embedding mass formed from solder resist material provides improved warpage-preventing properties for a component carrier assembly. Furthermore, by using solder resist material, the material properties of the component carrier can be distributed more evenly over the entire structure in this type of application. Therefore, its behaviour with regard to counteract warpage can be better predicted / calculated and thus prevented.

[0009] The invention can further provide better control of the warpage by using different thickness and / or different material in the package for compensation of young modulus of two sides of the component carrier.

[0010] Additionally, solder resist material is preferably a photo sensitive dielectric material with high resolution which is different from other dielectric material such as molding material or ABF material, therefore the pattern can be directly formed on the layer. Meanwhile solder resist is used as a protective layer formed on the external surface of component carrier to resist the harsh environment, so the formulation and the composition of the solder resist material is different from other dielectric material. Combination of the two properties of the solder resist material, the leverage of the material in the component carrier can provide a lower cost, high yield solution for the high-performance computing application since the solder resist material is directly used for encapsulation and a build-up layer as well as serving as protective layer.

[0011] A further advantage of the invention is to provide an adjustable warpage management of a component carrier, especially when having asymmetric structuring, wherein the warpage can be adjusted by the selected composition of the embedding mass.

[0012] The control of the warpage can be achieved by an (elastic / young) modulus of the solder resist material, which is preferably less than 10 GPa, in particular less than 5 GPa, further in particular less than 1 GPa, preferably less than 0,9 Gpa, which results in a lower warpage of the stack. In the context of the present application, the term “component carrier” may particularly denote any support structure which is capable of accommodating one or more components thereon and / or therein for providing mechanical support and / or electrical and / or thermal connectivity. In other words, a component carrier may be configured as a mechanical and / or electronic and / or carrier for components. In particular, a component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different ones of the above mentioned types of component carriers.

[0013] In an embodiment, the component carrier can comprise a component embedded in the component carrier. The component can be embedded in the core of the component carrier or a buildup of the component carrier. With the component embedded in, such kind of component carrier can provide a shorter interconnection path between the component and component carrier, which increases the data transmission speed and decreases the signal loss.

[0014] In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.

[0015] In the context of the present application, the term “printed circuit board” (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and / or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise resin and / or glass fibers, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB). Apart from one or more components which may be embedded in a printed circuit board, a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. A dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).

[0016] In the context of the present application, the term “main surface” of a body may particularly denote one of two largest opposing surfaces of the body or the outermost layers. The main surfaces may be connected by circumferential side walls. The thickness of a body, such as a stack, may be defined by the distance between the two opposing main surfaces.

[0017] In the context of the present application, the term “substrate” may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB. For instance, a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and / or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and / or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term “substrate” also includes “IC substrates”. A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).

[0018] The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and / or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo- and / or thermosensitive molecules) like polyimide or polybenzoxazole as electrically insulating material.

[0019] Especially, in the field of such technologies, for example the interposer, which preferably has a horizontal and / or vertical asymmetry, a warpage can be particularly counteracted. In the context of the present application, the term “stack” may particularly denote an arrangement of multiple planar layer structures which are mounted in parallel on top of one another.

[0020] After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.

[0021] In the context of the present application, the term “layer structure” may particularly denote a continuous layer, a patterned layer or a plurality of non-consecutive islands within a common plane. It may also comprise the interconnection structure which protrudes from the planar layer structure.

[0022] An advantage of the invention is to provide better dielectric thickness control on redistribution layer side, for example, with a surface flattening of a core layer.

[0023] Preferably the solder resist material forming the embedding mass fills at least partially, preferably completely, the space between the wall of the cavity and surfaces of the component that extend transverse to the planar extension of the stack. Advantageous here is the embedding of the component with as little stress as possible, as well as an optimum attachment to the stack.

[0024] In one preferred embodiment, at least a portion of a first main surface of the stack, which preferably extends parallel to the planar extension of the stack, is formed by a first external layer structure formed from solder resist material, wherein the solder resist material forming the embedding mass and the solder resist material forming the first external layer structure merge into one another and / or form together a monolithic body. With this variant, an improved distribution of the material properties (of the solder resist material) can be achieved to counteract warpage over the surface of the carrier, or over its entire cross-section.

[0025] Furthermore, a second main surface of the stack, which is opposed to the first main surface of the stack and preferably extends parallel to the planar extension of the stack, may be formed by a second external layer structure formed from solder resist material. In this way, a better distribution of the properties of the invention to be benefited from can be achieved in the component carrier assembly.

[0026] Preferably the first and second external layer structure of solder resist material are connected one to each other, preferably at least in the cavity where the component is embedded by said solder resist material. With this embodiment, an interposed body can be formed between the two layers, which is arranged over the height of the entire stack. Furthermore, the component can preferably form the geometric core of this formed body so that it is enclosed by it.

[0027] According to one possible embodiment, the solder resist material of the first external layer structure and the solder resist material of the second external layer structure are connected to each other, preferably via the solder resist material of the embedding mass, and / or form together a monolithic body, preferably together with the solder resist material of the embedding mass. This may bring the advantage of forming a hybrid-like material combining the physical and / or chemical properties of the solder resist material of the first external layer structure and the solder resist material of the second external layer structure and thus enhance the integrity of the embedding mass. As a consequence, the warpage can be controlled.

[0028] According to one embodiment, the solder resist material of the first external layer structure and the solder resist material of the second external layer structure have the same composition. This embodiment can be used to achieve improved properties and a simplified, predictable behaviour of the layers. The same material property can have same CTE, so issues such as delamination, crack, warpage from CTE mismatch can be mitigated.

[0029] Preferably the thickness of the first external layer structure is different from the thickness of the second external layer structure, preferably by a factor of at least 1,5. With this design, one of the two (opposing) layers can be determined as the more dominant layer in terms of its properties and their effect on / against the warpage. Since the warpage issue resulted from asymmetrical structure is compensated by the different thickness of the first external layer structure.

[0030] With reference to a thickness in general, the component carrier thickness is preferably defined by the first and second external surface of the solder resist layer structure. Therefore, a (elastic) modulus of the component carrier assembly can be adjusted by the thickness of each solder resist layer structure and their relationship to each other.

[0031] In a further embodiment, the thickness of the first external layer structure is greater than, preferably at least 1,5 times greater than, the thickness of the second external layer structure; and / or wherein the mechanical stiffness of the first external layer structure is greater than, preferably at least 1,5 times greater than, the mechanical stiffness of the second external layer structure. In this way, one layer can exert a greater influence on the warpage, so that a combination of the two layers acts in a predetermined direction with regard to these properties and at the same time exerts its properties as a solder resist, especially when used in asymmetric arranged layer structures of the stack. Especially if this is applied to asymmetrically formed layers, which often also exhibit a warpage in a predetermined direction due to their different material properties.

[0032] In accordance with a possible embodiment, the solder resist material of the first external layer structure and the solder resist material of the second external layer structure are connected to each other, preferably via the solder resist material of the embedding mass, and / or form together a monolithical body, preferably together with the solder resist material of the embedding mass. With this embodiment, a body made of solder resist material can be formed inside the stack, which extends to both main, surfaces. The component may be enclosed by this body formed of solder resist material, preferably at least on its lateral walls. With such structure, the CTE is aligned, the shrinkage of the external layer is also aligned, therefore the inner stress of the package is deducted and the alignment of layer to layer is also improved.

[0033] Preferably the solder resist material of the first external layer structure and the solder resist material of the second external layer structure are connected to each other along a boundary plane, wherein preferably the boundary plane flushes with the external main surface of the stack, in particular within a flatness range of less than 15 pm, in particular less than 8 pm, further in particular less than 5 pm, further more particular to achieve 1 pm, preferably with flatness treatment (for example, grinding). The flatness along the boundary plane of the first external layer structure and the second external layer structure may reduce the overall thickness of the component carrier. Additionally or alternatively, the flatness along the boundary plane may enhance the adhesion and / or cohesion and / or attractive forces of the solder resist material of the first external layer structure and the solder resist material of the second external layer structure.

[0034] Additionally at least a portion of the component may have a different flatness range with respect to that between said boundary plane and said external main surface of the stack and / or said boundary plane may have a planarity of less than 15 pm, in particular less than 8 pm, further in particular less than 5 pm preferably less than 1 pm and / or have a roughness of less than 300 nm, in particular less than 200 nm and / or wherein the roughness of the solder resist main surface facing the rest of the stack may be less than 180 nm, preferably less than 150 nm. The different flatness may be a recognisable feature by the use of the described method.

[0035] According to one embodiment, the external side of the first external layer structure and / or the external side of the second external layer structure is / are free of build-up layers. With this embodiment, an easier determination of the desired properties of the external layer structures with regard to their effect on the warpage can be provided. Meanwhile the number of layers can be reduced and the manufacturing process is simplified, so the yield of product can be improved and the cost of production can be decreased.

[0036] In a further embodiment, the arrangement of layer structures of the stack is asymmetrical in relation to the center plane that runs parallel to the planar extension of the stack, wherein preferably the number and / or thickness of layer structures arranged on one side of the center plane is different to the number and / or thickness of layer structures arranged on the other side of the center plane. In general, an asymmetrical arrangement of the stack is prone to warpage issues, however the use of the described method may reduce warpage issues significantly, while still having an asymmetrical arrangement of the stack. Such kind of structure is flexible to adjust the gap of the young modulus of material stacked in the layer structures on the two sides of the center plane, thus it finally can compensate the difference of the young modulus of the stack to get balance for the stack, thus the warpage is controlled.

[0037] According to one variant, the first external layer structure comprises at least one first opening, preferably a plurality of first openings, exposing at least one contact portion of at least one electrically conductive layer structure of the stack, wherein preferably the first external layer structure comprises at least two first openings of different size, and / or wherein the second external layer structure comprises at least one second opening, preferably a plurality of second openings, exposing at least one contact portion of at least one electrically conductive layer structure of the stack, wherein preferably the second external layer structure comprises at least two second openings of different size, wherein preferably the at least one opening of one of the external layer structures, preferably the at least one opening of the first external layer structure, is greater than the at least one opening of the other of the external layer structures, preferably the at least one opening of the second layer structure. This may bring the advantage of simplifying the access to an electrically conductive layer structure of the stack due to the described manufacturing method. With the different size of opening on the first external layer structure and / or the second external layer structure, it provides an electrically conductive portion to connect different size and type of components with different interconnection path, which provides a solution for advanced package from panel level.

[0038] Furthermore, a solder material or other interconnection structure (such as a copper bump) may be provided in the at least one opening or in each opening of the external layer structure(s), said solder material or other interconnection structure being in electrical contact with said contact portion of the electrically conductive layer structure, wherein preferably the at least one opening defines a portion of the geometrical shape of the solder material provided in that opening.

[0039] According to a further concept, the at least one contact portion is covered by a protective layer, wherein preferably a portion of the protective layer is sandwiched between the electrically conductive layer structure to which said at least one contact portion belongs and the external layer structure in which the at least one opening is provided and / or is externally provided on the external layer structure in which the at least one opening is provided. This may bring the advantage of efficiently embedding contact portions which enhances the electrical contacts and ensures high integrity of the stack. The protective layer may be an electrically conductive material, for example a metal, e.g. copper, gold, silver (or the like), Alternatively it may comprise electrically insulating material.

[0040] According to one embodiment, the component carrier assembly comprises at least one further component mounted to the component carrier and arranged outside the stack, wherein said further component is electrically connected, preferably by means of an electrically conducting material or bonding structure, preferably solder material, preferably in form of bumps and / or pillars, to at least one contact portion of at least one electrically conductive layer structure of the stack. This may enhance the functionality of the component carrier assembly.

[0041] Furthermore, the at least one further component may be encapsulated, particularly molded, on one of the main surfaces of the stack. Encapsulating the further component may protect it from the environment, for example air or moisture.

[0042] With such combined design structure with a component embedded in the component carrier and the components mounted on the component carrier, it is possible to provide an integrated final package which is suitable for high performance computing since the embedded component in the component carrier can be a bridge for the components mounted on the component carrier, which shortens the electrical transmission path and improve the signal integrity. Therefore, the data computing can be proceeded in a fast manner, and it supports the big hashrate / processing power of a final application.

[0043] Preferably the solder resist material forming the embedding mass is an epoxy resin based or acryl- or methacryl- based material, preferably lacquer, photo-imageable dielectric material, ABF-molding material, and / or has a thermal stability at temperatures below at least 270°C. It may further comprise filler particles made of SO2 and photosensitizer. Usually solder resist material is used as the external layer to protect the circuit of component carrier. However, in the invention it is preferably used as encapsulating material to fill the cavity of component embedded. The young modulus of solder resist material can be achieved at very low level such as Ippm or even less compared with other dielectric material, beside that it is photo imageable with possibility of direct pattern so that the production process can be simplified and also the manufacturing effort is lowered. Therefore, those property is leveraged in the invention to realize the product with low cost and good performance. PCB related manufacturing processes may be experienced in handling solder resist material and thus may applied solder resist material in a very precise manner.

[0044] The object of the invention is also achieved by a method for manufacturing a component carrier assembly, comprising the steps of:

[0045] - providing a component, preferably an electronic component,

[0046] - embedding the component within a cavity of a stack of at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein embedding the component is done by means of a solder resist material to form an embedding mass. Preferably the solder resist material is brought in direct contact with the component. Preferably, the steps are sequenced, in particular providing the component before embedding the component. Alternatively, providing the component and embedding the component may be done simultaneously. Moreover, the production method may be simplified as the amount of layers of the other side of stack can be reduced. Due to less production process applied, the yield of product will be also significantly improved. As mentioned before an embedding mass formed from solder resist material provides improved warpage-preventing properties for a component carrier assembly. By using solder resist material, the material properties of the component carrier can be distributed more evenly over the entire structure in this type of application. Therefore, its behaviour with regard to counteract warpage can be better predicted / calculated and thus prevented.

[0047] According to one embodiment, a first main surface of the stack is formed by means of a solder resist material to form a first external layer structure, such that the solder resist material forming the embedding mass and the solder resist material forming the first external layer structure merge into one another and / or form together a monolithic body, wherein preferably embedding the component and forming the first external layer structure is performed within a single step of applying solder resist material. This may bring the advantage of manufacturing the component carrier according to the previously described embodiments in a fast and reliable manner keeping the ration of scrap parts low. Additionally, due to the monolithic body of the solder resist embedding mass and the solder resist external layer is merged together, the same material is formed to encapsulate the component embedded in the component carrier, the CTE of layer structure is the same, thus the delamination, crack and misalignment of layer to layer can be avoided.

[0048] With reference to the solder resist material, in particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper and / or against mechanical influences, for example scratches.

[0049] Additionally, it can have additives to tune the surface tension and / or roughness. Also dyes are included to color the solder resist. The solder resist preferably has a green, blue, red color (preferably, resin without coloring dyes) like molding material.

[0050] Generally, a solder resist defines the appearance of a component carrier, without substantially altering the overall shape and / or dimensions of the component carrier as such. A further way to recognize the solder resist layer, is that the solder material connecting the component with the component carrier takes the shape of the solder resist structure; in other work, the solder resist structure at least partially impart the shape and / or adhesion quality to the solder material at the side of the component carrier; this is due to the fact that always the solder material is provided on the still formed solder resist layer, the latter having the function to protect the outer layer structure of the component carrier.

[0051] On the other hand, a molding material is different from the solder resist one because the former follow and takes the shape of the still existing structure of the solder material. This is unequivocally recognizable through the specific shape of the molded external profile wrapping the still existing solid body. A molding material is a kind of epoxy compound which is usually used for assembly, not much in the RDL or build-up of component carrier, as it is not photo sensitive.

[0052] In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimidetriazine resin, polyphenylene derivate (for example based on polyphenylenether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and / or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semi-cured resin in combination with a reinforcing agent, for example fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties for example FR4 or FR5, which describe their flame retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well. For high frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and / or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (ETCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.

[0053] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly (3, 4-ethylenedioxy thiophene) (PEDOT), respectively.

[0054] The at least one component can be selected from a group consisting of an electrically non- conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materi-als are defined according to their thermal conductivity, which should be at least 2 W / mK. Such materials are often based, but not limited to metals, metal-oxides and / or ceramics as for instance copper, aluminium oxide (A12O3) or aluminum nitride (AIN). In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAE), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal-oxide- semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs) and / or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, a photocoupler, a voltage converter (for example a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and / or may be embedded in an interior thereof. Moreover, also other components, in particular those which generate and emit electromagnetic radiation and / or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component.

[0055] To provide better understanding of the invention, the invention is explained in more detail with the aid of the following figures.

[0056] The following is shown in a strongly simplified, schematic representation:

[0057] Fig. 1 an embodiment of a component carrier assembly;

[0058] Fig. 2 a) b) an embodiment of an intermediate product;

[0059] Fig. 3 an embodiment of an intermediate product with an embedded component;

[0060] Fig. 4 an embodiment of an intermediate product with a build-up layer;

[0061] Fig. 5 an embodiment of an intermediate product with a layer of solder resist material;

[0062] Fig. 6 an embodiment of an intermediate product with openings;

[0063] Fig. 7 an embodiment of a component carrier assembly with solder material;

[0064] Fig. 8 a) and b) an embodiment of an intermediate product with a flattened surface;

[0065] Fig. 9 an embodiment of an intermediate product with an embedded component;

[0066] Fig. 10 an embodiment of an intermediate product with a layer of solder resist material;

[0067] Fig. 11 an embodiment of an intermediate product with attached elements;

[0068] Fig. 12 an embodiment of a component carrier assembly;

[0069] Fig. 13 a detail of an embodiment a component carrier assembly;

[0070] Fig. 14 a further embodiment of an intermediate product of a component carrier assembly. As an introduction, it should be noted that in the embodiments described in different ways, identical parts or method steps are indicated with identical reference numbers or identical component designations; at the same time, the disclosures contained in the entire description may be analogously applied to identical parts with identical reference numbers or identical component designations. Moreover, the position indications chosen in the description, such as at the top, at the bottom, laterally, etc. refer to the figure which is directly represented and described; and if a position changes, said position indications are to be applied analogously to the new position.

[0071] The embodiments show possible variants; however, it should be noted at this point that the invention is not limited to the variants specifically shown; rather, various combinations of the individual variants are possible as well, and, due to the technical information provided by the present invention, this variation possibility is subject to the skills of the person skilled in the art who works in this technical field.

[0072] The scope of protection is determined by the claims. However, the description and the drawings are to be used for construing the claims. Individual features or feature combinations from the different embodiments that are shown and described may per se constitute independent solutions according to the invention. The object underlying the independent solutions according to the invention may be gathered from the description.

[0073] For the sake of good order, it should finally be noted that, for better understanding, some of the facts shown in the figures have been represented unsealed and / or enlarged and / or in reduced size.

[0074] Fig .1 shows a component carrier assembly 1 comprising a component carrier 2, preferably formed as an integrated circuit substrate, comprising a stack 4 with planar extension P, said stack 4 comprising at least one electrically conductive layer structure 5, 6 and at least one electrically insulating layer structure 7, and a component 10, preferably an electronic component.

[0075] A cavity 8 is formed within the stack 4, and the component 10 is embedded within the cavity

[0076] 8 by means of an embedding mass 9, wherein the embedding mass 9 is formed from solder resist material and wherein preferably the solder resist material forming the embedding mass

[0077] 9 is in direct contact with the component 10. As further shown, solder resist material forming the embedding mass 9 may fill at least partially, preferably completely, the space between the wall of the cavity 8 and surfaces of the component 10 that extend transverse to the planar extension P of the stack 4.

[0078] A first main surface 11 of the stack 4, which preferably extends parallel to the planar extension P of the stack 4, may be formed by a first external layer structure 12 formed from solder resist material, wherein the solder resist material forming the embedding mass 9 and the solder resist material forming the first external layer structure 12 merge into one another and / or form together a monolithic body. Alternatively, the embedding mass and the external layer may be formed separately, so that between the embedding mass 9 and the first external layer structure 12 an interface may be formed. Nevertheless, the embedding mass and first external layer structure can be formed at the same time, or separately.

[0079] A second main surface 21 of the stack 4, which is opposed to the first main surface 11 of the stack 4 and preferably extends parallel to the planar extension P of the stack 4, can be formed by a second external layer structure 22 formed from solder resist material.

[0080] The solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 preferably have the same composition. Alternatively, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 may be different or the amount of filler material of the solder resist material of the first external layer structure 12 and the amount of the solder resist material of the second external layer structure 22 may be different. Optionally, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 and the material of the embedding mass 9 preferably have the same composition.

[0081] The first thickness 26 of the first external layer structure 12 is preferably different from the second thickness 27 of the second external layer structure 22, preferably by a factor of at least 1,5, preferably 1,75. Furthermore, the thickness of the first external layer structure 12 can be greater than, preferably at least 1,5 times greater than, the thickness of the second external layer structure 22 and / or wherein the mechanical stiffness of the first external layer structure 12 can be greater than, preferably at least 1,5 times greater than, the mechanical stiffness of the second external layer structure 22. Alternatively, the first thickness 26 of the first external layer structure 12 may be smaller than the factor of 1,5 compared to the second thickness 27, in particular may be 1. With the thickness difference of two solder resist layers, it finally compensates the young modulus of the layer structures of two sides of the stack. Thus the whole stack is balanced considering the warpage issue.

[0082] In one embodiment, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 are connected to each other, preferably via the solder resist material of the embedding mass 9, and / or form together a monolithic body, preferably together with the solder resist material of the embedding mass 9.

[0083] Furthermore, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 may be connected to each other along a boundary plane, wherein preferably the boundary plane flushes with the external main surface of the stack, in particular within a flatness range of less than 15 pm, in particular less than 8 pm, further in particular less than 5 pm.

[0084] Additionally, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 may be connected to each other along a boundary plane, wherein preferably the boundary plane extends along a direction parallel to the planar extension plane P.

[0085] Alternatively, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 may be connected to each other along a boundary plane, wherein preferably the boundary plane extends along a direction perpendicular to the planar extension plane P.

[0086] At least a portion of the component may have a different flatness range with respect to that between said boundary plane and said external main surface of the stack and / or wherein said boundary plane has a planarity of less than than 15 pm, in particular less than 8 pm, further in particular less than 5 pm preferably less than 1 pm and / or may have a roughness of less than 300 nm, in particular less than 200 nm and / or wherein the roughness of the solder resist main surface facing the rest of the stack may be less than 180nm, preferably less than 150 nm.

[0087] As further shown, the external side of the first external layer structure 12 and / or the external side of the second external layer structure 22 may be free of build-up layers. Preferably the arrangement of layer structures 5, 6, 7, 12, 22 of the stack 4 is asymmetrical in relation to a center plane C that runs parallel to the planar extension P of the stack 4, wherein preferably the number and / or thickness of layer structures arranged on one side of the center plane C can be different to the number and / or thickness of layer structures arranged on the other side of the center plane C.

[0088] Alternatively, the arrangement of layer structures 5, 6, 7, 12, 22 of the stack 4 may be symmetrical in relation to a center plane C that runs parallel to the planar extension P of the stack 4, wherein preferably the number and / or thickness of layer structures arranged on one side of the center plane C can be the same to the number and / or thickness of layer structures arranged on the other side of the center plane C. In another word, even if the number of the layer structures may be different, as long as the thickness of two sides on the center plane C is the same, the different young modulus of different material from the layers can be compensated. The warpage issue of symmetrical structure can be resolved.

[0089] As mentioned before, the first external layer structure 12 may comprise at least one first opening 13, preferably a plurality of first openings 13, exposing at least one contact portion 15 of at least one electrically conductive layer structure 5 of the stack 4, wherein preferably the first external layer structure 12 comprises at least two first openings 13 of different size, and / or the second external layer structure 22 may comprise at least one second opening 23, preferably a plurality of second openings 23, exposing at least one contact portion 16 of at least one electrically conductive layer structure 6 of the stack 4, wherein preferably the second external layer structure 22 comprises at least two second openings 23 of different size.

[0090] Whereby the at least one opening 13 of one of the external layer structures 12; 22 - preferably the at least one opening 13 of the first external layer structure 12 - is greater than the at least one opening 23 of the other of the external layer structures 22 - preferably the at least one opening 23 of the second layer structure 22.

[0091] As further indicated in Fig. 1, a solder material 17, 18 can be provided in the at least one opening 13, 23 or in each opening 13, 23 of the external layer structures 12, 22, said solder material 17, 18 being in electrical contact with said contact portion 15, 16 of the electrically conductive layer structure 5, 6, wherein preferably the at least one opening 13, 23 at least partially defines a portion of the geometrical shape of the solder material 17, 18 provided in that opening 13, 23.

[0092] The at least one contact portion 15, 16 may be covered by a protective layer 19 as shown in Fig. 13, which will be discussed later.

[0093] As further indicated with the vertical level 28, also independent of the embodiment shown, a surface of the component 10 and / or contact pads of the component 10 may be arranged in the same vertical level (or in a plane parallel to the planar extension) as one electrically conductive layer structure.

[0094] As indicated by the dashed lines in Fig. 1, the component carrier assembly 1 may comprise at least one further component 20 mounted to the component carrier 2 and arranged outside the stack 4, wherein said further component 20 is electrically connected, preferably by means of an electrically conducting material, preferably solder material 17, 18, preferably in form of bumps and / or pillars, to at least one contact portion 15, 16 of at least one electrically conductive layer structure 5, 6 of the stack 4.

[0095] Furthermore the at least one further component 20 can be optionally encapsulated, particularly molded, on / in one of the main surfaces 11, 21 of the stack 4, as also indicated with dashed lines.

[0096] Preferably at least three sides of the component 10 are in direct contact with the solder resist material.

[0097] As it can also be seen, the solder resist material may be in direct contact with at least three different layers.

[0098] As indicated by the dashed lines in Fig. 1, a further solder resist material 3 may also be applied on one main surface of the stack. Preferably, the further solder resist material 3 may have a different composition and / or comprising a different amount of filler material compared the solder resist material.

[0099] In the following, possible methods for manufacturing a component carrier assembly 1 are explained. An intermediate product is provided, as shown in Fig 2 a), whereby the intermediate product may be a core or the like, comprising an electrically insulating layer structure 7 and at least one electrically conductive layer structure 5. The intermediate product further comprises a cavity 8, preferably formed in the insulating layer structure 7. Before cavity formation, there may be a flatness treatment on the surface of the core, wherein it will provide a very flat surface. The flatness surface can ensure the component to be embedded flush with the said surface to get the same level between the core surface and component. Therefore, the alignment between the component and the pattern of the component carrier will be good. Additionally, it also ensure that a fine line structure of the component carrier can be realized.

[0100] At least one component 10 is placed in the cavity 8 as shown in Fig. 2b, preferably by attaching it to a planar surface of a temporary layer 25 or the like.

[0101] In a further step, as shown in Fig. 3, the component 10 is embedded by a solder resist material forming an embedding mass 9. Preferably the component 10 is in direct contact with the solder resist material / embedding mass 9. In an example the solder resist material / embedding mass 9 is free of voids or vacancies. In a further example, the component carrier 10 is in direct contact with the filler material of the solder resist material / embedding mass 9.

[0102] A first main surface 11 of the stack can already be provided at this point, which is formed by a first external layer structure 12 formed from solder resist material, wherein the solder resist material forming the embedding mass 9 and the solder resist material forming the first external layer structure 12 merge into one another and / or form together a monolithic body.

[0103] A carrier element (not shown) may be attached to the intermediate product or the solder resist material, for example on the first main surface 11.

[0104] As it can be seen, at least one sidewall of the component 10 is preferably in direct contact with the embedding mass 9 and an electrically insulating layer structure 7. This may ensure a reliable embedding / positioning of the component. Furthermore, at least two sidewalls, preferably opposite to each other, may be in direct contact with the embedding mass.

[0105] As further shown in Fig. 4, further layers can be provided on the intermediate product, for example at least one electrically insulating layer structure 7 and at least one electrically conductive layer structure 6. The manufacturing of the further layers may comprise several build-up steps, as also (at least partial) removal steps. The manufacturing process may include lamination steps, laser drilling, mechanical drilling, plasma etching, wet chemical etching, galvanic plating, electroless plating and / or physical vapour deposition and / or chemical vapour deposition.

[0106] Preferably a second external layer structure 22, formed from solder resist material is formed on the intermediate product, comprising a second main surface 21 which is opposed to the first main surface 11. As mentioned before, the solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 preferably have the same composition.

[0107] As shown in Fig. 6 at least one first opening 13, preferably a plurality of first openings 13 is formed the first external layer structure 12.

[0108] At least one second opening 23, preferably a plurality of second openings 23 can be formed in the second external layer structure 22.

[0109] Preferably, manufacturing the at least one first opening 13 and / or the at least one second opening 23 may comprise mechanical drilling, laser drilling and / or a photo process. Thereby the at least one first opening 13 and / or the at least one second opening 23 may comprise straight shape, for example a cylindrical shape, or a tapered shape, for example a frustoconical shape.

[0110] The first external layer 12 and / or the second external layer structure 22 can comprise at least two first openings 13 or at least two second openings 23 of different size, as indicated by the second openings 23. Preferably the at least one opening 13 of one of the external layer structures, is greater than the at least one opening 23 of the other of the external layer structures 22.

[0111] For example, the smaller size opening(s) 23 may be used for an electrical connection with the component 10 embedded - through vias formed by electrically conducive layer structure and can be directly electrically connected with a further component (not shown) by forming (solder) bumps in the openings. As an example, said components may be used for data computing. The opening(s) 23 that have a bigger size may be indirectly in electrically connection with the components embedded. The openings 13,23 can be formed in such way that least one contact portion 15,16 of at least one electrically conductive layer structure 5,6 is exposed (by means of the opening).

[0112] After forming the openings, a solder material 17, 18 can be provided in the at least one opening 13,23 or in each opening 13,23 of the external layer structure(s) 12,22.

[0113] The solder material 17, 18 is in electrical contact with said contact portion 15,16 of the electrically conductive layer structure 5,6, wherein preferably the at least one opening 13, 23 at least partially defines a portion of the geometrical shape of the solder material 17, 18 provided in that opening 13, 23, as it is also shown in Fig. 7.

[0114] A further method for manufacturing a component carrier assembly 1 is shown in Fig. 8 to 12.

[0115] An intermediate product is provided as shown in Fig 8 a), whereby the intermediate product may be a core or the like, comprising an electrically insulating layer structure 7 and at least one electrically conductive layer structure 5. A flat or even surface can be formed on the intermediate product on at least one exposing surface as shown in Fig. 8 a). The electrically conductive layer structure 5 can be flattened together with said surface, by a flatness treatment of the surface, as already mentioned. Therefore, an additional layer can be provided, for example, an electrically insulation layer.

[0116] From Fig. 8 a) to b) a part of the intermediate product is removed (e.g., cut out) to form a cavity 8, preferably at least in the insulating layer structure 7. As further shown, the intermediate product may be flipped upside down (as indicated) and fixed on a (preferably temporary) carrier layer 25.

[0117] At least one component 10 is placed in the cavity 8, preferably on the carrier layer 25.

[0118] According to Fig. 9 the component 10 is embedded within the cavity 8 by means of a solder resist material to form an embedding mass 9, wherein preferably the solder resist material is brought in direct contact with the component 10.

[0119] A further carrier element 14 can be provided, which is attached to the intermediate product, preferably on the solder resist material.

[0120] As indicated in Fig. 9 with dashed lines, a second intermediate product may be provided, on the opposite side of the carrier element 14, wherein both intermediate products can be identical to each other, preferably symmetrically arranged with respect to the carrier element 14 (as shown), to carry out further processing steps on both at the same time. The carrier element 14 may comprise 2 separate parts for each intermediate product.

[0121] Referring to Fig. 10, the carrier layer 25 is preferably removed and a solder resist material is applied to the intermediate product, forming the external layer structure 22, preferably having the same composition as the embedding mass 9.

[0122] At least a portion of a first main surface 11 of the stack 4, which preferably extends parallel to the planar extension P of the stack 4, can be formed by a first external layer structure 12 formed from solder resist material, wherein the solder resist material forming the embedding mass 9 and the solder resist material forming the first external layer structure 12 preferably merge into one another.

[0123] The solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 are preferably connected to each other along a boundary plane 24 as also shown.

[0124] A plurality of second openings 23 are preferably formed in the second external layer structure 22 exposing at least one contact portion 16 of at least one electrically conductive layer structure 6 of the stack 4, wherein preferably the second external layer structure 22 comprises at least two second openings 23 of different size. The number of layers on each of the two sides may be the same, the thickness of external solder resist material may be different, but the whole thickness comprising the external layer structure and the bumps of one side is same to other side, this structure mitigates the warpage.

[0125] As further shown in Fig. 10, a material for attaching further elements on the intermediate product can be applied on the electrically conductive layer structure 6. For example, the material can be provided by metallic plating, serving as a contact portion, preferably for attaching further elements to the stack.

[0126] According to Fig. 11, further contacting elements (and / or layers), preferably further components 20 are provided on the electrically conductive layer structure 6 (or on the external layer structure 22, - preferably connected by the applied material (as shown). The further components 20 can also be encapsulated, particularly molded, on one of the main surfaces 11, 21 of the stack 4 .

[0127] With reference to Fig. 12, first openings 13 are formed in the first external layer structure 12 exposing at least one contact portion 15 of at least one electrically conductive layer structure 5,6 of the stack 4, wherein the first external layer structure 12 may also comprises at least two first openings 13 of different size,

[0128] The external side of the first external layer structure 12 and / or the external side of the second external layer structure 22 may not be free of build-up layers or, alternatively, may be free of build-up layers.

[0129] As it can be seen, the arrangement of layer structures 5, 6, 7, 12, 22 of the stack 4 is asymmetrical in relation to the center plane C that runs parallel to the planar ex-tension P of the stack 4, wherein preferably the number and / or thickness of layer structures arranged on one side of the center plane C is different to the number and / or thickness of layer structures arranged on the other side of the center plane C. However, the whole thickness may be compensated by the bumps height.

[0130] A solder material 17 can be provided in at least one first opening 13 or in each first opening 13 of the first external layer structure 12, said solder material 17 being in electrical contact with said contact portion 15 of the electrically conductive layer structure 5,6 wherein preferably the at least one opening 13 preferably, at least partially, defines a portion of the geometrical shape of the solder material 17 provided in that opening 13. Alternatively, independent of the embodiment shown, a sinter material may be provided in the opening(s).

[0131] The solder resist material of the first external layer structure 12 and the solder resist material of the second external layer structure 22 are connected to each other, preferably via the solder resist material of the embedding mass 9, and / or form together a monolithic body, preferably together with the solder resist material of the embedding mass 9.

[0132] Beside that there may be an interface between the embedding mass 9 and the solder resist material of the second external layer structure 22 as there are gaps between the cavity and the core. After filling the gap, the second external layer 22 will be formed on the surface of the gap, therefore the interface can be seen after cross section. Referring to the detail of a component carrier assembly shown in Fig. 13 - independent of the embodiment, at least one contact portion 15, 16 can be covered by a protective layer 19, wherein preferably a portion of the protective layer 19 is sandwiched between;

[0133] - the electrically conductive layer structure to which said at least one contact portion 15, 16 belongs and

[0134] - the external layer structure 12, 22 in which the at least one opening 13, 23 is provided and / or is externally provided on the external layer structure 12, 22 in which the at least one opening 13, 23 is provided.

[0135] Alternatively, or additionally, a portion of the protective layer 19 is externally provided on the external layer structure 12,22, in particular at the lateral wall defined by the at least one opening, as indicated with dashed lines. As already mentioned before, the protective layer may comprise an electrically conductive material, for example a metal - copper, gold, silver or combinations thereof. Alternatively, or additionally, the protective layer may comprise an electrically insulating material.

[0136] As shown in Fig. 14 a) to b), the embedding of the component 10 by the embedding mass 9 may comprise a single step of forming a layer of solder resist material on each of two opposite external surfaces of the intermediate product (comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure) the via the solder resist material of the embedding mass 9, and / or form together a monolithic body, together with the solder resist material of the embedding mass 9. Preferably the two layers on the opposite external surfaces are parallel to the planar extension (P). Said layers can also form the first external layer structure and / or the second external layer structure.

[0137] Furthermore, the intermediate product may have conduits in form of breakthroughs, drill holes, or the like, for distributing the embedding mass, as indicated with dashed lines (preferably in the electrically insulating layer structure).

[0138] Furthermore; a dummy material (not shown) can be inserted in the area of the contact portions of the electrically conductive layers 5, said dummy material has the shape of openings and can be removed after / while curing the embedding mass to form the openings in the layer of solder material. Preferably said dummy material can also be used to fix the intermediate product to a carrier layer / element for filling the embedding mass 9. Further elements, as the already described solder materials may be provided in further steps, as also already mentioned with reference to the figures described above.

[0139] List of references component carrier assembly P planar extension component carrier C center plane further solder resist material stack conductive layer structure conductive layer structure insulating layer structure cavity embedding mass component first main surface first external layer structure first opening carrier element contact portion contact portion solder material solder material protective layer further component second main surface second external layer structure second opening boundary plane carrier layer first thickness second thickness level

Claims

C l a i m s1. A component carrier assembly (1) comprising: a component carrier (2), comprising a stack (4)with planar extension (P), said stack (4) comprising at least one electrically conductive layer structure (5, 6) and at least one electrically insulating layer structure (7), and a component (10), wherein a cavity (8) is formed within the stack (4), and the component (10) is embedded within the cavity (8) by means of an embedding mass (9), wherein the embedding mass (9) is formed from solder resist material.

2. A component carrier assembly (1), according to claim 1, wherein the solder resist material forming the embedding mass (9) is in direct contact with the component (10).

3. A component carrier assembly (1) according to claim 1 or 2, wherein the solder resist material forming the embedding mass (9) fills at least partially, preferably completely, the space between the wall of the cavity (8) and surfaces of the component (10) that extend transverse to the planar extension (P) of the stack (4).

4. A component carrier assembly (1) according to one of the preceding claims, wherein at least a portion of a first main surface (11) of the stack (4), which preferably extends parallel to the planar extension (P) of the stack (4), is formed by a first external layer structure (12) formed from solder resist material, wherein the solder resist material forming the embedding mass (9) and the solder resist material forming the first external layer structure (12) merge into one another and / or form together a monolithic body.

5. A component carrier assembly (1) according to one of the preceding claims, wherein a second main surface (21) of the stack (4), which is opposed to the first main surface (11) of the stack (4) and preferably extends parallel to the planar extension (P) of the stack (4), is formed by a second external layer structure (22) formed from solder resist material.

6. A component carrier assembly (1) according to claim 4, wherein the solder resist material of the first external layer structure (12) and the solder resist material of the second external layer structure (22) have the same composition.

7. A component carrier assembly (1) according to claim 4 or 5, wherein the thickness of the first external layer structure (12) is different from the thickness of the second external layer structure (22), preferably by a factor of at least 1,5.

8. A component carrier assembly (1) according to one the claims 4 to 6, wherein the thickness of the first external layer structure (12) is greater than, preferably at least 1,5 times greater than, the thickness of the second external layer structure (22) and / or wherein the mechanical stiffness of the first external layer structure (12) is greater than, preferably at least 1,5 times greater than, the mechanical stiffness of the second external layer structure (22).

9. .A component carrier assembly (1) according to one of the claims 4 to 8, wherein the solder resist material of the first external layer structure (12) and the solder resist material of the second external layer structure (22) are connected to each other along a boundary plane (24), wherein preferably the boundary plane flushes with the external main surface of the stack, in particular a flatness range of of less than 15 pm, in particular less than 8 pm, further in particular less than 5 pm preferably less than 1 pm.

10. A component carrier assembly (1) according to claim 9, wherein at least a portion of the component has a different flatness range with respect to that between said boundary plane and said external main surface of the stack and / or wherein said boundary plane has a planarity of less than 15 pm, in particular less than 8 pm, further in particular less than 5 pm preferably less than 1 pm and / or has a roughness of less than 300 nm, in particular less than 200 nm and / or wherein the roughness of the solder resist main surface facing the rest of the stack is less than 180 nm, preferably less than 150 nm.

11. A component carrier assembly (1) according to one of the claims 4 to 10, wherein the external side of the first external layer structure (12) and / or the external side of the second external layer structure (22) is / are free of build-up layers.

12. A component carrier assembly (1) according to one of the preceding claims, wherein the arrangement of layer structures (5, 6, 7, 12, 22) of the stack (4) is asymmetrical in relation to a center plane (C) that runs parallel to the planar extension (P) of the stack (4), wherein preferably the number and / or thickness of layer structures arranged on one side of the center plane (C) is different to the number and / or thickness of layer structures arranged on the other side of the center plane (C).

13. A component carrier assembly (1) according to one of the preceding claims, wherein the first external layer structure (12) comprises at least one first opening (13), preferably a plurality of first openings (13), exposing at least one contact portion (15) of at least one electrically conductive layer structure (5) of the stack (4), wherein preferably the first external layer structure (12) comprises at least two first openings (13) of different size, and / or wherein the second external layer structure (22) comprises at least one second opening (23), preferably a plurality of second openings (23), exposing at least one contact portion (16) of at least one electrically conductive layer structure (6) of the stack (4), wherein preferably the second external layer structure (22) comprises at least two second openings (23) of different size, wherein preferably the at least one opening (13) of one of the external layer structures (12), preferably the at least one opening (13) of the first external layer structure (12), is greater than the at least one opening (23) of the other of the external layer structures (22), preferably the at least one opening (23) of the second layer structure (22).

14. A component carrier assembly (1) according to claim 13, wherein a solder material (17, 18) is provided in the at least one opening (13, 23) or in each opening (13, 23) of the external layer structure(s) (12, 22), said solder material (17, 18) being in electrical contact with said contact portion (15, 16) of the electrically conductive layer structure (5, 6), wherein preferably the at least one opening (13, 23) defines a portion of the geometrical shape of the solder material (17, 18) provided in that opening (13, 23).

15. A component carrier assembly (1) according to claim 13 or 14, wherein the at least one contact portion (15, 16) is covered by a protective layer (19), ), wherein preferably a portion of the protective layer (19) is sandwiched between the electrically conductive layer structure to which said at least one contact portion (15, 16) belongs and the external layer structure (12, 22) in which the at least one opening (13, 23) is provided and / or is externally provided on the external layer structure (12, 22) in which the at least one opening (13, 13) is provided.

16. A component carrier assembly (1) according to one of the preceding claims, wherein the component carrier assembly (1) comprises at least one further component (20) mounted to the component carrier (2) and arranged outside the stack (4), wherein said further component (20) is electrically connected, preferably by means of an electrically conducting material, preferably solder material (17, 18), preferably in form of bumps and / or pillars, to at least one contact portion (15, 16) of at least one electrically conductive layer structure (5, 6) of the stack (4).

17. A component carrier assembly (1) according to claim 16, wherein the at least one further component (20) is encapsulated, particularly molded, on one of the main surfaces (11, 21) of the stack (4).

18. A component carrier assembly (1) according to one of the preceding claims, wherein the solder resist material forming the embedding mass (9) is an epoxy resin based or acryl- or methacryl- based material, preferably lacquer, and / or has a thermal stability at temperatures below at least 270°C.

19. A method for manufacturing a component carrier assembly (1) according to one of the preceding claims, comprising the steps of: providing a component (10), embedding the component (10) within a cavity (8) of a stack (4) of at least one electrically conductive layer structure (5, 6) and at least one electrically insulating layer structure (7), wherein embedding the component (10) is done by means of a solder resist material to form an embedding mass (9).

20. A method according to claim 19, wherein a first main surface (11) of the stack(4) is formed by means of a solder resist material to form a first external layer structure (12), such that the solder resist material forming the embedding mass (9) and the solder resist material forming the first external layer structure (12) merge into one another and / or form together a monolithic body, wherein preferably embedding the component (10) and forming the first external layer structure (12) is performed within a single step of applying solder resist material.

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