Printed circuit board and preparation method for printed circuit board

Abstract

The present application provides a printed circuit board and a preparation method for the printed circuit board. The printed circuit board comprises a main body layer. The main body layer comprises a plurality of insulating film layers arranged in a stacked manner, and the dielectric constants of adjacent insulating film layers are different; and the main body layer is provided with through holes passing through the main body layer, and the through holes comprise via holes passing through the insulating film layers. In two adjacent insulating film layers, the average area of the cross sections, perpendicular to the stacking direction of the insulating film layers, of the via holes of one insulating film layer is a first area, and the dielectric constant is a first dielectric constant; the average area of the cross sections, perpendicular to the stacking direction, of the via holes of the other insulating film layer is a second area, and the dielectric constant is a second dielectric constant; and the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.

Description

Printed circuit board and method for preparing printed circuit board Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a printed circuit board and a method for preparing the printed circuit board. Background Art

[0002] Printed circuit boards (PCBs) are important electronic components that support and connect electronic components. With the advancement of electronic communications technology, data transmission speeds are increasing, placing increasing demands on the signal transmission quality of PCBs.

[0003] The impedance of the signal during transmission is a key factor affecting the signal transmission quality. The impedance of the signal during transmission in the existing printed circuit board needs to be optimized to achieve the purpose of improving the signal transmission quality.

[0004] Summary of the Invention

[0005] The present application provides a printed circuit board and a method for preparing the printed circuit board.

[0006] According to a first aspect of an embodiment of the present application, a printed circuit board is provided. The printed circuit board comprises:

[0007] The main layer includes multiple stacked insulating film layers, and the dielectric constants of adjacent insulating film layers are different; the main layer is provided with through holes penetrating the main layer, and the through holes include via holes penetrating each insulating film layer; among two adjacent insulating film layers, the average area of ​​each cross-section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant; the average area of ​​each cross-section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.

[0008] In one embodiment, among two adjacent via holes of the same through hole, the orthographic projection of one of the via holes on a plane perpendicular to the stacking direction is a first projection, and the orthographic projection of the other via hole on the plane is a second projection, and the first projection falls on the second projection.

[0009] In one embodiment, the main body layer further includes a plurality of pads, the pads are provided between two adjacent insulating film layers, and the through hole further includes a contact hole passing through the pads.

[0010] In one embodiment, the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the first edge, and the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge, respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.

[0011] In one embodiment, at least two of the insulating film layers in the main body layer are made of the same material, and the average areas of the via holes in the insulating film layers of the same material perpendicular to the stacking direction are substantially the same.

[0012] In one embodiment, the total number of the insulating film layers is an odd number, the number of insulating film layers on both sides of the middle insulating film layer is the same, and the materials and thicknesses of the two insulating film layers with the same number of insulating film layers spaced apart from the middle insulating film layer are the same.

[0013] In one embodiment, the shapes and sizes of the cross sections of the same via hole perpendicular to the stacking direction are substantially the same.

[0014] In one embodiment, the insulating film layer includes multiple insulating material layers arranged in a stacked manner, the total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the via includes sub-vias passing through each of the insulating material layers; in the insulating material layers on both sides of the middle insulating material layer, in the direction toward the middle insulating material layer, the cross-sectional area of ​​the sub-vias of the insulating material layer perpendicular to the stacking direction gradually decreases.

[0015] In one embodiment, the main body layer further includes a plurality of pads, each of which is provided between two adjacent insulating material layers, and the through hole further includes a contact hole passing through the pads.

[0016] In one embodiment, the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the fourth edge, and the edges of the positive projections of the two sub-vias adjacent to the pad on the plane are the fifth edge and the sixth edge, respectively, and the fifth edge and the sixth edge are respectively located on the inner side of the fourth edge.

[0017] In one embodiment, the signal line includes at least one of a differential signal line and a single-ended signal line.

[0018] In one embodiment, the insulating film layer of the main layer includes adjacent first and second insulating film layers, the dielectric constant of the first insulating film layer is greater than the dielectric constant of the second insulating film layer, the through hole includes a first via hole penetrating the first insulating film layer and a second via hole penetrating the second insulating film layer, the average area of ​​each cross section of the first via hole perpendicular to the stacking direction is a first area, the average area of ​​each cross section of the second via hole perpendicular to the stacking direction is a second area, and the first area is smaller than the second area;

[0019] The first insulating film layers and the second insulating film layers are arranged alternately in the main body layer; or,

[0020] The main layer also includes a third insulating film layer, the dielectric constant of the material of the third insulating film layer is smaller than the dielectric constant of the material of the second insulating film layer; the through hole also includes a third via hole penetrating the third insulating film layer; the average area of ​​each cross-section of the third via hole perpendicular to the stacking direction is a third area, and the third area is larger than the second area; the third insulating film layer is provided on the side of the second insulating film layer away from the first insulating film layer, or the third insulating film layer is provided on the side of the first insulating film layer away from the second insulating film layer.

[0021] According to a second aspect of an embodiment of the present application, a method for preparing a printed circuit board is provided, the method comprising:

[0022] A main body layer is formed; the main body layer includes a plurality of insulating film layers stacked together; the dielectric constants of adjacent insulating film layers are different; the main body layer is provided with through holes penetrating the main body layer, and the through holes include via holes penetrating each insulating film layer; among two adjacent insulating film layers, the average area of ​​each cross section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant; the average area of ​​each cross section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.

[0023] In one embodiment, forming the main body layer includes:

[0024] Providing an intermediate structure, the intermediate structure comprising a first insulating film layer and two second insulating film layers located on both sides of the first insulating film layer, wherein the dielectric constant of a material of the first insulating film layer is smaller than the dielectric constant of the second insulating film layer;

[0025] forming an opening penetrating the main body layer, wherein the shapes and areas of the cross sections of the opening perpendicular to the stacking direction of the insulating film layers are substantially the same; the portion of the opening located in the first insulating film layer is a first via hole;

[0026] The material of the second insulating film layer in the area adjacent to the via hole is removed to form a second via hole, so that the area of ​​the cross section of the second via hole perpendicular to the stacking direction is larger than the area of ​​the cross section of the first via hole perpendicular to the stacking direction.

[0027] In one embodiment, forming the opening penetrating the main body layer comprises: drilling the main body layer with a first drill bit to form the opening penetrating the main body layer;

[0028] The removing of material from the area adjacent to the second insulating film layer and the via hole includes: drilling the second insulating film layer with a second drill bit, the maximum outer diameter of the second drill bit being larger than the maximum outer diameter of the first drill bit, and the second drill bit being partially located in the opening during drilling.

[0029] In one embodiment, the main body layer includes two second insulating film layers and a first insulating film layer located between the two second insulating film layers, wherein the dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer; forming the main body layer includes:

[0030] forming a first via hole penetrating the first insulating film layer;

[0031] Disposing the second insulating film layer on two opposite surfaces of the first insulating film layer, respectively, so that the first insulating film layer and the second insulating film layer are bonded together to form a second via hole penetrating the second insulating film layer and communicating with the first via hole;

[0032] or,

[0033] The main body layer includes two first insulating film layers and a second insulating film layer located between the two first insulating film layers, wherein the dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer; forming the main body layer includes:

[0034] forming a second via hole penetrating the second insulating film layer;

[0035] The first insulating film layer is respectively disposed on two opposite surfaces of the second insulating film layer, and the first insulating film layer is bonded to the second insulating film layer to form a first via hole penetrating the first insulating film layer and communicating with the second via hole.

[0036] In one embodiment, the step of bonding the first insulating film layer to the second insulating film layer includes:

[0037] The second insulating film layer and the first insulating film layer that are stacked are pressed together to make the second insulating film layer adhere to the first insulating film layer.

[0038] In one embodiment, the main body layer further includes a plurality of pads, the pads are provided between two adjacent insulating film layers, and the through hole includes a contact hole passing through the pads.

[0039] In one embodiment, the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the first edge, and the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge, respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.

[0040] In one embodiment, the insulating film layer includes a plurality of stacked insulating material layers; the via includes a sub-via that penetrates the insulating material layer; the printed circuit board further includes a conductive structure, the conductive structure including a conductive portion located in each of the sub-vias; and the steps of forming the main layer and the conductive structure include:

[0041] forming a sub-via in an insulating material layer and forming a conductive portion within the sub-via;

[0042] Repeat the following steps until the main layer and the conductive structure are formed:

[0043] Insulating material layers without sub-vias are respectively provided on two opposite surfaces of the structure obtained in the previous step, and the stacked insulating material layers are bonded together; sub-vias are formed on the insulating material layers without sub-vias, and conductive portions are formed within the sub-vias.

[0044] In one embodiment, the main layer also includes a plurality of pads, the pads are provided between two adjacent insulating material layers, the through hole includes a contact hole passing through the pads, the contact hole and a sub-via adjacent to it are formed synchronously, and the conductive part is partially located in the contact hole.

[0045] In one embodiment, the sub-via is formed by a laser etching process.

[0046] In one embodiment, the insulating material layers without sub-vias are respectively provided on two opposite surfaces of the structure obtained in the previous step, and the stacked insulating material layers are bonded together, comprising:

[0047] Insulating material layers are respectively arranged on both sides of the structure obtained in the previous step, and the stacked insulating material layers are pressed together to bond the stacked insulating material layers together.

[0048] In one embodiment, the total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the materials and thicknesses of the two insulating material layers with the same number of insulating material layers separated from the middle insulating material layer are the same.

[0049] The printed circuit board and the method for preparing the printed circuit board provided in the embodiments of the present application are such that, in two adjacent insulating film layers, the vias provided in the insulating film layer with the larger dielectric constant have a smaller average area of ​​each cross-section parallel to the stacking direction of the insulating film layers. This helps to reduce the difference in impedance between adjacent vias and improve the continuity of impedance between adjacent vias, thereby reducing signal reflection during signal transmission, improving the return loss of the through-hole, and improving signal integrity. The printed circuit board provided in the embodiments of the present application can make the impedance of each via substantially the same by adjusting the size of the vias in different insulating film layers, thereby effectively improving signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a partial cross-sectional view of a printed circuit board provided by an exemplary embodiment of the present application;

[0051] FIG2 is a top view of a portion of the printed circuit board shown in FIG1 ;

[0052] FIG3 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application;

[0053] FIG4 is a top view of a portion of the printed circuit board shown in FIG3 ;

[0054] FIG5 is a partial cross-sectional view of a printed circuit board provided by yet another exemplary embodiment of the present application;

[0055] FIG6 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application;

[0056] FIG7 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application;

[0057] FIG8 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application;

[0058] FIG9 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application;

[0059] 10 and 11 are diagrams showing simulation results of the printed circuit board shown in FIG5 ;

[0060] FIG12 is a partial cross-sectional view of a printed circuit board provided by an exemplary embodiment of the present application;

[0061] FIG13 is a flow chart of a method for preparing a printed circuit board provided by an exemplary embodiment of the present application;

[0062] FIG14 is a partial cross-sectional view of a first intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0063] FIG15 is a partial cross-sectional view of a second intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0064] FIG16 is a perspective schematic diagram of a partial structure of a first intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0065] FIG17 is a flow chart of a method for preparing a printed circuit board provided by another exemplary embodiment of the present application;

[0066] FIG18 is a partial cross-sectional view of a third intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0067] FIG19 is a partial cross-sectional view of a fourth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0068] FIG20 is a flow chart of a method for preparing a printed circuit board provided in yet another exemplary embodiment of the present application;

[0069] FIG21 is a partial cross-sectional view of a fifth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0070] FIG22 is a partial cross-sectional view of a sixth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0071] FIG23 is a perspective schematic diagram of a partial structure of a sixth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0072] FIG24 is a partial cross-sectional view of a seventh intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0073] FIG25 is a partial cross-sectional view of an eighth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application;

[0074] FIG. 26 is a partial cross-sectional view of a ninth intermediate structure of a printed circuit board according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0075] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0076] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0077] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0078] A printed circuit board (PCB) comprises multiple stacked insulating film layers and multiple signal lines. The PCB is provided with through-holes, within which conductive structures are located, electrically connecting the signal lines to the conductive structures. The signal lines may include differential signal lines, and the through-holes containing the conductive structures connected to the differential signal lines are called differential vias. The impedance of the differential vias significantly impacts the signal integrity of signals transmitted by the differential signal lines.

[0079] As shown in Figure 1, the printed circuit board includes two first insulating film layers 10', a second insulating film layer 20', a solder pad 30', a conductive structure 40' and a signal line 60'. The second insulating film layer 20' is located between the two first insulating film layers 10'. The first insulating film layer 10' and the second insulating film layer 20' each include a plurality of stacked insulating material layers 11'. The dielectric constant of the material of the first insulating film layer 10' is smaller than the dielectric constant of the material of the second insulating film layer 20'. Some of the solder pads 30' are located on the surfaces of the two first insulating film layers 10' away from the second insulating film layer 20', and some of the solder pads 30' are located between two adjacent insulating material layers 11'. The printed circuit board is provided with differential vias 101', and the aperture of the differential vias 101' is substantially the same at all locations; the differential vias 101' include vias penetrating each insulating film layer 11' and contact holes penetrating the solder pads 30', and the conductive structure 40' is located within the differential vias 101'. The signal line 60' is connected to the conductive structure 40' through the pad 30'. The printed circuit board also includes a plurality of conductive layers 50', a conductive layer 50' is provided between at least two adjacent insulating material layers 11' of the first insulating film layer 10', and a conductive layer 50' is provided between at least two adjacent insulating material layers 11' of the second insulating film layer 20'. The conductive layer 50' located in the first insulating film layer 10' is provided with anti-pads 501' corresponding to each conductive structure 40', and the conductive layer 50' located in the second insulating film layer 20' is provided with anti-pads 502' corresponding to each conductive structure 40'. In the present application, the anti-pad is an opening that passes through the conductive layer. As shown in Figure 2, the conductive structure 40' passes through the corresponding anti-pads 501', 502' to prevent the conductive layer 50' from contacting the conductive structure 40'.

[0080] When signals are transmitted through the conductive structure, ensuring that the impedance of the vias in each insulating film layer of the PCB is the same or has minimal differences can effectively improve signal reflection during signal transmission, improve the return loss of the differential vias, and enhance signal integrity. The target impedance of the vias in each insulating film layer is determined based on the overall impedance requirements of the system, including the PCB and the electronic components connected to it. When the impedance of the vias in each insulating film layer is the same as or has minimal differences from the target impedance, signal quality is improved.

[0081] The inventors have discovered that a greater dielectric constant of the insulating film layer results in a lower impedance of the insulating film's via hole; a smaller diameter of the insulating film's via hole results in a lower impedance of the insulating film's via hole; and a larger anti-pad size of the conductive layer within the insulating film layer results in a higher impedance of the insulating film's via hole. By varying the diameter of the insulating film's via hole and the size of the anti-pad, the impedance of the insulating film's via hole can be adjusted.

[0082] In the printed circuit board shown in FIG1 , the material of the first insulating film layer 10' is different from the material of the second insulating film layer 20'. The dielectric constant of the first insulating film layer 10' is 3, and the dielectric constant of the second insulating film layer 20' is 4. The target impedance of the vias in each insulating film layer is 92 ohms. If the size of the anti-pads located in the conductive layer of the first insulating film layer 10' is the same as the size of the anti-pads located in the conductive layer of the second insulating film layer 20', the impedance of the vias in the first insulating film layer will be smaller than the impedance of the vias in the second insulating film layer. If the size of each anti-pad is not restricted, the size of each anti-pad can be adjusted so that the size of the anti-pads located in the conductive layer within the second insulating film layer is larger than the size of the anti-pads located in the conductive layer within the first insulating film layer. This can reduce the difference in impedance between the vias in the first insulating film layer and the vias in the second insulating film layer, thereby making the impedance of the vias in each insulating film layer close to the target impedance. After optimizing the dimensions of each anti-pad, a first printed circuit board (PCB) was obtained. Simulation software was used to simulate this first PCB, yielding the following results: the impedance difference between the vias in each insulating film layer and the target impedance ranged from -2 ohms to 2 ohms. When the signal frequency ranged from 0 to 26.56 GHz, the differential via return loss reached a minimum of -25 dB, indicating good signal integrity. The dimensions of each anti-pad in the first PCB are considered ideal. The signal frequency range of 0 to 26.56 GHz refers to simulations performed at the fundamental frequency of Ethernet 112G signals, 26.56 GHz. The frequencies of the signals mentioned below are identical.

[0083] However, in the design of a printed circuit board (PCB), the size of the anti-pad on the conductive layer is limited by the traces located within the conductive layer, such as power signal lines. To avoid signal crosstalk and maintain the distance between traces adjacent to the anti-pad, a certain distance must be maintained between the traces and the anti-pad, resulting in the anti-pad on the conductive layer within the second insulating film layer being smaller than the ideal size. The size of the anti-pad on the conductive layer within the second insulating film layer of the first PCB was reduced to the minimum size allowed by the process to produce a second PCB. Simulation software was used to simulate the second PCB, yielding the following results: the maximum impedance of the vias in the first insulating film layer was 93 ohms, while the minimum impedance of the vias in the second insulating film layer was 84.5 ohms. When the signal frequency was in the range of 0 to 26.56 GHz, the maximum return loss of the differential vias was -16.5 dB, significantly reducing the signal integrity compared to the first PCB.

[0084] Because the impedance of the vias in the second insulating film layer was relatively low, to further improve signal quality, the PCB structure was further improved, reducing the aperture of the differential vias by 1 mil. This resulted in a third PCB. Simulation software for this third PCB yielded the following results: the minimum impedance of the vias in the second insulating film layer was 89.5 ohms, while the maximum impedance of the vias in the first insulating film layer was 99.2 ohms. When the signal frequency ranged from 0 to 26.56 GHz, the maximum return loss of the differential vias was -13.2 dB, significantly degrading the signal quality compared to the first PCB.

[0085] It can be seen that the above adjustment of the aperture of the differential via and the size of the anti-pad cannot effectively improve the signal quality.

[0086] The present invention provides a printed circuit board and a method for manufacturing a printed circuit board, which can improve signal quality. The printed circuit board and the printed circuit board in the present invention are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.

[0087] The embodiment of the present application provides a printed circuit board. As shown in FIG3 , the printed circuit board includes a main body layer 10 , a conductive structure 20 , and a signal line 30 .

[0088] The main layer 10 includes a plurality of stacked insulating film layers 11; the dielectric materials of adjacent insulating film layers 11 are different, so that the dielectric constants of adjacent insulating film layers 11 are different; the main layer 10 is provided with a through hole 101 passing through the main layer 10, and the through hole 101 includes a via hole 111 passing through each insulating film layer 11; among two adjacent insulating film layers 11, the average area of ​​each cross-section of the via hole 111 of one insulating film layer 11 perpendicular to the stacking direction X of the insulating film layer 11 is a first area, and the dielectric constant is the first dielectric constant; the average area of ​​each cross-section of the via hole 111 of the other insulating film layer 11 perpendicular to the stacking direction is a second area, and the dielectric constant is the second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area. If the areas of all cross sections of the via 111 along the stacking direction X are the same, the areas of all cross sections are the same as the average area. If the areas of all cross sections of the via 111 perpendicular to the stacking direction X are not all the same, the average area is the average of the areas of all cross sections. The conductive structure 20 is located within the through hole 101 of the main layer 10, completely filling the through hole 101. The signal line 30 is electrically connected to the conductive structure 20.

[0089] The printed circuit board provided in the embodiment of the present application is configured such that, in two adjacent insulating film layers, the average area of ​​each cross-section of the vias provided in the insulating film layer with a larger dielectric constant and parallel to the stacking direction of the insulating film layers is smaller, thereby helping to reduce the difference in impedance of the vias in adjacent insulating film layers and improve the impedance continuity of adjacent vias, thereby reducing signal reflection during signal transmission, improving the return loss of the through-holes, and improving signal integrity. The printed circuit board provided in the embodiment of the present application can make the impedance of each via substantially the same by adjusting the size of the vias in different insulating film layers, thereby effectively improving signal integrity.

[0090] In one embodiment, the signal lines include at least one of differential signal lines and single-ended signal lines. The signal integrity of differential signal lines and single-ended signal lines is significantly affected by the impedance of the vias. Designing the vias containing the conductive structures connected to the differential signal lines and single-ended signal lines to have the aforementioned structure can effectively improve the integrity of the signals transmitted therethrough. The vias containing the conductive structures connected to the differential signal lines are differential vias. The main body layer can be provided with multiple pairs of differential vias, with the two differential vias of the same pair being arranged adjacent to each other. The single-ended signal lines can be parallel buses.

[0091] In one embodiment, as shown in FIG3 , the first insulating film layer 11 and the second insulating film layer 12 each include multiple stacked insulating material layers 112 . Each insulating material layer within the same insulating film layer can have the same thickness. Adjacent insulating material layers are in direct contact with no gaps. The signal line 30 can be located between two adjacent insulating material layers 112 or on the surface of the main body layer 10 .

[0092] In one embodiment, as shown in FIG3 , the main body layer 10 further includes a plurality of conductive layers 40 . Some conductive layers 40 are located between two adjacent insulating material layers 112 of the first insulating film layer 11 , while other conductive layers 40 are located between two adjacent insulating material layers 112 of the second insulating film layer 12 . The conductive layers 40 may also be located between the first insulating film layer 11 and the second insulating film layer 12 . The conductive layers 40 located between two adjacent insulating material layers 112 of the first insulating film layer 11 are provided with anti-pads 41 , and the conductive layers 40 located between two adjacent insulating material layers 112 of the second insulating film layer 12 are provided with anti-pads 42 . Each conductive layer is provided with an anti-pad corresponding to the conductive structure 20 . The conductive structure 20 is provided with its corresponding anti-pad 41 and 42 to prevent the conductive layer 40 from contacting the conductive structure 20 and causing a short circuit. Two adjacent conductive structures 20 may pass through the same anti-pad 42 . The insulating material layer fills the anti-pad 42 . The conductive layer 40 may be a ground signal layer (GND layer) or a power signal layer (POWER layer).

[0093] 3 , the size of the anti-pad 41 provided on the conductive layer 40 between two adjacent insulating material layers 112 is smaller than the size of the anti-pad 42 provided on the conductive layer 40 between two adjacent insulating material layers 122. This configuration also helps to reduce the impedance difference between two adjacent vias.

[0094] In one embodiment, as shown in FIG. 3 , two adjacent conductive structures 20 pass through the same anti-pad 42 , that is, the anti-pads corresponding to the two adjacent conductive structures 20 are connected.

[0095] In one embodiment, the conductive structure 20 may completely fill the through hole 101 in which it is located. In other embodiments, the conductive structure 20 may be a hollow structure, only covering the hole wall of the through hole 101 in which it is located.

[0096] In one embodiment, as shown in FIG3 , the main body layer 10 further includes a return ground via 102 that extends through the main body layer 10. The printed circuit board also includes a conductive material portion 61 located within the return ground via 102. The return ground via 102 can reduce the return path of the signal transmitted by the conductive structure 20, thereby facilitating control of the via's impedance. The area and shape of each cross-section of the return ground via 102 perpendicular to the stacking direction X can be uniform; for example, the return ground via 102 can be cylindrical.

[0097] In one embodiment, as shown in FIG3 , the main body layer 10 may further include a pad structure 62. The pad structures 62 are provided on two opposing surfaces of the main body layer 10, one corresponding to the conductive material portion 61. The reflow ground via 102 further includes a contact hole 621 extending through the pad structure 62, with the conductive material portion 61 partially located within the contact hole 621. Some pad structures 62 are provided on the same layer as the ground signal layer, and the ground signal layer is connected to each of the pad structures 62 provided on the same layer. The ground signal layer is electrically connected to the conductive material portion 61 via the pad structures 62. The pad structures 62 provided on the same layer and the ground signal layer may be an integral structure.

[0098] In one embodiment, as shown in FIG3 , the main body layer 10 further includes a plurality of pads 50, and the through-hole 101 further includes a contact hole 51 extending through the pads 50. The conductive structure 20 is in direct contact with the pads 50. Some of the pads 50 are connected to the signal lines 30, and the signal lines 30 are electrically connected to the conductive structure 20 through the pads 50 connected thereto. The provision of the pads 50 facilitates the electrical connection between the signal lines 30 and the conductive structure 20.

[0099] In one embodiment, as shown in FIG3 , solder pads 50 are respectively provided on two opposing surfaces of the main body layer. The solder pads 50 on the same surface correspond one-to-one with the conductive structures 20, and portions of the conductive structures 20 are located within the contact holes 51 of the corresponding solder pads 50. The surfaces of the conductive structures 20 and the solder pads 50 on the same side may be flush.

[0100] In one embodiment, as shown in FIG3 , a pad 50 is provided between two adjacent insulating film layers 11. Thus, when the centers of two adjacent via holes 111 are offset, the portions of the conductive structure 20 located within the two adjacent via holes 111 can be electrically connected via the pad 50, thereby improving the electrical connection reliability of the portions of the conductive structure 20 located within the two adjacent via holes 111.

[0101] In one embodiment, as shown in FIG. 4 , the orthographic projection of the contact hole 51 of the pad 50 on a plane perpendicular to the stacking direction X coincides with the orthographic projection of one of the adjacent via holes 111 toward the pad 50 on the plane.

[0102] In one embodiment, as shown in FIG4 , the outer edge of the orthographic projection of the pad 50 onto a plane perpendicular to the stacking direction is a first edge 501. The orthographic projection edges of the two vias 111 adjacent to the pad 50 onto the plane are a second edge 114 and a third edge 115, respectively. The second edge 114 and the third edge 115 are located inward of the first edge 501. In the embodiment shown in FIG4 , the orthographic projection edge of the via with the larger average area onto the plane is the second edge 114, and the orthographic projection edge of the via with the smaller average area onto the plane is the third edge 115. This arrangement ensures that even if the geometric centers of two adjacent vias 111 shift relative to each other due to process variations during the manufacturing process, the portion of the conductive structure 20 located within the two adjacent vias 111 can be in contact with the pad 50 located between the two vias 111, thereby ensuring the electrical connection reliability of the portion of the conductive structure 20 located within the two adjacent vias 111.

[0103] 3 , some of the pads 50 connected to the conductive structure 20 on the printed circuit board are connected to the signal line 30. In other embodiments, all pads 50 on the main body layer may be connected to the signal line.

[0104] In one embodiment, of two adjacent vias 111 in the same through hole 101, the orthographic projection of one via 111 on a plane perpendicular to the stacking direction is a first projection, and the orthographic projection of the other via 111 on the plane is a second projection, with the first projection falling within the second projection. That is, of two adjacent vias 111 in the same through hole 101, the orthographic projection of the via 111 with a smaller average area on the plane is the first projection, and the orthographic projection of the via 111 with a larger average area on the plane is the second projection. With this arrangement, the size of the pad 50 can be set smaller, thereby reducing the impact of the pad 50 on the impedance of the via.

[0105] Furthermore, the via holes 111 of the same through hole 101 are coaxial.

[0106] In one embodiment, as shown in FIG4 , the cross-section of the via 111 perpendicular to the stacking direction X is circular. This makes the via 111 easier to process and simplifies the manufacturing process. In other embodiments, the cross-section of the via 111 perpendicular to the stacking direction X may be non-circular, such as rectangular or irregular.

[0107] In one embodiment, at least two insulating film layers 11 in the main layer 10 are made of the same material, and the vias 111 of the insulating film layers 11 made of the same material have substantially the same average area in each cross-section perpendicular to the stacking direction X. Substantially the same average area refers to the same average area, or a very small difference in average area. For example, the designed average areas are the same, but there may be a small difference in average area due to process errors. This configuration ensures that the vias in the insulating film layers 11 made of the same material have substantially the same impedance, which helps improve signal quality.

[0108] In one embodiment, the total number of insulating film layers 11 in the main body layer 10 is an odd number, the number of insulating film layers 11 on either side of the central insulating film layer 11 is the same, and the two insulating film layers 11 separated by the same number of insulating film layers 11 from the central insulating film layer 11 are made of the same material and have the same thickness. During the manufacture of the printed circuit board, a lamination process can be used to bond all the film layers of the main body layer. This arrangement ensures that the forces acting on both sides of each insulating material layer during the lamination process are relatively balanced, preventing deformation of the central insulating film layer 11 and helping to improve the quality of the printed circuit board.

[0109] In the embodiment shown in FIG3 , the main body layer 10 includes a first insulating film layer 71 and two second insulating film layers 72 located on either side of the first insulating film layer 71. The first insulating film layer 71 is the central insulating film layer, and no insulating film layer is interposed between the two second insulating film layers 72 and the first insulating film layer 71. The two second insulating film layers 71 are made of the same material and have the same thickness. In the embodiment shown in FIG5 , the main body layer 10 includes two first insulating film layers 71 and a second insulating film layer 72 located between the two first insulating film layers 71. The second insulating film layer 72 is the central insulating film layer, and no insulating film layer is interposed between the two first insulating film layers 71 and the second insulating film layer 72. The two first insulating film layers 71 are made of the same material and have the same thickness. In the embodiment shown in Figure 6, the main layer includes a first insulating film layer 71, two second insulating film layers 72 and two third insulating film layers 73; the two second insulating film layers 72 are located between the two third insulating film layers 73, and the first insulating film layer 71 is located between the two second insulating film layers 72; the first insulating film layer 71 is an insulating film layer located in the middle, and there is no insulating film layer between the two second insulating film layers 72 and the first insulating film layer 71, so the material and thickness of the two second insulating film layers 72 are the same; there is an insulating film layer between the two third insulating film layers 72 and the first insulating film layer 71, so the material and thickness of the two third insulating film layers 73 are the same. In the embodiment shown in Figure 7, the main layer includes a third insulating film layer 73, two second insulating film layers 72 and two first insulating film layers 71, the two second insulating film layers 72 are located between the two first insulating film layers 71, and the third insulating film layer 73 is located between the two second insulating film layers 72; the third insulating film layer 73 is an insulating film layer located in the middle, the material and thickness of the two second insulating film layers 72 are the same, and the material and thickness of the two first insulating film layers 71 are the same.

[0110] Furthermore, the multiple conductive layers 40 in the main body layer 10 are symmetrically distributed on both sides of the insulating material layer located in the middle. This ensures that during the lamination process of the insulating material layers, the lamination forces on both sides of the insulating material layers and the conductive layers are more balanced, preventing deformation of the film layers and helping to improve the quality of the printed circuit board.

[0111] In one embodiment, as shown in FIG. 3 and FIG. 5 to FIG. 8 , the shapes and sizes of the cross sections of the same via hole 111 perpendicular to the stacking direction X are substantially the same.

[0112] In another embodiment, as shown in FIG9 , the total number of insulating material layers 112 in the main body layer 10 is an odd number, and the number of insulating material layers 112 on both sides of the middle insulating material layer 112 is the same; the via 111 includes sub-vias 113 that penetrate each of the insulating material layers; in the insulating material layers 112 on both sides of the middle insulating material layer 112, the cross-sectional area of ​​the sub-vias 113 perpendicular to the stacking direction X gradually decreases in the direction toward the middle insulating material layer. The conductive structure 20 includes a plurality of conductive portions 21, with each conductive portion 21 located within a sub-via 113. In this embodiment, different sub-vias 113 of the same via 111 are formed in different steps of the same process, and different conductive portions 21 of the same conductive structure 20 are formed in different process steps. The sub-vias 113 of each insulating material layer 112 can be formed using a laser etching process.

[0113] Furthermore, as shown in FIG9 , a pad 50 is provided between each adjacent insulating material layer 112. The through hole 101 further includes a contact hole 51 extending through each pad 50. The conductive structure 20 is in direct contact with the pad 50. By providing a pad 50 between two adjacent insulating material layers, when the centers of two adjacent sub-vias 113 are offset, the two adjacent conductive portions 21 can be electrically connected via the pad 50, thereby improving the reliability of the electrical connection between the two adjacent conductive portions 21.

[0114] Furthermore, the outer edge of the orthographic projection of the pad 50 on a plane perpendicular to the stacking direction X is the fourth edge, and the edges of the orthographic projections of the two sub-vias 113 adjacent to the pad 50 on the plane are the fifth edge and the sixth edge, respectively. The fifth edge and the sixth edge are located inward of the fourth edge. This arrangement ensures the reliability of the electrical connection between the two adjacent conductive portions.

[0115] In one embodiment, as shown in FIG. 9 , at least one of the pads 50 is disposed on the same layer as the conductive layer 40 , and the pad 50 is located within the anti-pad of the conductive layer 40 disposed on the same layer.

[0116] In one embodiment, as shown in Figures 3 and 5 to 8, the insulating film layer of the main layer 10 includes adjacent first insulating film layers 71 and second insulating film layers 72, the dielectric constant of the first insulating film layer 71 is greater than the dielectric constant of the second insulating film layer 72, and the through hole 101 includes a first via hole 711 passing through the first insulating film layer 71 and a second via hole 721 passing through the second insulating film layer 72, the average area of ​​each cross section of the first via hole 711 perpendicular to the stacking direction X is a first area, the average area of ​​each cross section of the second via hole 721 perpendicular to the stacking direction X is a second area, and the first area is smaller than the second area.

[0117] In one embodiment, as shown in Figures 3 and 5 , the first insulating film layers 71 and the second insulating film layers 72 are alternately arranged in the main body layer 10. In the embodiment shown in Figure 3 , the main body layer 10 includes two first insulating film layers 71 and a second insulating film layer 72 located between the two first insulating film layers 71. In the embodiment shown in Figure 5 , the main body layer 10 includes two second insulating film layers 72 and a first insulating film layer 71 located between the two second insulating film layers 72.

[0118] In one embodiment, as shown in Figures 6 to 8, the main layer 10 further includes a third insulating film layer 73, and the dielectric constant of the material of the third insulating film layer 73 is greater than the dielectric constant of the material of the first insulating film layer 71; the through hole 101 further includes a third via hole 731 passing through the third insulating film layer 73; the average area of ​​each cross-section of the third via hole 731 perpendicular to the stacking direction X is a third area, and the third area is smaller than the first area.

[0119] In the embodiments shown in Figures 6 and 7, the third insulating film layer 73 is provided on the side of the second insulating film layer 72 away from the first insulating film layer 71. In the embodiment shown in Figure 6, the main layer includes two second insulating film layers 72 and a first insulating film layer 71 located between the two second insulating film layers 72, and the third insulating film layer 73 is provided on the side of the two second insulating film layers 72 away from the first insulating film layer 71; in the direction toward the insulating film layer located in the middle (that is, the first insulating film layer 71), the average area of ​​the via 111 gradually decreases. In the embodiment shown in Figure 7, the main layer 10 includes two first insulating film layers 71 and two insulating film layers 72 located between the two first insulating film layers 71, and the third insulating film layer 73 is located between the two second insulating film layers 72; from the insulating film layer located in the middle (that is, the third insulating film layer 73) to the insulating film layers on both sides, the average area of ​​the via 111 first increases and then decreases. In the embodiment shown in Figure 8, the third insulating film layer 73 is provided on the side of the first insulating film layer 71 away from the second insulating film layer 72, and the main layer 10 includes two first insulating film layers 71, and the third insulating film layer 73 is located between the two first insulating film layers 71; from the insulating film layer located in the middle (that is, the third insulating film layer 73) to the insulating film layers on both sides, the average area of ​​the via 111 first decreases and then increases.

[0120] It should be noted that the accompanying drawings only illustrate the example of the main layer including two or three insulating film layers with different dielectric constants. The main layer may include four or more insulating film layers with different dielectric constants, and the arrangement of the insulating film layers in the stacking direction can be selected according to needs.

[0121] In order to verify the effect of the printed circuit board provided in the embodiment of the present application on improving signal quality, simulation software was used to simulate the vias of the printed circuit board shown in Figure 5 of the present application. The simulation results shown in Figures 10 and 11 were obtained. Figure 10 is a graph showing the relationship between the impedance of the via and the test time, and Figure 11 is a graph showing the relationship between the return loss and the signal frequency. According to Figures 10 and 11, it can be seen that the minimum impedance of the via in the insulating film layer is 88.2 ohms, and the maximum impedance of the via is 93.3 ohms. When the signal frequency is in the range of 0 to 26.56 GHz, the minimum return loss of the differential via is -21.6 dB.

[0122] The printed circuit board shown in FIG5 of the present application can significantly improve signal integrity compared to the second and third printed circuit boards. Of the second and third printed circuit boards, the third printed circuit board has better signal quality. According to the simulation results of the third printed circuit board, the maximum absolute value of the difference between the impedance of the via and the target impedance is 7.2 ohms, and the minimum return loss of the differential via is -16.5dB. According to the simulation results of the printed circuit board shown in FIG5, the maximum absolute value of the difference between the impedance of the via and the target impedance is 3.8 ohms, and the minimum return loss of the differential via is -21.6dB. Calculations show that, compared to the third printed circuit board, the printed circuit board shown in FIG5 can reduce the maximum absolute value of the difference between the impedance of the via and the target impedance by 47% and increase the return loss by 31%, indicating that the printed circuit board provided by the embodiment of the present application can effectively improve signal integrity.

[0123] The present application also provides a method for preparing a printed circuit board. The preparation method includes the following steps: forming a main body layer; the main body layer includes a plurality of insulating film layers stacked together; the dielectric constants of adjacent insulating film layers are different; the main body layer is provided with through holes penetrating the main body layer, and the through holes include vias penetrating each insulating film layer; in two adjacent insulating film layers, the average area of ​​each cross section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant, and the average area of ​​each cross section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area. The main body layer also includes a signal line. The preparation method also includes the following steps: forming a conductive structure located in the through hole. The signal line is electrically connected to the conductive structure.

[0124] Example 1

[0125] In this embodiment, the printed circuit board is the printed circuit board shown in FIG. 3 . As shown in FIG. 12 , the preparation method includes the following steps 110 to 140 .

[0126] In step 110, an intermediate structure is provided, which includes a first insulating film layer, two second insulating film layers located on both sides of the first insulating film layer, and a signal line, wherein the dielectric constant of the material of the first insulating film layer is smaller than the dielectric constant of the second insulating film layer.

[0127] As shown in FIG13 , the intermediate structure includes three insulating film layers 11: a first insulating film layer 71 and two second insulating film layers 72, with the first insulating film layer 71 located between the two second insulating film layers 72. Both the first insulating film layer 71 and the second insulating film layer 72 include multiple insulating material layers 112. The intermediate structure also includes multiple conductive layers 40, multiple solder pads 50, multiple solder pad structures 62, and multiple signal lines 30. Each conductive layer 40 is located between two adjacent insulating material layers 112, and the conductive layer 40 is provided with anti-pads 41 and 42. A solder pad 50 corresponding to the through hole 101 to be formed is provided between each adjacent insulating film layer 11. Two opposing surfaces of the intermediate structure are provided with solder pads 50 corresponding to the through hole 101 to be formed. At least one solder pad 50 is connected to the signal line 30. In this step, both the solder pad 50 and the solder pad structure 62 are conductive blocks without contact holes.

[0128] In one embodiment, the intermediate structure can be formed by the following steps: first, all the insulating material layers 112, the conductive layer 40, the pad structure 62 and the pad 50 of the main layer are stacked, a conductive layer is formed on the surface of part of the insulating material layer 112, a pad 50 is formed on the surface of part of the insulating material layer 112, and a pad structure 62 is formed on the surface of part of the insulating material layer 112, at least one pad is connected to the signal line and is located on the surface of the same insulating material layer; then, the stacked insulating material layers are pressed together so that the insulating material layers 112 are bonded together, and the two adjacent insulating material layers 112 are in direct contact, and the anti-pads 41 and 42 of the conductive layer are filled with the adjacent insulating material layers.

[0129] In step 120, an opening is formed through the main layer, and the shapes and areas of the cross sections of the opening perpendicular to the stacking direction of the insulating film layer are substantially the same; the portion of the opening located in the first insulating film layer is a first via hole.

[0130] Through this step, a first intermediate structure can be obtained as shown in Figure 14. As shown in Figure 14, the openings 103 penetrate through each insulating film layer 11 and the corresponding pads 50.

[0131] In one embodiment, forming the opening through the main body layer includes the following process: drilling the main body layer using a first drill bit to form the opening through the main body layer. Using the first drill bit to form the opening is simple and easy to implement, and can better control the size of the opening 103. The opening 103 formed using the first drill bit has a substantially circular cross-section perpendicular to the stacking direction X.

[0132] In step 130 , material in the area of ​​the second insulating film layer adjacent to the via hole is removed to form a second via hole, so that the cross-sectional area of ​​the second via hole perpendicular to the stacking direction is larger than the cross-sectional area of ​​the first via hole perpendicular to the stacking direction.

[0133] This step results in a second intermediate structure, shown in Figures 15 and 16 , which is the main layer. As shown in Figures 15 and 16 , contact holes 51 are formed on pads 50. The main layer also has reflow vias 102 formed therein. Reflow vias 102 can be formed before or after the second vias are formed.

[0134] In one embodiment, the step of removing material from an area of ​​the second insulating film layer adjacent to the via hole to form the second via hole includes the following process: drilling the second insulating film layer using a second drill bit, wherein the maximum outer diameter of the second drill bit is greater than the maximum outer diameter of the first drill bit, and the second drill bit is partially located within the opening during drilling. Because the maximum outer diameter of the second drill bit is greater than the maximum outer diameter of the first drill bit, and the second drill bit is partially located within the opening during drilling of the second insulating film layer, the second drill bit can remove material from the second insulating film layer adjacent to the opening.

[0135] In one embodiment, when the size of the contact hole 51 of the pad 50 is the same as the size of the adjacent first via 711, the portion of the opening located in the pad 50 is the first via; when the size of the contact hole 51 of the pad 50 is the same as the size of the adjacent second via 712, when a second drill bit is used to drill the second insulating film layer 72, the second drill bit removes the material of the area adjacent to the pad 50 and the via, thereby forming a contact hole.

[0136] In one embodiment, the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction of the insulating film layer is the first edge, and the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge, respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.

[0137] In step 140 , a conductive structure is formed in the through hole including the first via hole and the second via hole.

[0138] In one embodiment, an electroplating process may be used to form the conductive structure in the through hole.

[0139] The method for preparing a printed circuit board through steps 110 to 140 requires only one lamination process, which helps to simplify the preparation process.

[0140] In one embodiment, the method for preparing a printed circuit board further includes forming a conductive structure within the return ground via. The step of forming the conductive structure within the return ground via can be performed simultaneously with step 140. This embodiment can produce the printed circuit board shown in FIG3 .

[0141] In one embodiment, the intermediate structure may further include a third insulating film layer located on a side of each second insulating film layer away from the first insulating film layer, wherein the dielectric constant of the material of the third insulating film layer is less than the dielectric constant of the material of the second insulating film layer. The opening formed in step 120 penetrates the third insulating film layer; in step 130, the second drill bit simultaneously removes the area of ​​the third insulating film layer adjacent to the opening, thereby forming a sub-via located in the third insulating film layer; after step 130, the method for preparing a printed circuit board further includes: drilling the third insulating film layer using a third drill bit, removing material from the area of ​​the third insulating film layer adjacent to the sub-via, thereby forming a third via that penetrates the third insulating film layer; the maximum outer diameter of the third drill bit is greater than the maximum outer diameter of the second drill bit. This embodiment can produce a printed circuit board as shown in Figure 6.

[0142] Example 2

[0143] In this embodiment, the main body layer includes two second insulating film layers and a first insulating film layer located between the two second insulating film layers. The dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer. At least one surface of at least one of the first insulating film layer and the second insulating film layer is provided with a signal line. As shown in Figure 17, the preparation method includes the following steps 210 to 230.

[0144] In step 210 , a first via hole is formed through the first insulating film layer.

[0145] This step yields a third intermediate structure as shown in FIG18 . As shown in FIG18 , the first insulating film layer 71 includes multiple stacked insulating material layers 112 ; the third intermediate structure also includes a conductive layer 40 , a signal line 30 , and a pad 50 . The conductive layer 40 is located on a surface of the first insulating film layer 71 . The first insulating film layer 71 has two opposing surfaces provided with pads 50 and signal lines corresponding to the first vias 711 , respectively. The signal lines 30 are connected to the pads 50 , and the first vias 711 penetrate each insulating film layer and the corresponding pads 50 .

[0146] In one embodiment, before step 210 , the conductive layer 40 , the signal line 30 , the pad 50 and the insulating material layer 112 are stacked and then bonded together using a lamination process.

[0147] In one embodiment, a first drill bit may be used to drill the first insulating film layer to form a first via hole.

[0148] In step 220 , the second insulating film layer is disposed on two opposite surfaces of the first insulating film layer, and the first insulating film layer and the second insulating film layer are bonded to form a second via hole penetrating the second insulating film layer and communicating with the first via hole.

[0149] In one embodiment, bonding the second insulating film layer to the first insulating film layer can produce a fourth intermediate structure as shown in FIG19 . As shown in FIG19 , the second insulating film layer 72 includes multiple insulating material layers 112 , and the fourth intermediate structure further includes a conductive layer 40 located between adjacent insulating material layers of the second insulating film layer 72 , a pad 50 located on a surface of the second insulating film layer 72 , a signal line 30 , and a pad structure.

[0150] In one embodiment, bonding the second insulating film layer to the first insulating film layer includes laminating the second insulating film layer and the first insulating film layer, and laminating the layer to bond the second insulating film layer to the first insulating film layer. Specifically, an insulating material layer, a conductive layer, and a pad of the second insulating film layer are disposed on two opposing surfaces of the third intermediate structure in a laminating order of the film layers, and then laminating the layers.

[0151] After forming the second via hole and the reflow via hole in the second insulating film layer, a second intermediate structure as shown in FIG. 15 and FIG. 16 can be obtained.

[0152] In step 230 , a conductive structure is formed in the through hole including the first via hole and the second via hole.

[0153] In one embodiment, the conductive structure may be formed using an electroplating process.

[0154] Through this step, a printed circuit board as shown in FIG3 can be obtained.

[0155] In one embodiment, the method for manufacturing a printed circuit board may further include the following steps: forming a return ground via extending through the main body layer; and forming a conductive structure within the return ground via. The steps of forming the return ground via and the conductive structure are described in Example 1 and are not further elaborated here.

[0156] In one embodiment, before step 230, the method for preparing a printed circuit board may further include the following steps: disposing a third insulating film layer on each of the two second insulating film layers on a side away from the first insulating film layer, laminating the third insulating film layer to adhere the second insulating film layer; and forming a third via hole penetrating the third insulating film layer. In this embodiment, the through hole further includes a third via hole. This embodiment can produce the printed circuit board shown in Figure 6.

[0157] Example 3

[0158] This embodiment only describes the differences from the second embodiment, and the similarities are not repeated here.

[0159] In this embodiment, the main body layer includes two first insulating film layers and a second insulating film layer located between the two first insulating film layers. The dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer. As shown in Figure 20, the preparation method includes the following steps 310 to 330. The following only describes the differences from the previous embodiment, and the similarities are not repeated.

[0160] In step 310 , a second via hole is formed through the second insulating film layer.

[0161] Through this step, a fifth intermediate structure as shown in FIG. 21 can be obtained.

[0162] In step 320 , the first insulating film layer is disposed on two opposite surfaces of the second insulating film layer, and the first insulating film layer and the second insulating film layer are bonded to form a first via hole penetrating the first insulating film layer and communicating with the second via hole.

[0163] Through this step, a sixth intermediate structure as shown in FIG. 22 and FIG. 23 can be obtained.

[0164] In step 330 , a conductive structure is formed in the through hole including the first via hole and the second via hole.

[0165] Through this embodiment, a printed circuit board as shown in FIG5 can be obtained.

[0166] The preparation process of the printed circuit boards shown in FIG. 7 and FIG. 8 is similar to that of the third embodiment and will not be described in detail.

[0167] Example 4

[0168] In this embodiment, the insulating film layer comprises a plurality of stacked insulating material layers, at least one of which has a signal line disposed on at least one side of at least one of the insulating material layers; the via comprises a sub-via extending through the insulating material layers; and the conductive structure comprises a conductive portion located within each of the sub-vias. The preparation method comprises the following steps:

[0169] First, a sub-via is formed in an insulating material layer, and a conductive portion is formed in the sub-via;

[0170] Then, the following steps are repeated until the main layer and the conductive structure are formed:

[0171] An insulating material layer without sub-vias is respectively provided on two opposite surfaces of the structure obtained in the previous step, and the stacked insulating material layers are bonded together; sub-vias are formed on the insulating material layer without sub-vias, and conductive parts are formed in the sub-vias.

[0172] In one embodiment, the conductive portions can be formed using an electroplating process. First, insulating material layers are provided on both sides of the structure obtained in the previous step, and then openings and conductive portions are formed within the openings. This allows for better contact between adjacent conductive portions, thereby improving the reliability of the electrical connection between adjacent conductive portions.

[0173] In one embodiment, the total number of insulating material layers in the main body layer is an odd number, and the number of insulating material layers on either side of the central insulating material layer is the same. The two insulating material layers separated by the same number of insulating material layers from the central insulating material layer are made of the same material and have the same thickness. The insulating material layer in which the sub-vias are first formed is the central insulating material layer in the main body layer. This ensures balanced forces on both sides of each insulating material layer during each lamination process, preventing deformation of the insulating material layers during the lamination process.

[0174] In one embodiment, the step of disposing an insulating material layer without sub-vias on two opposing surfaces of the structure obtained in the previous step and bonding the stacked insulating material layers comprises the following process: disposing an insulating material layer on each side of the structure obtained in the previous step, and laminating the stacked insulating material layers to bond the stacked insulating material layers. Specifically, in accordance with the stacking order of the film layers, insulating material layers, pads, signal lines, and conductive layers are disposed on two opposing surfaces of the structure obtained in the previous step, and the stacked film layers are laminated.

[0175] In one embodiment, the main body layer further includes a plurality of pads, the pads are provided between two adjacent insulating material layers, the through hole includes a contact hole passing through the pads, and the conductive portion is partially located in the contact hole.

[0176] In one embodiment, the total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the materials and thicknesses of the two insulating material layers with the same number of insulating material layers separated from the middle insulating material layer are the same.

[0177] In one embodiment, in the insulating material layers on both sides of the middle insulating material layer, the cross-sectional areas of the sub-vias of the insulating material layers perpendicular to the stacking direction gradually decrease in a direction toward the middle insulating material layer.

[0178] The following describes the formation process of a printed circuit board, taking the printed circuit board shown in Figure 9 as an example:

[0179] First, a sub-via is formed in an insulating material layer, and a conductive structure is formed in the via.

[0180] In this step, before forming the sub-via on the insulating material layer, a pad and a conductive layer can be provided on two opposite surfaces of the insulating material layer, respectively. The pad and the conductive layer located on the same surface of the insulating material layer can be formed simultaneously, and the pad is located inside the anti-pad of the conductive layer. This step can obtain the seventh intermediate structure shown in Figure 24. As shown in Figure 24, the insulating material layer 112 is provided with a pad 50 and a conductive layer 40 on two opposite surfaces, respectively; the pad 50 is formed with a contact hole 51, and the contact hole 51 is connected to the sub-via 113; the conductive layer 40 is provided with an anti-pad 41, and the pad 50 located on the same surface of the insulating material layer as the conductive layer 40 is located inside the anti-pad 41 of the conductive layer 40; the conductive portion 21 passes through the anti-pad 41, and a portion of the conductive portion 21 is located inside the contact hole 51.

[0181] In one embodiment, the contact hole 51 and the sub-via 113 of the pad 50 are formed by laser etching. In the direction from one surface to the other surface of the insulating material layer 112, the cross-section area of ​​the conductive portion 21 parallel to the surface gradually increases.

[0182] Subsequently, insulating material layers are respectively provided on two relative surfaces of the intermediate structure obtained in the previous step, that is, the seventh intermediate structure, and the insulating material layer without sub-vias is bonded to the insulating material layer with the sub-vias; sub-vias are formed on the insulating material layer without sub-vias, and a conductive part is formed within the sub-vias.

[0183] In this step, the insulating material layer without sub-vias is bonded to the insulating material layer with the sub-vias to obtain the eighth intermediate structure shown in Figure 25. As shown in Figure 25, the surfaces of the insulating material layer 112 on both sides are respectively provided with a pad 50 and a conductive layer 40.

[0184] Forming sub-vias in an insulating material layer without sub-vias and forming conductive portions within the sub-vias yields a ninth intermediate structure as shown in FIG26. As shown in FIG26, in the insulating material layers on both sides of the intermediate insulating material layer, the cross-sectional area of ​​the sub-vias 113 perpendicular to the stacking direction gradually decreases toward the intermediate insulating material layer.

[0185] Subsequently, insulating material layers are placed on both sides of the structure obtained in the previous step, and the stacked insulating material layers are laminated. Sub-vias are formed on the insulating material layers without sub-vias, and conductive portions are formed within the sub-vias. This step is repeated until a printed circuit board is obtained.

[0186] The embodiment of the method for printing a circuit board provided in the embodiment of the present application and the embodiment of the printed circuit board belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other.

[0187] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0188] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0189] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A printed circuit board, characterized in that: The printed circuit board comprises: The main layer includes multiple stacked insulating film layers, and the dielectric constants of adjacent insulating film layers are different; the main layer is provided with through holes penetrating the main layer, and the through holes include via holes penetrating each insulating film layer; among two adjacent insulating film layers, the average area of ​​each cross-section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant; the average area of ​​each cross-section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.

2. The printed circuit board according to claim 1, wherein: Among two adjacent via holes of the same through hole, the orthographic projection of one via hole on a plane perpendicular to the stacking direction is a first projection, the orthographic projection of the other via hole on the plane is a second projection, and the first projection falls within the second projection.

3. The printed circuit board according to claim 1, wherein: The main body layer further includes a plurality of pads, wherein the pads are arranged between two adjacent insulating film layers, and the through hole further includes a contact hole passing through the pads.

4. The printed circuit board according to claim 3, wherein: The outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the first edge, and the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.

5. The printed circuit board according to claim 1, wherein: At least two of the insulating film layers in the main layer are made of the same material, and the average areas of the via holes of the insulating film layers made of the same material and perpendicular to the stacking direction are substantially the same.

6. The printed circuit board according to claim 1, wherein: The total number of the insulating film layers is an odd number, the number of insulating film layers on both sides of the middle insulating film layer is the same, and the materials and thicknesses of the two insulating film layers with the same number of insulating film layers spaced apart from the middle insulating film layer are the same.

7. The printed circuit board according to claim 1, wherein: The shapes and sizes of the cross sections of the same via hole perpendicular to the stacking direction are substantially the same.

8. The printed circuit board according to claim 1, wherein: The insulating film layer includes multiple insulating material layers arranged in a stacked manner, the total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the via includes sub-vias passing through each of the insulating material layers; in the insulating material layers on both sides of the middle insulating material layer, in the direction toward the middle insulating material layer, the cross-sectional area of ​​the sub-vias of the insulating material layer perpendicular to the stacking direction gradually decreases.

9. The printed circuit board according to claim 8, wherein: The main body layer further includes a plurality of pads, each of which is provided between two adjacent insulating material layers, and the through hole further includes a contact hole passing through the pads.

10. The printed circuit board according to claim 9, wherein: The outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the fourth edge, and the edges of the positive projections of the two sub-vias adjacent to the pad on the plane are the fifth edge and the sixth edge respectively, and the fifth edge and the sixth edge are respectively located on the inner side of the fourth edge.

11. The printed circuit board according to claim 1, wherein The printed circuit board further includes a signal line and a conductive structure located in the through hole, wherein the signal line is electrically connected to the conductive structure; the signal line includes at least one of a differential signal line and a single-ended signal line.

12. The printed circuit board according to claim 1, wherein: The insulating film layer of the main body layer includes a first insulating film layer and a second insulating film layer adjacent to each other, the dielectric constant of the first insulating film layer is greater than the dielectric constant of the second insulating film layer, the through hole includes a first via hole penetrating the first insulating film layer and a second via hole penetrating the second insulating film layer, the average area of ​​each cross section of the first via hole perpendicular to the stacking direction is a first area, the average area of ​​each cross section of the second via hole perpendicular to the stacking direction is a second area, and the first area is smaller than the second area; The first insulating film layers and the second insulating film layers are arranged alternately in the main body layer; or, The main layer also includes a third insulating film layer, the dielectric constant of the material of the third insulating film layer is smaller than the dielectric constant of the material of the second insulating film layer; the through hole also includes a third via hole penetrating the third insulating film layer; the average area of ​​each cross-section of the third via hole perpendicular to the stacking direction is a third area, and the third area is larger than the second area; the third insulating film layer is provided on the side of the second insulating film layer away from the first insulating film layer, or the third insulating film layer is provided on the side of the first insulating film layer away from the second insulating film layer.

13. A method for preparing a printed circuit board, characterized in that: The preparation method comprises: A main body layer is formed; the main body layer includes a plurality of insulating film layers stacked together; the dielectric constants of adjacent insulating film layers are different; the main body layer is provided with through holes penetrating the main body layer, and the through holes include via holes penetrating each insulating film layer; among two adjacent insulating film layers, the average area of ​​each cross section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant; the average area of ​​each cross section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.

14. The method for preparing a printed circuit board according to claim 13, wherein: The forming body layer comprises: Providing an intermediate structure, the intermediate structure comprising a first insulating film layer and two second insulating film layers located on both sides of the first insulating film layer, wherein the dielectric constant of a material of the first insulating film layer is smaller than the dielectric constant of the second insulating film layer; forming an opening penetrating the main body layer, wherein the shapes and areas of the cross sections of the opening perpendicular to the stacking direction of the insulating film layers are substantially the same; the portion of the opening located in the first insulating film layer is a first via hole; The material of the second insulating film layer in the area adjacent to the via hole is removed to form a second via hole, so that the area of ​​the cross section of the second via hole perpendicular to the stacking direction is larger than the area of ​​the cross section of the first via hole perpendicular to the stacking direction.

15. The method for preparing a printed circuit board according to claim 14, wherein: The forming of the opening penetrating the main body layer comprises: drilling the main body layer with a first drill bit to form the opening penetrating the main body layer; The removing of material from the area adjacent to the second insulating film layer and the via hole includes: drilling the second insulating film layer with a second drill bit, the maximum outer diameter of the second drill bit being larger than the maximum outer diameter of the first drill bit, and the second drill bit being partially located in the opening during drilling.

16. The method for preparing a printed circuit board according to claim 13, wherein: The main body layer includes two second insulating film layers and a first insulating film layer located between the two second insulating film layers, wherein the dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer; The forming body layer comprises: forming a first via hole penetrating the first insulating film layer; Disposing the second insulating film layer on two opposite surfaces of the first insulating film layer, respectively, so that the first insulating film layer and the second insulating film layer are bonded together to form a second via hole penetrating the second insulating film layer and communicating with the first via hole; or, The main body layer includes two first insulating film layers and a second insulating film layer located between the two first insulating film layers, wherein the dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer; forming the main body layer includes: forming a second via hole penetrating the second insulating film layer; The first insulating film layer is respectively disposed on two opposite surfaces of the second insulating film layer, and the first insulating film layer is bonded to the second insulating film layer to form a first via hole penetrating the first insulating film layer and communicating with the second via hole.

17. The method for preparing a printed circuit board according to claim 16, wherein: The step of bonding the first insulating film layer to the second insulating film layer comprises: The second insulating film layer and the first insulating film layer that are stacked are pressed together to make the second insulating film layer adhere to the first insulating film layer.

18. The method for preparing a printed circuit board according to any one of claims 14 to 17, characterized in that: The main body layer further includes a plurality of pads, wherein the pads are provided between two adjacent insulating film layers, and the through hole includes a contact hole passing through the pads.

19. The method for preparing a printed circuit board according to claim 18, wherein: The outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the first edge, and the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.

20. The method for preparing a printed circuit board according to claim 13, wherein: The insulating film layer includes a plurality of stacked insulating material layers; the via includes a sub-via that penetrates the insulating material layer; the printed circuit board also includes a conductive structure located in the through hole, the conductive structure including a conductive portion located in each of the sub-vias; the steps of forming the main layer and the conductive structure include: forming a sub-via in an insulating material layer and forming a conductive portion within the sub-via; Repeat the following steps until the main layer and the conductive structure are formed: Insulating material layers without sub-vias are respectively provided on two opposite surfaces of the structure obtained in the previous step, and the stacked insulating material layers are bonded together; sub-vias are formed on the insulating material layers without sub-vias, and conductive portions are formed within the sub-vias.

21. The method for preparing a printed circuit board according to claim 20, wherein: The main body layer further includes a plurality of pads, wherein the pads are provided between two adjacent insulating material layers, the through hole includes a contact hole passing through the pads, and the conductive portion is partially located in the contact hole.

22. The method for preparing a printed circuit board according to claim 20, wherein: The sub-via holes are formed by laser etching process.

23. The method for preparing a printed circuit board according to claim 20, wherein: The step of providing insulating material layers without sub-vias on two opposite surfaces of the structure obtained in the previous step and bonding the stacked insulating material layers comprises: Insulating material layers are respectively arranged on both sides of the structure obtained in the previous step, and the stacked insulating material layers are pressed together to bond the stacked insulating material layers together.

24. The method for preparing a printed circuit board according to claim 23, wherein: The total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the materials and thicknesses of the two insulating material layers with the same number of insulating material layers spaced apart from the middle insulating material layer are the same.

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