Light-emitting assembly and manufacturing method therefor, and display substrate

Abstract

The present application relates to the technical field of display, and discloses a light-emitting assembly and a manufacturing method therefor, and a display substrate. The light-emitting assembly comprises a light-emitting unit and a driving unit. A first electrode in the light-emitting unit is electrically connected to a third electrode in the driving unit, and a second electrode in the light-emitting unit is electrically connected to a fourth electrode in the driving unit. In this way, the driving unit can provide a driving signal for the light-emitting unit, and the light-emitting unit can emit light under the driving of the driving unit. Moreover, in the driving unit, a first driving circuit layer comprising a first-type transistor and a second driving circuit layer comprising a second-type transistor are stacked, so that the area occupied by the driving unit can be reduced, and the utilization rate of a substrate needing to be used during manufacturing can be improved.

Description

Light-emitting component and preparation method thereof, and display substrate Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light-emitting component and a preparation method thereof, and a display substrate. Background Art

[0002] The display substrate includes a driving backplane and a plurality of light-emitting components connected to the driving backplane, wherein the driving backplane can provide driving signals for the light-emitting components to make the light-emitting components emit light, thereby realizing display.

[0003] Summary of the Invention

[0004] This application provides a light-emitting component and a method for preparing the same, and a display substrate. The technical solutions are as follows:

[0005] In one aspect, a light emitting assembly is provided, characterized in that the light emitting assembly comprises:

[0006] A light-emitting unit, comprising: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively;

[0007] a driving unit, the driving unit comprising a first driving circuit layer and a second driving circuit layer stacked together, the first driving circuit layer being located between the light-emitting unit and the second driving circuit layer; the first driving circuit layer comprising a third electrode and a fourth electrode, the third electrode and the fourth electrode being both located on a side of the first driving circuit layer facing the light-emitting unit, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode;

[0008] The first driving circuit layer includes a first type of transistors, the second driving circuit layer includes a second type of transistors, and the first type of transistors and the second type of transistors are of different types.

[0009] Optionally, the first type of transistor is an oxide thin film transistor, and the second type of transistor is a low temperature polysilicon thin film transistor; or,

[0010] The first type of transistor is a low-temperature polysilicon thin film transistor, and the second type of transistor is an oxide thin film transistor.

[0011] Optionally, the transistors in the first driving circuit layer are only transistors of the first type, and the transistors in the second driving circuit layer are only transistors of the second type.

[0012] Optionally, the driving unit includes an intermediate substrate, the intermediate substrate having a first surface and a second surface opposite to each other, the first driving circuit layer is located on the first surface, and the second driving circuit layer is located on the second surface;

[0013] The intermediate substrate has a plurality of through holes, the first driving circuit layer includes a plurality of first connection structures corresponding to the plurality of through holes, the second driving circuit layer includes a plurality of second connection structures corresponding to the plurality of through holes, and each of the first connection structures is electrically connected to the corresponding second connection structure through the corresponding through hole;

[0014] The first type of transistor is electrically connected to the second type of transistor through the first connection structure and the second connection structure.

[0015] Optionally, the intermediate substrate is made of glass or polyimide;

[0016] At least a portion of the first connection structure is located in the corresponding through-hole, and the second connection structure is located on a side of the intermediate substrate away from the first driving circuit layer; a surface of the portion of the first connection structure located in the through-hole close to the second driving circuit layer contacts a surface of the corresponding second connection structure close to the intermediate substrate; or

[0017] At least a portion of the second connection structure is located in the corresponding through-hole, and the first connection structure is located on a side of the intermediate substrate away from the second driving circuit layer; a surface of the portion of the second connection structure located in the through-hole close to the first driving circuit layer contacts the surface of the corresponding first connection structure close to the intermediate substrate; or

[0018] The driving unit further includes a conductive material located in the through hole. The first connecting structure and the corresponding second connecting structure are respectively located on both sides of the conductive material in the corresponding through hole and are both in contact with the conductive material.

[0019] Optionally, a first portion of a first target connection structure in the first connection structure and the second connection structure is located inside the through hole, and a second target connection structure in the first connection structure and the second connection structure is located outside the through hole;

[0020] The second portion of the first target connection structure is located on a side of the intermediate substrate away from the second target connection structure, and a distance between a surface of the intermediate substrate away from the second target connection structure and a surface of the intermediate substrate away from the second target connection structure is greater than or equal to a thickness of the intermediate substrate;

[0021] The first target connection structure is one of the first connection structure and the second connection structure, and the second target connection structure is the other of the first connection structure and the second connection structure.

[0022] Optionally, a portion of the multiple first connection structures is away from the surface of the second driving circuit layer and is used to be electrically connected to the first type of transistor, another portion of the multiple first connection structures is away from the surface of the second driving circuit layer and is used to be electrically connected to the first electrode in the light-emitting unit, and another portion of the multiple first connection structures is away from the surface of the second driving circuit layer and is used to be electrically connected to the second electrode in the light-emitting unit through the first type of transistor.

[0023] Optionally, a portion of the multiple second connection structures is away from the surface of the first driving circuit layer and is used to be electrically connected to the second type of transistor, and another portion of the multiple second connection structures is away from the surface of the first driving circuit layer and is used to be electrically connected to the driving backplane in the display substrate.

[0024] Optionally, the driving circuit layer including a plurality of low-temperature polysilicon thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a first structural layer, a first passivation layer, a first wiring layer, a first buffer layer, a polysilicon layer, a first gate insulating layer, a first gate layer, a first interlayer dielectric layer, a first source and drain electrode layer, and a first planarization layer stacked in sequence in a direction away from the intermediate substrate;

[0025] Wherein, the first structural layer includes a plurality of second target connection structures, and the second target connection structure is one of the first connection structure and the second connection structure;

[0026] The first wiring layer includes a plurality of first wiring patterns corresponding to the plurality of second target connection structures, the first wiring patterns are connected to the corresponding second target connection structures, and some of the plurality of first wiring patterns are connected to the low-temperature polysilicon thin film transistor;

[0027] The polysilicon layer includes a plurality of polysilicon patterns corresponding to the plurality of low-temperature polysilicon thin film transistors, each of the polysilicon patterns includes a source region, a drain region, and a channel region;

[0028] The source and the drain of the low-temperature polysilicon thin film transistor are located in the first source-drain layer, the source of the low-temperature polysilicon thin film transistor is connected to the source region, and the drain of the low-temperature polysilicon thin film transistor is connected to the drain region;

[0029] The first gate layer includes a plurality of first gate patterns corresponding to the plurality of low-temperature polysilicon thin film transistors, and the channel region is an overlapping area of ​​an orthographic projection of the first gate pattern on the intermediate substrate and an orthographic projection of the polysilicon pattern on the intermediate substrate.

[0030] Optionally, the driving circuit layer including a plurality of oxide thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a second structural layer, a second passivation layer, a second wiring layer, a second buffer layer, an oxide layer, a second gate insulating layer, a second gate layer, a second interlayer dielectric layer, a second source and drain electrode layer, and a second planarization layer stacked in sequence in a direction away from the intermediate substrate;

[0031] The second structure layer includes a plurality of first target connection structures, wherein the first target connection structure is the other connection structure of the first connection structure and the second connection structure;

[0032] The second wiring layer includes a plurality of second wiring patterns corresponding to the plurality of first target connection structures, the second wiring patterns are connected to the corresponding first target connection structures, and some of the plurality of second wiring patterns are connected to the oxide thin film transistor;

[0033] The oxide layer includes a plurality of oxide patterns corresponding to the plurality of oxide thin film transistors, each of the oxide patterns including a source region, a drain region, and a channel region;

[0034] The source and the drain of the oxide thin film transistor are located in the second source-drain layer, the source of the oxide thin film transistor is connected to the source region, and the drain of the oxide thin film transistor is connected to the drain region;

[0035] The second gate layer includes a plurality of second gate patterns corresponding to the plurality of oxide thin film transistors, and the channel region is an overlapping area of ​​an orthographic projection of the second gate pattern on the intermediate substrate and an orthographic projection of the oxide pattern on the intermediate substrate.

[0036] Optionally, the first driving circuit layer includes a plurality of first connection structures, the second driving circuit layer includes a plurality of second connection structures, and the first type of transistors and the second type of transistors are electrically connected via the first connection structures and the second connection structures;

[0037] In which, the first connection structure is close to the surface of the second driving circuit layer and the second connection structure is close to the surface of the first driving circuit layer and is arranged opposite to each other and electrically connected, a part of the first connection structures among the multiple first connection structures are away from the surface of the second driving circuit layer and are used to be electrically connected to the first type of transistors, and a part of the second connection structures among the multiple second connection structures are away from the surface of the first driving circuit layer and are used to be electrically connected to the second type of transistors.

[0038] Optionally, the driving circuit layer including a plurality of low-temperature polysilicon thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a first structural layer, a first passivation layer, a first wiring layer, a first buffer layer, a polysilicon layer, a first gate insulating layer, a first gate layer, a first interlayer dielectric layer, a first source and drain layer, and a first planarization layer stacked in sequence;

[0039] The first structure layer includes the plurality of first target connection structures, wherein the first target connection structure is one of the first connection structure and the second connection structure;

[0040] The first wiring layer includes a plurality of first wiring patterns corresponding to the plurality of first target connection structures, the first wiring patterns are connected to the corresponding first target connection structures, and some of the plurality of first wiring patterns are connected to the low-temperature poly-silicon thin film transistor;

[0041] The polysilicon layer includes a plurality of polysilicon patterns corresponding to the plurality of low-temperature polysilicon thin film transistors, each of the polysilicon patterns includes a source region, a drain region, and a channel region;

[0042] The source and drain of the low-temperature polysilicon thin film are located in the first source-drain layer, the source of the low-temperature polysilicon thin film is connected to the source region, and the drain of the low-temperature polysilicon thin film is connected to the drain region;

[0043] The first gate layer includes a plurality of first gate patterns corresponding to the plurality of low-temperature polysilicon thin films, and the channel region is an overlapping area of ​​an orthographic projection of the first gate pattern on the first planar layer and an orthographic projection of the polysilicon pattern on the first planar layer.

[0044] Optionally, the driving circuit layer including a plurality of oxide thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a second structure layer, a second passivation layer, a second wiring layer, a second buffer layer, an oxide layer, a second gate insulating layer, a second gate layer, a second interlayer dielectric layer, a second source and drain electrode layer, and a second planarization layer;

[0045] The second structure layer includes the plurality of second target connection structures, and the first target connection structure is the other connection structure between the first connection structure and the second connection structure;

[0046] The second wiring layer includes a plurality of second wiring patterns corresponding to the plurality of second target connection structures, the second wiring patterns are connected to the corresponding second target connection structures, and some of the plurality of second wiring patterns are connected to the oxide thin film transistor;

[0047] The oxide layer includes a plurality of oxide patterns corresponding to the plurality of oxide thin film transistors, each of the oxide patterns including a source region, a drain region, and a channel region;

[0048] The source and the drain of the oxide thin film transistor are located in the second source-drain layer, the source of the oxide thin film transistor is connected to the source region, and the drain of the oxide thin film transistor is connected to the drain region;

[0049] The second gate layer includes a plurality of second gate patterns corresponding to the plurality of oxide thin film transistors, and the channel region is an overlapping area of ​​an orthographic projection of the second gate pattern on the second planar layer and an orthographic projection of the oxide pattern on the second planar layer.

[0050] Optionally, the driving unit includes a plurality of pins, and the plurality of pins are located on a side of the second driving circuit layer away from the first driving circuit layer, one or more of the plurality of pins are electrically connected to the first type of transistor, and one or more of the plurality of pins are electrically connected to the second type of transistor.

[0051] Optionally, the driving unit includes a first transistor, the first transistor is located in the first driving circuit layer or the second driving circuit layer, and the drain of the first transistor is electrically connected to the fourth electrode;

[0052] One of the plurality of pins is electrically connected to the third electrode.

[0053] Optionally, the driving unit further includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor;

[0054] The gate of the first transistor is coupled to the first light emitting control signal terminal HF, the first electrode of the first transistor is coupled to the first node J1, and the second electrode of the first transistor is the drain of the first transistor;

[0055] The gate of the second transistor is coupled to the reset signal terminal RST, the first electrode of the second transistor is coupled to the pull-down power supply terminal VSS, and the second electrode of the second transistor is coupled to the second node J2;

[0056] The gate of the third transistor is coupled to the gate signal terminal Gate, the first electrode of the third transistor is coupled to the first node J1, and the second electrode of the third transistor is coupled to the second node J2;

[0057] The gate of the fourth transistor is coupled to the second node J2, the first electrode of the fourth transistor is coupled to the first node J1, and the second electrode of the fourth transistor is coupled to the third node J3;

[0058] The gate of the fifth transistor is coupled to the gate signal terminal Gate, the first electrode of the fifth transistor is coupled to the data signal terminal DATA, and the second electrode of the fifth transistor is coupled to the third node J3;

[0059] The gate of the sixth transistor is coupled to the second light emitting control signal terminal EM, the first electrode of the sixth transistor is coupled to the driving power supply terminal VDD, and the second electrode of the sixth transistor is coupled to the third node J3;

[0060] The gate of the seventh transistor is coupled to the reset signal terminal RST, the first electrode of the seventh transistor is coupled to the pull-down power supply terminal VSS, and the second electrode of the seventh transistor is coupled to the second electrode of the light emitting unit;

[0061] A first electrode of the first capacitor is coupled to the second node J2 , and a second electrode of the first capacitor is coupled to the driving power supply terminal VDD.

[0062] Optionally, the second transistor and the seventh transistor are oxide thin film transistors;

[0063] The first transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are low-temperature polysilicon thin-film transistors.

[0064] Optionally, the first capacitor is located in a driving circuit layer where the low-temperature polysilicon thin film transistor is located.

[0065] Optionally, the driving unit further includes: an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor;

[0066] The gate of the first transistor is coupled to a fourth node J4;

[0067] The gate of the eighth transistor is coupled to the fifth node J5, the first electrode of the eighth transistor is coupled to the first light emitting control signal terminal HF, and the second electrode of the eighth transistor is coupled to the fourth node J4;

[0068] The gate of the ninth transistor is coupled to the fifth node J5, the first electrode of the ninth transistor is coupled to the fourth node J4, and the second electrode of the ninth transistor is coupled to the second light emitting control signal terminal EM;

[0069] The gate of the tenth transistor is coupled to the reset signal terminal RST, the first electrode of the tenth transistor is coupled to the data signal terminal DATA, and the second electrode of the tenth transistor is coupled to the fifth node J5;

[0070] A first electrode of the second capacitor is coupled to the fifth node J5 , and a second electrode of the second capacitor is coupled to the pull-down power supply terminal VSS.

[0071] Optionally, the eighth transistor is an oxide thin film transistor;

[0072] The ninth transistor and the tenth transistor are low-temperature polysilicon thin film transistors.

[0073] Optionally, the second capacitor is located in the driving circuit layer where the oxide thin film transistor is located.

[0074] Optionally, the light emitting portion includes: a first semiconductor layer, and a plurality of sub-light emitting functional layers located on one side of the first semiconductor layer;

[0075] The first semiconductor layer includes: a plurality of connecting parts corresponding one-to-one to the plurality of sub-light-emitting functional layers, and an auxiliary part connected to the plurality of connecting parts, the connecting parts are connected to the corresponding sub-light-emitting functional layers, at least part of the auxiliary part is located between adjacent connecting parts, and the auxiliary part and the connecting part are an integral structure.

[0076] Optionally, the light-emitting component further includes a first substrate, and a color conversion unit located on one side of the first substrate, wherein the light-emitting unit is located on a side of the color conversion unit away from the first substrate; the color conversion unit includes:

[0077] a light shielding layer located on one side of the first substrate, the light shielding layer having a plurality of light through holes;

[0078] a defining dam layer located on a side of the light-shielding layer facing away from the first substrate, the defining dam layer having a plurality of opening areas corresponding one-to-one to the plurality of light-through holes, and the plurality of opening areas corresponding one-to-one to the plurality of sub-light-emitting functional layers, wherein orthographic projections of the opening areas on the second substrate overlap with orthographic projections of corresponding light-through holes on the first substrate, and overlap with orthographic projections of corresponding sub-light-emitting functional layers on the first substrate;

[0079] an optical functional layer located in the opening area, at least a portion of the optical functional layer being used to convert the color of light entering the optical functional layer;

[0080] And, a filter layer is located between the first substrate and the optical functional layer; the filter layer includes a plurality of filter units corresponding one-to-one to the plurality of light holes, and the orthographic projections of the filter units on the first substrate overlap with the orthographic projections of the corresponding light holes on the second substrate.

[0081] Optionally, the plurality of sub-light-emitting functional layers include: a first sub-light-emitting functional layer, a second sub-light-emitting functional layer and a third sub-light-emitting functional layer;

[0082] The multiple opening areas include: a first opening area, a second opening area and a third opening area. The first opening area is arranged opposite to the first sub-light-emitting functional layer, the second opening area is arranged opposite to the second sub-light-emitting functional layer, and the third opening area is arranged opposite to the third sub-light-emitting functional layer.

[0083] Optionally, the second electrode is connected to the first semiconductor layer;

[0084] The auxiliary portion includes a first auxiliary portion, a second auxiliary portion, and a third auxiliary portion; the orthographic projection of the first auxiliary portion on the first substrate overlaps with the orthographic projection of the second electrode on the first substrate; a portion of the second auxiliary portion is located between adjacent connecting portions, and another portion is located between the first auxiliary portion and the connecting portion; the third auxiliary portion is arranged around the first auxiliary portion, the second auxiliary portion, and the plurality of connecting portions, and the auxiliary portion is made of the same material as the connecting portion;

[0085] The sub-light-emitting functional layer includes: a second semiconductor layer and the light-emitting layer; the first electrode, the second semiconductor layer and the light-emitting layer are stacked in a direction perpendicular to and toward the first substrate; wherein the light-emitting layer is connected to the corresponding connecting portion in the first semiconductor layer.

[0086] Optionally, the first semiconductor layer includes: a first sublayer and a second sublayer stacked in a direction perpendicular to and toward the first substrate, the first sublayer being located between the second sublayer and the light-emitting layer, the first sublayer being made of N-type doped gallium nitride, and the second sublayer being a gallium nitride buffer layer;

[0087] The material of the second semiconductor layer includes P-type doped gallium nitride, and the light-emitting layer is a multi-quantum well layer.

[0088] Another aspect provides a method for preparing a light-emitting component, the method comprising:

[0089] Acquire a first target structure, where the first target structure includes a light-emitting unit, and the light-emitting unit includes: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively;

[0090] Acquire a second target structure, the second target structure including a driving unit, the driving unit including: a first driving circuit layer and a second driving circuit layer stacked together, the first driving circuit layer including a third electrode and a fourth electrode, the third electrode and the fourth electrode both being located on a side of the second driving circuit layer away from the light-emitting unit;

[0091] Bonding the first target structure and the second target structure so that the first electrode of the light-emitting unit is electrically connected to the third electrode of the driving unit, and the second electrode of the light-emitting unit is electrically connected to the fourth electrode of the driving unit;

[0092] The first driving circuit layer includes a first type of transistors, the second driving circuit layer includes a second type of transistors, and the first type of transistors and the second type of transistors are of different types.

[0093] Optionally, obtaining a second target structure includes:

[0094] obtaining an intermediate substrate;

[0095] forming a first driving circuit layer on the first surface of the intermediate substrate, wherein the first driving circuit layer includes a plurality of first connection structures;

[0096] A plurality of through holes are formed on the second surface of the intermediate substrate, each of the through holes being used to expose a corresponding one of the first connecting structures;

[0097] A second driving circuit layer is formed on the second surface of the intermediate substrate. The second driving circuit layer includes a plurality of second connecting structures. Each second connecting structure is located in a corresponding one of the through holes and is electrically connected to the first connecting structure exposed in the through hole.

[0098] Optionally, obtaining a second target structure includes:

[0099] forming a first driving circuit layer on a first temporary substrate, wherein the first driving circuit layer includes a plurality of second connection structures;

[0100] forming a second driving circuit layer on a second temporary substrate, wherein the second driving circuit layer includes a plurality of first connection structures;

[0101] removing the first temporary substrate to expose the plurality of second connection structures;

[0102] removing the second temporary substrate to expose the plurality of first connection structures;

[0103] The plurality of first connection structures and the corresponding plurality of second connection structures are electrically connected.

[0104] In another aspect, a display substrate is provided, comprising a driving backplane, and a plurality of light-emitting components as described in the above aspects arranged in an array and located on one side of the driving backplane;

[0105] The driving backplane is used to provide a driving signal to the driving unit through a plurality of pins in the light-emitting component, so that the driving unit drives the light-emitting unit to emit light.

[0106] Optionally, the driving backplane is a passive matrix driving backplane.

[0107] In another aspect, a method for preparing a display substrate is provided, the method comprising:

[0108] Obtain a light-emitting unit, a first drive circuit layer, a second drive circuit layer, and a drive backplane, wherein the light-emitting unit includes: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode, respectively; the first drive circuit layer includes a third electrode, a fourth electrode, and a plurality of second connection structures; the second drive circuit layer includes a plurality of first connection structures and a plurality of pins;

[0109] Bonding the first driving circuit layer and the second driving circuit layer so that the plurality of first connection structures are electrically connected to the corresponding plurality of second connection structures, and the third electrode and the fourth electrode are arranged away from the second driving circuit layer;

[0110] Bonding the light-emitting unit to the first driving circuit layer so that the first electrode is electrically connected to the third electrode, and the second electrode is electrically connected to the fourth electrode;

[0111] The driving backplane and a plurality of pins of the second driving circuit layer are bonded and connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0113] FIG1 is a schematic structural diagram of a light-emitting component provided in an embodiment of the present application;

[0114] FIG2 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0115] FIG3 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0116] FIG4 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0117] FIG5 is a schematic diagram of a low-temperature polysilicon driving circuit layer provided in an embodiment of the present application;

[0118] FIG6 is a schematic diagram of another low-temperature polysilicon driving circuit layer provided in an embodiment of the present application;

[0119] FIG7 is a schematic diagram of a driving unit provided in an embodiment of the present application;

[0120] FIG8 is a schematic diagram of another driving unit provided in an embodiment of the present application;

[0121] FIG9 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer provided in an embodiment of the present application;

[0122] FIG10 is a schematic diagram showing the connection between another first driving circuit layer and a second driving circuit layer provided in an embodiment of the present application;

[0123] FIG11 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0124] FIG12 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0125] 13 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0126] FIG14 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0127] FIG15 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0128] FIG16 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0129] FIG17 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0130] FIG18 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0131] FIG19 is a schematic diagram of another driving unit provided in an embodiment of the present application;

[0132] FIG20 is a schematic diagram of another driving unit provided in an embodiment of the present application;

[0133] FIG21 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0134] FIG22 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0135] FIG23 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0136] FIG24 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0137] FIG25 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0138] FIG26 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0139] FIG27 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0140] FIG28 is a schematic diagram showing a connection between a first driving circuit layer and a second driving circuit layer according to another embodiment of the present application;

[0141] FIG29 is a circuit diagram of a driving unit provided in an embodiment of the present application;

[0142] FIG30 is a top view of a plurality of pins provided in an embodiment of the present application;

[0143] FIG31 is a circuit diagram of another driving unit provided in an embodiment of the present application;

[0144] FIG32 is a schematic diagram of a light-emitting unit and a color conversion unit provided in an embodiment of the present application;

[0145] FIG33 is a top view of a first semiconductor layer provided in an embodiment of the present application;

[0146] FIG34 is a top view of a light-emitting unit and a color conversion unit provided in an embodiment of the present application;

[0147] FIG35 is a schematic diagram of the film layer structure at AA' in FIG34;

[0148] FIG36 is a schematic diagram of the film layer structure at BB' in FIG34;

[0149] FIG37 is a schematic diagram of another light-emitting unit and color conversion unit provided in an embodiment of the present application;

[0150] FIG38 is a top view of a first electrode, a second electrode, and a light-emitting portion located on a connecting layer provided in an embodiment of the present application;

[0151] FIG39 is a schematic diagram of the film layer structure at CC' in FIG38;

[0152] FIG40 is a top view of another first semiconductor layer provided in an embodiment of the present application;

[0153] FIG41 is a top view of another first electrode, a second electrode, and a light-emitting portion provided in an embodiment of the present application;

[0154] FIG42 is a schematic diagram of the film layer structure at DD' in FIG41;

[0155] FIG43 is a flow chart of a method for preparing a light-emitting component provided in an embodiment of the present application;

[0156] FIG44 is a flow chart of obtaining a second target structure according to an embodiment of the present application;

[0157] FIG45 is another flowchart of obtaining a second target structure provided by an embodiment of the present application;

[0158] FIG46 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0159] FIG47 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0160] FIG48 is a schematic structural diagram of a display substrate provided in an embodiment of the present application;

[0161] FIG49 is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

[0162] FIG50 is a top view of a display substrate provided in an embodiment of the present application;

[0163] FIG51 is a flow chart of a method for preparing a display substrate provided in an embodiment of the present application;

[0164] FIG52 is a flow chart of another method for preparing a display substrate provided in an embodiment of the present application;

[0165] FIG53 is a structural flow chart of a method for preparing a display substrate provided in an embodiment of the present application;

[0166] FIG54 is a structural flow chart of another method for preparing a display substrate provided in an embodiment of the present application;

[0167] Figure 55 is a structural flow chart of another method for preparing a display substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0168] To make the purpose, technical solutions and advantages of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. In the related art, the light-emitting component includes a light-emitting unit and a driving unit. The driving unit includes a driving circuit and a driving electrode. The driving circuit includes a pixel circuit corresponding to the light-emitting unit, and the pixel circuit includes a plurality of thin-film transistors connected to each other. The driving backplane provides a driving signal to the light-emitting unit through the plurality of thin-film transistors and driving electrodes connected to each other in the driving circuit to drive the light-emitting unit to emit light.

[0169] However, since the driving circuit includes a plurality of thin film transistors and requires a relatively large area for layout design, the utilization rate of the substrate required for preparing the driving circuit is relatively low.

[0170] In the current process of preparing a display substrate including a light-emitting diode (LED), it is necessary to first prepare a driving backplane including a driving circuit, and then use a mass transfer process to transfer the light-emitting unit to the driving backplane. In this case, the utilization rate of the driving backplane is low. To this end, a new preparation method is proposed. This new method can first bond the light-emitting unit and the driving unit including the driving circuit, and then cut the unit to obtain multiple independent LED chips. Finally, the LED chip with the driver is transferred together onto the driving backplane that provides wiring and signal input. This can improve the utilization rate of the driving backplane and reduce the preparation cost.

[0171] However, in order to meet the cost requirements of low-frequency driving and minimizing chip size, the driving unit needs to include an oxide thin film transistor (Oxide TFT) and a low-temperature polysilicon thin film transistor (LTPS TFT).

[0172] But this design will create new problems:

[0173] 1. When LTPS TFT and oxide TFT are designed on the same driving layer, the channel surface of the oxide TFT will be uneven (the channel layer of the oxide TFT is located on the side of the channel layer of the LTPS TFT away from the substrate), and the characteristics of the oxide TFT will be offset.

[0174] 2. After the light-emitting unit and the driving unit are bonded, the laser lift-off (LLO) process is required to peel off the substrate on the side of the driving unit away from the light-emitting unit to expose the connection pad in the driving unit that needs to be subsequently solidified with the driving backplane. In addition, a tin (Sn) layer needs to be chemically plated on the connection pad to achieve connection with the driving backplane. However, during the chemical plating process, the entire structure needs to be placed in a special solution, which may penetrate from the bonding gap between the light-emitting unit and the driving unit, bringing reliability risks. Therefore, it is necessary to design a dam layer between the light-emitting unit and the driving unit to protect the bonding position of the light-emitting unit and the driving unit. However, the distance between the dam layer and the bonding position needs to be designed to be larger, which will increase the area of ​​the LED chip and reduce the cost advantage.

[0175] 3. The LLO process will cause the periphery of the flexible substrate in the driver unit to warp, affecting the reliability of subsequent die bonding.

[0176] FIG1 is a schematic diagram of the structure of a light emitting assembly provided in an embodiment of the present application. Referring to FIG1 , the light emitting assembly 000 includes: a light emitting unit 100 and a driving unit 200 .

[0177] The light emitting unit 100 includes a first electrode 101, a second electrode 102, and a light emitting portion 103 electrically connected to the first electrode 101 and the second electrode 102. Optionally, the light emitting unit 100 may be an LED, or a micro light emitting diode (Micro LED).

[0178] The driving unit 200 includes a first driving circuit layer 201 and a second driving circuit layer 202 that are stacked. The first driving circuit layer 201 is located between the light emitting unit 100 and the second driving circuit layer 202 .

[0179] The first driving circuit layer 201 includes a third electrode 2011 and a fourth electrode 2012, both of which are located on a side of the first driving circuit layer 201 facing the light emitting unit 100. The third electrode 2011 is electrically connected to the first electrode 101, and the fourth electrode 2012 is electrically connected to the second electrode 102.

[0180] The first driving circuit layer 201 includes a first type of transistors (not shown in FIG1 ), and the second driving circuit layer 202 includes a second type of transistors (not shown in FIG1 ). The first type of transistors and the second type of transistors are of different types.

[0181] In the embodiment of the present application, since the first driving circuit layer 201 including the first type of transistors and the second driving circuit layer 202 including the second type of transistors are stacked, the area occupied by the driving unit 200 on the reference plane can be reduced, thereby improving the utilization rate of the substrate required for manufacturing the driving unit 200. The reference plane is parallel to the surface on the substrate where the driving unit 200 is installed.

[0182] In summary, an embodiment of the present application provides a light-emitting component, which includes a light-emitting unit and a driving unit. The first electrode in the light-emitting unit is electrically connected to the third electrode in the driving unit, and the second electrode in the light-emitting unit is electrically connected to the fourth electrode in the driving unit. As a result, the driving unit can provide a driving signal to the light-emitting unit, and the light-emitting unit can emit light under the drive of the driving unit. In addition, the first driving circuit layer including the first type of transistor and the second driving circuit layer including the second type of transistor in the driving unit are stacked, thereby reducing the area required to be occupied by the driving unit and improving the utilization rate of the substrate required for preparation.

[0183] Optionally, the transistors in the first driving circuit layer 201 may be only first-type transistors, and the transistors in the second driving circuit layer 202 may be only second-type transistors. In other words, the first-type transistors and the second-type transistors may be arranged in different driving circuit layers.

[0184] That is, different types of first-type transistors and second-type transistors are located in different drive circuit layers. Thus, both drive circuit layers can be formed on a flat surface, thereby ensuring the flatness of the channel surfaces of the two types of transistors and preventing the characteristics of the transistors from shifting.

[0185] Optionally, the first type of transistor may be an oxide thin film transistor (Oxide TFT), and the second type of transistor may be a low temperature polycrystalline silicon thin film transistor (LTPS TFT). Accordingly, the first drive circuit layer 201 may be referred to as an oxide drive circuit layer or an oxide drive substrate (Oxide substrate), and the second drive circuit layer 202 may be referred to as a low temperature polycrystalline silicon drive circuit layer or a low temperature polycrystalline silicon drive substrate (LTPS substrate).

[0186] Alternatively, the first type of transistors are low-temperature polysilicon thin film transistors, and the second type of transistors are oxide thin film transistors. Accordingly, the first driving circuit layer 201 can be called a low-temperature polysilicon driving circuit layer, and the second driving circuit layer 202 can be called an oxide driving circuit layer.

[0187] Typically, crosstalk may occur between different types of transistors, affecting the driving performance of the drive unit and, in turn, the performance of the light-emitting component. However, in the embodiment of the present application, since the first type of transistors are located in the first driving circuit layer and the second type of transistors are located in the second driving circuit layer, the distance between the first type of transistors and the second type of transistors can be increased, which can reduce the possibility of mutual influence between the first type of transistors and the second type of transistors during operation, improve the driving performance of the drive unit, and, in turn, improve the performance of the light-emitting component.

[0188] As an optional implementation, referring to Figures 2 and 3, the driving unit 200 includes an intermediate substrate 203. The intermediate substrate 203 has a first surface 203a and a second surface 203b opposite to each other. The first driving circuit layer 201 is located on the first surface 203a, and the second driving circuit layer 202 is located on the second surface 203b.

[0189] For example, the thickness of the intermediate substrate 203 may be in the range of 2 microns to 5 microns.

[0190] Optionally, the material of the intermediate substrate 203 can be glass or polyimide (PI). If the material of the intermediate substrate 203 is glass, the intermediate substrate 203 can provide sufficient support for the preparation of the first drive circuit layer 201 and the second drive circuit layer 202, and no additional support plate is required. If the material of the intermediate substrate 203 is PI, a support plate can be provided on one side of the intermediate substrate 203 to improve the support force during the preparation of the first drive circuit layer 201 and the second drive circuit layer 202.

[0191] The intermediate substrate 203 has a plurality of through-holes 203c, the first driving circuit layer 201 includes a plurality of first connecting structures 2013 corresponding to the plurality of through-holes 203c, and the second driving circuit layer 202 includes a plurality of second connecting structures 2021 corresponding to the plurality of through-holes 203c. Each first connecting structure 2013 is electrically connected to the corresponding second connecting structure 2021 through the corresponding through-hole.

[0192] Optionally, the electrical connection between each first connection structure 2013 and the corresponding second connection structure 2021 through the corresponding through hole may include the following situations: 1. At least a portion of at least one connection structure in each first connection structure 2013 and the corresponding second connection structure 2021 can be located in the corresponding through hole, and each first connection structure 2013 and the corresponding second connection structure 2021 are electrically connected; 2. Referring to Figure 4, there is a conductive material in the through hole 203c, and the first connection structure 2013 and the second connection structure 2021 are respectively located on both sides of the conductive material, and are both in contact with the conductive material and electrically connected, thereby realizing the electrical connection between the first connection structure 2013 and the second connection structure 2021.

[0193] For the first scenario described above, referring to FIG2 , the first connecting structure 2013 is located within the corresponding through-hole 203c, and the second connecting structure 2021 is located outside the through-hole 203c. The second connecting structure 2021 and the portion of the first connecting structure 2013 located within the through-hole 203c are in contact and electrically connected. Alternatively, referring to FIG3 , the second connecting structure 2021 is located within the corresponding through-hole 203c, and the first connecting structure 2013 is located outside the through-hole 203c. The portions of the first connecting structure 2013 and the second connecting structure 2021 located within the through-hole 203c are in contact and electrically connected. Alternatively, at least a portion of the first connecting structure 2013 and at least a portion of the second connecting structure are located within the corresponding through-hole 203c, and the first connecting structure 2013 and the second connecting structure 2021 are in contact and electrically connected within the through-hole 203c.

[0194] In the second case, the conductive material can be part of the first connection structure 2013 or part of the second connection structure 2021. One end of the conductive material can be flush with the first surface 203a, and the other end of the conductive material can be flush with the second surface 203b. Specifically, this can be achieved by grinding at least one end of the intermediate substrate 203 and the conductive material together.

[0195] The first type of transistor is electrically connected to the second type of transistor via the first connection structure 2013 and the second connection structure 2021. For example, the first connection structure 2013 is closer to the first driver circuit layer 201 than the second connection structure 2021, that is, closer to the first type of transistor. The second connection structure 2021 is closer to the second driver circuit layer 202 than the first connection structure 2013, that is, closer to the second type of transistor. Thus, the first type of transistor can be connected to the first connection structure 2013, the first connection structure 2013 is connected to the second connection structure 2021, and the second connection structure 2021 is connected to the second type of transistor, thereby electrically connecting the first type of transistor to the second type of transistor via the first connection structure 2013 and the second connection structure 2021 in sequence.

[0196] Optionally, a first portion A11 of the first target connection structure A1 in the first connection structure 2013 and the second connection structure 2021 is located within the through-hole 203c. The second target connection structure in the first connection structure 2013 and the second connection structure 2021 is located outside the through-hole 203c. The first target connection structure A1 is one of the first connection structure 2013 and the second connection structure 2021, and the second target connection structure A2 is the other of the first connection structure 2013 and the second connection structure 2021.

[0197] The second portion A12 of the first target connection structure A1 is located on a side of the intermediate substrate 203 away from the second target connection structure A2. The distance h1 between the surface where the first target connection structure A1 and the second target connection structure A2 contact each other and the surface of the intermediate substrate 203 away from the second target connection structure A2 is greater than or equal to the thickness h2 of the intermediate substrate 203. The first portion A11 is the portion of the first target connection structure A1 located within the through-hole 203c, and the second portion A12 is the portion of the first target connection structure A1 located outside the through-hole 203c.

[0198] Optionally, the plurality of through holes 203c of the intermediate substrate 203 are formed by etching the through holes 203c after the second target connection structure A2 is formed. During etching, the intermediate substrate 203 can be etched through, that is, the second target connection structure A2 is just exposed. Thus, the contact surface between the subsequently formed first target connection structure A1 and the second target connection structure A2 is coplanar with the surface of the intermediate substrate 203 near the second target connection structure A2. Alternatively, during etching, after the intermediate substrate 203 is etched through, the etching can continue to extend onto the second target connection structure A2, that is, a portion of the second target connection structure A2 is also etched. Thus, the contact surface between the subsequently formed first target connection structure A1 and the second target connection structure A2 is further away from the surface of the intermediate substrate 203 farthest from the second target connection structure A2 relative to the surface of the intermediate substrate 203 near the second target connection structure A2.

[0199] In the embodiment of the present application, it is assumed that the first connection structure 2013 is the first target connection structure A1, and the second connection structure 2021 is the second target connection structure A2. Specifically, referring to FIG2 , at least a portion of the first connection structure 2013 is located within the corresponding through-hole 203c, and the second connection structure 2021 is located on the side of the intermediate substrate 203 away from the first driver circuit layer 201. The surface of the portion of the first connection structure 2013 located within the through-hole 203c, which is close to the second driver circuit layer 202, contacts the corresponding surface of the second connection structure 2021, which is close to the intermediate substrate 203.

[0200] For example, a portion of the first connection structure 2013 is located within the through-hole 203c, and another portion is located on a side of the intermediate substrate 203 (e.g., the first surface 203a) away from the second connection structure 2021. The second connection structure 2021 is located on the other side of the intermediate substrate 203 (e.g., the second surface 203b). The orthographic projection of the second connection structure 2021 on the intermediate substrate 203 has an overlapping area with the through-hole 203c, that is, the through-hole 203c can expose a portion of the second connection structure 2021, and the portion of the first connection structure 2013 located within the through-hole 203c is in contact with the portion of the second connection structure 2021 exposed by the through-hole 203c.

[0201] In this case, the preparation process may include: forming a plurality of second connection structures 2021 on the second surface 203b of the intermediate substrate 203; forming a second driving circuit layer 202 on the side of the plurality of second connection structures 2021 away from the intermediate substrate 203; after flipping the entire structure, etching the intermediate substrate 203 to form a plurality of through holes 203c, the plurality of through holes 203c corresponding to the plurality of second connection structures 2021, and each through hole 203c can expose a portion of a corresponding second connection structure 2021; forming a plurality of first connection structures 2013 on the side of the intermediate substrate 203 away from the second driving circuit layer 202, each first connection structure 2013 being located in a corresponding through hole 203c and in contact with the second connection structure 2021 exposed by the through hole 203c; and forming a first driving circuit layer 201 on the side of the plurality of first connection structures 2013 away from the intermediate substrate 203.

[0202] Alternatively, assuming that the second connection structure 2021 is the first target connection structure A1 and the first connection structure 2013 is the second target connection structure A2, referring to Figure 3 , at least a portion of the second connection structure 2021 is located within the corresponding through-hole 203c, and the first connection structure 2013 is located on a side of the intermediate substrate 203 away from the second driver circuit layer 202. The portion of the second connection structure 2021 located within the through-hole 203c is close to the surface of the first driver circuit layer 201 and contacts the corresponding surface of the first connection structure 2013 close to the intermediate substrate 203.

[0203] For example, a portion of the second connection structure 2021 is located within the through-hole 203c, and another portion is located on a side of the intermediate substrate 203 (e.g., the second surface 203b) away from the first connection structure 2013. The first connection structure 2013 is located on the other side of the intermediate substrate 203 (e.g., the first surface 203a). The orthographic projection of the first connection structure 2013 on the intermediate substrate 203 has an overlapping area with the through-hole 203c, that is, the through-hole 203c can expose a portion of the first connection structure 2013, and the portion of the second connection structure 2021 located within the through-hole 203c contacts the portion of the first connection structure 2013 exposed by the through-hole 203c.

[0204] In this case, the preparation process may include: forming a plurality of first connection structures 2013 on the first surface 203a of the intermediate substrate 203; forming a first driving circuit layer 201 on a side of the plurality of first connection structures 2013 away from the intermediate substrate 203; after flipping the entire structure, etching the intermediate substrate 203 to form a plurality of through holes 203c, wherein the plurality of through holes 203c correspond to the plurality of first connection structures 2013, and each through hole 203c can expose a portion of a corresponding first connection structure 2013; forming a plurality of second connection structures 2021 on a side of the intermediate substrate 203 away from the first driving circuit layer 201, wherein each second connection structure 2021 is located in a corresponding through hole 203c and contacts the first connection structure 2013 exposed by the through hole 203c; and forming a second driving circuit layer 202 on a side of the plurality of second connection structures 2021 away from the intermediate substrate 203.

[0205] In the embodiment of the present application, a portion of the plurality of first connection structures 2013, whose surface is away from the second driving circuit layer 202, is used to electrically connect to the first type transistor G1, as shown in Figures 10, 11, 14, and 16 below. Another portion of the plurality of first connection structures 2013, whose surface is away from the second driving circuit layer 202, is used to electrically connect to the first electrode 101 in the light-emitting unit 100, as shown in Figures 9 and 13 below. Yet another portion of the plurality of first connection structures 2013, whose surface is away from the second driving circuit layer 202, is used to electrically connect to the second electrode 102 in the light-emitting unit 100 via the first type transistor G1, as shown in Figures 10, 11, 14, and 16 below.

[0206] Among them, a part of the multiple first connection structures 2013, another part of the first connection structure 2013, and a part of another part of the first connection structure 2013 can all refer to one or multiple, and the embodiments of the present application do not limit this.

[0207] In the embodiment of the present application, a portion of the plurality of second connection structures 2021, which is located away from the surface of the first drive circuit layer 201, is used to electrically connect to the second-type transistor G2, as shown in Figures 10, 12, 14, and 15 below. Another portion of the plurality of second connection structures 2021, which is located away from the surface of the first drive circuit layer 201, is used to electrically connect to the drive backplane in the display substrate, as shown in Figures 9, 11, 13, and 16 below.

[0208] Among them, a part of the second connection structures 2021 in the multiple second connection structures 2021 and a part of another part of the second connection structures 2021 can refer to one or multiple, and the embodiment of the present application does not limit this.

[0209] Optionally, the driving backplane in the display substrate is a driving signal transmitted by the driving unit 200 of the light-emitting component 000, including: 1. A signal transmitted to the third electrode 2011 through the second connection structure 2021 and the first connection structure 2013 in sequence, and then transmitted to the first electrode 101 of the light-emitting unit 100, refer to Figures 9 and 13; 2. A signal transmitted to the first type of transistor through the second connection structure 2021 and the first connection structure 2013 in sequence, refer to Figures 11 and 16; 3. A signal transmitted to the fourth electrode 2012 through the second type of transistor, the second connection structure 2021, the first connection structure 2013 and the first type of transistor in sequence, and then transmitted to the second electrode 102 of the light-emitting unit 100, refer to Figures 10 and 14; 4. A signal directly transmitted to the second type of transistor, refer to Figures 12 and 15.

[0210] In an embodiment of the present application, referring to Figure 5, the driving circuit layer M (hereinafter referred to as the low-temperature polysilicon driving circuit layer) including multiple low-temperature polysilicon thin film transistors in the first driving circuit layer 201 and the second driving circuit layer 202 includes: a first structural layer m1 stacked in sequence along the direction away from the intermediate substrate 203, a first passivation layer (passivation layer, PVX) m2, a first connecting line (fanout) m3, a first buffer layer (buffer) m4, a polysilicon layer m5, a first gate insulating layer (gate insulator, GI) m6, a first gate layer (gate) m7, a first inter-level dielectric layer (inter-level dielectric, ILD) m8, a first source and drain layer m9, and a first planarization layer (planarization layer, PLN) m10.

[0211] 5 , the first structure layer m1 of the low-temperature polysilicon driving circuit layer M includes a plurality of second target connection structures A2 as an example. That is, the second target connection structures A2 are located on one side of the intermediate substrate 203 rather than in the through holes 203 c of the intermediate substrate 203 .

[0212] The first wiring layer m2 includes a plurality of first wiring patterns m31 corresponding to the plurality of second target connection structures A2. The first wiring patterns m31 are connected to the corresponding second target connection structures A2, and some of the plurality of first wiring patterns m31 are connected to low-temperature poly-silicon thin-film transistors. In other words, the first wiring patterns m31 can serve as connection patterns for connecting the second target connection structures A2 and the low-temperature poly-silicon thin-film transistors.

[0213] The polysilicon layer m5 includes a plurality of polysilicon patterns m51 corresponding to a plurality of low-temperature polysilicon thin film transistors. Each polysilicon pattern m51 includes a source region, a drain region, and a channel region.

[0214] The source and drain of the low-temperature polysilicon thin film transistor are located in the first source-drain layer m9 . The source of the low-temperature polysilicon thin film transistor is connected to the source region, and the drain of the low-temperature polysilicon thin film transistor is connected to the drain region.

[0215] The first gate layer m7 includes a plurality of first gate patterns m71 corresponding to a plurality of low-temperature polysilicon thin film transistors. The channel region is an overlapping area of ​​the orthographic projections of the first gate patterns m71 on the intermediate substrate 203 and the orthographic projections of the plurality of polysilicon patterns m51 on the intermediate substrate 203 .

[0216] Optionally, referring to FIG5 , the driver circuit layer including multiple low-temperature polysilicon thin-film transistors may include a single gate layer. Generally, the greater the number of transistors in the driver circuit layer, the more difficult it is to lay out the film layer. Therefore, to reduce the difficulty of layout design, referring to FIG6 , the low-temperature polysilicon driver circuit layer may further include a third gate insulating layer m11 and a third gate layer m12 located between the first gate layer m7 and the first interlayer dielectric layer m8. In other words, the driver circuit layer may include a double gate layer.

[0217] Furthermore, in order to ensure the preparation effect of each film layer in the driving circuit layer, a first barrier layer m13 may be designed between the first wiring layer and the first buffer layer m4.

[0218] In addition, referring to Figure 7, the driving circuit layer N (hereinafter referred to as the oxide driving circuit layer) including multiple oxide thin film transistors in the first driving circuit layer 201 and the second driving circuit layer 202 includes: a second structural layer n1, a second passivation layer n2, a second wiring layer n3, a second buffer layer n4, an oxide layer n5, a second gate insulating layer n6, a second gate layer n7, a second interlayer dielectric layer n8, a second source and drain layer n9 and a second planarization layer n10 stacked in sequence along the direction away from the intermediate substrate 203.

[0219] 7 , the second structure layer n1 of the oxide driving circuit layer N includes a plurality of first target connection structures A1 as an example. That is, at least a portion of the first target connection structures A1 is located in the through hole 203 c of the intermediate substrate 203 .

[0220] The second connection layer n3 includes multiple second connection patterns n31 corresponding to the multiple second connection structures 2021. The second connection patterns n31 are connected to the corresponding second connection structures 2021. Some of the multiple second connection patterns n31 are connected to the oxide thin film transistors.

[0221] The oxide layer n5 includes a plurality of oxide patterns n51 corresponding to the plurality of oxide thin film transistors. Each oxide pattern n51 includes a source region, a drain region, and a channel region.

[0222] The source and drain of the oxide thin film transistor are located in the second source-drain layer n9. The source of the oxide thin film transistor is connected to the source region, and the drain of the oxide thin film transistor is connected to the drain region.

[0223] The second gate layer n7 includes a plurality of second gate patterns n71 corresponding to a plurality of oxide thin film transistors. The channel region is an overlapping area of ​​an orthographic projection of the second gate pattern n71 on the intermediate substrate 203 and an orthographic projection of the oxide pattern n51 on the intermediate substrate 203 .

[0224] Optionally, referring to FIG7 , the driving circuit layer including a plurality of oxide thin film transistors may include a single gate layer. Generally, the more transistors there are in the driving circuit layer, the more difficult it is to layout the film layer. Therefore, in order to reduce the difficulty of layout design, referring to FIG8 , a fourth gate layer n11 is provided between the second buffer layer n4 and the oxide layer n5. That is, the oxide driving circuit layer N may include a double-layer gate layer. At the same time, by designing the fourth gate layer n11 on the side of the oxide layer n5 close to the intermediate substrate 203, the fourth gate layer n11 can play a light-shielding role to prevent the oxide layer n5 from being disturbed by light.

[0225] Furthermore, to ensure the fabrication quality of each film layer in the driving circuit layer, a second barrier layer n12 can be provided between the second wiring layer n3 and the second buffer layer n4. The second barrier layer n12 can also be provided between the fourth gate layer n11 and the oxide layer n5 to provide insulation.

[0226] Alternatively, referring to Figures 9 to 12 , taking the example of the first driver circuit layer 201 being an oxide driver circuit layer N and the second driver circuit layer 202 being a low-temperature polysilicon driver circuit layer M, the first gate layer m7 further includes a plurality of first gate connection patterns m72, and the first source-drain layer m9 further includes a plurality of first source-drain connection patterns m91. Each first gate connection pattern m72 is connected to a corresponding first connection pattern m31 via a via in the first gate insulating layer m6 and the first buffer layer m4, and each first source-drain connection pattern m91 is connected to a corresponding first gate connection pattern m72 via a via in the first interlayer dielectric layer m8.

[0227] For a part of the multiple first source-drain connection patterns m91, they can be electrically connected through the vias in the first flat layer m10 and the pins 2022 (pins 2022 can be called pin feet) included in the second driving circuit layer 202, and another part of the first source-drain connection patterns m91 can be directly electrically connected to the source or drain located in the source-drain layer of the low-temperature polycrystalline silicon thin film transistor.

[0228] The second gate layer n7 further includes a plurality of second gate connection patterns n72, and the first source-drain layer m9 further includes a plurality of second source-drain connection patterns n91. Each second gate connection pattern n72 is connected to a corresponding second wiring pattern n31 through a via in the second gate insulating layer n6 and the second buffer layer n4, and each second source-drain connection pattern n91 is connected to a corresponding second gate connection pattern n72 through a via in the second interlayer dielectric layer n8.

[0229] For a part of the multiple second source-drain connection patterns n91, they can be electrically connected to the third electrode 2011 through the via in the second flat layer n10, and another part of the second source-drain connection pattern n91 can be directly electrically connected to the source or drain in the source-drain layer of the oxide thin film transistor.

[0230] Referring to FIG9 , the pin 2022 can provide a signal to the third electrode 2011 via various connection patterns. Referring to FIG10 , the first-type transistor G1 and the second-type transistor G2 can be electrically connected via various connection patterns. Referring to FIG11 , the pin 2022 can provide a signal to the first-type transistor G1 via various connection patterns. Referring to FIG12 , the second-type transistor G2 can provide a signal to the fourth electrode 2012 via various connection patterns.

[0231] Alternatively, referring to Figures 13 to 16 , taking the example of a first driver circuit layer 201 being a low-temperature polysilicon driver circuit layer M and a second driver circuit layer 202 being an oxide driver circuit layer N, the first gate layer m7 further includes a plurality of first gate connection patterns m72, and the first source-drain layer m9 further includes a plurality of first source-drain connection patterns m91. Each first gate connection pattern m72 is connected to a corresponding first wiring pattern m31 via a via in the first gate insulating layer m6 and the first buffer layer m4, and each first source-drain connection pattern m91 is connected to a corresponding first gate connection pattern m72 via a via in the first interlayer dielectric layer m8.

[0232] For a part of the multiple first source-drain connection patterns m91, they can be electrically connected to the third electrode 2011 through the via hole in the first flat layer m10, and another part of the first source-drain connection pattern m91 can be directly electrically connected to the source or drain located in the source-drain layer of the low-temperature polycrystalline silicon thin film transistor.

[0233] The second gate layer n7 further includes a plurality of second gate connection patterns n72, and the first source-drain layer m9 further includes a plurality of second source-drain connection patterns n91. Each second gate connection pattern n72 is connected to a corresponding second wiring pattern n31 through a via in the second gate insulating layer n6 and the second buffer layer n4, and each second source-drain connection pattern n91 is connected to a corresponding second gate connection pattern n72 through a via in the second interlayer dielectric layer n8.

[0234] For a part of the multiple second source-drain connection patterns n91, they can be electrically connected through the vias and pins 2022 in the second flat layer n10, and another part of the second source-drain connection patterns n91 can be directly electrically connected to the source or drain located in the source-drain layer of the oxide thin film transistor.

[0235] Referring to Figure 13 , the pin 2022 can provide a signal to the third electrode 2011 via various connection patterns. Referring to Figure 14 , the first-type transistor G1 and the second-type transistor G2 can be electrically connected via various connection patterns. Referring to Figure 15 , the second-type transistor G2 can provide a signal to the fourth electrode 2012 via various connection patterns. Referring to Figure 16 , the pin 2022 can provide a signal to the first-type transistor G1 via various connection patterns.

[0236] 19 , the first driving circuit layer 201 includes a plurality of first connection structures 2013, and the second driving circuit layer 202 includes a plurality of second connection structures 2021. The first and second transistors are electrically connected via the first and second connection structures 2013 and 2021.

[0237] The first connection structure 2013 is adjacent to a surface of the second driving circuit layer 202 and the second connection structure 2021 is adjacent to a surface of the first driving circuit layer 201 , and is disposed opposite to and electrically connected to each other.

[0238] Optionally, a portion of the plurality of first connection structures 2013 is located away from the surface of the second driving circuit layer 202 and is used to electrically connect to the first type of transistor. A portion of the plurality of second connection structures 2021 is located away from the surface of the first driving circuit layer 201 and is used to electrically connect to the second type of transistor.

[0239] Part of the plurality of first connection structures 2013 may refer to one first connection structure or multiple first connection structures, and part of the plurality of second connection structures 2021 may refer to one second connection structure or multiple second connection structures.

[0240] In the embodiment of the present application, the first connection structure 2013 is close to the surface of the second driving circuit layer 202 and the second connection structure 2021 is close to the surface of the first driving circuit layer 201. The electrical connection may include the following situations: 1. Referring to Figure 17, the first connection structure 2013 is close to the surface of the second driving circuit layer 202 and the second connection structure 2021 is close to the surface of the first driving circuit layer 201. Direct contact and fixed to achieve electrical connection; 2. The first connection structure 2013 is close to the surface of the second driving circuit layer 202 and the second connection structure 2021 is close to the surface of the first driving circuit layer 201. The surfaces of the dynamic circuit layer 201 are in contact with each other and are fixed by the conductive material around the first connection structure 2013 and the second connection structure 2021; 3. A conductive adhesive (ACF) is provided between the first connection structure 2013 and the second connection structure 2021, and the first connection structure 2013 and the second connection structure 2021 are electrically connected through the conductive adhesive (ACF); 4. As shown in Figure 18, an intermediate electrode 204 is provided between the first connection structure 2013 and the second connection structure 2021, and the first connection structure 2013 and the second connection structure 2021 are electrically connected through the intermediate electrode 204.

[0241] The present embodiment uses the fourth scenario as an example. Referring to FIG18 , the surface of the first connection structure 2013 near the second driver circuit layer 202 contacts the surface of the intermediate electrode 204 near the first driver circuit layer 201. A portion of the plurality of first connection structures 2013, located away from the second driver circuit layer 202, is electrically connected to the first-type transistor G1. See FIG22 , FIG23 , FIG26 , and FIG28 . Another portion of the plurality of first connection structures 2013, located away from the second driver circuit layer 202, is electrically connected to the first electrode 101 in the light-emitting unit 100. See FIG21 and FIG25 . Yet another portion of the plurality of first connection structures 2013, located away from the second driver circuit layer 202, is electrically connected to the second electrode 102 in the light-emitting unit 100 via the first-type transistor. See FIG22 and FIG26 .

[0242] Among them, a part of the multiple first connection structures 2013, another part of the first connection structure 2013, and a part of another part of the first connection structure 2013 can all refer to one or multiple, and the embodiments of the present application do not limit this.

[0243] The second connection structure 2021 contacts the surface of the first drive circuit layer 201 and the surface of the intermediate electrode 204 contacting the second drive circuit layer 202. A portion of the plurality of second connection structures 2021, located away from the surface of the first drive circuit layer 201, is used for electrical connection to the second type of transistors, as shown in Figures 22, 24, 26, and 27 below. Another portion of the plurality of second connection structures 2021, located away from the surface of the first drive circuit layer 201, is used for electrical connection to the driver backplane, as shown in Figures 21, 23, 25, and 28 below.

[0244] Optionally, the driving backplane in the display substrate is a driving signal transmitted by the driving unit 200 of the light-emitting component 000, including: 1. A signal transmitted to the third electrode 2011 through the second connection structure 2021, the intermediate electrode 204, and the first connection structure 2013 in sequence, and then transmitted to the first electrode 101 of the light-emitting unit 100, refer to Figures 21 and 25; 2. A signal transmitted to the first type of transistor through the second connection structure 2021, the intermediate electrode 204 and the first connection structure 2013 in sequence, refer to Figures 23 and 28; 3. A signal transmitted to the fourth electrode 2012 through the second type of transistor, the second connection structure 2021, the intermediate electrode 204, the first connection structure 2013 and the first type of transistor, and then transmitted to the second electrode 102 of the light-emitting unit 100, refer to Figures 22 and 26; 4. A signal directly transmitted to the second type of transistor, refer to Figures 24 and 27.

[0245] In the embodiment of the present application, referring to FIG19 , the first drive circuit layer 201 and the second drive circuit layer 202 include a plurality of low-temperature polysilicon thin-film transistor drive circuit layers (hereinafter referred to as the low-temperature polysilicon drive circuit layer M), which include a first structural layer m1, a first passivation layer m2, a first wiring layer m3, a first buffer layer m4, a polysilicon layer m5, a first gate insulating layer m6, a first gate layer m7, a first interlayer dielectric layer m8, a first source and drain layer m9, and a first planarization layer m10, which are stacked in sequence. The first passivation layer m2 can also be a planarization layer to provide a planarization effect for the formation of subsequent film layers.

[0246] The first structure layer m1 includes multiple first target connection structures A1, which is one of the first connection structure 2013 and the second connection structure 2021. For example, the first target connection structure A1 is the second connection structure 2021, that is, the first structure layer m1 includes multiple second connection structures 2021.

[0247] The first wiring layer m3 includes a plurality of first wiring patterns m31 corresponding to the plurality of second connection structures 2021. The first wiring patterns m31 are connected to the corresponding first connection structures 2013. Some of the plurality of first wiring patterns m31 are connected to low-temperature poly-silicon thin-film transistors. In other words, the first wiring patterns m31 can serve as connection patterns for connecting the first wiring patterns m31 to the low-temperature poly-silicon thin-film transistors.

[0248] The polysilicon layer m5 includes a plurality of polysilicon patterns m51 corresponding to a plurality of low-temperature polysilicon thin film transistors. Each polysilicon pattern m51 includes a source region, a drain region, and a channel region.

[0249] The source and drain of the low-temperature polysilicon thin film transistor are located in the first source-drain layer m9 . The source of the low-temperature polysilicon thin film transistor is connected to the source region, and the drain of the low-temperature polysilicon thin film transistor is connected to the drain region.

[0250] The first gate layer m7 includes a plurality of first gate patterns m71 corresponding to the plurality of low-temperature polysilicon thin-film transistors. The channel region is the overlapping area of ​​the orthographic projections of the first gate patterns m71 on the first planar layer m10 and the orthographic projections of the plurality of polysilicon patterns m51 on the first planar layer m10. Optionally, the material of the first planar layer m10 can be polyimide (PI), which can provide support.

[0251] Optionally, referring to FIG19 , the driving circuit layer including multiple low-temperature polysilicon thin-film transistors may include a single-layer gate layer. Generally, the more transistors there are in the driving circuit layer, the more difficult it is to layout the film layer. Therefore, in order to reduce the difficulty of layout design, referring to FIG20 , the low-temperature polysilicon driving circuit layer M may further include a third gate insulating layer m11 and a third gate layer m12 located between the first gate layer m7 and the first interlayer dielectric layer m8. In other words, the low-temperature polysilicon driving circuit layer M may include a double-layer gate layer.

[0252] Furthermore, in order to ensure the preparation effect of each film layer in the low-temperature polysilicon driving circuit layer M, a first barrier layer m13 may be designed between the first connection layer m3 and the first buffer layer m4.

[0253] In addition, referring to Figure 19, the driving circuit layer N (abbreviated as: oxide driving circuit layer) including multiple oxide thin film transistors in the first driving circuit layer 201 and the second driving circuit layer 202 includes: a second structural layer n1, a second passivation layer n2, a second wiring layer n3, a second buffer layer n4, an oxide layer n5, a second gate insulating layer n6, a second gate layer n7, a second interlayer dielectric layer n8, a second source and drain layer n9 and a second flat layer n10 stacked in sequence.

[0254] The second structural layer n1 includes multiple second target connection structures A2, which is the other connection structure between the first connection structure 2013 and the second connection structure 2021. For example, if the second target connection structure A2 is the first connection structure 2013, the first structural layer m1 includes multiple first connection structures 2013.

[0255] The second connection layer n3 includes multiple second connection patterns n31 corresponding to the multiple second connection structures 2021. The second connection patterns n31 are connected to the corresponding second connection structures 2021. Some of the multiple second connection patterns n31 are connected to the oxide thin film transistors.

[0256] The oxide layer n5 includes a plurality of oxide patterns n51 corresponding to the plurality of oxide thin film transistors. Each oxide pattern n51 includes a source region, a drain region, and a channel region.

[0257] The source and drain of the oxide thin film transistor are located in the second source-drain layer n9. The source of the oxide thin film transistor is connected to the source region, and the drain of the oxide thin film transistor is connected to the drain region.

[0258] The second gate pattern n71 includes a plurality of second gate patterns n71 corresponding to a plurality of oxide thin film transistors, and the channel region is an overlapping area of ​​an orthographic projection of the second gate pattern n71 on the second planar layer n10 and an orthographic projection of the oxide pattern n51 on the second planar layer n10.

[0259] Optionally, referring to FIG19 , the driving circuit layer N including multiple oxide thin film transistors may include a single gate layer. Generally, the more transistors there are in the driving circuit layer, the more difficult it is to lay out the film layer. A fourth gate layer n11 is provided between the second buffer layer n4 and the oxide layer n5. In other words, the driving circuit layer may include a double-layer gate layer. At the same time, by designing the fourth gate layer n11 on the side of the oxide layer n5 close to the intermediate substrate 203, the fourth gate layer n11 can act as a light shielding layer to prevent the oxide layer n5 from being disturbed by light.

[0260] Furthermore, to ensure the fabrication quality of each film layer in the driver circuit layer, a second barrier layer n12 can be provided between the second wiring layer n3 and the second buffer layer n4. Furthermore, the second barrier layer n12 is located between the fourth gate layer n11 and the oxide layer n5, providing insulation. Furthermore, the oxide driver circuit layer N also includes a substrate n13 located between the second structural layer n1 and the second passivation layer n2. This substrate n13 can provide support. For example, this substrate n13 can be a flexible substrate made of polyimide (PI).

[0261] Optionally, the first driving circuit layer 201 may be an upright driving circuit layer, and the second driving circuit layer 202 may be an inverted driving circuit layer. For example, assuming that the first driving circuit layer 201 is a low-temperature polycrystalline silicon driving circuit layer and the second driving circuit layer 202 is an oxide driving circuit layer, the low-temperature polycrystalline silicon driving circuit layer is an upright driving circuit layer and the oxide driving circuit layer is an inverted driving circuit layer. Alternatively, referring to Figures 19 and 20, assuming that the first driving circuit layer 201 is an oxide driving circuit layer and the second driving circuit layer 202 is a low-temperature polycrystalline silicon driving circuit layer, the oxide driving circuit layer is an upright driving circuit layer and the low-temperature polycrystalline silicon driving circuit layer is an inverted driving circuit layer.

[0262] Alternatively, referring to Figures 21 to 24 , taking the example of an oxide drive circuit layer as the first drive circuit layer 201 and a low-temperature polysilicon drive circuit layer as the second drive circuit layer 202, the first gate layer m7 further includes a plurality of first gate connection patterns m72, and the first source-drain layer m9 further includes a plurality of first source-drain connection patterns m91. Each first gate connection pattern m72 is connected to a corresponding first wiring pattern m31 via a via in the first gate insulating layer m6 and the first buffer layer m4, and each first source-drain connection pattern m91 is connected to a corresponding first gate connection pattern m72 via a via in the first interlayer dielectric layer m8.

[0263] For a part of the multiple first source-drain connection patterns m91, they can be electrically connected through the vias in the first flat layer m10 and the pins 2022 (pins 2022 can be called pin feet) included in the second driving circuit layer 202, and another part of the first source-drain connection patterns m91 can be directly electrically connected to the source or drain located in the source-drain layer of the low-temperature polycrystalline silicon thin film transistor.

[0264] The second gate layer n7 further includes a plurality of second gate connection patterns n72, and the first source-drain layer m9 further includes a plurality of second source-drain connection patterns n91. Each second gate connection pattern n72 is connected to a corresponding second wiring pattern n31 through a via in the second gate insulating layer n6 and the second buffer layer n4, and each second source-drain connection pattern n91 is connected to a corresponding second gate connection pattern n72 through a via in the second interlayer dielectric layer n8.

[0265] For a part of the multiple second source-drain connection patterns n91, they can be electrically connected to the third electrode 2011 through the via in the second flat layer n10, and another part of the second source-drain connection pattern n91 can be directly electrically connected to the source or drain in the source-drain layer of the oxide thin film transistor.

[0266] 21 , the pin 2022 can provide a signal to the third electrode 2011 via various connection patterns and the intermediate electrode 204. Referring to FIG22 , the first-type transistor G1 and the second-type transistor G2 can be electrically connected via various connection patterns and the intermediate electrode 204. Referring to FIG23 , the pin 2022 can provide a signal to the first-type transistor G1 via various connection patterns and the intermediate electrode 204. Referring to FIG24 , the second-type transistor G2 can provide a signal to the fourth electrode 2012 via various connection patterns and the intermediate electrode 204.

[0267] Alternatively, referring to Figures 25 to 28 , taking the example of an oxide drive circuit layer as the second drive circuit layer 202 and a low-temperature polysilicon drive circuit layer as the first drive circuit layer 201, the first gate layer m7 further includes a plurality of first gate connection patterns m72, and the first source-drain layer m9 further includes a plurality of first source-drain connection patterns m91. Each first gate connection pattern m72 is connected to a corresponding first wiring pattern m31 via a via in the first gate insulating layer m6 and the first buffer layer m4, and each first source-drain connection pattern m91 is connected to a corresponding first gate connection pattern m72 via a via in the first interlayer dielectric layer m8.

[0268] For a part of the multiple first source-drain connection patterns m91, they can be electrically connected to the third electrode 2011 through the via hole in the first flat layer m10, and another part of the first source-drain connection pattern m91 can be directly electrically connected to the source or drain located in the source-drain layer of the low-temperature polycrystalline silicon thin film transistor.

[0269] The second gate layer n7 further includes a plurality of second gate connection patterns n72, and the first source-drain layer m9 further includes a plurality of second source-drain connection patterns n91. Each second gate connection pattern n72 is connected to a corresponding second wiring pattern n31 through a via in the second gate insulating layer n6 and the second buffer layer n4, and each second source-drain connection pattern n91 is connected to a corresponding second gate connection pattern n72 through a via in the second interlayer dielectric layer n8.

[0270] For a part of the multiple second source-drain connection patterns n91, they can be electrically connected to the pin 2011 through the via in the second flat layer n10, and another part of the second source-drain connection pattern n91 can be directly electrically connected to the source or drain in the source-drain layer of the oxide thin film transistor.

[0271] 25 , the pin 2022 can provide a signal to the third electrode 2011 via various connection patterns and the intermediate electrode 204. Referring to FIG26 , the first-type transistor G1 and the second-type transistor G2 can be electrically connected via various connection patterns and the intermediate electrode 204. Referring to FIG27 , the second-type transistor G2 can provide a signal to the fourth electrode 2012 via various connection patterns and the intermediate electrode 204. Referring to FIG28 , the pin 2022 can provide a signal to the first-type transistor G1 via various connection patterns and the intermediate electrode 204.

[0272] In the embodiment of the present application, referring to Figures 1 to 28 , the driving unit 200 includes a plurality of pins 2022. The plurality of pins 2022 are located on a side of the second driving circuit layer 202 away from the first driving circuit layer 201. The material of the pins 2022 may be copper (Cu). One or more of the plurality of pins 2022 are electrically connected to the first type transistor G1, and one or more of the plurality of pins 2022 are electrically connected to the second type transistor G2.

[0273] For example, the first driver circuit layer 201 is a low-temperature polysilicon driver circuit layer M, and the second driver circuit layer 202 is an oxide driver circuit layer N. One or more of the multiple pins 2022 are electrically connected to the source of the second type of transistor (oxide thin film transistor) located in the second source-drain layer n9 through a via in the second planar layer n10. One or more of the multiple pins 2022 are electrically connected to the second source-drain connection pattern n91 located in the second source-drain layer n9 through a via in the second planar layer n10. The second source-drain connection pattern n91 can be used to connect to the first type of transistor (low-temperature polysilicon thin film transistor).

[0274] For example, the first driver circuit layer 201 is an oxide driver circuit layer N, and the second driver circuit layer 202 is a low-temperature polysilicon driver circuit layer M. One or more of the multiple pins 2022 are electrically connected to the source of the second type of transistor (low-temperature polysilicon thin-film transistor) located in the first source-drain layer m9 through a via in the first planar layer m10. One or more of the multiple pins 2022 are electrically connected to a first source-drain connection pattern m91 located in the first source-drain layer m9 through a via in the first planar layer m10. This first source-drain connection pattern m91 can be used to connect to the first type of transistor (oxide thin-film transistor).

[0275] In an embodiment of the present application, referring to FIG29 , the driving unit 200 includes a first transistor T1, which is located in the first driving circuit layer 201 or in the second driving circuit layer 202. The drain of the first transistor T1 is electrically connected to the fourth electrode 2012. For example, when the first transistor T1 is located in the first driving circuit layer 201, the drain of the first transistor T1 can be directly electrically connected to the fourth electrode 2012. Alternatively, when the first transistor T1 is located in the second driving circuit layer 202, the drain of the first transistor T1 is electrically connected to the fourth electrode 2012 via a plurality of connection patterns (such as a first gate connection pattern m72, a first source-drain connection pattern m91, a second gate connection pattern n72, and a second source-drain connection pattern n91) without being indirectly connected through other transistors. The drain of the first transistor T1 can directly provide a signal to the fourth electrode 2012. In addition, one of the plurality of pins 2022 may be electrically connected to the third electrode 2011 , that is, one of the pins 2022 may be directly electrically connected to the third electrode 2011 through a plurality of connection patterns, and the pin 2022 directly provides a signal to the third electrode 2011 .

[0276] 29 , the driving unit 200 further includes a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 and a first capacitor C1 .

[0277] The gate of the first transistor T1 is coupled to the first light emission control signal terminal HF, the first electrode of the first transistor T1 is coupled to the first node J1, and the second electrode of the first transistor T1 is the drain of the first transistor T1, that is, the second electrode of the first transistor T1 is coupled to the fourth electrode 2012. Since the gate of the first transistor T1 is connected to the first light emission control signal terminal HF, the first transistor T1 can also be called a light emission control transistor.

[0278] The gate of the second transistor T2 is coupled to the reset signal terminal RST, the first electrode of the second transistor T2 is coupled to the pull-down power supply terminal VSS, and the second electrode of the second transistor T2 is coupled to the second node J2. The second transistor T2 can also be called a reset transistor.

[0279] The gate of the third transistor T3 is coupled to the gate signal terminal Gate, the first electrode of the third transistor T3 is coupled to the first node J1, and the second electrode of the third transistor T3 is coupled to the second node J2. The third transistor T3 can also be called a compensation transistor.

[0280] The gate of the fourth transistor T4 is coupled to the second node J2, the first electrode of the fourth transistor T4 is coupled to the first node J1, and the second electrode of the fourth transistor T4 is coupled to the third node J3. The fourth transistor T4 may also be referred to as a driving transistor.

[0281] A gate of the fifth transistor T5 is coupled to the gate signal terminal Gate, a first electrode of the fifth transistor T5 is coupled to the data signal terminal DATA, and a second electrode of the fifth transistor T5 is coupled to the third node J3.

[0282] The gate of the sixth transistor T6 is coupled to the second emission control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the driving power supply terminal VDD, and the second electrode of the sixth transistor T6 is coupled to the third node J3. Since the gate of the sixth transistor T6 is connected to the second emission control signal terminal EM, the sixth transistor T6 can also be referred to as a light emission control transistor.

[0283] A gate of the seventh transistor T7 is coupled to the reset signal terminal RST, a first electrode of the seventh transistor T7 is coupled to the pull-down power supply terminal VSS, and a second electrode of the seventh transistor T7 is coupled to the second electrode 102 of the light emitting unit 100 .

[0284] A first electrode of the first capacitor C1 is coupled to a second node J2, and a second electrode of the second electrode 102 is coupled to the driving power supply terminal VDD. Optionally, the first capacitor C1 may be a storage capacitor, which may include two capacitor plates Cst1 and Cst2. In the embodiment of the present application, the capacitor plate Cst1 may be referred to as one end, a first end, or a first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the other end, a second end, or a second storage capacitor electrode of the storage capacitor Cst.

[0285] In the embodiment of the present application, the signals received by the above-mentioned first light-emitting control signal terminal HF, reset signal terminal RST, pull-down power supply terminal VSS, gate signal terminal Gate, data signal terminal DATA, second light-emitting control signal terminal EM, and driving power supply terminal VDD all come from the driving backplane.

[0286] Optionally, the plurality of light-emitting units 100 include a first color light-emitting unit, a second color light-emitting unit, and a third color light-emitting unit. The first color, the second color, and the third color are different from each other. For example, the first color is red (R), the second color is green (G), and the third color is blue (B).

[0287] Therefore, when light-emitting units 100 of different colors emit light, the first electrodes of the corresponding fifth transistors T5 receive different signals from the driver backplane via the data signal terminal DATA. Therefore, the data signal terminal DATA included in the light-emitting assembly may include: a data signal terminal R-DATA corresponding to the red light-emitting unit, a data signal terminal G-DATA corresponding to the green light-emitting unit, and a data signal terminal B-DATA corresponding to the blue light-emitting unit.

[0288] As can be seen, the driver backplane needs to provide nine signals to the light-emitting components: an HF signal, an RST signal, a VSS signal, a Gate signal, an R-DATA signal, a G-DATA signal, a B-DATA signal, an EM signal, and a VDD signal. Accordingly, referring to FIG30 , the driver unit 200 may include nine pins 2022: an HF pin, an RST pin, a VSS pin, a Gate pin, an R-DATA pin, a G-DATA pin, a B-DATA pin, an EM pin, and a VDD pin. These nine pins can receive these nine signals.

[0289] 30 , the nine pins 2022 can be arranged in three rows and three columns. The specific signal of each pin can be determined based on the actual product design. The embodiment of the present application does not limit the specific arrangement of the pins.

[0290] In the embodiment of the present application, the second transistor T2 and the seventh transistor T7 may be oxide thin film transistors. Oxide thin film transistors may be referred to as N-type transistors. The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be low-temperature polysilicon thin film transistors. Low-temperature polysilicon thin film transistors may be referred to as P-type transistors.

[0291] Optionally, assuming that the first driving circuit layer 201 is an oxide driving circuit layer and the second driving circuit layer 202 is a low-temperature polysilicon driving circuit layer, the second transistor T2 and the seventh transistor T7 can be located in the first driving circuit layer 201, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be located in the second driving circuit layer 202. In this case, the second transistor T2 and the seventh transistor T7 are closer to the light-emitting unit 100 than the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0292] The gate of the second transistor T2 is connected to the reset signal terminal RST and needs to receive the RST signal transmitted by the driver backplane via the RST pin. Since the second transistor T2 is located in the first driver circuit layer 201, the RST pin can be connected to the gate of the second transistor T2 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. The connection pattern in the second driver circuit layer 202 includes: the first gate connection pattern m72 and the second source-drain connection pattern n91 included in the low-temperature polysilicon driver circuit layer.

[0293] Similarly, the gate of the seventh transistor T7 is connected to the reset signal terminal RST and needs to receive the RST signal transmitted by the driver backplane via the RST pin. Since the seventh transistor T7 is located in the first driver circuit layer 201, the RST pin can be connected to the gate of the seventh transistor T7 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013.

[0294] The gate of the first transistor T1 is connected to the first light-emitting control signal terminal HF, and needs to receive the HF signal transmitted by the driving backplane through the HF pin. Since the first transistor T1 is located in the second driving circuit layer 202, the HF pin can be connected to the gate of the first transistor T1. In addition, since the first transistor T1 is also connected to the second electrode 102 of the light-emitting unit 100, the first transistor T1 can be connected to the second electrode 102 through the second connection structure 2021, the first connection structure 2013 and the connection pattern in the first driving circuit layer 201. Among them, the connection pattern in the first driving circuit layer 201 includes: the second gate connection pattern n72 and the second source-drain connection pattern n91 included in the oxide driving circuit layer N.

[0295] The gate of the third transistor T3 is connected to the gate signal terminal Gate and needs to receive the Gate signal transmitted by the driver backplane through the Gate pin. Since the third transistor T3 is located in the second driver circuit layer 202, the Gate pin can be connected to the gate of the third transistor T3. Moreover, since the third transistor T3 is also connected to the second transistor T2, and the second transistor T2 is located in the first driver circuit layer 201, the third transistor T3 can be connected to the second transistor T2 via the second connection structure 2021 and the first connection structure 2013.

[0296] The gate, the first electrode and the second electrode of the fourth transistor T4 are all connected to the transistor located in the second driving circuit layer 202 , so the connection can be directly designed in the second driving circuit layer 202 .

[0297] The gate of the fifth transistor T5 is connected to the gate signal terminal Gate and needs to receive the Gate signal transmitted by the driver backplane via the Gate pin. Since the fifth transistor T5 is located in the second driver circuit layer 202, the Gate pin can be connected to the gate of the fifth transistor T5. The first electrode of the fifth transistor T5 is connected to the data signal terminal DATA and needs to receive the DATA signal transmitted by the driver backplane via the DATA pin. Since the fifth transistor T5 is located in the second driver circuit layer 202, the DATA pin can be connected to the first electrode of the fifth transistor T5.

[0298] The gate of the sixth transistor T6 is connected to the second light-emission control signal terminal EM and needs to receive the EM signal transmitted by the driver backplane via the EM pin. Since the sixth transistor T6 is located in the second driver circuit layer 202, the EM pin can be connected to the gate of the sixth transistor T6. The first electrode of the sixth transistor T6 is connected to the driver power supply terminal VDD and needs to receive the VDD signal transmitted by the driver backplane via the VDD pin. Since the sixth transistor T6 is located in the second driver circuit layer 202, the VDD pin can be connected to the first electrode of the sixth transistor T6.

[0299] In the embodiment of the present application, referring to FIG. 29 , the first electrode of the first capacitor C1 is connected to the second node J2, and the third transistor T3 and the fourth transistor T4 of the transistors connected to the second node J2 are both located in the second driver circuit layer 202. Therefore, to simplify the connection, the first capacitor C1 can be located in the second driver circuit layer 202. Alternatively, the first capacitor C1 can be located in the driver circuit layer where the low-temperature polysilicon thin-film transistor is located.

[0300] In addition, the second electrode of the first capacitor C1 is connected to the driving power supply terminal VDD and needs to receive the VDD signal transmitted by the driving backplane through the VDD pin. Since the first capacitor C1 is located in the second driving circuit layer 202, the VDD pin can be connected to the second electrode of the first capacitor C1.

[0301] Optionally, assuming that the first driving circuit layer 201 is a low-temperature polysilicon driving circuit layer and the second driving circuit layer 202 is an oxide driving circuit layer, the second transistor T2 and the seventh transistor T7 can be located in the second driving circuit layer 202, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be located in the first driving circuit layer 201. In this case, the second transistor T2 and the seventh transistor T7 are farther away from the light-emitting unit 100 than the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0302] The gate of the second transistor T2 is connected to the reset signal terminal RST and needs to receive the RST signal transmitted by the driving backplane through the RST pin. Since the second transistor T2 is located in the second driving circuit layer 202, the RST pin can be connected to the gate of the second transistor T2.

[0303] Similarly, the gate of the seventh transistor T7 is connected to the reset signal terminal RST and needs to receive the RST signal transmitted by the driver backplane through the RST pin. Since the seventh transistor T7 is located in the second driver circuit layer 202, the RST pin can be connected to the gate of the seventh transistor T7. The second electrode of the seventh transistor T7 is connected to the second electrode 102 of the light-emitting unit 100, so the seventh transistor T7 can be connected to the second electrode 102 of the light-emitting unit 100 through the second connection structure 2021, the first connection structure 2013 and the connection pattern in the first driver circuit layer 201. Among them, the connection pattern in the first driver circuit layer 201 includes: the first gate connection structure and the first source-drain connection structure included in the low-temperature polysilicon driver circuit layer.

[0304] The gate of the first transistor T1 is connected to the first light-emitting control signal terminal HF, and needs to receive the HF signal transmitted by the driving backplane through the HF pin. Since the first transistor T1 is located in the first driving circuit layer 201, the HF pin can be connected to the gate of the first transistor T1 through the connection pattern in the second driving circuit layer 202, the second connection structure 2021 and the first connection structure 2013. In addition, since the first transistor T1 is also connected to the second electrode 102 of the light-emitting unit 100, the first transistor T1 can be connected to the second electrode 102. Among them, the connection pattern in the second driving circuit layer 202 includes: the second gate connection pattern n72 and the second source-drain connection pattern n91 included in the oxide driving circuit layer N.

[0305] The gate of the third transistor T3 is connected to the gate signal terminal Gate and needs to receive the Gate signal transmitted by the driver backplane through the Gate pin. Since the third transistor T3 is located in the first driver circuit layer 201, the Gate pin can be connected to the gate of the third transistor T3 through the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. Furthermore, since the third transistor T3 is also connected to the second transistor T2, and the second transistor T2 is located in the second driver circuit layer 202, the third transistor T3 can be connected to the second transistor T2 through the second connection structure 2021 and the first connection structure 2013.

[0306] The gate, the first electrode and the second electrode of the fourth transistor T4 are all connected to the transistor located in the first driving circuit layer 201 , so the connection can be directly designed in the first driving circuit layer 201 .

[0307] The gate of the fifth transistor T5 is connected to the gate signal terminal Gate and needs to receive the Gate signal transmitted by the driver backplane via the Gate pin. Since the fifth transistor T5 is located in the first driver circuit layer 201, the Gate pin can be connected to the gate of the fifth transistor T5 via the connection pattern of the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. The first electrode of the fifth transistor T5 is connected to the data signal terminal DATA and needs to receive the DATA signal transmitted by the driver backplane via the DATA pin. Since the fifth transistor T5 is located in the first driver circuit layer 201, the DATA pin can be connected to the first electrode of the fifth transistor T5 via the connection pattern of the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013.

[0308] The gate of the sixth transistor T6 is connected to the second light-emitting control signal terminal EM and needs to receive the EM signal transmitted by the driver backplane via the EM pin. Since the sixth transistor T6 is located in the first driver circuit layer 201, the EM pin can be connected to the gate of the sixth transistor T6 via the connection pattern of the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. The first electrode of the sixth transistor T6 is connected to the driver power supply terminal VDD and needs to receive the VDD signal transmitted by the driver backplane via the VDD pin. Since the sixth transistor T6 is located in the first driver circuit layer 201, the VDD pin can be connected to the first electrode of the sixth transistor T6 via the connection pattern of the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013.

[0309] In the embodiment of the present application, in order to simplify the connection, the first capacitor C1 can be located in the first driving circuit layer 201. Alternatively, the first capacitor C1 can be located in the driving circuit layer where the low-temperature polysilicon thin film transistor is located.

[0310] In addition, the second electrode of the first capacitor C1 is connected to the driver power supply terminal VDD and needs to receive the VDD signal transmitted by the driver backplane through the VDD pin. Since the first capacitor C1 is located in the first driver circuit layer 201, the VDD pin can be connected to the second electrode of the first capacitor C1 through the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013.

[0311] FIG31 is a circuit diagram of another driving unit provided in an embodiment of the present application. Referring to FIG31 , the driving unit 200 further includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2.

[0312] The gate of the first transistor T1 is not directly coupled to the first light emitting control signal terminal HF, but is indirectly connected via another transistor. For example, the gate of the first transistor T1 is coupled to the fourth node J4.

[0313] A gate of the eighth transistor T8 is coupled to the fifth node J5 , a first electrode of the eighth transistor T8 is coupled to the first light emitting control signal terminal HF, and a second electrode of the eighth transistor T8 is coupled to the fourth node J4 .

[0314] A gate of the ninth transistor T9 is coupled to the fifth node J5 , a first electrode of the ninth transistor T9 is coupled to the fourth node J4 , and a second electrode of the ninth transistor T9 is coupled to the second light emitting control signal terminal EM.

[0315] A gate of the tenth transistor T10 is coupled to the reset signal terminal RST, a first electrode of the tenth transistor T10 is coupled to the data signal terminal DATA, and a second electrode of the tenth transistor T10 is coupled to the fifth node J5.

[0316] A first electrode of the second capacitor C2 is coupled to the fifth node J5 , and a second electrode of the second capacitor C2 is coupled to the pull-down power supply terminal VSS.

[0317] In the embodiment of the present application, the ninth transistor T9 and the tenth transistor T10 may be oxide thin film transistors. Oxide thin film transistors may be referred to as N-type transistors. The eighth transistor T8 may be a low-temperature polysilicon thin film transistor. Low-temperature polysilicon thin film transistors may be referred to as P-type transistors.

[0318] Optionally, assuming that the first driving circuit layer 201 is an oxide driving circuit layer and the second driving circuit layer 202 is a low-temperature polysilicon driving circuit layer, the ninth transistor T9 and the tenth transistor T10 can be located in the first driving circuit layer 201, and the eighth transistor T8 can be located in the second driving circuit layer 202.

[0319] The first electrode of the eighth transistor T8 is connected to the first light-emitting control signal terminal HF and needs to receive the HF signal transmitted by the driving backplane through the HF pin. Since the eighth transistor T8 is located in the second driving circuit layer 202, the RST pin can be connected to the eighth transistor T8.

[0320] The second electrode of the ninth transistor T9 is connected to the second emission control signal terminal EM and is required to receive the EM signal transmitted by the driver backplane via the EM pin. Since the ninth transistor T9 is located in the first driver circuit layer 201, the EM pin can be connected to the ninth transistor T9 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. The first electrode of the ninth transistor T9 and the second electrode of the eighth transistor T8 are connected via a fourth node J4. Since the ninth transistor T9 and the eighth transistor T8 are located in different driver circuit layers, they need to be connected via the second connection structure 2021 and the first connection structure 2013.

[0321] The gate of the tenth transistor T10 is connected to the reset signal terminal RST and is required to receive the RST signal transmitted by the driver backplane via the RST pin. Since the tenth transistor T10 is located in the first driver circuit layer 201, the RET pin 2022 can be connected to the gate of the tenth transistor T10 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. The first electrode of the tenth transistor T10 is connected to the data signal terminal DATA and is required to receive the DATA signal transmitted by the driver backplane via the DATA pin. Since the tenth transistor T10 is located in the first driver circuit layer 201, the DATA pin can be connected to the first electrode of the tenth transistor T10 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013. The second electrode of the tenth transistor T10, the gate of the eighth transistor T8, and the gate of the ninth transistor T9 are all connected to the fifth node J5. Since the ninth transistor T9 and the tenth transistor T10 are both located in the first driver circuit layer 201, they can be directly connected. The eighth transistor T8 , the ninth transistor T9 , and the tenth transistor T10 are located in different driving circuit layers, so the gate of the eighth transistor T8 can be connected to the fifth node J5 through the second connection structure 2021 and the first connection structure 2013 .

[0322] In the embodiment of the present application, referring to FIG31 , the first electrode of the second capacitor C2 is connected to the fifth node J5, and the ninth transistor T9 and the tenth transistor T10 of the transistors connected to the fifth node J5 are both located in the first driving circuit layer 201. Therefore, to simplify the connection, the second capacitor C2 can be located in the first driving circuit layer 201. Alternatively, the first capacitor C1 can be located in the driving circuit layer where the oxide thin film transistor is located.

[0323] In addition, the second electrode of the second capacitor C2 is connected to the pull-down power supply terminal VSS and needs to receive the VSS signal transmitted by the driver backplane via the VSS pin. Since the second capacitor C2 is located in the first driver circuit layer 201, the VSS pin can be connected to the second electrode of the second capacitor C2 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013.

[0324] Optionally, assuming that the first driving circuit layer 201 is a low-temperature polysilicon driving circuit layer and the second driving circuit layer 202 is an oxide driving circuit layer, the ninth transistor T9 and the tenth transistor T10 can be located in the second driving circuit layer 202, and the eighth transistor T8 can be located in the first driving circuit layer 201.

[0325] The first electrode of the eighth transistor T8 is connected to the first light-emitting control signal terminal HF and is required to receive the HF signal transmitted by the driver backplane via the HF pin. Since the eighth transistor T8 is located in the first driver circuit layer 201, the RST pin can be connected to the eighth transistor T8 via the connection pattern in the second driver circuit layer 202, the second connection structure 2021, and the first connection structure 2013.

[0326] The second electrode of the ninth transistor T9 is connected to the second light-emitting control signal terminal EM and is required to receive the EM signal transmitted by the driver backplane via the EM pin. Since the ninth transistor T9 is located in the second driver circuit layer 202, the EM pin can be connected to the ninth transistor T9. The first electrode of the ninth transistor T9 and the second electrode of the eighth transistor T8 are connected via a fourth node J4. Since the ninth transistor T9 and the eighth transistor T8 are located in different driver circuit layers, they need to be connected to the first connection structure 2013 via a second connection structure 2021.

[0327] The gate of the tenth transistor T10 is connected to the reset signal terminal RST and needs to receive the RST signal transmitted by the driver backplane via the RST pin. Since the tenth transistor T10 is located in the second driver circuit layer 202, the RST pin can be connected to the gate of the tenth transistor T10. The first electrode of the tenth transistor T10 is connected to the data signal terminal DATA and needs to receive the DATA signal transmitted by the driver backplane via the DATA pin. Since the tenth transistor T10 is located in the second driver circuit layer 202, the DATA pin can be connected to the first electrode of the tenth transistor T10. The second electrode of the tenth transistor T10, the gate of the eighth transistor T8, and the gate of the ninth transistor T9 are all connected to the fifth node J5. The ninth transistor T9 and the tenth transistor T10 are all located in the second driver circuit layer 202 and can therefore be directly connected. Since the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are located in different driver circuit layers, the gate of the eighth transistor T8 can be connected to the fifth node J5 via the second connection structure 2021 and the first connection structure 2013.

[0328] In the embodiment of the present application, in order to simplify the connection, the second capacitor C2 can be located in the second driving circuit layer 202. In other words, the second capacitor C2 can be located in the driving circuit layer where the oxide thin film transistor is located.

[0329] In addition, the second electrode of the second capacitor C2 is connected to the pull-down power supply terminal VSS and needs to receive the VSS signal transmitted by the driving backplane through the VSS pin. Since the second capacitor C2 is located in the second driving circuit layer 202, the VSS pin can be connected to the second electrode of the second capacitor C2.

[0330] In the embodiment of the present application, in FIG. 29 above, the driving unit 200 may be a 7T1C circuit design, i.e., including 7 thin-film transistors and 1 capacitor. In FIG. 31 above, the driving unit 200 may be a 10T2C circuit design, i.e., including 10 thin-film transistors and 2 capacitors. The above two circuits are merely examples of the embodiments of the present application. In fact, the solutions provided in the embodiments of the present application can be applied to various circuit designs, such as 8T2C and 12T3C, etc., and the embodiments of the present application do not limit this.

[0331] In the embodiment of the present application, the light-emitting component 000 further includes a first substrate 300. The light-emitting unit 100 may be located on one side of the first substrate 300. Referring to FIG32 , the light-emitting portion 103 of the light-emitting unit 100 includes a first semiconductor layer 1031 and a plurality of sub-light-emitting functional layers 103a located on one side of the first semiconductor layer 1031. To more clearly illustrate the structure of the first semiconductor layer 1031, please refer to FIG33 , which is a top view of a first semiconductor layer provided in the embodiment of the present application. The first semiconductor layer 1031 may include a plurality of connecting portions 10311 corresponding one-to-one to the plurality of sub-light-emitting functional layers 103a, and an auxiliary portion 10312 connected to the plurality of connecting portions 10311.

[0332] In which, each connection portion 10311 in the first semiconductor layer 1031 can be connected to the corresponding sub-light-emitting functional layer 103a, and the outer boundary of the orthographic projection of each connection portion 10311 on the first substrate 300 can completely coincide with the outer boundary of the orthographic projection of the corresponding sub-light-emitting functional layer 103a on the first substrate 300.

[0333] In the embodiment of the present application, at least a portion of the auxiliary portion 10312 is located between adjacent connecting portions 10311, and the multiple connecting portions 10311 and the auxiliary portion 10312 in the first semiconductor layer 1031 form an integral structure. Furthermore, the material of the connecting portions 10311 in the first semiconductor layer 1031 can be the same as that of the auxiliary portion 10312. It is understood that the multiple connecting portions 10311 and the auxiliary portion 10312 in the first semiconductor layer 1031 are arranged in a direction parallel to the extending surface of the first substrate 300, and the first semiconductor layer 1031 is a planar structure arranged as a whole layer. All portions of the first semiconductor layer 1031 except the multiple connecting portions 10311 are auxiliary portions 10312. The multiple connecting portions 10311 can be connected by the auxiliary portions 10312 in the first semiconductor layer 1031.

[0334] 32 , the light emitting component 000 further includes a color conversion unit 400 located between the first substrate 300 and the light emitting unit 100 . The color conversion unit 400 includes a light shielding layer 401 , a defining dam layer 402 , an optical function layer 403 and a filter layer 404 .

[0335] The light-shielding layer 401 in the color conversion unit 400 can be located on one side of the first substrate 300. The light-shielding layer 401 can have multiple light-through holes K1. Here, the multiple light-through holes K1 can correspond one-to-one to the multiple sub-light-emitting functional layers 103a in the light-emitting portion 103. The orthographic projection of each light-through hole K1 on the first substrate 300 can overlap with the orthographic projection of the corresponding sub-light-emitting functional layer 103a on the first substrate 300. For example, the orthographic projection of each sub-light-emitting functional layer 103a in the light-emitting portion 103 on the first substrate 300 can be located within the orthographic projection of the corresponding light-through hole K1 on the first substrate 300.

[0336] The defining dam layer 402 in the color conversion unit 400 can be located on the side of the light shielding layer 401 facing away from the first substrate 300. The defining dam layer 402 can have multiple opening areas K2 corresponding one-to-one to the multiple light-through holes K1, and these opening areas K2 can also correspond one-to-one to the multiple sub-light-emitting functional layers 103a of the light-emitting portion 103. Here, the orthographic projection of each opening area K2 in the defining dam layer 402 on the first substrate 300 can overlap with the orthographic projection of the corresponding light-through hole K1 on the first substrate 300, and can overlap with the orthographic projection of the corresponding sub-light-emitting functional layer 103a on the first substrate 300. For example, the light-emitting side of each sub-light-emitting functional layer 103a in the light-emitting portion 103 can face the corresponding opening area K2, and the orthographic projection of each sub-light-emitting functional layer 103a on the first substrate 300 can be located within the orthographic projection of the corresponding opening area K2 on the first substrate 300. The orthographic projection of each opening region K2 in the dam layer 402 on the first substrate 300 may be located within the orthographic projection of the corresponding light-through hole K1 on the first substrate 300 .

[0337] In the embodiment of the present application, as shown in Figures 34 to 36, Figure 34 is a top view of a light-emitting unit and a color conversion unit provided in the embodiment of the present application, Figure 35 is a schematic diagram of the film structure of the light-emitting at A-A' shown in Figure 34, and Figure 36 is a schematic diagram of the film structure at B-B' in Figure 34. The multiple sub-light-emitting functional layers 103a in the light-emitting portion 103 may include: a first sub-light-emitting functional layer 103a1, a second sub-light-emitting functional layer 103a2, and a third sub-light-emitting functional layer 103a3. Among them, the first sub-light-emitting functional layer 103a1, the second sub-light-emitting functional layer 103a2, and the third sub-light-emitting functional layer 103a3 are all used to emit a first light in the working state.

[0338] Accordingly, the plurality of opening regions K2 defined in the dam layer 402 may include a first opening region K21, a second opening region K22, and a third opening region K23. The first opening region K21 may be disposed opposite the first sub-light-emitting functional layer 103a1, the second opening region K22 may be disposed opposite the second sub-light-emitting functional layer 103a2, and the third opening region K23 may be disposed opposite the third sub-light-emitting functional layer 103a3.

[0339] The first opening area K21 and the second opening area K22 are arranged in a row in a first direction X, and the second opening area K22 and the third opening area K23 are arranged in a row in a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X can be perpendicular to the second direction Y. In the embodiment of the present application, the area enclosed by the outer contour of the dam layer 402 is rectangular; the first opening area K21, the second opening area K22, and the third opening area K23 are all rectangular in shape.

[0340] The optical functional layer 403 in the color conversion unit 400 can be located within the opening region K2 defining the dam layer 402. At least a portion of the optical functional layer 403 is configured to convert the color of light entering the optical functional layer 403. Here, light emitted from the light-emitting unit 100 can be directed toward the optical functional layer 403, where it is converted in color before being emitted through the apertures in the light-shielding layer 401.

[0341] Optionally, the optical functional layer 403 in the color conversion unit 400 may include a first color conversion portion 403a, a second color conversion portion 403b, and a third color conversion portion 403c. The first color conversion portion 403a may be located within the first opening area K21, the second color conversion portion 403b may be located within the second opening area K22, and the third color conversion portion 403c may be located within the third opening area K23.

[0342] In this case, the first light emitted by the first sub-light-emitting functional layer 103a1 can be directed toward the first color conversion region 403a, where it is converted into light of another color by the first color conversion region 403a. The first light emitted by the second sub-light-emitting functional layer 103a2 can be directed toward the second color conversion region 403b, where it is converted into light of another color by the second color conversion region 403b. The first light emitted by the third sub-light-emitting functional layer 103a3 can be directed toward the third color conversion region 403c, where it can be transmitted through or converted by the third color conversion region 403c.

[0343] For example, the light emitting component may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The first light emitted by the first sub-light emitting functional layer 103a1, the second sub-light emitting functional layer 103a2, and the third sub-light emitting functional layer 103a3 in the light emitting portion 103 includes at least one of blue light and ultraviolet light.

[0344] The first color conversion unit 403a is used to convert the first light into red light. For example, the first color conversion unit 403a includes red quantum dots that convert the first light into red light. Preferably, the first color conversion unit 403a also includes scattering particles for scattering the light. After the first light emitted by the first sub-light-emitting functional layer 103a1 strikes the first color conversion unit 403a distributed within the first opening area K21, the red quantum dots convert the first light into red light. The scattering particles scatter the first light and red light, ensuring that more of the first light is converted into red light by the red quantum dots. This also ensures that the output angle of the converted red light is wide, thereby ensuring a wide viewing angle for the display substrate integrated with the light-emitting component. To this end, the red sub-pixel R in the light-emitting component 000 may include: the first sub-light-emitting functional layer 103a1 and the first color conversion unit 403a.

[0345] The second color conversion portion 403b is used to convert the first light into green light. For example, the second color conversion portion 403b includes green quantum dots that convert the first light into green light. Preferably, the second color conversion portion 403b also includes scattering particles for scattering the light. Here, after the first light emitted from the second sub-light-emitting functional layer 103a2 is emitted into the second color conversion portion 403b distributed within the second opening area K22, it is converted into green light by the green quantum dots. The scattering particles scatter the first and green light, ensuring that more of the first light is converted into green light by the green quantum dots. This ensures that the emitted green light has a larger emission angle, thereby ensuring a wider viewing angle for the display substrate integrated with the light-emitting component. To this end, the green sub-pixel G in the light-emitting component may include: the second sub-light-emitting functional layer 103a2 and the second color conversion portion 403b.

[0346] The third color conversion portion 403c is used to convert the first light into blue light or maintain blue light emission. For example, when the first light contains only blue light, the third color conversion portion 403c can be a transparent portion or can include blue quantum dots. The transparent portion directly transmits the first light, while the blue quantum dots convert the first light into blue light of a different wavelength. Preferably, the third color conversion portion 403c also includes scattering particles for scattering light. Here, after the first light emitted by the third sub-light-emitting functional layer 103a3 reaches the third color conversion portion 403c distributed within the third opening area K23, the scattering particles scatter the first light, ensuring a wide emission angle for the blue light and, in turn, a wide viewing angle for the display substrate integrated with the light-emitting component. For another example, when the first light contains ultraviolet light, the third color conversion portion 403c can include blue quantum dots that convert the first light into blue light. Alternatively, the third color conversion portion 403c can include both scattering particles for scattering light and blue quantum dots for converting ultraviolet light into blue light. Here, after the first light emitted by the third sub-light-emitting functional layer 103a3 reaches the third color conversion portion 403c distributed in the third opening area K23, the blue quantum dots convert the ultraviolet light in the first light into blue light. The scattering particles scatter the first light and the blue light, ensuring that more ultraviolet light is converted into blue light by the blue quantum dots. This also ensures that the output angle of the converted blue light is large, thereby ensuring a wide viewing angle for the display substrate integrated with the light-emitting component. To this end, the blue sub-pixel B in the light-emitting component can include: the third sub-light-emitting functional layer 103a3 and the third color conversion portion 403c.

[0347] Optionally, the material defining the dam layer 402 in the color conversion unit 400 may include a light-absorbing organic material or a light-reflecting organic material. Here, the light-absorbing organic material is typically black and absorbs light emitted from the sides of the optical functional layer 403; the light-reflecting organic material is typically gray and reflects light emitted from the sides of the optical functional layer 403.

[0348] To this end, when the material of the definition dam layer 402 includes a reflective organic material, light emitted from the side of the optical functional layer 403 can be reflected back into the optical functional layer 403 by the definition dam layer 402, allowing the quantum dots in the optical functional layer 403 to convert the blue or ultraviolet light in the reflected light into light of the corresponding color, thereby further improving the excitation efficiency of the quantum dots. In addition, the light reflected back by the definition dam layer 402 can be emitted from the side of the optical functional layer 403 facing the first substrate 300, so that the light can be emitted after passing through the corresponding light hole K1, thereby effectively improving the light extraction efficiency of the light-emitting component.

[0349] The filter layer 404 may include: a plurality of filter units corresponding one-to-one to the plurality of light through holes K1 , and the orthographic projection of each filter unit on the first substrate 300 may overlap with the orthographic projection of the corresponding light through hole K1 on the first substrate 300 .

[0350] For example, the multiple filter units in the filter layer 404 may include a first filter unit 404a, a second filter unit 404b, and a third filter unit 404c. Here, the first filter unit 404a may be provided corresponding to the first color conversion unit 403a, the second filter unit 404b may be provided corresponding to the second color conversion unit 403b, and the third filter unit 404c may be provided corresponding to the third color conversion unit 403c. To this end, the red sub-pixel R in the light-emitting component 000 may further include the first filter unit 404a; the green sub-pixel G in the light-emitting component 000 may further include the second filter unit 404b; and the blue sub-pixel B in the light-emitting component 000 may further include the third filter unit 404c.

[0351] For example, the first light emitted by the first sub-light-emitting functional layer 103a1, the second sub-light-emitting functional layer 103a2, and the third sub-light-emitting functional layer 103a3 in the light-emitting unit 100 is all blue light. The first filter unit 404a can be a red color block that transmits red light and absorbs light of other colors. In this way, the light emitted from the first color conversion unit 403a can pass through the first filter unit 404a before being emitted. The first filter unit 404a can filter out light of other colors except red light, thereby ensuring that the red sub-pixel R in the light-emitting component can filter out the blue light component. It should be noted that, in other possible implementations, the first filter unit 404a may also be a film layer for transmitting red light and reflecting blue light. In this way, after the light emitted from the first color conversion portion 403a hits the first filter unit 404a, the red light in this light can pass through the first filter unit 404a before being emitted again, while the blue light in this light can be reflected back to the first color conversion portion 403a by the first filter unit 404a. This allows the red quantum dots in the first color conversion portion 403a to excite the blue light into red light, thereby further improving the excitation efficiency of the red quantum dots.

[0352] For example, the first light emitted by the first sub-light-emitting functional layer 103a1, the second sub-light-emitting functional layer 103a2, and the third sub-light-emitting functional layer 103a3 in the light-emitting unit 100 is all blue light. The second filter unit 404b can be a green color block that transmits green light and absorbs light of other colors. In this way, the light emitted from the second color conversion unit 403b can pass through the second filter unit 404b before being emitted. The second filter unit 404b can filter out light of other colors except green light, thereby ensuring that the green sub-pixel G in the light-emitting component can filter out the blue light component. It should be noted that, in other possible implementations, the second filter unit 404b may also be a film layer for transmitting green light and reflecting blue light. In this way, after the light emitted from the second color conversion portion 403b hits the second filter unit 404b, the green light in this light can pass through the second filter unit 404b before being emitted, while the blue light in this light can be reflected back to the second color conversion portion 403b by the second filter unit 404b. The green quantum dots in the second color conversion portion 403b can then excite the blue light into green light, thereby further improving the excitation efficiency of the green quantum dots.

[0353] It should be noted that the film structures of the first filter unit 404a and the second filter unit 404b can be the same and can be prepared through the same process; for example, the first filter unit 404a and the second filter unit 404b are both films that transmit red light and green light and reflect blue light.

[0354] For example, the first light emitted by the first sub-light-emitting functional layer 103a1, the second sub-light-emitting functional layer 103a2, and the third sub-light-emitting functional layer 103a3 in the light-emitting unit 100 is all blue light. The third filter unit 404c can be a blue color block that transmits blue light and absorbs light of other colors. In this way, the light emitted from the third color conversion unit 403c can pass through the third filter unit 404c before being emitted. The third filter unit 404c can filter out light of other colors except blue light, thereby ensuring that the blue sub-pixel B in the light-emitting component can emit relatively pure blue light.

[0355] For example, the first light emitted by the first sub-light-emitting functional layer 103a1, the second sub-light-emitting functional layer 103a2 and the third sub-light-emitting functional layer 103a3 in the light-emitting unit 100 are all blue light, and the third filter unit 404c can be a transparent block that can transmit blue light.

[0356] It should be noted that, because the orthographic projections of the respective filter units in the filter layer 404 on the first substrate 300 overlap with the orthographic projections of the corresponding light holes K1 in the light shielding layer 401 on the first substrate 300, portions of the light shielding layer 401 are distributed between two adjacent filter units in the filter layer 404 in a direction parallel to the extended surface of the first substrate 300. In this way, light emitted from the side of a filter unit in the filter layer 404 can be absorbed by the light shielding layer 401, thereby ensuring that the intensity of light emitted by each sub-pixel toward adjacent sub-pixels is low, effectively reducing the probability of color crosstalk in the light-emitting component 000.

[0357] 35 and 36 , the color conversion unit 400 includes a first encapsulation layer 405, which can be located on the side of the definition dam layer 402 facing away from the first substrate 300. The first encapsulation layer 405 can encapsulate the definition dam layer 402, the optical functional layer 403, and the filter layer 404 to prevent water and oxygen in the external environment from penetrating the definition dam layer 402 and corroding the optical functional layer 403 or the filter layer 404. This ensures that the optical functional layer 403 can stably convert the color of light, thereby increasing the reliability of the optical functional layer 403.

[0358] For example, the first encapsulation layer 405 in the color conversion unit 400 may include a first encapsulation portion 4051 and a second encapsulation portion 4052. The first encapsulation portion 4051 is located on the side of the definition dam layer 402 away from the first substrate 300, and the second encapsulation portion 4052 is located on the outer side of the definition dam layer 402 and the light shielding layer 401. In this manner, the first encapsulation layer 405 can encapsulate the definition dam layer 402 and the light shielding layer 401, preventing water and oxygen in the external environment from corroding the optical functional layer 403 through the light shielding layer 401 and the definition dam layer 402.

[0359] Alternatively, as shown in Figures 35 and 36, the color conversion unit 400 in the light-emitting component 000 may further include a second encapsulation layer 406 located between the light-shielding layer 401 and the defining dam layer 402. The optically functional layer 403 and the defining dam layer 402 in the color conversion unit 400 may both be located on the side of the second encapsulation layer 406 facing away from the first substrate 300, and the second encapsulation layer 406 needs to cover at least the outer side of the light-shielding layer 401 and the side of the light-shielding layer 401 facing away from the first substrate 300. In this case, the second encapsulation layer 406 can encapsulate the light-shielding layer 401, preventing water and oxygen in the external environment from corroding the optically functional layer 403 through the light-shielding layer 401 and the defining dam layer 402. Moreover, in this case, the first encapsulation layer 405 only needs to cover the outer side surface of the dam layer 402, that is, the second encapsulation part 4052 in the first encapsulation layer 405 does not need to extend to the outer side surface of the light-shielding layer 401, thereby reducing the step difference of the first encapsulation layer 405 and reducing the risk of breakage of the first encapsulation layer 405.

[0360] The first encapsulation layer 405 can be a film structure that is continuously distributed at all locations. Of course, the second encapsulation layer 406 can also be a film structure that is continuously distributed at all locations. In addition, the orthographic projections of the definition dam layer 402 and the optical functional layer 403 on the first substrate 300 are both located within the orthographic projection of the first encapsulation layer 405 on the first substrate 300, and are also located within the orthographic projection of the second encapsulation layer 406 on the first substrate 300. At the same time, the second encapsulation layer 406 and the first encapsulation layer 405 are arranged in contact, so that the first encapsulation layer 405 and the second encapsulation layer 406 can completely encapsulate the definition dam layer 402 and the optical functional layer 403 through cooperation. Here, the area where the second encapsulation layer 406 contacts the first encapsulation layer 405 is distributed around the definition dam layer 402, so that the cooperation between the first encapsulation layer 405 and the second encapsulation layer 406 can ensure a good encapsulation effect on the optical functional layer 403, further improving the reliability of the optical functional layer 403.

[0361] For example, as shown in FIG37 , the first encapsulation layer 405 may further include a third encapsulation portion 4053. The third encapsulation portion 4053 may be connected to a side of the second encapsulation portion 4052 facing away from the first encapsulation portion 4051. The third encapsulation portion 4053 may be located on a side of the second encapsulation layer 406 facing away from the first substrate 300, and may directly contact a side of the second encapsulation layer 406 facing away from the first substrate 300. In this way, it is ensured that a portion of the first encapsulation layer 405 is in contact with the second encapsulation layer 406.

[0362] In the embodiment of the present application, the side of the third packaging part 4053 facing away from the second packaging part 4052 is the outer side surface of the first packaging layer 405. The outer side surface of the first packaging layer 405 can be flush with the outer side surface of the second packaging layer 406, so that the contact area between the first packaging layer 405 and the second packaging layer 406 is wider, thereby ensuring that the first packaging layer 405 and the second packaging layer 406 have a better packaging effect on the defined dam layer 402.

[0363] In an embodiment of the present application, the light-emitting unit 100 and the color conversion unit 400 in the light-emitting component 000 can be bonded via a connecting layer 500. That is, a connecting layer 500 for bonding the light-emitting unit 100 and the color conversion unit 400 is distributed between them. In order to more clearly see the structure of the light-emitting unit 100 in the light-emitting component, please refer to Figures 38 and 39. Figure 38 is a top view of a first electrode, a second electrode, and a light-emitting unit located on a connecting layer provided in an embodiment of the present application, and Figure 39 is a schematic diagram of the film layer structure at C-C' in Figure 38. The first semiconductor layer 1031 included in the light-emitting portion 103 can be connected to the first electrode 101.

[0364] Each sub-light-emitting functional layer 103a in the light-emitting portion 103 may include: a second semiconductor layer 1032 and a light-emitting layer 1033 stacked in a direction perpendicular to and toward the first substrate 300. The second electrode 102, the second semiconductor layer 1032, and the light-emitting layer 1033 are stacked in a direction perpendicular to and toward the first substrate 300. That is, the light-emitting layer 1033 in the sub-light-emitting functional layer 103a is closer to the first semiconductor layer 1031 than the second electrode 102.

[0365] The light-emitting layer 1033 in each sub-light-emitting functional layer 103a can be connected to the first semiconductor layer 1031. Here, since the first semiconductor layer 1031 in the light-emitting portion 103 is located on the light-emitting side of each sub-light-emitting functional layer 103a, and the first semiconductor layer 1031 is closer to the first substrate 300 than each sub-light-emitting functional layer 103a, the first semiconductor layer 1031 can contact the side of the light-emitting layer 1033 in each sub-light-emitting functional layer 103a that is away from the second semiconductor layer 1032.

[0366] In the embodiment of the present application, please refer to Figure 40, which is a top view of another first semiconductor layer 1031 provided in the embodiment of the present application. The auxiliary portion 10312 in the first semiconductor layer 1031 may include: a first auxiliary portion 10312a, a second auxiliary portion 10312b, and a third auxiliary portion 10312c.

[0367] The orthographic projection of the first auxiliary portion 10312a on the first substrate 300 may overlap with the orthographic projection of the first electrode 101 on the first substrate 300. For example, the outer boundary of the orthographic projection of the first auxiliary portion 10312a on the first substrate 300 coincides with the outer boundary of the orthographic projection of the first electrode 101 on the first substrate 300.

[0368] A portion of the second auxiliary portion 10312 b may be located between adjacent connecting portions 10311 , and another portion may be located between the first auxiliary portion 10312 a and the connecting portion 10311 .

[0369] The third auxiliary portion 10312 c may be disposed around the first auxiliary portion 10312 a , the second auxiliary portion 10312 b , and the plurality of connection portions 10311 .

[0370] To this end, the first auxiliary portion 10312 a , the second auxiliary portion 10312 b , the third auxiliary portion 10312 c and the plurality of connecting portions 10311 in the first semiconductor layer 1031 may form a planar structure provided as a whole layer.

[0371] Optionally, in the light-emitting portion 103, the material of the second semiconductor layer 1032 in each sub-light-emitting functional layer 103a may include p-type doped gallium nitride (P-GaN); and the light-emitting layer 1033 in each sub-light-emitting functional layer 103a may be a multiple quantum well (MQW) layer. As shown in FIG39 , the first semiconductor layer 1031 may include a first sublayer 1031a and a second sublayer 1031b stacked perpendicularly and facing the first substrate 300. In other words, the second sublayer 1031b is closer to the connection layer 500 than the first sublayer 1031a. It is understood that the first semiconductor layer 1031 can be divided into an auxiliary portion 10312 and a plurality of connection portions 10311 in a direction parallel to the extension surface of the first substrate 300, and can be divided into a first sublayer 1031a and a second sublayer 1031b in a direction perpendicular to the extension surface of the first substrate 300.

[0372] The first sublayer 1031a in the first semiconductor layer 1031 can be located between the second sublayer 1031b and the light-emitting layer 1033 in each sub-light-emitting functional layer 103a. That is, the first sublayer 1031a is closer to the light-emitting layer 1033 in each sub-light-emitting functional layer 103a than the second sublayer 1031b. Here, the material of the first sublayer 1031a in the first semiconductor layer 1031 can be N-type doped gallium nitride (N-GaN), and the second sublayer 1031b in the first semiconductor layer 1031 can be a gallium nitride buffer layer (buffer GaN).

[0373] In this case, in the light-emitting unit 100, after the first electrode 101 is loaded with a cathode signal, if the second electrode 102 in a sub-light-emitting functional layer 103a is loaded with an anode signal, the light-emitting layer 1033 in this sub-light-emitting functional layer 103a can emit the first light.

[0374] In the embodiment of the present application, each sub-light-emitting functional layer 103a in the light-emitting unit 100 may further include a current spreading layer 1034 located between the second electrode 102 and the second semiconductor layer 1032. Here, one side of the current spreading layer 1034 in each sub-light-emitting functional layer 103a may be in contact with the second semiconductor layer 1032, and the other side may be electrically connected to the second electrode 102. Optionally, the current spreading layer 1034 may be made of indium tin oxide (ITO). Providing the current spreading layer 1034 in the sub-light-emitting functional layer 103a facilitates hole transport and improves the electrical performance of the light-emitting unit 100.

[0375] In the embodiment of the present application, please refer to Figures 41 and 42. Figure 41 is a top view of another first electrode 101, a second electrode 102 and a light-emitting unit 100 provided in the embodiment of the present application, and Figure 42 is a schematic diagram of the film layer structure at D-D' in Figure 41. The light-emitting unit 100 may also include: a common electrode layer 1035 arranged in contact with the first semiconductor layer 1031, and the side of the common electrode layer 1035 facing away from the first substrate 300 may be electrically connected to the first electrode 101. Here, the first electrode 101 can be arranged in the same layer and with the same material as the second electrode 102 in each sub-light-emitting functional layer 103a, that is, the first electrode 101 and each second electrode 102 are formed using the same patterning process.

[0376] In the embodiment of the present application, the light-emitting unit 100 may further include an insulating protective layer 1036 located on a side of the common electrode layer 1035 and each sub-light-emitting functional layer 103a facing away from the first semiconductor layer 1031. The insulating protective layer 1036 may include a first connection hole V1 corresponding to the first electrode 101 and a plurality of second connection holes V2 corresponding one-to-one to the plurality of second electrodes 102.

[0377] The first connection hole V1 may correspond to the common electrode layer 1035, and the first electrode 101101 may be electrically connected to the common electrode layer 1035 via the first connection hole V1. The plurality of second connection holes V2 may also correspond one-to-one to the plurality of sub-light-emitting functional layers 103a, and each second electrode 102 may be electrically connected to the current spreading layer 1034 in the corresponding sub-light-emitting functional layer 103a via the corresponding second connection hole V2. It should be noted that, for ease of viewing, the insulating protective layer 1036 is shown in the light-emitting unit 100 shown in FIG. 39 , but is not shown in the light-emitting unit 100 shown in FIG. 42 .

[0378] For example, the common electrode layer 1035 can function as a current spreader.

[0379] For example, the common electrode layer 1035 and the first electrode 101 are both made of metal.

[0380] Optionally, the thickness of the common electrode layer 1035 can be significantly greater than that of the current spreading layer 1034. For example, the surface of the common electrode layer 1035 facing away from the first semiconductor layer 1031 can be flush with the surface of the current spreading layer 1034 facing away from the first semiconductor layer 1031. That is, the thickness of the common electrode layer 1035 can be equal to the sum of the thicknesses of the current spreading layer 1034, the second semiconductor layer 1032, and the light-emitting layer 1033 in the sub-light-emitting functional layer 103a. In this way, the second electrode 102 and the first electrode 101 facing away from the connection layer 500 are also flush. Since the second electrode 102 and the first electrode 101 in the light-emitting unit 100 will need to be welded to the driver unit 200 when the light-emitting unit 100 is subsequently connected to the driver unit 200, when the second electrode 102 and the first electrode 101 facing away from the connection layer 500 are flush, the light-emitting unit 100 can be stably fixed to the driver unit 200.

[0381] In the embodiment of the present application, the common electrode layer 1035 may include: a common electrode body 10351, a first support portion 10352 fixedly connected to the common electrode body 10351, and two second support portions 10353 fixedly connected to the first support portion 10352. The common electrode body 10351 may be electrically connected to the first electrode 101, the first support portions 10352 may be distributed around the common electrode body 10351, and each second support portion 10353 may be distributed on a side of the first support portion 10352 facing away from the common electrode body 10351. Of the two second support portions 10353, one may be located between two adjacent sub-light-emitting functional layers 103a distributed in the row direction, and the other may be located between two adjacent sub-light-emitting functional layers 103a distributed in the column direction. In this way, the intensity of the entire light-emitting unit 100 can be ensured to be high, and the volume of the common electrode layer 1035 can be ensured to be large, thereby reducing the resistance for transmitting the common cathode signal in the light-emitting unit 100.

[0382] In summary, an embodiment of the present application provides a light-emitting component, which includes a light-emitting unit and a driving unit. The first electrode in the light-emitting unit is electrically connected to the third electrode in the driving unit, and the second electrode in the light-emitting unit is electrically connected to the fourth electrode in the driving unit. As a result, the driving unit can provide a driving signal to the light-emitting unit, and the light-emitting unit can emit light under the drive of the driving unit. In addition, the first driving circuit layer including the first type of transistor and the second driving circuit layer including the second type of transistor in the driving unit are stacked, thereby reducing the area required to be occupied by the driving unit and improving the utilization rate of the substrate required for preparation.

[0383] FIG43 is a flow chart of a method for preparing a light-emitting component according to an embodiment of the present application. Referring to FIG43 , the method includes:

[0384] Step S101: Acquire a first target structure.

[0385] In the embodiment of the present application, the first target structure includes a first substrate 300 and a light emitting unit 100 located on the first substrate 300. The light emitting unit 100 includes a first electrode 101, a second electrode 102, and a light emitting portion 103 electrically connected to the first electrode 101 and the second electrode 102 respectively.

[0386] Step S102: Acquire a second target structure.

[0387] In the embodiment of the present application, the second target structure includes a drive unit 200, which includes a first drive circuit layer 201 and a second drive circuit layer 202. The first drive circuit layer 201 includes a third electrode 2011 and a fourth electrode 2012. The third electrode 2011 and the fourth electrode 2012 are both located on a side of the first drive circuit layer 201 away from the second drive circuit layer 202.

[0388] Optionally, taking the structure shown in FIG8 as an example, referring to FIG44 , the process of obtaining the second target structure includes:

[0389] Step S1021a: Obtain an intermediate substrate.

[0390] Optionally, the intermediate substrate 203 may be glass.

[0391] Step S1022a: forming a first driving circuit layer on the first surface of the intermediate substrate.

[0392] In the embodiment of the present application, the process of forming the first driving circuit layer 201 (low-temperature polysilicon driving circuit layer) includes:

[0393] 1. A plurality of second target connection structures A2 (first connection structures 2013 ) are fabricated on the first surface 203 a of the intermediate substrate 203 by photolithography. The second target connection structures A2 serve as a portion connecting the second driving circuit layer 202 and the first driving circuit layer 201 .

[0394] 2. A first passivation layer m2 is applied to the side of the plurality of first connection structures 2013 away from the intermediate substrate 203. The first passivation layer m2 has via holes, which can serve as via holes for connecting the first connection pattern m31 in the subsequent first connection layer m3 to the first connection structure 2013;

[0395] 3. A first connection layer m3 is formed on a side of the first passivation layer m2 away from the intermediate substrate 203. The first connection layer m3 includes a plurality of first connection patterns m31 corresponding to the plurality of first connection structures 2013. Each first connection pattern m31 is connected to a first connection structure 2013 through a via in the first passivation layer m2.

[0396] 4. A first barrier layer m13 and a first buffer layer m4 are formed on a side of the first wiring layer m3 away from the intermediate substrate 203 .

[0397] 5. A polysilicon layer m5 is formed on the side of the first buffer layer m4 away from the intermediate substrate 203 through a photolithography process. The polysilicon layer m5 can be used as a semiconductor layer of a low-temperature polysilicon thin film transistor.

[0398] 6. A first gate insulating layer m6 is coated on the side of the polysilicon layer m5 away from the intermediate substrate 203. The first gate insulating layer m6 has multiple vias, which can serve as vias for connecting the first gate connection pattern m72 in the subsequent first gate layer m7 with the first connection pattern m31.

[0399] 7. A first gate layer m7 is formed by photolithography on the side of the first gate insulating layer m6 away from the intermediate substrate 203. The gate pattern in the first gate layer m7 may be a mask layer for doping low-temperature polysilicon thin film transistors.

[0400] 8. Coat a third gate insulating layer m11 on the side of the first gate layer m7 away from the intermediate substrate 203 .

[0401] 9. A third gate layer m12 is formed on the side of the third gate insulating layer m11 away from the intermediate substrate 203 through a photolithography process. The third gate layer m12 can be used as a connection line of the transistor to reduce the space area.

[0402] 10. A first interlayer dielectric layer m8 is formed on a side of the third gate layer m12 away from the intermediate substrate 203. The first interlayer dielectric layer m8 has a via hole, which can serve as a via hole connecting the pattern in the subsequent first source and drain layer m9 to the pattern in the first gate layer m7 or the third gate layer m12.

[0403] 11. A first source-drain electrode layer m9 is formed on the side of the first interlayer dielectric layer m8 away from the intermediate substrate 203 by a photolithography process. The first source-drain electrode layer m9 includes a source and a drain of a low-temperature polysilicon thin film transistor.

[0404] 12. A first flat layer m10 is formed on the side of the first source / drain electrode layer m9 away from the intermediate substrate 203 . The first flat layer m10 plays a flat role for subsequent bonding with the light emitting unit 100 .

[0405] 13. A third electrode 2011 and a fourth electrode 2012 are formed on a side of the first planar layer m10 away from the intermediate substrate 203 by a photolithography process. The third electrode 2011 and the fourth electrode 2012 are used for subsequent eutectic bonding with the light emitting unit 100 .

[0406] 14. A photoresist is deposited on the entire surface of the third electrode 2011 and the fourth electrode 2012 away from the intermediate substrate 203 to protect the third electrode 2011 and the fourth electrode 2012 .

[0407] Step S1023a: forming a plurality of through holes on the second surface of the intermediate substrate, each through hole being used to expose a corresponding second target connection structure.

[0408] In an embodiment of the present application, the entire structure formed before step S1023a is first placed upside down, and then a plurality of through holes 203c are formed by etching on the second surface 203b of the intermediate substrate 203. The through holes 203c can be used for subsequent connection between the first target connection structure A1 and the second target connection structure A2.

[0409] Step S1024a: forming a second driving circuit layer on the second surface of the intermediate substrate.

[0410] In the embodiment of the present application, the process of forming the second driving circuit layer 202 (oxide driving circuit layer) includes:

[0411] 1. A plurality of first target connection structures A1 (second connection structures 2021) are formed on the second surface 203b of the intermediate substrate 203 by photolithography. Each first target connection structure A1 can be connected to a second target connection structure A2 exposed by a via hole in the intermediate substrate 203.

[0412] 2. A second passivation layer n2 is coated on the side of the plurality of first target connection structures A1 away from the intermediate substrate 203. The second passivation layer n2 has via holes, which can be used as via holes to connect the second connection pattern n31 in the second connection layer n3 to the second connection structure 2021.

[0413] 3. A second wiring layer n3 is formed on the side of the second passivation layer n2 away from the intermediate substrate 203. The second wiring layer n3 includes a plurality of second wiring patterns n31, each of which is connected to a second connection structure 2021 via a via hole in the second passivation layer n2.

[0414] 4. A second barrier layer n12 is formed by coating on the side of the second wiring layer n3 away from the intermediate substrate 203 .

[0415] 5. A fourth gate layer n11 is formed on the side of the second barrier layer n12 away from the intermediate substrate 203 by a photolithography process. The fourth gate layer n11 may include a bottom gate of an oxide thin film transistor and serve as a light shield.

[0416] 6. A second buffer layer n4 is formed by coating on a side of the fourth gate layer n11 away from the intermediate substrate 203 .

[0417] 7. An oxide layer n5 is formed on the side of the second buffer layer n4 away from the intermediate substrate 203 by a photolithography process. The oxide layer n5 can serve as a semiconductor layer of an oxide transistor.

[0418] 8. A second gate insulating layer n6 is formed by coating on the side of the oxide layer n5 away from the intermediate substrate 203. The second gate insulating layer n6 has a via hole, which serves as a via hole for connecting the subsequent second gate layer n7 and the second wiring layer n3.

[0419] 9. A second gate layer n7 is formed on the side of the second gate insulating layer n6 away from the intermediate substrate 203 by photolithography. The gate pattern in the second gate layer n7 serves as a mask layer for doping the oxide thin film transistor. For example, the oxide layer n5 is doped using the gate pattern for self-alignment.

[0420] 10. A second interlayer dielectric layer n8 is formed on the side of the second gate layer n7 away from the intermediate substrate 203. The second interlayer dielectric layer n8 has via holes, which serve as via holes connecting the patterns in the subsequent second source and drain layer n9 with the patterns in the second gate layer n7.

[0421] 11. A second source-drain electrode layer n9 is formed on a side of the second interlayer dielectric layer n8 away from the intermediate substrate 203 by a photolithography process. The second source-drain electrode layer n9 includes a source electrode and a drain electrode of the oxide thin film transistor.

[0422] 12. A second flat layer n10 is formed on the side of the second source / drain layer n9 away from the intermediate substrate 203 . The second flat layer n10 plays a flat role for subsequent bonding with the driving backplane.

[0423] 13. A plurality of pins 2022 are formed on the side of the second planar layer n10 away from the intermediate substrate 203 by photolithography. The pins 2022 are used for subsequent die bonding with the driver backplane. Optionally, the thickness of the pins 2022 can range from 1.5 μm (micrometers) to 1.8 μm.

[0424] In the embodiment of the present application, since the preparation temperature of the low-temperature polysilicon driving circuit layer M is higher than the preparation temperature of the oxide driving circuit layer N, the low-temperature polysilicon driving circuit layer M can be first formed on one side of the intermediate substrate 203, and then the oxide driving circuit layer N can be formed on the other side of the intermediate substrate 203. In this way, the high temperature caused by first forming the oxide driving circuit layer N and then forming the low-temperature polysilicon driving circuit layer M can be avoided from affecting the performance of the already prepared oxide driving circuit layer N.

[0425] Furthermore, the present embodiment uses an example in which the first driver circuit layer is a low-temperature polysilicon driver circuit layer and the second driver circuit layer is an oxide driver circuit layer. That is, the low-temperature polysilicon driver circuit layer is closer to the light-emitting unit than the oxide driver circuit layer. This facilitates the connection between the transistors in the low-temperature polysilicon driver circuit layer and the light-emitting unit. Of course, the first driver circuit layer may also be an oxide driver circuit layer, and the second driver circuit layer may also be a low-temperature polysilicon driver circuit layer; this embodiment of the present application does not limit this.

[0426] Optionally, taking the structure shown in FIG20 as an example, referring to FIG45 , the process of obtaining the second target structure includes:

[0427] Step S1021b: forming a first driving circuit layer on the first temporary substrate.

[0428] The first driving circuit 201 includes a second target connection structure A2, which may be the first connection structure 2013. The process of forming the first driving circuit layer (oxide driving circuit layer) includes:

[0429] 1. A sacrificial layer (DBL) is formed on one side of the first temporary substrate. The first temporary substrate needs to be removed later, so the sacrificial layer can be designed to facilitate the subsequent removal of the first temporary substrate by laser lift-off.

[0430] 2. A plurality of first connection structures 2013 are formed on a side of the sacrificial layer away from the first temporary substrate by a photolithography process. The first connection structures 2013 are used for subsequent bonding with the low-temperature polysilicon driving circuit layer.

[0431] 3. A second passivation layer n2 is coated on the side of the plurality of second target connection structures A2 away from the first temporary substrate. The second passivation layer n2 has via holes, which can be used as via holes to connect the second connection pattern n31 in the second connection layer n3 to the first connection structure 2013.

[0432] 4. A second wiring layer n3 is formed on the side of the second passivation layer n2 away from the first temporary substrate. The second wiring layer n3 includes a plurality of second wiring patterns n31, each of which is connected to a first connection structure 2013 via a via hole in the second passivation layer n2.

[0433] 5. A second barrier layer n12 and a second buffer layer n4 are formed by coating on a side of the second connection layer n3 away from the first temporary substrate.

[0434] 6. An oxide layer n5 is formed on the side of the second buffer layer n4 away from the intermediate substrate 203 by a photolithography process. The oxide layer n5 can serve as a semiconductor layer of an oxide transistor.

[0435] 7. A second gate insulating layer n6 is formed on the side of the oxide layer n5 away from the first temporary substrate. The second gate insulating layer n6 has a via hole, which serves as a via hole for connecting the subsequent second gate layer n7 and the second wiring layer n3.

[0436] 8. A second gate layer n7 is formed on the side of the second gate insulating layer n6 away from the first temporary substrate by photolithography. The second gate layer n7 serves as a mask layer for doping the oxide thin film transistor.

[0437] 9. A second interlayer dielectric layer n8 is formed on the side of the second gate layer n7 away from the first temporary substrate. The second interlayer dielectric layer n8 has a via hole, which serves as a via hole connecting the pattern in the subsequent second source and drain layer n9 with the pattern in the second gate layer n7.

[0438] 10. A second source-drain electrode layer n9 is formed on the side of the second interlayer dielectric layer n8 away from the first temporary substrate by a photolithography process. The second source-drain electrode layer n9 includes a source electrode and a drain electrode of the oxide thin film transistor.

[0439] 11. A second flat layer n10 is formed on the side of the second source / drain electrode layer n9 away from the first temporary substrate. The second flat layer n10 plays a flat role for subsequent bonding with the light emitting unit 100.

[0440] 12. A third electrode 2011 and a fourth electrode 2012 are formed on the side of the second planar layer n10 away from the first temporary substrate by photolithography. The third electrode 2011 and the fourth electrode 2012 are used for subsequent eutectic bonding with the light emitting unit 100.

[0441] Step S1022b: forming a second driving circuit layer on the second temporary substrate.

[0442] In the embodiment of the present application, the second driving circuit layer 202 may include a plurality of first target connection structures A1, and the first target connection structure A1 may be a second connection structure 2021. The process of forming the second driving circuit layer 202 (low-temperature polysilicon driving circuit layer) includes:

[0443] 1. A sacrificial layer (DBL) is formed on one side of the second temporary substrate. The second temporary substrate needs to be removed later, so the sacrificial layer can be designed to facilitate the subsequent removal of the second temporary substrate by laser lift-off.

[0444] 2. A plurality of second connection structures 2021 are formed on a side of the sacrificial layer away from the second temporary substrate by a photolithography process. The second connection structures 2021 are used for subsequent bonding to the oxide driving circuit layer N.

[0445] 3. A first passivation layer m2 is formed on the side of the plurality of second connection structures 2021 facing away from the second temporary substrate. This first passivation layer m2 can have a flat surface to facilitate subsequent bonding with the oxide drive circuit layer N. The first passivation layer m2 has vias that can serve as vias for connecting the first wiring pattern m31 in the first wiring layer to the second connection structures 2021.

[0446] 3. A first connection layer m3 is formed on the side of the first passivation layer m2 away from the second temporary substrate using a photolithography process. The first connection layer m3 includes a plurality of first connection patterns m31 corresponding to the plurality of first connection structures 2013. Each first connection pattern m31 is connected to the second connection structure 2021 through a via in the first passivation layer m2.

[0447] 4. A first barrier layer m13 and a first buffer layer m4 are formed on the side of the first wiring layer m3 away from the second temporary substrate. The first barrier layer m13 and the first buffer layer m4 can play a protective role in the subsequent preparation of low-temperature polysilicon thin film transistors.

[0448] 5. A polysilicon layer m5 is formed on the side of the first buffer layer m4 away from the second temporary substrate. The polysilicon layer m5 can serve as a semiconductor layer of a low-temperature polysilicon thin film transistor.

[0449] 6. A first gate insulating layer m6 is coated on the side of the polysilicon layer m5 away from the intermediate substrate 203. The first gate insulating layer m6 has multiple vias, which can serve as vias for connecting the first gate connection pattern m72 in the subsequent first gate layer m7 with the first connection pattern m31.

[0450] 7. A first gate layer m7 is formed on the side of the first gate insulating layer m6 away from the intermediate substrate 203 using a photolithography process. The gate pattern in the first gate layer m7 can be a mask layer for doping a low-temperature polysilicon thin-film transistor. For example, the polysilicon layer m5 is doped using the gate pattern for self-alignment.

[0451] 8. A first interlayer dielectric layer m8 is formed on the side of the first gate layer m7 away from the second temporary substrate. The first interlayer dielectric layer m8 has a via hole, which can be used as a via hole to connect the pattern in the subsequent first source and drain layer m9 with the pattern in the first gate layer m7.

[0452] 9. Form a first source-drain electrode layer m9 on the side of the first interlayer dielectric layer m8 away from the second temporary substrate by photolithography. The first source-drain electrode layer m9 includes the source and drain of the low-temperature polysilicon thin film transistor.

[0453] 10. A first planarization layer m10 is formed on the side of the first source / drain layer m9 facing away from the second temporary substrate. This first planarization layer m10 can be made of polyimide (PI) and provides support for the film layer after the second temporary substrate is removed. The first planarization layer m10 has vias for connecting the pins 2022 to the second driver circuit layer 202.

[0454] 11. A plurality of pins 2022 are formed on the side of the first planar layer m10 away from the second temporary substrate by photolithography. The pins 2022 are used for subsequent die bonding with the driver backplane. Optionally, the thickness of the pins 2022 can range from 1.5 μm to 2 μm.

[0455] Step S1023b: removing the first temporary substrate to expose a plurality of second target connection structures.

[0456] In the embodiment of the present application, before bonding the first driving circuit layer 201 and the second driving circuit layer 202 together, a laser lift-off process may be used to remove the first temporary substrate, thereby exposing a plurality of second target connection structures.

[0457] Optionally, before removing the first temporary substrate, a cutting process may be used to cut the entire structure into 4-inch circular structures for subsequent bonding with the second driving circuit layer 202 .

[0458] Step S1024b: removing the second temporary substrate to expose a plurality of first target connection structures.

[0459] In the embodiment of the present application, before bonding the first driving circuit layer 201 and the second driving circuit layer 202 together, a laser lift-off process may be used to remove the second temporary substrate, thereby exposing the plurality of first target connection structures A1.

[0460] Optionally, before removing the second temporary substrate, the entire structure may be cut into 4-inch circular structures using a cutting process so as to facilitate subsequent bonding with the first driving circuit layer 201 .

[0461] Step S1025b: electrically connecting the plurality of first target connection structures and the corresponding plurality of second target connection structures.

[0462] In the embodiment of the present application, an electroless plating process can be used to plate tin (Sn) on the surface of the first target connection structure A1 or the second target connection structure A2 to form an intermediate electrode 204, thereby electrically connecting the first target connection structure A1 (the second connection structure 2021) and the second target connection structure A2 (the first connection structure 2013) via the intermediate electrode 204. After the plurality of first connection structures 2013 and the corresponding plurality of second connection structures 2021 are electrically connected, the first drive circuit layer 201 and the second drive circuit layer 202 can be bonded. Optionally, the height of the intermediate electrode 204 ranges from 1.0 μm to 1.5 μm.

[0463] In the embodiment of the present application, since the low-temperature polysilicon driving circuit layer M and the oxide driving circuit layer N are fabricated on different temporary substrates, the fabrication of the two driving circuit layers does not affect each other. Therefore, the aforementioned steps S1021b and S1022b can be performed simultaneously, with step S1023b being performed after step S1021b, and step S1024b being performed after step S1022b, thus saving fabrication time.

[0464] Furthermore, the present embodiment uses an example in which the first drive circuit layer is an oxide drive circuit layer and the second drive circuit layer is a low-temperature polysilicon drive circuit layer. That is, the oxide drive circuit layer is closer to the light-emitting unit than the low-temperature polysilicon drive circuit layer. This facilitates the connection between the transistors in the oxide drive circuit layer and the light-emitting unit. Of course, the first drive circuit layer can also be a low-temperature polysilicon drive circuit layer, and the second drive circuit layer can also be an oxide drive circuit layer. This embodiment of the present application does not limit this.

[0465] Step S103: bonding the first target structure and the second target structure.

[0466] In an embodiment of the present application, before bonding, for the first solution with an intermediate substrate 203 in the above-mentioned step S102, it is necessary to remove the entire surface of the photoresist formed on the side of the third electrode 2011 and the fourth electrode 2012 in the second target structure away from the intermediate substrate 203, and then cut the first target structure and the second target structure into structures of the same shape, for example, both are cut into 4-inch circles.

[0467] 46 and 47 , the first target structure and the second target structure can be bonded together. Furthermore, after the bonding, the first electrode 101 of the light-emitting unit 100 and the third electrode 2011 of the driving unit 200 can be electrically connected, and the second electrode 102 of the light-emitting unit 100 and the fourth electrode 2012 of the driving unit 200 can be electrically connected.

[0468] Because the third electrode 2011 and the fourth electrode 2012 included in the driving unit 200 are closer to the first driving circuit layer 201 than to the second driving circuit layer 202, after bonding, the first driving circuit layer 201 can be closer to the light-emitting unit 100 than the second driving circuit layer 202. In other words, the first driving circuit layer 201 is located between the light-emitting unit 100 and the second driving circuit layer 202.

[0469] Optionally, for the first solution with an intermediate substrate 203 in step S102 above, after the light-emitting unit 100 and the driving unit 200 are bonded together, the first substrate 300 in the first target structure and the intermediate substrate 203 in the second target structure can be cut twice (e.g., laser hidden cutting) to obtain multiple independent light-emitting components. For the second solution with an intermediate electrode 204 bonded together in step S102 above, after the light-emitting unit 100 and the driving unit 200 are bonded together, the first substrate 300 in the first target structure can be cut (e.g., laser hidden cutting) to obtain multiple independent light-emitting components.

[0470] In the embodiment of the present application, since the pins 2022 can be formed during the process of forming the first drive circuit layer 201 or the second drive circuit layer 202, without the need for chemical plating in a special solution, the problem of liquid seepage is avoided. Furthermore, there is no need to provide a dam layer to prevent liquid seepage, thereby improving cost advantages.

[0471] Moreover, for the solution of preparing the first driving circuit layer 201 and the second driving circuit layer 202 on both surfaces of the intermediate substrate, the LLO process is not required, and the intermediate substrate itself is a rigid material (such as glass), and there will be no curling problem, which can ensure the reliability of subsequent die bonding.

[0472] In summary, an embodiment of the present application provides a method for preparing a light-emitting component, and the light-emitting component prepared by the method includes a light-emitting unit and a driving unit. The first electrode in the light-emitting unit is electrically connected to the third electrode in the driving unit, and the second electrode in the light-emitting unit is electrically connected to the fourth electrode in the driving unit. As a result, the driving unit can provide a driving signal to the light-emitting unit, and the light-emitting unit can emit light under the drive of the driving unit. In addition, the driving unit includes a first driving circuit layer including a first type of transistor and a second driving circuit layer including a second type of transistor, which are stacked, thereby reducing the area required to be occupied by the driving unit and improving the utilization rate of the substrate required for preparation.

[0473] Figure 48 is a schematic diagram of the structure of a display substrate provided in an embodiment of the present application. Figure 49 is a schematic diagram of the structure of another display substrate provided in an embodiment of the present application. Referring to Figures 48 and 49, the display substrate includes a driver backplane 111 and the light-emitting assembly 000 provided in the above embodiment. Driver backplane 111 includes a driver substrate 1111 and solder pads located on driver substrate 1111. The solder pads include a plurality of conductive pads 1112. Conductive pads 1112 are used to electrically connect to pins 2022 in light-emitting assembly 000.

[0474] 50 , multiple light-emitting components 000 are located in the display area a of the display substrate, and the multiple light-emitting components 000 are arranged in an array. The driving backplane 111 is used to provide a driving signal to the driving unit 200 via the multiple pins 2022 in the light-emitting components 000, so that the driving unit 200 drives the light-emitting unit 100 to emit light.

[0475] Furthermore, the multiple light-emitting assemblies 000 in the display substrate are independently arranged, that is, the light-emitting assemblies 000 are independent of each other, so that individual light-emitting assemblies can be repaired and replaced. Optionally, the light-emitting assemblies 000 can be independent chip structures, with different light-emitting assemblies 000 spaced apart. For example, different light-emitting assemblies 000 are isolated by air.

[0476] Optionally, the display substrate may be a display screen in a mobile phone, a laptop computer, or a flat-panel computer, or an outdoor advertising screen.

[0477] Since the display substrate can have substantially the same technical effects as the light-emitting assembly described in the previous embodiment, the technical effects of the display substrate will not be repeatedly described here for the purpose of brevity.

[0478] FIG51 is a flow chart of a method for preparing a display substrate provided in an embodiment of the present application. The method can be applied to a solution for preparing a light-emitting component 000 including an intermediate substrate 203. Referring to FIG51 , the method includes:

[0479] Step S201: Obtain a light-emitting component and a driving backplane.

[0480] In the embodiment of the present application, the light emitting assembly may include a light emitting unit 100 and a driving unit 200. The driving unit 200 includes a plurality of pins 2022 on a side away from the light emitting unit 100. The driving backplane includes a driving substrate and a pad on the driving substrate, the pad including a plurality of conductive pads.

[0481] Step S202: Die-bonding the light-emitting component and the driving backplane.

[0482] In an embodiment of the present application, the plurality of pins 2022 of the driving unit 200 of the light-emitting component and the plurality of conductive pads in the driving backplane can be die-bonded to form a Micro LED direct display product and obtain a display substrate.

[0483] Since the method for preparing the display substrate can have substantially the same technical effects as the light-emitting component described in the previous embodiment, the technical effects of the method for preparing the display substrate will not be repeatedly described here for the purpose of brevity.

[0484] FIG52 is a flow chart of another method for preparing a display substrate according to an embodiment of the present application. This method can be applied to a solution in which the first drive circuit layer 201 and the second drive circuit layer 202 of the drive unit 200 in the light-emitting assembly 000 are bonded together using an intermediate electrode 204. Referring to FIG52 , the method includes:

[0485] Step S301: Acquire a light-emitting unit, a first driving circuit layer, a second driving circuit layer, and a driving backplane.

[0486] In the embodiment of the present application, the light-emitting unit 100 includes: a first electrode 101, a second electrode 102, and a light-emitting portion 103 electrically connected to the first electrode 101 and the second electrode 102. The first driving circuit layer 201 includes a third electrode 2011, a fourth electrode 2012, and a plurality of second connecting structures 2021. The second driving circuit layer 202 includes a plurality of first connecting structures 2013 and a plurality of pins 2022.

[0487] Step S302: bonding the first driving circuit layer and the second driving circuit layer.

[0488] In an embodiment of the present application, a chemical plating process can be used to plate tin (Sn) on the surface of the first connecting structure 2013 or the second connecting structure 2021 to form an intermediate electrode 204, thereby electrically connecting multiple first connecting structures 2013 and corresponding multiple second connecting structures 2021, and setting the third electrode 2011 and the fourth electrode 2012 away from the second driving circuit layer 202.

[0489] Step S303: bonding the light-emitting unit and the first driving circuit layer.

[0490] In an embodiment of the present application, the light-emitting unit 100 and the first driving circuit layer 201 can be bonded and connected first, thereby electrically connecting the first electrode 101 of the light-emitting unit 100 and the third electrode 2011 of the first driving circuit layer 201, and electrically connecting the second electrode 102 of the light-emitting unit 100 and the fourth electrode 2012 of the first driving circuit layer 201.

[0491] Step S304: bonding the driving backplane and the plurality of pins of the second driving circuit layer.

[0492] In the embodiment of the present application, the conductive pads in the driving backplane and the plurality of pins 2022 of the second driving circuit layer 202 may be bonded and connected to obtain a display substrate.

[0493] It should be noted that the order of the steps in the method for preparing a display substrate provided in the embodiments of the present application can be adjusted appropriately. For example, the order of executing steps S302 to S304 can be arbitrarily combined. Any method that can be easily conceived by a person skilled in the art within the scope of the present disclosure is intended to be covered by the scope of protection of the present disclosure, and therefore will not be described in detail.

[0494] The first method is to prepare in the order of step S302, step S303 and step S304. Referring to FIG53 , the specific process may include:

[0495] 1. Prepare a second driver circuit layer 202 (using a low-temperature polysilicon driver circuit layer as an example) formed on a second temporary substrate and temporarily bond the second driver circuit layer 202 to the first cover plate using hot melt adhesive. The first cover plate is located on the side of the second temporary substrate away from the plurality of pins 2022. The size and shape of the first cover plate can match those of the second driver circuit layer 202. For example, the first cover plate can be a 4-inch circular glass cover plate, and the second driver circuit layer 202 can be a 4-inch circular circuit layer.

[0496] 2. The second temporary substrate is peeled off from one side of the second driving circuit layer 202 using a laser lift-off process to expose the plurality of second connection structures 2021 .

[0497] 3. Tin (Sn) is plated on the surfaces of the plurality of second connection structures 2021 using a chemical plating process to form a plurality of intermediate electrodes 204 .

[0498] 4. Temporarily bond the first drive circuit layer 201 (using an oxide drive circuit layer as an example) to the second cover plate using hot melt adhesive. The second cover plate is located on the side of the third electrode 2011 and the fourth electrode 2012 away from the first temporary substrate. The size and shape of the second cover plate can match those of the first drive circuit layer 201. For example, the second cover plate can be a 4-inch circular glass cover plate, and the first drive circuit layer 201 can be a 4-inch circular circuit layer.

[0499] 5. Use a laser lift-off process to peel off the first temporary substrate from one side of the first driving circuit layer 201 to expose the multiple first connection structures 2013.

[0500] 6. Eutectic bonding is performed between the first driving circuit layer 201 and the second driving circuit layer 202 using the intermediate electrode 204 .

[0501] 7. Use a laser lift-off process to peel the second cover plate from the first driving circuit layer 201 to expose the third electrode 2011 and the fourth electrode 2012.

[0502] 8. Perform eutectic bonding on the first driving circuit layer 201 and the light emitting unit 100 to obtain the entire structure after the driving unit 200 and the light emitting unit 100 are bonded.

[0503] 9. Use a laser lift-off process to peel off the first cover plate from one side of the second driving circuit layer 202 to expose a plurality of pins 2022 for die bonding.

[0504] 10. Perform a laser blind cutting process on the first substrate 300 on one side of the light-emitting unit 100 to obtain multiple independent light-emitting components. In other words, through the double eutectic bonding method in steps 4 and 8 above, the light-emitting unit (LED chip) and the driver unit (LTPS substrate and oxide substrate) are packaged into a single chip to form a driver-packaged active LED chip.

[0505] 11. The light-emitting component is die-bonded onto the driving backplane, so that the multiple pins 2022 in the light-emitting component and the multiple conductive pads in the driving backplane are bonded, thereby obtaining a Micro LED direct display product and a display substrate.

[0506] The second method is to prepare in the order of step S303, step S302 and step S304. Referring to FIG54 , the specific process may include:

[0507] 1. Eutectic bonding is performed on the light-emitting unit 100 and the first drive circuit layer 201 (using the oxide drive circuit layer N as an example), so that the first electrode 101 of the light-emitting unit 100 is connected to the third electrode 2011 of the first drive circuit layer 201, and the second electrode 102 of the light-emitting unit 100 is connected to the fourth electrode 2012 of the first drive circuit layer 201. The shape and size of the light-emitting unit 100 can match the shape and size of the first drive circuit layer 201. For example, the light-emitting unit 100 can be a 4-inch circular light-emitting unit 100, and the first drive circuit layer 201 can be a 4-inch circular circuit layer.

[0508] 2. The first temporary substrate on one side of the first driving circuit layer 201 is peeled off using a laser lift-off process to expose a plurality of second target connection structures A2.

[0509] 3. Temporarily bond the second driver circuit layer 202 (using a low-temperature polysilicon driver circuit layer as an example) to the first cover plate using hot melt adhesive. The first cover plate is located on the side of the second temporary substrate away from the plurality of pins 2022. The size and shape of the first cover plate can match the size and shape of the second driver circuit layer 202. For example, the first cover plate can be a 4-inch circular glass cover plate, and the second driver circuit layer 202 can be a 4-inch circular circuit layer.

[0510] 4. The second temporary substrate on one side of the second driving circuit layer 202 is peeled off using a laser lift-off process to expose a plurality of first target connection structures A1.

[0511] 5. A plurality of intermediate electrodes 204 are formed by plating tin (Sn) on the surfaces of the plurality of first target connection structures A1 using a chemical plating process.

[0512] 6. Eutectic bonding is performed between the first driving circuit layer 201 and the second driving circuit layer 202 using the intermediate electrode 204 .

[0513] 7. Use a laser lift-off process to peel off the first cover from one side of the second driving circuit layer 202 to expose the multiple pins 2022.

[0514] 8. Perform a laser blind cutting process on the first substrate 300 on one side of the light-emitting unit 100 to obtain multiple independent light-emitting components. In other words, through the double eutectic bonding method in steps 3 and 6 above, the light-emitting unit (LED chip) and the driver unit (LTPS substrate and oxide substrate) are packaged into a single chip to form a driver-packaged active LED chip.

[0515] 9. Bond the light-emitting component to the driver backplane, so that the multiple pins 2022 in the light-emitting component and the multiple conductive pads in the driver backplane are bonded, thereby obtaining a Micro LED direct display product and a display substrate.

[0516] The third method is to prepare in the order of step S304, step S303, and step S302. Referring to FIG. 55 , the specific process may include:

[0517] 1. The second driving circuit layer 202 (taking the low-temperature polysilicon driving circuit layer as an example) is die-bonded onto the driving backplane, so that the plurality of pins 2022 of the second driving circuit layer 202 are bonded to the plurality of conductive pads in the driving backplane.

[0518] 2. The second temporary substrate is peeled off from one side of the second driving circuit layer 202 using a laser lift-off process to expose a plurality of first target connection structures A1.

[0519] 3. Eutectic bonding is performed on the light-emitting unit 100 and the first drive circuit layer 201 (using the oxide drive circuit layer N as an example), so that the first electrode 101 of the light-emitting unit 100 is connected to the third electrode 2011 of the first drive circuit layer 201, and the second electrode 102 of the light-emitting unit 100 is connected to the fourth electrode 2012 of the first drive circuit layer 201. The shape and size of the light-emitting unit 100 can match the shape and size of the first drive circuit layer 201. For example, the light-emitting unit 100 can be a 4-inch circular light-emitting unit 100, and the first drive circuit layer 201 can be a 4-inch circular circuit layer.

[0520] 4. Use a laser lift-off process to peel off the first temporary substrate from one side of the first driving circuit layer 201 to expose a plurality of second target connection structures A2.

[0521] 5. The first substrate 300 on one side of the light emitting unit 100 is subjected to a laser stealth cutting process to obtain a plurality of independent first driving circuit layers 201 .

[0522] 6. The packaged chip formed by bonding the first drive circuit layer 201 and the light-emitting unit 100 is die-bonded to the drive backplane bonded with the second drive circuit layer 202 to form a Micro LED direct display product and a display substrate. During die bonding, tin plating can be used to form the intermediate electrode 204 through a chemical plating process.

[0523] Since the method for preparing the display substrate can have substantially the same technical effects as the light-emitting component described in the previous embodiment, the technical effects of the method for preparing the display substrate will not be repeatedly described here for the purpose of brevity.

[0524] The terms used in the embodiments of this application are only used to explain the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the common meaning understood by people with ordinary skills in the field to which this application belongs.

[0525] The terms used in the embodiments of this application are intended solely to illustrate the embodiments of this application and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in the embodiments of this application should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this application belongs. The terms "first," "second," "third," and similar terms used in this patent specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish between different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one. Terms such as "include" or "comprising" and similar terms mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used solely to indicate relative positions. When the absolute position of the described objects changes, the relative positions may also change accordingly.

[0526] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A light emitting component, characterized in that: The light emitting component comprises: A light-emitting unit, comprising: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively; a driving unit, the driving unit comprising a first driving circuit layer and a second driving circuit layer stacked together, the first driving circuit layer being located between the light-emitting unit and the second driving circuit layer; the first driving circuit layer comprising a third electrode and a fourth electrode, the third electrode and the fourth electrode being both located on a side of the first driving circuit layer facing the light-emitting unit, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode; The first driving circuit layer includes a first type of transistors, the second driving circuit layer includes a second type of transistors, and the first type of transistors and the second type of transistors are of different types.

2. The light emitting assembly according to claim 1, characterized in that: The first type of transistor is an oxide thin film transistor, and the second type of transistor is a low temperature polysilicon thin film transistor; or The first type of transistor is a low-temperature polysilicon thin film transistor, and the second type of transistor is an oxide thin film transistor.

3. The light emitting assembly according to claim 1, wherein: The transistors in the first driving circuit layer are only first-type transistors, and the transistors in the second driving circuit layer are only second-type transistors.

4. The light emitting assembly according to claim 1, wherein: The driving unit includes an intermediate substrate having a first surface and a second surface opposite to each other, the first driving circuit layer is located on the first surface, and the second driving circuit layer is located on the second surface; The intermediate substrate has a plurality of through holes, the first driving circuit layer includes a plurality of first connection structures corresponding to the plurality of through holes, the second driving circuit layer includes a plurality of second connection structures corresponding to the plurality of through holes, and each of the first connection structures is electrically connected to the corresponding second connection structure through the corresponding through hole; The first type of transistor is electrically connected to the second type of transistor through the first connection structure and the second connection structure.

5. The light emitting assembly according to claim 4, characterized in that: The material of the intermediate substrate is glass or polyimide; At least a portion of the first connection structure is located in the corresponding through-hole, and the second connection structure is located on a side of the intermediate substrate away from the first driving circuit layer; a surface of the portion of the first connection structure located in the through-hole close to the second driving circuit layer contacts a surface of the corresponding second connection structure close to the intermediate substrate; or At least a portion of the second connection structure is located in the corresponding through-hole, and the first connection structure is located on a side of the intermediate substrate away from the second driving circuit layer; a surface of the portion of the second connection structure located in the through-hole close to the first driving circuit layer contacts the surface of the corresponding first connection structure close to the intermediate substrate; or The driving unit further includes a conductive material located in the through hole. The first connecting structure and the corresponding second connecting structure are respectively located on both sides of the conductive material in the corresponding through hole and are both in contact with the conductive material.

6. The light emitting assembly according to claim 4, characterized in that: A first portion of a first target connection structure among the first connection structure and the second connection structure is located inside the through hole, and a second target connection structure among the first connection structure and the second connection structure is located outside the through hole; The second portion of the first target connection structure is located on a side of the intermediate substrate away from the second target connection structure, and a distance between a surface of the intermediate substrate away from the second target connection structure and a surface of the intermediate substrate away from the second target connection structure is greater than or equal to a thickness of the intermediate substrate; The first target connection structure is one of the first connection structure and the second connection structure, and the second target connection structure is the other of the first connection structure and the second connection structure.

7. The light emitting assembly according to claim 4, characterized in that: A portion of the multiple first connection structures is away from the surface of the second driving circuit layer and is used to be electrically connected to the first type of transistor, another portion of the multiple first connection structures is away from the surface of the second driving circuit layer and is used to be electrically connected to the first electrode in the light-emitting unit, and another portion of the multiple first connection structures is away from the surface of the second driving circuit layer and is used to be electrically connected to the second electrode in the light-emitting unit through the first type of transistor.

8. The light emitting assembly according to claim 4, characterized in that: A portion of the multiple second connection structures is away from the surface of the first driving circuit layer and is used to electrically connect to the second type of transistor, and another portion of the multiple second connection structures is away from the surface of the first driving circuit layer and is used to electrically connect to the driving backplane in the display substrate.

9. The light emitting assembly according to claim 4, characterized in that: The driving circuit layer including a plurality of low-temperature polysilicon thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a first structural layer, a first passivation layer, a first wiring layer, a first buffer layer, a polysilicon layer, a first gate insulating layer, a first gate layer, a first interlayer dielectric layer, a first source and drain layer, and a first planarization layer stacked in sequence in a direction away from the intermediate substrate; Wherein, the first structural layer includes a plurality of second target connection structures, and the second target connection structure is one of the first connection structure and the second connection structure; The first wiring layer includes a plurality of first wiring patterns corresponding to the plurality of second target connection structures, the first wiring patterns are connected to the corresponding second target connection structures, and some of the plurality of first wiring patterns are connected to the low-temperature polysilicon thin film transistor; The polysilicon layer includes a plurality of polysilicon patterns corresponding to the plurality of low-temperature polysilicon thin film transistors, each of the polysilicon patterns includes a source region, a drain region, and a channel region; The source and the drain of the low-temperature polysilicon thin film transistor are located in the first source-drain layer, the source of the low-temperature polysilicon thin film transistor is connected to the source region, and the drain of the low-temperature polysilicon thin film transistor is connected to the drain region; The first gate layer includes a plurality of first gate patterns corresponding to the plurality of low-temperature polysilicon thin film transistors, and the channel region is an overlapping area of ​​an orthographic projection of the first gate pattern on the intermediate substrate and an orthographic projection of the polysilicon pattern on the intermediate substrate.

10. The light emitting assembly according to claim 4, characterized in that: The driving circuit layer including a plurality of oxide thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a second structural layer, a second passivation layer, a second wiring layer, a second buffer layer, an oxide layer, a second gate insulating layer, a second gate layer, a second interlayer dielectric layer, a second source and drain electrode layer, and a second planarization layer stacked in sequence in a direction away from the intermediate substrate; The second structure layer includes a plurality of first target connection structures, wherein the first target connection structure is the other connection structure of the first connection structure and the second connection structure; The second wiring layer includes a plurality of second wiring patterns corresponding to the plurality of first target connection structures, the second wiring patterns are connected to the corresponding first target connection structures, and some of the plurality of second wiring patterns are connected to the oxide thin film transistor; The oxide layer includes a plurality of oxide patterns corresponding to the plurality of oxide thin film transistors, each of the oxide patterns including a source region, a drain region, and a channel region; The source and the drain of the oxide thin film transistor are located in the second source-drain layer, the source of the oxide thin film transistor is connected to the source region, and the drain of the oxide thin film transistor is connected to the drain region; The second gate layer includes a plurality of second gate patterns corresponding to the plurality of oxide thin film transistors, and the channel region is an overlapping area of ​​an orthographic projection of the second gate pattern on the intermediate substrate and an orthographic projection of the oxide pattern on the intermediate substrate.

11. The light emitting assembly according to claim 1, characterized in that: The first driving circuit layer includes a plurality of first connection structures, the second driving circuit layer includes a plurality of second connection structures, and the first type of transistors and the second type of transistors are electrically connected via the first connection structures and the second connection structures; In which, the first connection structure is close to the surface of the second driving circuit layer and the second connection structure is close to the surface of the first driving circuit layer and is arranged opposite to each other and electrically connected, a part of the first connection structures among the multiple first connection structures are away from the surface of the second driving circuit layer and are used to be electrically connected to the first type of transistors, and a part of the second connection structures among the multiple second connection structures are away from the surface of the first driving circuit layer and are used to be electrically connected to the second type of transistors.

12. The light emitting assembly according to claim 11, wherein: The driving circuit layer including a plurality of low-temperature polysilicon thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a first structural layer, a first passivation layer, a first wiring layer, a first buffer layer, a polysilicon layer, a first gate insulating layer, a first gate layer, a first interlayer dielectric layer, a first source and drain electrode layer, and a first planarization layer stacked in sequence; The first structure layer includes the plurality of first target connection structures, wherein the first target connection structure is one of the first connection structure and the second connection structure; The first wiring layer includes a plurality of first wiring patterns corresponding to the plurality of first target connection structures, the first wiring patterns are connected to the corresponding first target connection structures, and some of the plurality of first wiring patterns are connected to the low-temperature poly-silicon thin film transistor; The polysilicon layer includes a plurality of polysilicon patterns corresponding to the plurality of low-temperature polysilicon thin film transistors, each of the polysilicon patterns includes a source region, a drain region, and a channel region; The source and drain of the low-temperature polysilicon thin film are located in the first source-drain layer, the source of the low-temperature polysilicon thin film is connected to the source region, and the drain of the low-temperature polysilicon thin film is connected to the drain region; The first gate layer includes a plurality of first gate patterns corresponding to the plurality of low-temperature polysilicon thin films, and the channel region is an overlapping area of ​​an orthographic projection of the first gate pattern on the first planar layer and an orthographic projection of the polysilicon pattern on the first planar layer.

13. The light emitting assembly according to claim 11, characterized in that: The driving circuit layer including a plurality of oxide thin film transistors in the first driving circuit layer and the second driving circuit layer includes: a second structure layer, a second passivation layer, a second wiring layer, a second buffer layer, an oxide layer, a second gate insulating layer, a second gate layer, a second interlayer dielectric layer, a second source and drain electrode layer, and a second planarization layer; The second structure layer includes the plurality of second target connection structures, and the first target connection structure is the other connection structure between the first connection structure and the second connection structure; The second wiring layer includes a plurality of second wiring patterns corresponding to the plurality of second target connection structures, the second wiring patterns are connected to the corresponding second target connection structures, and some of the plurality of second wiring patterns are connected to the oxide thin film transistor; The oxide layer includes a plurality of oxide patterns corresponding to the plurality of oxide thin film transistors, each of the oxide patterns including a source region, a drain region, and a channel region; The source and the drain of the oxide thin film transistor are located in the second source-drain layer, the source of the oxide thin film transistor is connected to the source region, and the drain of the oxide thin film transistor is connected to the drain region; The second gate layer includes a plurality of second gate patterns corresponding to the plurality of oxide thin film transistors, and the channel region is a positive projection of the second gate pattern on the second planar layer and the oxide thin film transistors. The overlapping area of ​​the positive projection of the object pattern on the second flat layer.

14. The light emitting assembly according to any one of claims 1 to 13, characterized in that: The driving unit includes multiple pins, which are located on a side of the second driving circuit layer away from the first driving circuit layer. One or more of the multiple pins are electrically connected to the first type of transistors, and one or more of the multiple pins are electrically connected to the second type of transistors.

15. The light emitting assembly according to claim 14, characterized in that: The driving unit includes a first transistor, the first transistor is located in the first driving circuit layer or the second driving circuit layer, and the drain of the first transistor is electrically connected to the fourth electrode; One of the plurality of pins is electrically connected to the third electrode.

16. The light emitting assembly according to claim 15, characterized in that: The driving unit further includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor; The gate of the first transistor is coupled to the first light emitting control signal terminal HF, the first electrode of the first transistor is coupled to the first node J1, and the second electrode of the first transistor is the drain of the first transistor; The gate of the second transistor is coupled to the reset signal terminal RST, the first electrode of the second transistor is coupled to the pull-down power supply terminal VSS, and the second electrode of the second transistor is coupled to the second node J2; The gate of the third transistor is coupled to the gate signal terminal Gate, the first electrode of the third transistor is coupled to the first node J1, and the second electrode of the third transistor is coupled to the second node J2; The gate of the fourth transistor is coupled to the second node J2, the first electrode of the fourth transistor is coupled to the first node J1, and the second electrode of the fourth transistor is coupled to the third node J3; The gate of the fifth transistor is coupled to the gate signal terminal Gate, the first electrode of the fifth transistor is coupled to the data signal terminal DATA, and the second electrode of the fifth transistor is coupled to the third node J3; The gate of the sixth transistor is coupled to the second light emitting control signal terminal EM, the first electrode of the sixth transistor is coupled to the driving power supply terminal VDD, and the second electrode of the sixth transistor is coupled to the third node J3; The gate of the seventh transistor is coupled to the reset signal terminal RST, and the first electrode of the seventh transistor is connected to the reset signal terminal RST. The first electrode of the seventh transistor is coupled to the second electrode of the light emitting unit; A first electrode of the first capacitor is coupled to the second node J2 , and a second electrode of the first capacitor is coupled to the driving power supply terminal VDD.

17. The light emitting assembly according to claim 16, wherein: The second transistor and the seventh transistor are oxide thin film transistors; The first transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are low-temperature polysilicon thin-film transistors.

18. The light emitting assembly according to claim 17, characterized in that: The first capacitor is located in the driving circuit layer where the low-temperature polysilicon thin film transistor is located.

19. The light emitting assembly according to claim 16, wherein: The driving unit further includes: an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor; The gate of the first transistor is coupled to a fourth node J4; The gate of the eighth transistor is coupled to the fifth node J5, the first electrode of the eighth transistor is coupled to the first light emitting control signal terminal HF, and the second electrode of the eighth transistor is coupled to the fourth node J4; The gate of the ninth transistor is coupled to the fifth node J5, the first electrode of the ninth transistor is coupled to the fourth node J4, and the second electrode of the ninth transistor is coupled to the second light emitting control signal terminal EM; The gate of the tenth transistor is coupled to the reset signal terminal RST, the first electrode of the tenth transistor is coupled to the data signal terminal DATA, and the second electrode of the tenth transistor is coupled to the fifth node J5; A first electrode of the second capacitor is coupled to the fifth node J5 , and a second electrode of the second capacitor is coupled to the pull-down power supply terminal VSS.

20. The light emitting assembly according to claim 19, wherein: The eighth transistor is an oxide thin film transistor; The ninth transistor and the tenth transistor are low-temperature polysilicon thin film transistors.

21. The light emitting assembly according to claim 20, characterized in that The second capacitor is located in the driving circuit layer where the oxide thin film transistor is located.

22. The light emitting assembly according to any one of claims 1 to 13, characterized in that: The light emitting portion includes: a first semiconductor layer, and a plurality of sub-light emitting functional layers located on one side of the first semiconductor layer; The first semiconductor layer includes: a plurality of connecting parts corresponding one-to-one to the plurality of sub-light-emitting functional layers, and an auxiliary part connected to the plurality of connecting parts, the connecting parts are connected to the corresponding sub-light-emitting functional layers, at least part of the auxiliary part is located between adjacent connecting parts, and the auxiliary part and the connecting part are an integral structure.

23. The light emitting assembly according to claim 22, characterized in that: The light-emitting component further includes a first substrate and a color conversion unit located on one side of the first substrate, wherein the light-emitting unit is located on a side of the color conversion unit away from the first substrate; the color conversion unit includes: a light shielding layer located on one side of the first substrate, the light shielding layer having a plurality of light through holes; a defining dam layer located on a side of the light-shielding layer facing away from the first substrate, the defining dam layer having a plurality of opening areas corresponding one-to-one to the plurality of light-through holes, and the plurality of opening areas corresponding one-to-one to the plurality of sub-light-emitting functional layers, wherein orthographic projections of the opening areas on the second substrate overlap with orthographic projections of corresponding light-through holes on the first substrate, and overlap with orthographic projections of corresponding sub-light-emitting functional layers on the first substrate; an optical functional layer located in the opening area, at least a portion of the optical functional layer being used to convert the color of light entering the optical functional layer; And, a filter layer is located between the first substrate and the optical functional layer; the filter layer includes a plurality of filter units corresponding one-to-one to the plurality of light holes, and the orthographic projections of the filter units on the first substrate overlap with the orthographic projections of the corresponding light holes on the second substrate.

24. The light emitting assembly according to claim 23, characterized in that The plurality of sub-light emitting functional layers include: a first sub-light emitting functional layer, a second sub-light emitting functional layer and a third sub-light emitting functional layer; The multiple opening areas include: a first opening area, a second opening area and a third opening area. The first opening area is arranged opposite to the first sub-light-emitting functional layer, the second opening area is arranged opposite to the second sub-light-emitting functional layer, and the third opening area is arranged opposite to the third sub-light-emitting functional layer.

25. The light emitting assembly according to claim 22, wherein: The second electrode is connected to the first semiconductor layer; The auxiliary portion includes a first auxiliary portion, a second auxiliary portion, and a third auxiliary portion; the orthographic projection of the first auxiliary portion on the first substrate overlaps with the orthographic projection of the second electrode on the first substrate; a portion of the second auxiliary portion is located between adjacent connecting portions, and another portion is located between the first auxiliary portion and the connecting portion; the third auxiliary portion is arranged around the first auxiliary portion, the second auxiliary portion, and the plurality of connecting portions, and the auxiliary portion is made of the same material as the connecting portion; The sub-light-emitting functional layer includes: a second semiconductor layer and the light-emitting layer; the first electrode, the second semiconductor layer and the light-emitting layer are stacked in a direction perpendicular to and toward the first substrate; wherein the light-emitting layer is connected to the corresponding connecting portion in the first semiconductor layer.

26. The light emitting assembly according to claim 25, characterized in that The first semiconductor layer includes: a first sublayer and a second sublayer stacked in a direction perpendicular to and toward the first substrate, the first sublayer being located between the second sublayer and the light-emitting layer, the first sublayer being made of N-type doped gallium nitride, and the second sublayer being a gallium nitride buffer layer; The material of the second semiconductor layer includes P-type doped gallium nitride, and the light-emitting layer is a multi-quantum well layer.

27. A method for preparing a light-emitting component, characterized in that: The method comprises: Acquire a first target structure, where the first target structure includes a light-emitting unit, and the light-emitting unit includes: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively; Acquire a second target structure, the second target structure including a driving unit, the driving unit including: a first driving circuit layer and a second driving circuit layer stacked together, the first driving circuit layer including a third electrode and a fourth electrode, the third electrode and the fourth electrode both being located on a side of the second driving circuit layer away from the light-emitting unit; The first target structure and the second target structure are bonded together so that the first target structure of the light emitting unit an electrode electrically connected to the third electrode of the driving unit, and electrically connected to the second electrode of the light-emitting unit and the fourth electrode of the driving unit; The first driving circuit layer includes a first type of transistors, the second driving circuit layer includes a second type of transistors, and the first type of transistors and the second type of transistors are of different types.

28. The method according to claim 27, characterized in that Obtaining a second target structure, including: obtaining an intermediate substrate; forming a first driving circuit layer on the first surface of the intermediate substrate, wherein the first driving circuit layer includes a plurality of first connection structures; A plurality of through holes are formed on the second surface of the intermediate substrate, each of the through holes being used to expose a corresponding one of the first connecting structures; A second driving circuit layer is formed on the second surface of the intermediate substrate. The second driving circuit layer includes a plurality of second connecting structures. Each second connecting structure is located in a corresponding one of the through holes and is electrically connected to the first connecting structure exposed in the through hole.

29. The method according to claim 27, characterized in that Obtaining a second target structure, including: forming a first driving circuit layer on a first temporary substrate, wherein the first driving circuit layer includes a plurality of second connection structures; forming a second driving circuit layer on a second temporary substrate, wherein the second driving circuit layer includes a plurality of first connection structures; removing the first temporary substrate to expose the plurality of second connection structures; removing the second temporary substrate to expose the plurality of first connection structures; The plurality of first connection structures and the corresponding plurality of second connection structures are electrically connected.

30. A display substrate, characterized in that: The display substrate includes a driving backplane, and a plurality of light-emitting components according to any one of claims 1 to 26 arranged in an array and located on one side of the driving backplane; The driving backplane is used to provide a driving signal to the driving unit through a plurality of pins in the light-emitting component, so that the driving unit drives the light-emitting unit to emit light.

31. The display substrate according to claim 30, wherein: The driving backplane is a passive matrix driving backplane.

32. A method for preparing a display substrate, characterized in that: The method comprises: Obtain a light-emitting unit, a first drive circuit layer, a second drive circuit layer, and a drive backplane, wherein the light-emitting unit includes: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode, respectively; the first drive circuit layer includes a third electrode, a fourth electrode, and a plurality of second connection structures; the second drive circuit layer includes a plurality of first connection structures and a plurality of pins; Bonding the first driving circuit layer and the second driving circuit layer so that the plurality of first connection structures are electrically connected to the corresponding plurality of second connection structures, and the third electrode and the fourth electrode are arranged away from the second driving circuit layer; Bonding the light-emitting unit to the first driving circuit layer so that the first electrode is electrically connected to the third electrode, and the second electrode is electrically connected to the fourth electrode; The driving backplane and a plurality of pins of the second driving circuit layer are bonded and connected.

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