Pixel driving circuit, display panel, and light-emitting control method

Abstract

A pixel driving circuit, a display panel, and a light-emitting control method. The pixel driving circuit comprises: a regulation circuit (1), a pixel circuit (2) and a light-emitting device (L); the regulation circuit (1) is coupled to an anode of the light-emitting device (L); the regulation circuit (1) is configured to generate, on the basis of a first data voltage, a first current to be input into the anode of the light-emitting device (L); the pixel circuit (2) is coupled to the anode of the light-emitting device (L); the pixel circuit (2) is configured to generate, on the basis of a second data voltage, a second current to be input into the anode of the light-emitting device (L); and the light-emitting device (L) is configured to emit light under the combined action of the first current and the second current. A large current difference of the pixel driving circuit during high-to-low grayscale conversion is avoided, thereby ensuring the color consistency of the display panel during grayscale transition, and improving the display effect of the display panel.

Description

Pixel driving circuit, display panel and light emitting control method Technical Field

[0001] The present application relates to the field of display technology and provides a pixel driving circuit, a display panel and a light emitting control method. Background Art

[0002] In LED display products, especially in the pixel driving circuits of glass-based Mini / Micro LED display products, a combination of current control and duration control is usually used to achieve image display. Among them, high-grayscale images are usually achieved by current control, and low-grayscale images are usually achieved by duration control. However, when the image is converted between high grayscale and low grayscale, the current required for current control and duration control is extremely different, resulting in large differences in the color of the displayed image.

[0003] Summary of the Invention

[0004] Embodiments of the present application provide a pixel driving circuit, a display panel, and a light emitting control method to ensure current stability and color uniformity of the display panel during high and low grayscale conversion.

[0005] The specific technical solutions provided in this application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a pixel driving circuit, comprising: a control circuit, a pixel circuit, and a light-emitting device;

[0007] The control circuit is coupled to the anode of the light emitting device, and is configured to generate a first current input to the anode of the light emitting device according to the first data voltage;

[0008] The pixel circuit is coupled to the anode of the light emitting device, and the pixel circuit is configured to generate a second current input to the anode of the light emitting device according to the second data voltage;

[0009] The light emitting device is configured to emit light under the combined effect of a first current and a second current.

[0010] Optionally, the control circuit includes: a first driving transistor, a first data writing subcircuit and a time length control subcircuit;

[0011] The first data writing sub-circuit is coupled to the gate of the first driving transistor and is configured to provide a first data voltage to the gate of the first driving transistor in response to a signal from the first scanning control terminal;

[0012] The second end of the first driving transistor is coupled to the anode of the light emitting device via the time length control subcircuit and is configured to generate a first driving current according to the first data voltage;

[0013] The duration control subcircuit is coupled to the anode of the light emitting device and is configured to generate a first current according to the first driving current in response to a signal at the duration control terminal and provide the first current to the anode of the light emitting device.

[0014] Optionally, the duration control subcircuit includes: a first transistor;

[0015] The control end of the first transistor is coupled to the duration control end, the first end of the first transistor is coupled to the second end of the first driving transistor, and the second end of the first transistor is coupled to the anode of the light emitting device.

[0016] Optionally, the first data writing sub-circuit includes: a second transistor and a third transistor;

[0017] The control terminal of the second transistor is coupled to the first scan control terminal, the first terminal of the second transistor is coupled to the second terminal of the first driving transistor, and the second terminal of the second transistor is coupled to the gate of the first driving transistor;

[0018] The control end of the third transistor is coupled to the first scan control end, the first end of the third transistor is coupled to the first end of the first driving transistor, and the second end of the third transistor is coupled to the first data signal end.

[0019] Optionally, the first data writing sub-circuit includes: a fourth transistor;

[0020] The control end of the fourth transistor is coupled to the first scan control end, the first end of the fourth transistor is coupled to the second end of the first driving transistor, and the second end of the fourth transistor is coupled to the gate of the first driving transistor.

[0021] Optionally, the first data writing sub-circuit includes: a fifth transistor, a first capacitor, a sixth transistor and a seventh transistor;

[0022] The control terminal of the fifth transistor is coupled to the second scan control terminal, the first terminal of the fifth transistor is coupled to the pixel circuit, and the second terminal of the fifth transistor is coupled to the first terminal of the first capacitor;

[0023] The second terminal of the first capacitor is coupled to the first power supply terminal;

[0024] The control terminal of the sixth transistor is coupled to the first scan control terminal, the first terminal of the sixth transistor is coupled to the first terminal of the first capacitor, and the second terminal of the sixth transistor is coupled to the first terminal of the first driving transistor;

[0025] The control end of the seventh transistor is coupled to the first scan control end, the first end of the seventh transistor is coupled to the second end of the first driving transistor, and the second end of the seventh transistor is coupled to the gate of the first driving transistor.

[0026] Optionally, the control circuit further includes: a second capacitor;

[0027] A first terminal of the second capacitor is coupled to the first power supply terminal, and a second terminal of the second capacitor is coupled to the gate of the first driving transistor.

[0028] Optionally, the control circuit further includes: a first reset subcircuit;

[0029] The first reset sub-circuit is coupled to the gate of the first driving transistor and is configured to provide a reset signal to the gate of the first driving transistor in response to a signal at the reset signal terminal.

[0030] Optionally, the first reset sub-circuit includes: an eighth transistor;

[0031] The control terminal of the eighth transistor is coupled to the reset signal terminal, the first terminal of the eighth transistor is coupled to the gate of the first driving transistor, and the second terminal of the eighth transistor is coupled to the initialization signal terminal.

[0032] Optionally, the first reset sub-circuit includes: a ninth transistor;

[0033] The control terminal of the ninth transistor is coupled to the reset signal terminal, the first terminal of the ninth transistor is coupled to the gate of the first driving transistor, and the second terminal of the ninth transistor is coupled to the cathode of the light emitting device.

[0034] Optionally, the pixel circuit includes: a second driving transistor, a second data writing subcircuit and a light emitting control subcircuit;

[0035] The second data writing sub-circuit is coupled to the gate of the second driving transistor and is configured to provide a second data voltage to the gate of the second driving transistor in response to a signal from the second scan control terminal;

[0036] The second end of the second driving transistor is coupled to the anode of the light emitting device via the light emitting control subcircuit and is configured to generate a second current according to the second data voltage;

[0037] The light emitting control subcircuit is coupled to the first power supply terminal and the anode of the light emitting device. The light emitting control subcircuit is configured to provide the second current generated by the second driving transistor to the light emitting device in response to a signal from the light emitting control terminal.

[0038] Optionally, the second data writing sub-circuit includes: a tenth transistor and an eleventh transistor;

[0039] The control terminal of the tenth transistor is coupled to the second scan control terminal, the first terminal of the tenth transistor is coupled to the gate of the second driving transistor, and the second terminal of the tenth transistor is coupled to the second terminal of the second driving transistor;

[0040] The control terminal of the eleventh transistor is coupled to the second scan control terminal, the first terminal of the eleventh transistor is coupled to the second data signal terminal, and the second terminal of the eleventh transistor is coupled to the first terminal of the second driving transistor.

[0041] Optionally, the second data writing sub-circuit includes: a twelfth transistor and a thirteenth transistor;

[0042] The control terminal of the twelfth transistor is coupled to the third scan control terminal, the first terminal of the twelfth transistor is coupled to the third data signal terminal, and the second terminal of the twelfth transistor is coupled to the first terminal of the second driving transistor;

[0043] The control end of the thirteenth transistor is coupled to the second scan control end, the first end of the thirteenth transistor is coupled to the gate of the second driving transistor, and the second end of the thirteenth transistor is coupled to the second end of the second driving transistor.

[0044] Optionally, the second data writing sub-circuit includes: a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0045] A control terminal of the fourteenth transistor is coupled to the third scan control terminal, a first terminal of the fourteenth transistor is coupled to the third data signal terminal, and a second terminal of the fourteenth transistor is coupled to the first terminal of the fifteenth transistor;

[0046] A control terminal of the fifteenth transistor is coupled to the first scan control terminal, and a second terminal of the fifteenth transistor is coupled to the first terminal of the second driving transistor;

[0047] The control end of the sixteenth transistor is coupled to the first scan control end, the first end of the sixteenth transistor is coupled to the gate of the second driving transistor, and the second end of the sixteenth transistor is coupled to the second end of the second driving transistor.

[0048] Optionally, the control circuit further includes: a second reset subcircuit;

[0049] The second reset sub-circuit is coupled to the gate of the second driving transistor and is configured to provide a reset signal to the gate of the second driving transistor in response to a signal at the reset signal terminal.

[0050] Optionally, the second reset sub-circuit includes: a seventeenth transistor;

[0051] The control terminal of the seventeenth transistor is coupled to the reset signal terminal, the first terminal of the seventeenth transistor is coupled to the gate of the second driving transistor, and the second terminal of the seventeenth transistor is coupled to the initialization signal terminal or the cathode of the light emitting device.

[0052] Optionally, the device further comprises: an eighteenth transistor;

[0053] The control end of the eighteenth transistor is coupled to the light emitting control end, the first end of the eighteenth transistor is coupled to the anode of the light emitting device, and the second end of the eighteenth transistor is coupled to the second end of the first transistor.

[0054] Optionally, the device further comprises: a third capacitor;

[0055] A first terminal of the third capacitor is coupled to the first power supply terminal, and a second terminal of the third capacitor is coupled to the second terminal of the fourteenth transistor.

[0056] Optionally, the device further comprises: a nineteenth transistor;

[0057] The control terminal of the nineteenth transistor is coupled to the reset signal terminal, the first terminal of the nineteenth transistor is coupled to the initialization signal terminal, and the second terminal of the nineteenth transistor is coupled to the anode of the light emitting device.

[0058] In a second aspect, an embodiment of the present application further provides a display panel comprising any of the above-mentioned pixel driving circuits.

[0059] In a third aspect, an embodiment of the present application further provides a light emission control method applied to any of the above pixel driving circuits, comprising:

[0060] The control circuit generates a first current input to the anode of the light emitting device according to the first data voltage;

[0061] The pixel circuit generates a second current input to the anode of the light emitting device according to the second data voltage;

[0062] The light emitting device emits light under the combined action of the first current and the second current.

[0063] The beneficial effects of this application are as follows:

[0064] In summary, an embodiment of the present application provides a pixel driving circuit, a display panel and a light-emitting control method, wherein the pixel driving circuit includes: a control circuit, a pixel circuit and a light-emitting device, wherein the control circuit is coupled to the anode of the light-emitting device, and the control circuit is configured to generate a first current input to the anode of the light-emitting device according to a first data voltage, and the pixel circuit is coupled to the anode of the light-emitting device, and the pixel circuit is configured to generate a second current input to the anode of the light-emitting device according to a second data voltage, and the light-emitting device is configured to emit light under the combined action of the first current and the second current. The above-mentioned control circuit and pixel circuit jointly provide current to the light-emitting device, thereby avoiding a large current difference in the pixel driving circuit during the high and low grayscale conversion process, thereby ensuring the color consistency of the display panel during the grayscale transition, and improving the display effect of the display panel.

[0065] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0067] FIG1 is a connection diagram of a pixel driving circuit in the related art;

[0068] FIG2 is a first circuit connection diagram of a pixel driving circuit in an embodiment of the present application;

[0069] FIG3 is a first circuit connection diagram of the control circuit in an embodiment of the present application;

[0070] FIG4 is a second circuit connection diagram of the control circuit in an embodiment of the present application;

[0071] FIG5 is a circuit connection diagram of a pixel circuit in an embodiment of the present application;

[0072] FIG6 is a second circuit connection diagram of the pixel driving circuit in an embodiment of the present application;

[0073] FIG7 is a circuit connection diagram of a first pixel driving circuit in an embodiment of the present application;

[0074] FIG8 is a circuit connection diagram of a second pixel driving circuit in an embodiment of the present application;

[0075] FIG9 is a circuit connection diagram of a third pixel driving circuit in an embodiment of the present application;

[0076] FIG10 is a circuit connection diagram of a fourth pixel driving circuit in an embodiment of the present application;

[0077] FIG11 is a circuit connection diagram of a fifth pixel driving circuit in an embodiment of the present application;

[0078] FIG12 is a circuit connection diagram of a sixth pixel driving circuit in an embodiment of the present application;

[0079] FIG13 is a circuit connection diagram of a seventh pixel driving circuit in an embodiment of the present application;

[0080] FIG14 is a circuit connection diagram of an eighth pixel driving circuit in an embodiment of the present application;

[0081] FIG15 is a circuit connection diagram of a ninth pixel driving circuit according to an embodiment of the present application;

[0082] FIG16 is a circuit connection diagram of a tenth pixel driving circuit in an embodiment of the present application;

[0083] FIG17 is a timing diagram of a first pixel driving circuit according to an embodiment of the present application;

[0084] FIG18 is a timing diagram of a second pixel driving circuit according to an embodiment of the present application;

[0085] FIG19 is a timing diagram of a third pixel driving circuit according to an embodiment of the present application;

[0086] FIG20 is a flow chart of a light control method in an embodiment of the present application. DETAILED DESCRIPTION

[0087] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of the technical solutions of this application, but not all of them. Based on the embodiments described in this application document, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the technical solutions of this application.

[0088] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0089] In related technologies, pixel driver circuits typically use a combination of current control and duration control to achieve image display. Current control utilizes current magnitude to achieve different grayscales, specifically by controlling the conversion current magnitude of the driver transistor via voltage. However, during current control, the smaller the light-emitting device, the more unstable its color coordinates become at low currents, leading to inconsistent image quality at low grayscales. Duration control ensures that the light-emitting device operates under stable, high-current conditions, achieving low grayscales by controlling the duration of the driver transistor, etc. However, controlling the duration of the light-emitting device remains a major challenge.

[0090] Moreover, when the display screen is converted from high grayscale to low grayscale, that is, when the current control mode is switched to the duration control mode, the display screen has a large color difference before and after the transition due to the large current difference, and the color of the display panel is uneven during the grayscale transition.

[0091] The working process of a conventional pixel driving circuit in the related art is described in detail below. Referring to Figure 1, the conventional pixel driving circuit includes a first switching transistor T1, a second switching transistor T2, a driving transistor T3, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, a ninth switching transistor T9, a tenth switching transistor T10, an eleventh switching transistor T11, a twelfth switching transistor T12, a capacitor 1 and a capacitor 2.

[0092] When the reset signal is valid, the first switch transistor T1 supplies the initialization signal vinit to the gate of the driving transistor T3, thereby resetting the gate. The second switch transistor T2 supplies the initialization signal vinit to the anode of the light-emitting device, thereby resetting the anode of the light-emitting device. When the data signal is valid, the data signal reaches the gate of the driving transistor T3 via the fourth switch transistor T4, the driving transistor T3, and the fifth switch transistor T5, thereby implementing the writing of the data voltage. Furthermore, during the light-emitting phase, the sixth switch transistor T6, the seventh switch transistor T7, and the eighth switch transistor T8 are turned on, and the current generated by the data voltage causes the light-emitting device to emit light.

[0093] It should be noted that the eighth switch transistor T8 has a gating function. When a high-grayscale image is to be displayed, the ninth switch transistor T9, the tenth switch transistor T10, and the capacitor 1 act to keep the eighth switch transistor T8 constantly on. Alternatively, when a low-grayscale image is to be displayed, the eleventh switch transistor T11, the twelfth switch transistor T12, and the capacitor 2 act to keep the eighth switch transistor T8 intermittently on in response to the hf signal.

[0094] In addition, the turn-on voltage in the currently commonly used PMOS pixel driver circuit is negative, while the commonly used driver IC can only output positive voltage. Therefore, the entire voltage range needs to be adjusted to positive voltage, resulting in excessively high data voltage, high driver IC power consumption and difficulty in selection.

[0095] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0096] 2 , a pixel driving circuit proposed in an embodiment of the present application includes: a control circuit 1 , a pixel circuit 2 and a light emitting device L.

[0097] The control circuit 1 is coupled to the anode of the light emitting device L, and is configured to generate a first current input to the anode of the light emitting device L according to a first data voltage.

[0098] The pixel circuit 2 is coupled to the anode of the light emitting device L, and is configured to generate a second current input to the anode of the light emitting device L according to the second data voltage.

[0099] The light emitting device L is configured to emit light under the combined effect of the first current and the second current.

[0100] It should be noted that the pixel driving circuit in the present application consists of three parts: a control circuit 1, a pixel circuit 2 and a light-emitting device L. The current of the light-emitting device L in the light-emitting stage is the result of the combined action of the first current generated by the control circuit 1 and the second current generated by the pixel circuit 2. Compared with the second current generated by the pixel circuit 2, the first current generated by the control circuit 1 has a smaller value. The combined action of the above-mentioned first current and second current realizes a smooth transition between high grayscale display and low grayscale display of the display panel.

[0101] In an embodiment of the present application, in order to write the first data voltage into the first driving transistor DT1 of the control circuit 1 and write the second data voltage into the second driving transistor DT2 of the pixel circuit 2, three data voltage writing situations are proposed in the embodiment of the present application: the first situation: the first data voltage and the second data voltage are independently written into the first driving transistor DT1 and the second driving transistor DT2 respectively; the second situation: the first data voltage and the second data voltage are superimposed and multiplexed in timing to write into the first driving transistor DT1 and the second driving transistor DT2 in a time-sharing manner; the third situation: the first data voltage and the second data voltage are synchronously written into the first driving transistor DT1 and the second driving transistor DT2 during the above-mentioned light-emitting phase. The writing situation of the first data voltage in the control circuit 1 is first described in detail below.

[0102] It should be noted that, in the first case, the first data signal terminal Data1 providing the first data voltage and the second data signal terminal Data2 providing the second data voltage are independent; in the second and third cases, the first data signal terminal Data1 providing the first data voltage and the third data signal terminal Data3 providing the second data voltage are time-division multiplexed.

[0103] The control circuit 1 in the present application is first introduced below. Referring to FIG. 3 , the control circuit 1 includes: a first driving transistor DT1 , a first data writing sub-circuit 10 and a duration control sub-circuit 11 .

[0104] The first data writing sub-circuit 10 is coupled to the gate of the first driving transistor DT1 and is configured to provide a first data voltage to the gate of the first driving transistor DT1 in response to a signal of the first scan control terminal Gate_1 .

[0105] A second terminal of the first driving transistor DT1 is coupled to the anode of the light emitting device L via the duration control sub-circuit 11 , and is configured to generate a first driving current according to the first data voltage.

[0106] The duration control subcircuit 11 is coupled to the anode of the light emitting device L and is configured to generate a first current according to the first driving current in response to a signal of the duration control terminal HF and provide the first current to the anode of the light emitting device L.

[0107] During implementation, when the signal of the first scan control terminal Gate_1 is a valid signal, the first data writing sub-circuit 10 provides the first data voltage to the gate of the first driving transistor DT1, and the first driving transistor DT1 further generates a first driving current according to the first data voltage. When the signal of the duration control terminal HF is a valid signal, the duration control sub-circuit 11 generates a first current according to the first driving current and provides the first current to the anode of the light-emitting device L, so that the light-emitting device L obtains the first current.

[0108] The following is a detailed description of each transistor in the control circuit 1 with reference to the accompanying drawings. For example, referring to FIG7 , the duration control subcircuit 11 includes: a first transistor M1.

[0109] The connection relationship between the first transistor M1 and other components is: the control end of the first transistor M1 is coupled to the time control end HF, the first end of the first transistor M1 is coupled to the second end of the first driving transistor DT1, and the second end of the first transistor M1 is coupled to the anode of the light-emitting device L.

[0110] During implementation, when the duration control terminal HF is at a low level, the first transistor M1 is turned on, and the first drive current generated by the first drive transistor DT1 flows to the anode of the light-emitting device L through the turned-on first transistor M1. It should be noted that the signal of the above-mentioned duration control terminal HF is usually a pulse signal with a settable duty cycle. Therefore, when the above-mentioned first drive current flows through the first transistor M1, it will become a first current with a value smaller than the first drive current.

[0111] Corresponding to the first case, referring to FIG. 7 , the first data writing sub-circuit 10 includes a second transistor M2 and a third transistor M3 .

[0112] The connection relationship between the second transistor M2 and other components is: the control end of the second transistor M2 is coupled to the first scan control end Gate_1, the first end of the second transistor M2 is coupled to the second end of the first driving transistor DT1, and the second end of the second transistor M2 is coupled to the gate of the first driving transistor DT1.

[0113] During implementation, when the first scan control terminal Gate_1 is at a low level, the second transistor M2 is turned on, and the first data signal terminal Data1 providing the first data voltage is connected to the second terminal of the first driving transistor DT1 via the turned-on second transistor M2.

[0114] The connection relationship between the third transistor M3 and other components is: the control end of the third transistor M3 is coupled to the first scan control end Gate_1, the first end of the third transistor M3 is coupled to the first end of the first driving transistor DT1, and the second end of the third transistor M3 is coupled to the first data signal end Data1.

[0115] During implementation, when the first scan control terminal Gate_1 is at a low level, the third transistor M3 is turned on, and the first data signal terminal Data1, which provides the first data voltage, is connected to the first terminal of the first drive transistor DT1 via the turned-on third transistor M3. In this way, the first data voltage can be provided to the gate of the first drive transistor DT1 via the turned-on third transistor M3, the first drive transistor DT1, and the second transistor M2, thereby achieving the writing of the first data voltage.

[0116] Corresponding to the second situation, referring to FIG. 11 , the first data writing sub-circuit 10 includes: a fourth transistor M4 .

[0117] The connection relationship between the fourth transistor M4 and other components is: the control end of the fourth transistor M4 is coupled to the first scan control end Gate_1, the first end of the fourth transistor M4 is coupled to the second end of the first driving transistor DT1, and the second end of the fourth transistor M4 is coupled to the gate of the first driving transistor DT1.

[0118] During implementation, when the first scan control terminal Gate_1 is at a low level, the fourth transistor M4 is turned on, and the first data signal terminal Data1 providing the first data voltage is connected to the gate of the first driving transistor DT1 through the turned-on first driving transistor DT1 and the fourth transistor M4, thereby providing the first data voltage to the gate of the first driving transistor DT1.

[0119] Corresponding to the third case, referring to FIG. 15 , the first data writing sub-circuit 10 includes: a fifth transistor M5 , a first capacitor C1 , a sixth transistor M6 , and a seventh transistor M7 .

[0120] The connection relationship between the fifth transistor M5 and other components is as follows: the control end of the fifth transistor M5 is coupled to the second scan control end Gate_2, the first end of the fifth transistor M5 is coupled to the pixel circuit 2, the second end of the fifth transistor M5 is coupled to the first end of the first capacitor C1, and the second end of the first capacitor C1 is coupled to the first power supply end LVDD.

[0121] During implementation, when the second scan control terminal Gate_2 is at a low level, the fifth transistor M5 is turned on, and the first data voltage is provided to the first capacitor C1 through the turned-on fifth transistor M5, that is, the first data voltage is stored through the first capacitor C1, and the second end of the above-mentioned first capacitor C1 is electrically connected to the first power supply terminal LVDD. It should be supplemented that, referring to Figures 13 and 14, in other embodiments, the second end of the above-mentioned first capacitor C1 can also be electrically connected to the second power supply terminal VSS and the initialization signal terminal VinitVinit, so as to maintain the stability of the second end of the first capacitor C1.

[0122] During implementation, the first capacitor C1 is used to pre-store a first data voltage provided to the first driving transistor DT1. Thus, the first capacitor C1 can be used to provide the first data voltage to the gate of the first driving transistor DT1 during the light-emitting phase. It should be noted that the first data voltage corresponding to the first current of the first driving transistor DT1 during the light-emitting phase corresponds to the current frame. The first data voltage provided by the first capacitor C1 is the data voltage required by the first driving transistor DT1 during the display of the next frame.

[0123] The connection relationship between the sixth transistor M6 and other components is: the control end of the sixth transistor M6 is coupled to the first scan control end Gate_1, the first end of the sixth transistor M6 is coupled to the first end of the first capacitor C1, and the second end of the sixth transistor M6 is coupled to the first end of the first driving transistor DT1.

[0124] During implementation, when the first scan control terminal Gate_1 is at a low level, the sixth transistor M6 is turned on, and the first data voltage stored in the first capacitor C1 is provided to the first terminal of the first driving transistor DT1 via the turned-on sixth transistor M6.

[0125] The connection relationship between the seventh transistor M7 and other components is: the control end of the seventh transistor M7 is coupled to the first scan control end Gate_1, the first end of the seventh transistor M7 is coupled to the second end of the first driving transistor DT1, and the second end of the seventh transistor M7 is coupled to the gate of the first driving transistor DT1.

[0126] During implementation, when the first scan control terminal Gate_1 is at a low level, the seventh transistor M7 is turned on, and the first data voltage is provided to the gate of the first driving transistor DT1 via the first driving transistor DT1 and the turned-on seventh transistor M7. That is, the first data voltage is provided to the gate of the first driving transistor DT1.

[0127] In addition, in order to ensure that the first data voltage is normally written into the first driving transistor DT1 , referring to FIG. 15 and FIG. 16 , the control circuit 1 further includes: a second capacitor C2 .

[0128] The connection relationship between the second capacitor C2 and other components is as follows: a first end of the second capacitor C2 is coupled to the first power supply terminal LVDD, and a second end of the second capacitor C2 is coupled to the gate of the first driving transistor DT1.

[0129] The second capacitor C2 is provided to ensure that the first data voltage continues to be provided to the light emitting control sub-circuit 21 in the next timing, and the first data voltage is first stored through the second capacitor C2 in the current timing.

[0130] In addition, in order to reset the gate of the first driving transistor DT1 after a frame of image is displayed, referring to FIG. 4 and FIG. 6 , the control circuit 1 further includes a first reset sub-circuit 12 .

[0131] The first reset sub-circuit 12 is coupled to the gate of the first driving transistor DT1 and is configured to provide a reset signal to the gate of the first driving transistor DT1 in response to a signal at the reset signal terminal RST.

[0132] During implementation, when the reset signal terminal RST is at a low level, the first reset sub-circuit 12 is turned on, and the reset signal is provided to the gate of the first driving transistor DT1 via the turned-on first reset sub-circuit 12 .

[0133] In one embodiment, referring to FIG. 8 , the first reset sub-circuit 12 includes an eighth transistor M8 .

[0134] The connection relationship between the eighth transistor M8 and other components is: the control end of the eighth transistor M8 is coupled to the reset signal end RST, the first end of the eighth transistor M8 is coupled to the gate of the first driving transistor DT1, and the second end of the eighth transistor M8 is coupled to the initialization signal end Vinit.

[0135] During implementation, when the reset signal terminal RST is at a low level, the eighth transistor M8 is turned on, and the initialization signal of the initialization signal terminal Vinit is provided to the gate of the first driving transistor DT1 via the turned-on eighth transistor M8, thereby resetting the gate of the first driving transistor DT1.

[0136] In another embodiment, referring to FIG. 10 , the first reset sub-circuit 12 includes a ninth transistor M9 .

[0137] The connection relationship between the ninth transistor M9 and other components is: the control end of the ninth transistor M9 is coupled to the reset signal end RST, the first end of the ninth transistor M9 is coupled to the gate of the first driving transistor DT1, and the second end of the ninth transistor M9 is coupled to the cathode of the light-emitting device L.

[0138] During implementation, when the reset signal terminal RST is at a low level, the ninth transistor M9 is turned on, and the signal of the cathode of the light emitting device L is provided to the gate of the first driving transistor DT1 via the turned-on eighth transistor M8, thereby resetting the gate of the first driving transistor DT1.

[0139] After introducing the control circuit 1, the pixel circuit 2 in the embodiment of the present application will be introduced next.

[0140] 5 and 6 , the pixel circuit 2 includes a second driving transistor DT2 , a second data writing sub-circuit 20 and a light emitting control sub-circuit 21 .

[0141] The second data writing sub-circuit 20 is coupled to the gate of the second driving transistor DT2 and is configured to provide the second data voltage to the gate of the second driving transistor DT2 in response to a signal of the second scan control terminal Gate_2 .

[0142] A second terminal of the second driving transistor DT2 is coupled to the anode of the light emitting device L via the light emitting control sub-circuit 21 , and is configured to generate a second current according to the second data voltage.

[0143] The light emitting control subcircuit 21 is coupled to the first power supply terminal LVDD and the anode of the light emitting device L. The light emitting control subcircuit 21 is configured to provide the second current generated by the second driving transistor DT2 to the light emitting device L in response to a signal of the light emitting control terminal EM.

[0144] During implementation, when the signal of the second scan control terminal Gate_2 is a valid signal, the second data writing sub-circuit 20 provides the second data voltage to the gate of the second driving transistor DT2, and the second driving transistor DT2 further generates a second current according to the second data voltage. When the signal of the light-emitting control terminal EM is a valid signal, the light-emitting control sub-circuit 21 is turned on, and the second current generated by the second driving transistor DT2 is provided to the light-emitting device L, thereby causing the light-emitting device L to emit light.

[0145] Similarly, in order to write the second data voltage to the second driving transistor DT2 of the pixel circuit 2, the second data writing sub-circuit 20 in the embodiment of the present application also has the three data voltage writing situations of the first situation, the second situation and the third situation mentioned above, which are described in detail below.

[0146] Corresponding to the first case, referring to FIG. 7 and FIG. 9 , the second data writing sub-circuit 20 includes a tenth transistor M10 and an eleventh transistor M11 .

[0147] The connection relationship between the tenth transistor M10 and other components is: the control end of the tenth transistor M10 is coupled to the second scan control end Gate_2, the first end of the tenth transistor M10 is coupled to the gate of the second driving transistor DT2, and the second end of the tenth transistor M10 is coupled to the second end of the second driving transistor DT2.

[0148] During implementation, when the second scan control terminal Gate_2 is at a low level, the tenth transistor M10 is turned on, and the second data signal terminal Data2 providing the second data voltage is connected to the gate of the second driving transistor DT2 via the turned-on tenth transistor M10.

[0149] The connection relationship between the eleventh transistor M11 and other components is: the control end of the eleventh transistor M11 is coupled to the second scan control end Gate_2, the first end of the eleventh transistor M11 is coupled to the second data signal end Data2, and the second end of the eleventh transistor M11 is coupled to the first end of the second driving transistor DT2.

[0150] During implementation, when the second scan control terminal Gate_2 is at a low level, the eleventh transistor M11 is turned on, and the second data voltage provided by the second data signal terminal Data2 is written into the gate of the second driving transistor DT2 via the turned-on eleventh transistor M11, the second driving transistor DT2 and the tenth transistor M10.

[0151] In addition, as shown in FIG10 , the pixel circuit 2 further includes a fourth capacitor C4 , a first end of the fourth capacitor C4 is coupled to the first power supply terminal LVDD, and a second end of the fourth capacitor C4 is coupled to the gate of the second driving transistor DT2 .

[0152] During implementation, after the second data voltage is supplied to the gate of the second driving transistor DT2, in order to ensure that the second data voltage continues to be supplied to the light emitting control sub-circuit 21 in the next timing, the second data voltage is stored by the fourth capacitor C4.

[0153] Corresponding to the second situation, referring to FIG. 11 , the second data writing sub-circuit 20 includes a twelfth transistor M12 and a thirteenth transistor M13 .

[0154] The connection relationship between the twelfth transistor M12 and other components is: the control end of the twelfth transistor M12 is coupled to the third scan control end Gate_3, the first end of the twelfth transistor M12 is coupled to the third data signal end Data3, and the second end of the twelfth transistor M12 is coupled to the first end of the second driving transistor DT2.

[0155] During implementation, when the third scan control terminal Gate_3 is at a low level, the twelfth transistor M12 is turned on, and the third data signal terminal Data3 provides the data voltage to the first terminal of the second driving transistor DT2 via the turned-on twelfth transistor M12.

[0156] The connection relationship between the thirteenth transistor M13 and other components is: the control end of the thirteenth transistor M13 is coupled to the second scan control end Gate_2, the first end of the thirteenth transistor M13 is coupled to the gate of the second driving transistor DT2, and the second end of the thirteenth transistor M13 is coupled to the second end of the second driving transistor DT2.

[0157] During implementation, when the second scan control terminal Gate_2 is at a low level, the thirteenth transistor M13 is turned on, and the data voltage provided by the third data signal terminal Data3 is provided to the gate of the second driving transistor DT2 via the turned-on twelfth transistor M12, the second driving transistor DT2 and the thirteenth transistor M13.

[0158] Corresponding to the third case, referring to FIG. 12 , FIG. 13 and FIG. 14 , the second data writing sub-circuit 20 includes: a fourteenth transistor M14 , a fifteenth transistor M15 and a sixteenth transistor M16 .

[0159] The connection relationship between the fourteenth transistor M14 and other components is: the control end of the fourteenth transistor M14 is coupled to the third scan control end Gate_3, the first end of the fourteenth transistor M14 is coupled to the third data signal end Data3, and the second end of the fourteenth transistor M14 is coupled to the first end of the fifteenth transistor M15.

[0160] During implementation, when the third scan control terminal Gate_3 is at a low level, the fourteenth transistor M14 is turned on, and the third data signal terminal Data3 is connected to the first terminal of the fifteenth transistor M15 via the turned-on fourteenth transistor M14.

[0161] The connection relationship between the fifteenth transistor M15 and other components is as follows: the control end of the fifteenth transistor M15 is coupled to the first scan control end Gate_1 , and the second end of the fifteenth transistor M15 is coupled to the first end of the second driving transistor DT2 .

[0162] During implementation, when the first scan control terminal Gate_1 is at a low level, the fifteenth transistor M15 is turned on, and the data signal of the third data signal terminal Data3 is provided to the first terminal of the second driving transistor DT2 via the turned-on fourteenth transistor M14 and fifteenth transistor M15.

[0163] The connection relationship between the sixteenth transistor M16 and other components is: the control end of the sixteenth transistor M16 is coupled to the first scan control end Gate_1, the first end of the sixteenth transistor M16 is coupled to the gate of the second driving transistor DT2, and the second end of the sixteenth transistor M16 is coupled to the second end of the second driving transistor DT2.

[0164] During implementation, when the first scan control terminal Gate_1 is at a low level, the sixteenth transistor M16 is turned on, and the data voltage provided to the first terminal of the second driving transistor DT2 is provided to the gate of the second driving transistor DT2 via the second driving transistor DT2 and the sixteenth transistor M16, thereby realizing the writing of the second data voltage.

[0165] Similarly, in order to reset the gate of the second driving transistor DT2 , the control circuit 1 further includes a second reset sub-circuit 22 .

[0166] The second reset sub-circuit 22 is coupled to the gate of the second driving transistor DT2 and is configured to provide a reset signal to the gate of the second driving transistor DT2 in response to a signal at the reset signal terminal RST.

[0167] During implementation, when the signal at the reset signal terminal RST is valid, the reset signal is provided to the gate of the second driving transistor DT2 via the turned-on second reset sub-circuit 22 , thereby resetting the gate of the second driving transistor DT2 .

[0168] Exemplarily, referring to FIG. 15 , the second reset sub-circuit 22 includes a seventeenth transistor M17 .

[0169] The connection relationship between the seventeenth transistor M17 and other components is as follows: the control end of the seventeenth transistor M17 is coupled to the reset signal end RST, the first end of the seventeenth transistor M17 is coupled to the gate of the second driving transistor DT2, and the second end of the seventeenth transistor M17 is coupled to the initialization signal end Vinit or the cathode of the light-emitting device L.

[0170] In one embodiment, when the reset signal terminal RST is at a low level and the second terminal of the seventeenth transistor M17 is coupled to the initialization signal terminal Vinit, the seventeenth transistor M17 is turned on, and the initialization signal of the initialization signal terminal Vinit is provided to the gate of the second driving transistor DT2 via the turned-on seventeenth transistor M17, thereby resetting the gate of the second driving transistor DT2.

[0171] In another embodiment, when the reset signal terminal RST is at a low level and the second terminal of the seventeenth transistor M17 is coupled to the cathode of the light-emitting device L, the seventeenth transistor M17 is turned on, and the signal of the cathode of the light-emitting device L is provided to the gate of the second driving transistor DT2 via the turned-on seventeenth transistor M17, thereby resetting the gate of the second driving transistor DT2.

[0172] In addition, referring to FIG. 16 , the pixel circuit 2 further includes an eighteenth transistor M18 .

[0173] A control terminal of the eighteenth transistor M18 is coupled to the light emitting control terminal EM, a first terminal of the eighteenth transistor M18 is coupled to the anode of the light emitting device L, and a second terminal of the eighteenth transistor M18 is coupled to the second terminal of the first transistor M1.

[0174] During implementation, when the light emitting control terminal EM is at a low level, the eighteenth transistor M18 is turned on, that is, when the light emitting control terminal EM is at a high level, the eighteenth transistor M18 is turned off, thereby avoiding the signal of the duration control terminal HF from affecting the light emitting device L during the non-light emitting stage.

[0175] In addition, referring to FIG. 15 and FIG. 16 , the pixel circuit 2 further includes a third capacitor C3 .

[0176] A first terminal of the third capacitor C3 is coupled to the first power supply terminal LVDD, and a second terminal of the third capacitor C3 is coupled to the second terminal of the fourteenth transistor M14.

[0177] During implementation, the third capacitor C3 is used to pre-store the second data voltage provided by the third data signal terminal Data3 to the second driving transistor DT2. In this way, the third capacitor C3 can be used to provide the second data voltage to the gate of the second driving transistor DT2 during the light emitting phase.

[0178] It should be noted that the second data voltage corresponding to the second current of the second driving transistor DT2 in the light emitting stage corresponds to the current frame image, and the second data voltage provided by the third capacitor C3 is the data voltage required by the second driving transistor DT2 during the display process of the next frame image.

[0179] In addition, referring to FIG. 7 , FIG. 15 and FIG. 16 , the pixel circuit 2 further includes a nineteenth transistor M19 .

[0180] A control terminal of the nineteenth transistor M19 is coupled to the reset signal terminal RST, a first terminal of the nineteenth transistor M19 is coupled to the initialization signal terminal Vinit, and a second terminal of the nineteenth transistor M19 is coupled to the anode of the light emitting device L.

[0181] During implementation, a nineteenth transistor M19 is further provided to reset the light-emitting device L. When the reset signal terminal RST is at a low level, the nineteenth transistor M19 is turned on, and the initialization signal from the initialization signal terminal Vinit is provided to the anode of the light-emitting device L via the turned-on nineteenth transistor M19, thereby resetting the anode of the light-emitting device L.

[0182] It should be noted that the control end of the nineteenth transistor M19 can also be electrically connected to the first scan control end Gate_1, the second scan control end Gate_2 or the third scan control end Gate_3, so that the anode of the light-emitting device L is reset during the process of writing the first data voltage into the first driving transistor DT1 or the second data voltage into the second driving transistor DT2.

[0183] In another embodiment, referring to FIG9 , when the eighteenth transistor M18 is present in the pixel driving circuit, the anode of the light-emitting device L will not be disturbed due to the presence of the eighteenth transistor M18 during the non-light-emitting stage. Therefore, there is no need to reset the anode of the light-emitting device L, and the nineteenth transistor M19 can be removed from the pixel driving circuit.

[0184] In addition, it should be supplemented that, referring to FIG. 7 , FIG. 10 and FIG. 12 , the light emitting control subcircuit 21 of the pixel circuit 2 further includes: a twentieth transistor M20 , a twenty-first transistor M21 and a twenty-second transistor M22 .

[0185] A control terminal of the twentieth transistor M20 is coupled to the light emitting control terminal EM, a first terminal of the twentieth transistor M20 is coupled to the first power terminal LVDD, and a second terminal of the twentieth transistor M20 is coupled to the first terminal of the second driving transistor DT2.

[0186] During implementation, when the light emitting control terminal EM is at a low level, the twentieth transistor M20 is turned on, and under the action of the first power supply terminal LVDD, the twentieth transistor M20 is connected to the second driving transistor DT2.

[0187] The control terminal of the 21st transistor M21 is coupled to the light emitting control terminal EM, the first terminal of the 21st transistor M21 is coupled to the second terminal of the second driving transistor DT2 , and the second terminal of the 21st transistor M21 is coupled to the anode of the light emitting device L.

[0188] During implementation, when the light emitting control terminal EM is at a low level, the twenty-first transistor M21 is turned on, and the second driving transistor DT2 is connected to the light emitting device L via the twenty-first transistor M21 , thereby providing the second current to the light emitting device L.

[0189] A control terminal of the 22nd transistor M22 is coupled to the light emitting control terminal EM, a first terminal of the 22nd transistor M22 is coupled to the first terminal of the second driving transistor DT2 , and a second terminal of the 22nd transistor M22 is coupled to the first terminal of the first driving transistor DT1 .

[0190] During implementation, when the light-emitting control terminal EM is at a low level, the twenty-second transistor M22 is turned on, and the twenty-second transistor M22 is connected to the light-emitting device L through the first driving transistor DT1 and the first transistor M1, thereby providing the first current to the light-emitting device L. The light-emitting device L emits light under the combined action of the above-mentioned first current and the second current.

[0191] The working process of the pixel driving circuit in the embodiment of the present application is described in detail below with reference to FIG. 7 and FIG. 17 .

[0192] Timing T1 stage: RST = 0, Gate_1 = 1, Gate_2 = 1, EM = 1, HF = 1

[0193] When the signal at the reset signal terminal RST is at a low level, the eighth transistor M8 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the gate of the first driving transistor DT1 via the turned-on eighth transistor M8, thereby resetting the gate of the first driving transistor DT1. When the signal at the reset signal terminal RST is at a low level, the seventeenth transistor M17 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the gate of the second driving transistor DT2 via the turned-on seventeenth transistor M17, thereby resetting the gate of the second driving transistor DT2. When the signal at the reset signal terminal RST is at a low level, the nineteenth transistor M19 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the anode of the light-emitting device L via the turned-on nineteenth transistor M19, thereby resetting the anode of the light-emitting device L.

[0194] Timing T2 stage: RST = 1, Gate_1 = 0, Gate_2 = 1, EM = 1, HF = 1

[0195] When the first scan control terminal Gate_1 is at a low level, the second transistor M2 and the third transistor M3 are turned on, and the first data voltage of the first data signal terminal Data1 is provided to the gate of the first driving transistor DT1 via the turned-on third transistor M3, the first driving transistor DT1 and the second transistor M2. In order to ensure that the first data voltage continues to be provided to the light-emitting control sub-circuit 21 in the next timing, the first data voltage is stored through the second capacitor C2.

[0196] Timing T3 stage: RST = 1, Gate_1 = 1, Gate_2 = 0, EM = 1, HF = 1

[0197] When the second scan control terminal Gate_2 is at a low level, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the second data voltage of the second data signal terminal Data2 is provided to the gate of the second driving transistor DT2 via the turned-on eleventh transistor M11, the second driving transistor DT2 and the tenth transistor M10. In order to ensure that the second data voltage continues to be provided to the light-emitting control sub-circuit 21 in the next timing, the second data voltage is stored through the fourth capacitor C4.

[0198] Timing T4 stage: RST = 1, Gate_1 = 1, Gate_2 = 1, EM = 0, HF changes from 1 to 0. Usually, the duty cycle of HF is 10%

[0199] When the signal at the light-emitting control terminal EM is at a low level, the twentieth transistor M20 and the twenty-first transistor M21 are turned on, thereby conducting the circuit between the first power supply terminal LVDD and the light-emitting device L. When the duration control terminal HF is at a low level, the first transistor M1 is turned on, and the first drive current is converted into a first current through the turned-on first transistor M1, and the first current is supplied to the anode of the light-emitting device L. Simultaneously, a second current is also supplied to the anode of the light-emitting device L, and the light-emitting device L emits light under the combined action of the first and second currents.

[0200] The working process of the pixel driving circuit in the embodiment of the present application is described in detail below with reference to FIG11 and FIG18.

[0201] Timing t1 stage: RST = 0, Gate_1 = 1, Gate_2 = 1, Gate_3 = 1, EM = 1, HF = 1

[0202] When the signal at the reset signal terminal RST is at a low level, the eighth transistor M8 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the gate of the first driving transistor DT1 via the turned-on eighth transistor M8, thereby resetting the gate of the first driving transistor DT1. When the signal at the reset signal terminal RST is at a low level, the seventeenth transistor M17 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the gate of the second driving transistor DT2 via the turned-on seventeenth transistor M17, thereby resetting the gate of the second driving transistor DT2. When the signal at the reset signal terminal RST is at a low level, the nineteenth transistor M19 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the anode of the light-emitting device L via the turned-on nineteenth transistor M19, thereby resetting the anode of the light-emitting device L.

[0203] Timing t2 stage: RST = 1, Gate_1 = 0, Gate_2 = 1, Gate_3 = 0, EM = 1, HF = 1

[0204] When the first scan control terminal Gate_1 is at a low level, the fourth transistor M4 is turned on, and when the third scan control terminal Gate_3 is at a low level, the twelfth transistor M12 is turned on. The first data voltage at the third data signal terminal Data3 is provided to the gate of the first drive transistor DT1 via the turned-on twelfth transistor M12, the first drive transistor DT1, and the fourth transistor M4. To ensure that the first data voltage continues to be provided to the light-emitting control sub-circuit 21 in the next timing sequence, the first data voltage is stored by the second capacitor C2.

[0205] Timing t3 stage: RST = 1, Gate_1 = 1, Gate_2 = 0, Gate_3 = 0, EM = 1, HF = 1

[0206] When the second scan control terminal Gate_2 is at a low level, the thirteenth transistor M13 is turned on, and when the third scan control terminal Gate_3 is at a low level, the twelfth transistor M12 is turned on. The second data voltage of the third data signal terminal Data3 is provided to the gate of the second driving transistor DT2 via the turned-on twelfth transistor M12, the second driving transistor DT2, and the thirteenth transistor M13. To ensure that the second data voltage continues to be provided to the light-emitting control sub-circuit 21 in the next timing sequence, the second data voltage is stored by the fourth capacitor C4.

[0207] Timing t4 stage: RST = 1, Gate_1 = 1, Gate_2 = 1, Gate_3 = 1, EM = 0, HF changes from 1 to 0. Usually, the duty cycle of HF is 10%

[0208] When the signal at the light-emitting control terminal EM is at a low level, the twentieth transistor M20 and the twenty-first transistor M21 are turned on, thereby conducting the circuit between the first power supply terminal LVDD and the light-emitting device L. When the duration control terminal HF is at a low level, the first transistor M1 is turned on, and the first drive current is converted into a first current through the turned-on first transistor M1 and supplied to the anode of the light-emitting device L. Simultaneously, the second current generated by the second drive transistor DT2 is also supplied to the anode of the light-emitting device L. The light-emitting device L emits light under the combined action of the first and second currents.

[0209] The working process of the pixel driving circuit in the embodiment of the present application is described in detail below with reference to FIG15 and FIG19.

[0210] Timing tt1 stage: RST = 0, Gate_1 = 1, Gate_2 = 1, Gate_3 = 1, EM = 1, HF = 1

[0211] When the signal at the reset signal terminal RST is at a low level, the eighth transistor M8 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the gate of the first driving transistor DT1 via the turned-on eighth transistor M8, thereby resetting the gate of the first driving transistor DT1. When the signal at the reset signal terminal RST is at a low level, the seventeenth transistor M17 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the gate of the second driving transistor DT2 via the turned-on seventeenth transistor M17, thereby resetting the gate of the second driving transistor DT2. When the signal at the reset signal terminal RST is at a low level, the nineteenth transistor M19 is turned on, and the initialization signal at the initialization signal terminal Vinit is provided to the anode of the light-emitting device L via the turned-on nineteenth transistor M19, thereby resetting the anode of the light-emitting device L.

[0212] Timing tt2 stage: RST = 1, Gate_1 = 1, Gate_2 = 0, Gate_3 = 0, EM = 1, HF = 1

[0213] When the second scan control terminal Gate_2 is at a low level, the fifth transistor M5 is turned on. When the third scan control terminal Gate_3 is at a low level, the fourteenth transistor M14 is turned on. The first data voltage of the third data signal terminal Data3 is provided to the first capacitor C1 via the turned-on fourteenth transistor M14 and the turned-on fifth transistor M5. To ensure that the first data voltage continues to be provided to the first drive transistor DT1 in the next timing sequence, the first data voltage is stored by the first capacitor C1. The second data voltage of the third data signal terminal Data3 is provided to the third capacitor C3. To ensure that the second data voltage continues to be provided to the second drive transistor DT2 in the next timing sequence, the second data voltage is stored by the third capacitor C3.

[0214] Timing tt3 stage: RST = 1, Gate_1 = 0, Gate_2 = 1, Gate_3 = 1, EM = 0, HF changes from 1 to 0. Usually, the duty cycle of HF is 10%

[0215] When the first scan control terminal Gate_1 is at a low level, the sixth transistor M6, the seventh transistor M7, the fifteenth transistor M15, and the sixteenth transistor M16 are turned on. The second data voltage stored in the third capacitor C3 is provided to the gate of the second drive transistor DT2 via the turned-on fifteenth transistor M15, the second drive transistor DT2, and the sixteenth transistor M16. To ensure that the second data voltage continues to be provided to the light-emitting control sub-circuit 21 in the next timing sequence, the second data voltage is stored via the fourth capacitor C4. Simultaneously, the first data voltage stored in the first capacitor C1 is written to the gate of the first drive transistor DT1 via the turned-on sixth transistor M6, the first drive transistor DT1, and the seventh transistor M7. To ensure that the first data voltage continues to be provided to the light-emitting control sub-circuit 21 in the next timing sequence, the first data voltage is stored via the second capacitor C2.

[0216] When the signal at the light-emitting control terminal EM is at a low level, the 20th transistor M20, the 21st transistor M21, and the 22nd transistor M22 are turned on, thereby conducting the circuit between the first power supply terminal LVDD and the light-emitting device L. When the duration control terminal HF is at a low level, the first transistor M1 is turned on, and the first drive current is converted into the first current through the turned-on first transistor M1 and supplied to the anode of the light-emitting device L. Simultaneously, the second current generated by the second drive transistor DT2 is also supplied to the anode of the light-emitting device L. The light-emitting device L emits light under the combined action of the first current and the second current.

[0217] Based on the same inventive concept, an embodiment of the present application provides a display panel comprising any of the above-mentioned pixel driving circuits.

[0218] In the embodiments of the present invention, the display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display panel are well understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting the present invention.

[0219] Based on the same inventive concept, an embodiment of the present application provides a light emitting control method applied to any of the above-mentioned pixel driving circuits, as shown in FIG20 , including:

[0220] Step 201: the control circuit 1 generates a first current input to the anode of the light-emitting device L according to a first data voltage.

[0221] During the implementation process, after the first data voltage is written into the gate of the first driving crystal of the control circuit 1, the first driving transistor DT1 generates a first driving current according to the first data voltage, and converts the first driving current into a first current under the action of the duration control terminal HF, and the above-mentioned first current is further provided to the anode of the light-emitting device L.

[0222] Step 202: The pixel circuit 2 generates a second current input to the anode of the light emitting device L according to the second data voltage.

[0223] During implementation, after the second data voltage is written into the gate of the second driving transistor of the pixel circuit 2 , the second driving transistor DT2 generates a second current according to the second data voltage, and the second current is further provided to the anode of the light emitting device L.

[0224] Step 203: the light emitting device L emits light under the combined effect of the first current and the second current.

[0225] When the light emitting control terminal EM is at an effective level, the light emitting device L emits light under the combined action of the first current and the second current.

[0226] In summary, the embodiments of the present application provide a pixel driving circuit, a display panel, and a light-emitting control method. The pixel driving circuit includes: a control circuit, a pixel circuit, and a light-emitting device. The control circuit is coupled to the anode of the light-emitting device, and the control circuit is configured to generate a first current input to the anode of the light-emitting device according to a first data voltage. The pixel circuit is coupled to the anode of the light-emitting device, and the pixel circuit is configured to generate a second current input to the anode of the light-emitting device according to a second data voltage. The light-emitting device is configured to emit light under the combined action of the first current and the second current. The above-mentioned control circuit and pixel circuit jointly provide current to the light-emitting device, thereby avoiding a large current difference in the pixel driving circuit during the high and low grayscale conversion process, thereby ensuring the color consistency of the display panel during the grayscale transition, and improving the display effect of the display panel.

[0227] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program product systems. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0228] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0229] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0230] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0231] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A pixel driving circuit, wherein: include: Control circuits, pixel circuits and light-emitting devices; The control circuit is coupled to the anode of the light emitting device, and the control circuit is configured to generate a first current input to the anode of the light emitting device according to a first data voltage; The pixel circuit is coupled to the anode of the light emitting device, and the pixel circuit is configured to generate a second current input to the anode of the light emitting device according to a second data voltage; The light emitting device is configured to emit light under the combined effect of the first current and the second current.

2. The pixel driving circuit according to claim 1, wherein: The control circuit includes: a first driving transistor, a first data writing subcircuit and a time length control subcircuit; The first data writing sub-circuit is coupled to the gate of the first driving transistor and is configured to provide a first data voltage to the gate of the first driving transistor in response to a signal from the first scanning control terminal; The second end of the first driving transistor is coupled to the anode of the light emitting device via the duration control sub-circuit, and is configured to generate a first driving current according to the first data voltage; The duration control subcircuit is coupled to the anode of the light-emitting device, and is configured to generate the first current according to the first driving current in response to a signal at the duration control terminal, and provide the first current to the anode of the light-emitting device.

3. The pixel driving circuit according to claim 2, wherein: The duration control subcircuit includes: a first transistor; The control end of the first transistor is coupled to the duration control end, the first end of the first transistor is coupled to the second end of the first driving transistor, and the second end of the first transistor is coupled to the anode of the light emitting device.

4. The pixel driving circuit according to claim 2, wherein: The first data writing sub-circuit includes: a second transistor and a third transistor; The control terminal of the second transistor is coupled to the first scan control terminal, and the second transistor The first end of the second transistor is coupled to the second end of the first driving transistor, and the second end of the second transistor is coupled to the gate of the first driving transistor; The control end of the third transistor is coupled to the first scan control end, the first end of the third transistor is coupled to the first end of the first driving transistor, and the second end of the third transistor is coupled to the first data signal end.

5. The pixel driving circuit according to claim 2, wherein: The first data writing sub-circuit includes: a fourth transistor; The control end of the fourth transistor is coupled to the first scan control end, the first end of the fourth transistor is coupled to the second end of the first driving transistor, and the second end of the fourth transistor is coupled to the gate of the first driving transistor.

6. The pixel driving circuit according to claim 2, wherein: The first data writing sub-circuit includes: a fifth transistor, a first capacitor, a sixth transistor and a seventh transistor; The control terminal of the fifth transistor is coupled to the second scan control terminal, the first terminal of the fifth transistor is coupled to the pixel circuit, and the second terminal of the fifth transistor is coupled to the first terminal of the first capacitor; The second terminal of the first capacitor is coupled to the first power supply terminal; A control terminal of the sixth transistor is coupled to the first scan control terminal, a first terminal of the sixth transistor is coupled to the first terminal of the first capacitor, and a second terminal of the sixth transistor is coupled to the first terminal of the first driving transistor; The control end of the seventh transistor is coupled to the first scan control end, the first end of the seventh transistor is coupled to the second end of the first driving transistor, and the second end of the seventh transistor is coupled to the gate of the first driving transistor.

7. The pixel driving circuit according to any one of claims 2 to 6, wherein: The control circuit further includes: a second capacitor; A first terminal of the second capacitor is coupled to the first power supply terminal, and a second terminal of the second capacitor is coupled to the gate of the first driving transistor.

8. The pixel driving circuit according to any one of claims 2 to 6, wherein: The control circuit further includes: a first reset subcircuit; The first reset sub-circuit is coupled to the gate of the first driving transistor and is configured to provide a reset signal to the gate of the first driving transistor in response to a signal at a reset signal terminal.

9. The pixel driving circuit according to claim 8, wherein: The first reset sub-circuit includes: an eighth transistor; The control terminal of the eighth transistor is coupled to the reset signal terminal, the first terminal of the eighth transistor is coupled to the gate of the first driving transistor, and the second terminal of the eighth transistor is coupled to the initialization signal terminal.

10. The pixel driving circuit according to claim 8, wherein: The first reset sub-circuit includes: a ninth transistor; The control terminal of the ninth transistor is coupled to the reset signal terminal, the first terminal of the ninth transistor is coupled to the gate of the first driving transistor, and the second terminal of the ninth transistor is coupled to the cathode of the light emitting device.

11. The pixel driving circuit according to any one of claims 1 to 10, wherein: The pixel circuit includes: a second driving transistor, a second data writing subcircuit and a light emitting control subcircuit; The second data writing sub-circuit is coupled to the gate of the second driving transistor and is configured to provide a second data voltage to the gate of the second driving transistor in response to a signal from the second scan control terminal; The second end of the second driving transistor is coupled to the anode of the light emitting device via the light emitting control sub-circuit, and is configured to generate the second current according to the second data voltage; The light emitting control subcircuit is coupled to the first power supply terminal and the anode of the light emitting device, and is configured to provide the second current generated by the second driving transistor to the light emitting device in response to a signal from the light emitting control terminal.

12. The pixel driving circuit according to claim 11, wherein: The second data writing sub-circuit includes: a tenth transistor and an eleventh transistor; The control terminal of the tenth transistor is coupled to the second scan control terminal, the first terminal of the tenth transistor is coupled to the gate of the second drive transistor, and the second terminal of the tenth transistor is coupled to the gate of the first drive transistor. The second terminal of the second driving transistor is coupled; The control end of the eleventh transistor is coupled to the second scan control end, the first end of the eleventh transistor is coupled to the second data signal end, and the second end of the eleventh transistor is coupled to the first end of the second driving transistor.

13. The pixel driving circuit according to claim 11, wherein: The second data writing sub-circuit includes: a twelfth transistor and a thirteenth transistor; The control terminal of the twelfth transistor is coupled to the third scan control terminal, the first terminal of the twelfth transistor is coupled to the third data signal terminal, and the second terminal of the twelfth transistor is coupled to the first terminal of the second driving transistor; The control end of the thirteenth transistor is coupled to the second scan control end, the first end of the thirteenth transistor is coupled to the gate of the second driving transistor, and the second end of the thirteenth transistor is coupled to the second end of the second driving transistor.

14. The pixel driving circuit according to claim 11, wherein: The second data writing sub-circuit includes: a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The control terminal of the fourteenth transistor is coupled to the third scan control terminal, the first terminal of the fourteenth transistor is coupled to the third data signal terminal, and the second terminal of the fourteenth transistor is coupled to the first terminal of the fifteenth transistor; The control terminal of the fifteenth transistor is coupled to the first scan control terminal, and the second terminal of the fifteenth transistor is coupled to the first terminal of the second driving transistor; The control end of the sixteenth transistor is coupled to the first scan control end, the first end of the sixteenth transistor is coupled to the gate of the second driving transistor, and the second end of the sixteenth transistor is coupled to the second end of the second driving transistor.

15. The pixel driving circuit according to any one of claims 11 to 14, wherein: The control circuit further includes: a second reset subcircuit; The second reset sub-circuit is coupled to the gate of the second driving transistor and is configured to provide a reset signal to the gate of the second driving transistor in response to a signal at a reset signal terminal.

16. The pixel driving circuit according to claim 15, wherein: The second reset sub-circuit includes: a seventeenth transistor; The control terminal of the seventeenth transistor is coupled to the reset signal terminal, the first terminal of the seventeenth transistor is coupled to the gate of the second driving transistor, and the second terminal of the seventeenth transistor is coupled to the initialization signal terminal or the cathode of the light emitting device.

17. The pixel driving circuit according to claim 2, wherein: Also included: an eighteenth transistor; The control terminal of the eighteenth transistor is coupled to the light emitting control terminal, the first terminal of the eighteenth transistor is coupled to the anode of the light emitting device, and the second terminal of the eighteenth transistor is coupled to the second terminal of the first transistor.

18. The pixel driving circuit according to claim 14, wherein: Also included: a third capacitor; A first terminal of the third capacitor is coupled to the first power supply terminal, and a second terminal of the third capacitor is coupled to the second terminal of the fourteenth transistor.

19. The pixel driving circuit according to any one of claims 11 to 18, wherein: Also included: a nineteenth transistor; The control terminal of the nineteenth transistor is coupled to the reset signal terminal, the first terminal of the nineteenth transistor is coupled to the initialization signal terminal, and the second terminal of the nineteenth transistor is coupled to the anode of the light emitting device.

20. A display panel, wherein: The method comprises the pixel driving circuit according to any one of claims 1 to 19.

21. A light emitting control method applied to the pixel driving circuit according to any one of claims 1 to 19, wherein: include: The control circuit generates a first current input to the anode of the light emitting device according to the first data voltage; The pixel circuit generates a second current input to the anode of the light emitting device according to the second data voltage; The light emitting device emits light under the combined action of the first current and the second current.

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