Instruction processing method and apparatus, processor, and computer-readable storage medium

Abstract

Embodiments of the present disclosure provide an instruction processing method and apparatus, a processor, and a computer-readable storage medium. The instruction processing method comprises: acquiring inter-thread resource contention information of a plurality of threads being processed in a processor, so as to determine at least two threads that have resource contention from among the plurality of threads; determining candidate threads to be arbitrated for scheduling in a current operation cycle from among the plurality of threads, wherein the candidate threads do not simultaneously comprise the at least two threads that have resource contention; and determining a target thread to be scheduled in the current operation cycle from among the candidate threads. By avoiding simultaneous scheduling of threads having resource contention, the instruction processing method improves instruction execution parallelism and resource utilization efficiency of the processor based on simultaneous multithreading technology.

Description

Instruction processing method and device, processor and computer-readable storage medium

[0001] This application claims priority to Chinese Patent Application No. 202410350133.5 filed on March 26, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an instruction processing method and apparatus, a processor, and a computer-readable storage medium. Background Art

[0003] Modern, multi-issue, high-performance CPUs (Central Processing Units) include at least one processor core, each of which has multiple execution units to execute instructions. For example, the instruction execution pipeline consists of five stages: instruction fetch (IF), decode (ID), execute (EX), access memory (MEM), and write back (WB), which updates the result of instruction execution to registers.

[0004] In order to improve the parallelism of instruction execution in the processor, the processor can use simultaneous multithreading (SMT) technology, so that the pipeline structure (also referred to as "pipeline") used for instruction execution in the processor can support the simultaneous execution of two or more (hardware) threads. For example, an SMT processor can be SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads), or SMT8 (supporting up to eight concurrent threads). When a single-threaded processor is running, multiple execution units inside the processor may be idle due to stalls such as cache misses. For processors using SMT technology, even when a thread is paused, other threads can continue to use these hardware resources. This improves the utilization of hardware resources, avoids idling, and improves processor throughput and performance-power ratio.

[0005] However, as the number of threads in an SMT processor increases, competition for shared resources between threads becomes more intense. This resource competition can weaken the parallelism of multiple threads, reducing processor performance and resource utilization. Therefore, alleviating resource competition between threads and improving parallelism have become important research directions in simultaneous multithreaded processors.

[0006] Summary of the Invention

[0007] At least one embodiment of the present disclosure provides an instruction processing method, comprising: obtaining inter-thread resource conflict information of multiple threads being processed in a processor to determine at least two threads having resource conflicts among the multiple threads; determining, from the multiple threads, candidate threads to be arbitrated for scheduling in a current operation cycle, wherein the candidate threads do not simultaneously include the at least two threads having resource conflicts; and determining, from the candidate threads, a target thread to be scheduled in the current operation cycle.

[0008] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the candidate thread is selected from the multiple threads and is a thread that is in a schedulable state in the current operation cycle.

[0009] For example, in the instruction processing method provided in at least one embodiment of the present disclosure, the candidate thread is further selected from threads having a thread priority higher than a preset priority among the multiple threads.

[0010] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: selecting a thread with a higher priority from the at least two threads having resource conflicts as the candidate thread.

[0011] For example, in the instruction processing method provided by at least one embodiment of the present disclosure, the at least two threads with resource conflicts have the resource conflicts for the first type of resources in the processor, and the alternative threads are arbitrated for scheduling in the current operation cycle based on the allocation of the first type of resources.

[0012] For example, in the instruction processing method provided in at least one embodiment of the present disclosure, obtaining inter-thread resource conflict information of multiple threads processed in the processor includes: obtaining the inter-thread resource conflict information through information based on resource competition between the multiple threads recorded by multiple counters within a first time.

[0013] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: after obtaining inter-thread resource conflict information of multiple threads processed in the processor, marking the flag bits of the at least two threads having resource conflicts.

[0014] For example, in the instruction processing method provided in at least one embodiment of the present disclosure, the candidate threads are determined by using flag bits corresponding to the multiple threads, so that the candidate threads do not simultaneously include the at least two threads with resource conflicts.

[0015] For example, the instruction processing method provided by at least one embodiment of the present disclosure further includes: clearing the mark bits of the multiple threads before marking the mark bits of the threads having the resource conflict.

[0016] For example, the instruction processing method provided by at least one embodiment of the present disclosure includes: after marking the flag bit of the thread having the resource conflict, clearing the multiple counters.

[0017] At least one embodiment of the present disclosure also provides an instruction processing device, comprising: an acquisition module, configured to acquire inter-thread resource conflict information of multiple threads processed in a processor to determine at least two threads having resource conflicts between the multiple threads; and a scheduling module, configured to determine, from the multiple threads, alternative threads that are arbitrated for scheduling in a current operation cycle, and determine, from the alternative threads, a target thread to be scheduled in the current operation cycle, wherein the alternative threads do not simultaneously include the at least two threads having resource conflicts.

[0018] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the candidate thread is selected from the multiple threads and is a thread that is in a schedulable state in the current operation cycle.

[0019] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the candidate thread is further selected from threads having a thread priority higher than a preset priority among the multiple threads.

[0020] For example, in the instruction processing device provided in at least one embodiment of the present disclosure, the scheduling module is further configured to select a thread with a higher priority from the at least two threads having resource conflicts as a candidate thread.

[0021] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the at least two threads with resource conflicts have the resource conflicts for the first type of resources in the processor; the scheduling module enables the alternative threads to be arbitrated for scheduling in the current operation cycle based on the allocation of the first type of resources.

[0022] For example, the instruction processing device provided by at least one embodiment of the present disclosure also includes: a conflict detection module, including multiple counters, and configured to obtain the resource conflict information between the threads through the information on resource competition between the multiple threads recorded by the multiple counters within the first time.

[0023] For example, the instruction processing device provided by at least one embodiment of the present disclosure further includes: a marking module configured to mark the flag bits of at least two threads having resource conflicts after obtaining inter-thread resource conflict information of multiple threads processed in the processor.

[0024] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the marking module is further configured to clear the mark bits of the multiple threads before marking the mark bits of the threads having the resource conflict.

[0025] For example, in the instruction processing device provided by at least one embodiment of the present disclosure, the conflict detection module is further configured to clear the multiple counters after marking the flag bits of the at least two threads having resource conflicts.

[0026] At least one embodiment of the present disclosure further provides an instruction processing device, comprising: a processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to the processing unit; the processing unit executes the computer-readable instructions stored in the memory to implement the instruction processing method provided in any of the above embodiments.

[0027] At least one embodiment of the present disclosure further provides a processor, an instruction processing device provided according to at least one embodiment of the present disclosure.

[0028] At least one embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the instruction processing method provided by any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0030] FIG1 shows a schematic diagram of a pipeline of a processor core;

[0031] FIG2 shows a schematic diagram of a thread scheduling process of an SMT4 processor;

[0032] FIG3A shows an example of performing shared resource arbitration during the renaming phase;

[0033] FIG3B shows another example of performing shared resource arbitration during the renaming phase;

[0034] FIG4 is a schematic flow chart showing an instruction processing method according to at least one embodiment of the present disclosure;

[0035] FIG5 shows a schematic diagram of obtaining inter-thread conflict information provided by at least one embodiment of the present disclosure;

[0036] FIG6 shows a schematic structural diagram of an instruction processing device provided by at least one embodiment of the present disclosure;

[0037] FIG7 shows a schematic structural diagram of another instruction processing device provided by at least one embodiment of the present disclosure;

[0038] FIG8 is a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure; and

[0039] FIG9 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] In this disclosure, an operation cycle can be, for example, a clock cycle or a machine cycle, or any other time period in a processor's instruction pipeline that is used to complete a single operation. The execution of an instruction consists of several stages, each of which completes a basic operation (e.g., instruction fetch, memory read, memory write, etc.). The time required to complete a basic operation is called a machine cycle, also known as a CPU cycle.

[0043] In order to improve the performance of the processor core, the processor core can use a pipeline approach, that is, the entire process of an instruction from extraction, decoding, execution, and result writing is divided into multiple pipeline stages, and an instruction can only be in one of the pipeline stages in one operation cycle; and the processor core can make multiple instructions run in different pipeline stages.

[0044] FIG1 shows a schematic diagram of a pipeline of a processor core, where the dashed line with an arrow represents a redirected instruction flow.

[0045] As shown in Figure 1, the processor cores (e.g., CPU cores) of single-core or multi-core processors utilize pipelining technology to enhance instruction-level parallelism. The pipeline within the processor core includes multiple stages, such as branch prediction, which predicts the program counter (PC), performs instruction fetch, decode, dispatch and rename, execute, and retire based on the PC. Waiting queues are set between each pipeline stage as needed, typically in a first-in, first-out (FIFO) configuration. For example, after the branch prediction unit, there's a branch prediction (BP) FIFO queue to store branch prediction results; after the instruction fetch unit, there's an instruction cache (IC) FIFO to cache fetched instructions; after the instruction decode unit, there's a decode (DE) FIFO to cache decoded instructions; and after the instruction dispatch and rename unit, there's a finish (RT) FIFO to cache instructions waiting for completion confirmation. The processor core's pipeline also includes an instruction queue to cache instructions waiting for execution by the instruction execution unit after dispatch and renaming.

[0046] As mentioned above, in order to improve the parallelism of instruction execution in the processor, the processor can also adopt simultaneous multi-threading (SMT) technology. The processor's pipeline structure for instruction execution (also referred to as "pipeline") can support the simultaneous execution of two or more (hardware) threads, for example, it can be SMT2 (supporting up to two concurrent threads), SMT4 (supporting up to four concurrent threads) or SMT8 (supporting up to eight concurrent threads). In the pipeline of a processor that supports simultaneous multi-threading technology, the computing resources in the processor are shared by multiple threads. For example, each thread can have its own independent logical register, but the multiple physical registers in the processor are shared by multiple threads. Among the queues of various control functions in the pipeline, some can be shared by multiple threads, such as the instruction scheduling queue, and others can be statically divided between multiple threads, such as the instruction reordering queue. Simultaneous multi-threading technology can use the parallelism between threads to improve pipeline resource utilization.

[0047] Furthermore, processors that utilize simultaneous multithreading (SMT) technology can operate in either SMT or single-threaded mode. For example, in SMT mode, when one thread encounters a wait state, other threads can continue executing, effectively improving hardware resource utilization and thereby enhancing the multithreaded processing capabilities, overall performance, and performance-per-watt ratio of the CPU core.

[0048] For example, FIG2 shows a schematic diagram of a thread scheduling process of an SMT4 processor.

[0049] Take the SMT4 processor, which can schedule two threads per operation cycle, as an example. As shown in Figure 2, for the scheduling of a queue shared by multiple threads in a pipeline stage, four threads, T0-T3, are stored in a first-in-first-out (FIFO) queue. The four threads are ranked from high to low priority from the head to the tail of the FIFO queue. In operation cycle 0, the FIFO queue initially stores the thread priorities T0, T1, T2, and T3, and all four threads are schedulable. When threads T0 and T1 are successfully scheduled, the FIFO queue status is updated to T2, T3, T0, and T1. In operation cycle 1, the thread priorities are T2, T3, T0, and T1. Since thread T2 is unschedulable (indicated by the gray box in Figure 2), the schedulable threads are T3, T0, and T1. When threads T3 and T0 are successfully scheduled, the FIFO queue status is updated to T2, T1, T3, and T0. The subsequent thread scheduling process is similar and will not be described here.

[0050] For a simultaneous multithreaded processor (hereinafter also referred to as an SMT processor), when the schedulable shared resources meet the needs of all threads to be scheduled (such as thread T0 and thread T1), the threads to be scheduled can be scheduled simultaneously; otherwise, there is a resource conflict between the threads to be scheduled, and shared resource arbitration is required to determine the target thread for scheduling. For example, if the shared resource punching scheme is to select the thread with a high priority among the threads to be scheduled for scheduling, the execution of the remaining threads to be scheduled with a low priority will be suspended.

[0051] For example, the resources shared by multiple threads in an SMT processor include but are not limited to: execution units (e.g., arithmetic logic units, floating-point operation units, etc.), caches (e.g., first-level data cache, first-level instruction cache, second-level data cache, etc.), predicted execution path caches during branch prediction, physical registers, etc.

[0052] For example, during the renaming phase, the SMT processor dynamically allocates physical register resources within the SMT processor to the architectural registers in the thread to be scheduled. Within the processor, the number of physical registers used for renaming operations is generally greater than the number of architectural registers. Architectural registers include, but are not limited to, fixed-point architectural registers and floating-point architectural registers, wherein fixed-point architectural registers are used for operand operations of fixed-point instructions, and floating-point architectural registers are used for operand operations of floating-point instructions. When allocating physical register resources, the type of architectural register corresponds to the type of physical register. For example, a fixed-point architectural register requires a corresponding fixed-point physical register resource (IntPReg), and a floating-point architectural register requires a corresponding floating-point physical register resource. During the renaming phase, the shared resources allocated to the thread to be scheduled also include resources other than physical register resources. In the following Figures 3A and 3B, only fixed-point physical register resources are used as an example to illustrate the thread arbitration process.

[0053] FIG. 3A shows an example of performing shared resource arbitration during the renaming phase.

[0054] As shown in Figure 3A, during the current operation cycle of the rename phase, the threads to be scheduled include thread T0 and thread T1. Before being scheduled to perform the rename operation, shared resource arbitration must be performed on thread T0 and thread T1. Thread T0 requires three fixed-point physical registers (IntPReg), and thread T1 requires four fixed-point physical registers. The current available number of fixed-point physical register resources is 8, which is greater than the number of fixed-point physical registers required to schedule both threads T0 and T1 simultaneously (i.e., 3 + 4 ≤ 8). Therefore, there is no resource conflict between threads T0 and T1, and threads T0 and T1 can be scheduled simultaneously to perform the rename operation.

[0055] For example, FIG3B shows another example of performing shared resource arbitration during the renaming phase.

[0056] As shown in Figure 3B, in the current operation cycle of the renaming phase, the threads to be scheduled include thread T0 and thread T1. Thread T0 requires 3 fixed-point physical registers, and thread T1 requires 4 fixed-point physical registers. The current number of available fixed-point physical registers is 6, which is less than the number of fixed-point physical registers required to schedule thread T0 and thread T1 simultaneously, that is, 3+4>6. Therefore, there is a resource conflict between thread T0 and thread T1, and thread T0 and thread T1 cannot be scheduled at the same time to perform the renaming operation. When the arbitration logic selects the thread to be scheduled with a higher priority for scheduling, since the priority of thread T0 is higher than that of thread T1, thread T0 is selected to perform the renaming operation, and thread T1 is suspended from scheduling. On the other hand, the remaining 3 physical registers are not used, resulting in a decrease in thread parallelism in this operation cycle and a decrease in the utilization rate of fixed-point physical registers.

[0057] The inventors of the present disclosure noticed that in a simultaneous multi-threaded processor with dynamic resource sharing, multiple threads compete for the hardware resources in the SMT processor in their respective pipeline stages, and as the number of threads increases, the resource competition between threads becomes more intense, resulting in a weakening of the parallelism of multiple threads and a reduction in the performance and resource utilization of the processor.

[0058] To address at least one or more of the above deficiencies, one or more embodiments of the present disclosure provide an instruction processing method and apparatus, a processor, and a computer-readable storage medium.

[0059] The instruction processing method includes: obtaining inter-thread resource conflict information of multiple threads being processed in a processor to determine at least two threads with resource conflicts among the multiple threads; determining candidate threads to be arbitrated for scheduling in a current operation cycle from the multiple threads, wherein the candidate threads do not simultaneously include the at least two threads with resource conflicts; and determining a target thread to be scheduled in the current operation cycle from the candidate threads. By identifying inter-thread resource conflict information of multiple threads, the method avoids arbitrating at least two threads with intense resource competition or resource conflicts in the same operation cycle, thereby reducing the problem of thread execution being suspended due to resource conflicts and thereby improving the parallelism of multiple threads and the utilization rate of shared resources.

[0060] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0061] FIG4 shows a flow chart of an instruction processing method provided by at least one embodiment of the present disclosure. The instruction processing method includes steps S410 to S430 .

[0062] Step S410: obtaining inter-thread resource conflict information of a plurality of threads being processed in a processor to determine at least two threads having resource conflicts among the plurality of threads.

[0063] Step S420: determining candidate threads to be arbitrated for scheduling in the current operation cycle from a plurality of threads, wherein the candidate threads do not simultaneously include at least two threads having resource conflicts.

[0064] Step S430: Determine a target thread to be scheduled in the current operation cycle from the candidate threads.

[0065] For example, the inter-thread resource conflict information records information about the degree of resource conflict between multiple threads being processed in the processor, such as information about which threads experienced resource conflicts over a period of time (e.g., 1000 operating cycles) and which resulted in one or more threads being suspended. For example, the at least two threads determined to have resource conflicts based on the inter-thread resource conflict information may be threads with the highest probability of resource conflicts or the most conflicts occurring over the previous period of time.

[0066] For example, the candidate threads are selected from multiple threads that are in a schedulable state in the current operation cycle. During the process of the processor scheduling instructions, not all threads in each operation cycle are in a schedulable state. For example, in the case where there is a resource conflict between at least two threads including a first thread, the first thread may fail due to speculative execution of a jump instruction and perform a re-fetch operation in the current operation cycle. At this time, the first thread is in an unschedulable state, so that the candidate threads for the current operation cycle do not include the first thread.

[0067] For example, the alternative thread can be further selected from threads with a thread priority higher than a preset priority among multiple threads. For example, in digital integrated circuit design, RTL (Register-Transfer Level) design timing constraints are causal requirements for circuit design in terms of timing, which mainly define the time limit required for data to be transferred from one register to another within the circuit to ensure the correctness and timeliness of data transmission in the entire design. Due to the existence of RTL design timing constraints, not all threads in the schedulable state in the current operation cycle will be arbitrated, and threads with a priority higher than the preset priority among the schedulable threads are usually selected for arbitration. For example, assuming the priority is 1-5, 5 represents the highest priority, then the preset priority can be determined as 3, and the threads with a priority higher than 3 among the schedulable threads are selected as alternative threads for arbitration.

[0068] It should be noted that the arbitration in the embodiments of the present disclosure may target a single resource required by a thread at the same stage, or may target multiple resources required by a thread at the same stage (for example, taking into account two or more resources), and the present disclosure does not impose any restrictions on this.

[0069] The instruction processing method provided by at least one embodiment of the present disclosure may further include: selecting a thread with a higher priority from among the at least two threads experiencing a resource conflict as a candidate thread. For example, if the at least two threads experiencing a resource conflict include a first thread and a second thread, and both the first thread and the second thread are in a schedulable state and have a priority higher than a preset priority, the thread with the higher priority may be selected from among the first thread and the second thread as the candidate thread, and the other thread may be deselected in the current operation cycle.

[0070] For example, at least two threads with resource conflicts have resource conflicts for first-class resources in the processor, and the candidate threads are arbitrated for scheduling in the current operation cycle based on the allocation of the first-class resources. The first-class resources in the above embodiment can be any of the shared resources mentioned above, which will not be described in detail here.

[0071] For example, inter-thread resource conflict information of multiple threads processed in a processor can be obtained by using information about resource competition between multiple threads recorded by multiple counters within a first period of time.

[0072] For example, after obtaining inter-thread resource conflict information of multiple threads processed in a processor, the flag bits of at least two threads having resource conflicts are marked, and the marked information can be used subsequently.

[0073] For example, after marking the flag bit of the thread with resource conflict, multiple counters are cleared to perform new counting and statistics, thereby reflecting the status of multiple threads in the processor in relatively real time and avoiding delay or even failure of resource conflict information between threads.

[0074] FIG5 shows a schematic diagram of obtaining inter-thread conflict information provided by at least one embodiment of the present disclosure.

[0075] This embodiment takes a 4-thread simultaneous multithreading (SMT4) processor that supports two threads being arbitrated for scheduling as an example, and resource conflicts exist between the two threads. As shown in Figure 5, the SMT4 processor includes four threads, T0, T1, T2, and T3. The SMT4 processor includes a conflict detection module 510 for recording information about resource competition between multiple threads within a first time. For example, the first time can be 1000 operating cycles (e.g., cycle 0-cycle 999), and the embodiments of the present disclosure are not limited to this.

[0076] Since there are six possible combinations of resource contention between the four threads T0-T3, the conflict detection module 510 can use six counters 511 to record the number of resource contention events between each pair of threads. Here, PMC[0][1] represents the number of resource contention events between threads T0 and T1 recorded by the counters 511 corresponding to the two threads within 1000 operation cycles; PMC[0][2] represents the number of resource contention events between threads T0 and T2 recorded by the counters corresponding to the two threads within 1000 operation cycles. The meanings of PMC[0][3], PMC[1][2], PMC[1][3], and PMC[2][3] are similar to those of PMC[0][1] and PMC[0][2] and are not further described. For example, in operation cycle 0, when threads T0 and T1 compete for resources, causing thread T0 to be suspended, the values ​​of PMC[0][1] recorded by the counters 511 corresponding to threads T0 and T1 are incremented by 1. After 1000 operation cycles, the obtained competition times PMC[0][1]-PMC[2][3] between the four threads T0-T3 are the resource conflict information between threads.

[0077] It should be noted that the conflict detection module in the above embodiment ( FIG. 5 ) is used to detect a scenario in which a resource conflict exists between two threads, but the present disclosure is not limited thereto. For example, for an SMT4 processor, when detecting a scenario in which a resource conflict exists between three threads, there are four combinations of resource contention among the four threads. The conflict detection module can use four counters to record the number of resource contention occurrences between each of the three threads. As shown in FIG. 5 , after obtaining inter-thread resource conflict information, the two threads in which a resource conflict exists can be determined by comparing the number of contention times PMC[0][1]-PMC[2][3] between the four threads T0-T3. For example, among PMC[0][1]-PMC[2][3], the value of PMC[0][2] is the largest, indicating that in the past 1000 operation cycles, the number of resource competitions between thread T0 and thread T2 is the largest. In subsequent operation cycles, the probability that thread T0 or thread T2 is suspended due to resource conflicts is the largest. In this case, the flag bits of thread T0 and thread T2 can be marked so that the alternative threads do not include thread T0 and thread T2 at the same time.

[0078] For example, in one example, the priority list includes the flag bits of threads T0-T3, where the initial flag bit of each thread can be set to 2b'00. When marking the flag bits of threads T0 and T2, the initial flag bits 2b'00 of threads T0 and T2 can be updated to 2b'01, indicating that the conflict level between threads T0 and T2 is high (i.e., the conflict level between the two threads both marked as 01 is high), while the conflict level between either thread T0 or thread T2 and threads T1 and T3 is low (i.e., the conflict level between the two threads marked as 00 and 01 is low). After marking the flag bits of threads T0 and T2, the six counters 511 in the conflict detection module 510 are cleared to zero, and the six counters 511 are caused to re-record the number of resource contention events between threads T0-T3 in the next 1000 operation cycles, thereby obtaining new inter-thread resource conflict information.

[0079] In another example of the above embodiment, other threads with resource conflicts may be marked based on inter-thread resource conflict information. For example, among PMC[0][1]-PMC[2][3], the value of PMC[0][2] is the largest (e.g., 500), and the value of PMC[1][3] is the second largest (e.g., 300). In this case, the mark bits of threads T0 and T2 may be marked as 2b'01, and the mark bits of threads T1 and T3 may be marked as 2b'10, so that the candidate threads cannot include both threads T0 and T2, nor threads T1 and T3.

[0080] In an embodiment of the present disclosure, identifying threads with a high probability of resource conflicts is achieved based on the number of times that multiple threads compete for resources with each other. In other examples, this can also be achieved in other ways, and the present disclosure is not limited to this. For example, threads with a high probability of resource conflicts can be identified by the occupancy rate of each thread on a shared resource. For example, for a certain shared resource (such as a fixed-point physical register), in the current operation cycle, the occupancy rate of thread T0 is 40%, the occupancy rate of thread T1 is 40%, the occupancy rate of thread T2 is 0% (thread T2 does not use the shared resource), and the occupancy rate of thread T3 is 20%. When thread T0 and thread T1 are arbitrated as alternative threads, since threads T0 and thread T1 have a high demand for the shared resource in the current operation cycle, the shared resource that can be called may not be sufficient to meet the needs of threads T0 and T1 at the same time, which may result in only one thread being called to enter the next stage, while the other thread is temporarily called. Therefore, it can be determined that there is a high probability of resource conflict between threads T0 and T1, and the flag bits of threads T0 and T1 can be marked.

[0081] Therefore, in the instruction processing method provided in at least one embodiment of the present disclosure, candidate threads may also be determined by using thread flags, so that the candidate threads do not simultaneously include at least two threads with resource conflicts.

[0082] For example, the judgment logic for determining the candidate threads can be to select the candidate threads in descending order of priority, while skipping the threads whose mark bits are not 2b'00 and are the same as the mark bits of the selected highest priority thread. Referring to Figure 5, the value of PMC[0][2] is the largest, so thread T0 and thread T2 are determined to be two threads with resource conflicts. The SMT4 processor supports two threads to be arbitrated for scheduling. If in the current operation cycle, threads T0-T3 are all in a schedulable state, then two threads can be determined from threads T0-T3 as candidate threads. The priority list also includes the priority order of the threads. For example, in the 1001st operation cycle (i.e., cycle 1000), the priority order of the four threads T0-T3 from high to low is T0, T2, T1 and T3. According to the thread priority order, thread T0 has the highest priority, so thread T0 is determined to be one of the candidate threads. Thread T2 has the second-highest priority, but its flag bit is not 2b'00 and is identical to the flag bit 2b'01 of the already-selected, highest-priority thread T0. Therefore, when determining the second candidate thread in descending priority order, thread T2 is skipped. Thread T1 has the third-highest priority, and its flag bit is 2b'00, making it the second candidate thread. Therefore, the candidate threads in cycle 1000 are threads T0 and T1. During the subsequent thread scheduling process, the currently schedulable resources are likely greater than or equal to the sum of the resources required by threads T0 and T1, respectively. Therefore, threads T0 and T1 are scheduled as target threads.

[0083] The instruction processing method provided by at least one embodiment of the present disclosure may further include: clearing the flag bits of multiple threads before marking the flag bits of the threads having resource conflicts.

[0084] In one example of the present disclosure, for an SMT4 processor, the current mark bits of the four threads T0-T3 are 2b'01, 2b'00, 2b'01, and 2b'00, respectively. In the next 1000 operation cycles, the maximum value of the number of contentions between the four threads PMC[0][1]-PMC[2][3] is recorded as PMC[1][3]. Before marking the mark bits of threads T1 and T3, the current mark bits of threads T0-T3 (2b'01, 2b'00, 2b'01, and 2b'00) are all cleared, that is, all reset to 2b'00. Then, the mark bits of threads T1 and T3 are marked as 2b'01, so that the mark bits of threads T0-T3 are 2b'00, 2b'01, 2b'00, and 2b'01, respectively.

[0085] In another example of the present disclosure, before marking the flag bits of threads with resource conflicts, the flag bits of multiple threads may be partially cleared. For example, for an SMT4 processor, the current flag bits of four threads T0-T3 are 2b'01, 2b'10, 2b'01, and 2b'10, respectively. In the next 1000 operation cycles, the maximum value of the number of contentions between the four threads among PMC[0][1]-PMC[2][3] is recorded as PMC[0][1]. Before marking the mark bits of threads T0 and T1, the current mark bit of thread T0 (2b'01) can be retained, and only the current marks of threads T1-T3 are cleared to zero, and then the mark bit of thread T1 is marked as 2b'01; or, the current mark bits of threads T0 and thread T2 (both are 2b'01) can be retained, and only the current mark bits of threads T1 and thread T3 are cleared to zero, and then the mark bit of thread T1 is marked as 2b'01, so that the mark bits of threads T0, T1 and T2 are all 2b'01. In this way, any two threads among threads T0, T1 and T2 cannot be included in the candidate threads at the same time.

[0086] In another example of the present disclosure, whether to clear the mark bits of multiple threads can be determined based on the number of contention times between the multiple threads. For example, for an SMT4 processor, the current mark bits of the four threads T0-T3 are 2b'01, 2b'00, 2b'01, and 2b'00, respectively. In the next 1000 operation cycles, the number of contention times between the four threads PMC[0][1]-PMC[2][3] is recorded. The value of PMC[1][3] is the largest (e.g., 500), and the value of PMC[0][2] is the second largest (e.g., 300). Then, the current mark bits of thread 0 and thread 2 (both 2b'01) can be retained, the current mark bits of thread 1 and thread 3 (both 2b'00) can be cleared, and then the mark bits of thread 1 and thread 3 can be marked as 2b'10, so that the candidate threads cannot include thread T0 and thread T2 at the same time, nor can they include thread T1 and thread T4 at the same time.

[0087] There may be multiple marking rules for each thread based on the latest PMC array value or historical value, which can be designed according to the application scenario, requirements or design specifications, and this disclosure does not impose any restrictions on this.

[0088] It should be noted that in the above example, clearing the current mark bits of thread 1 and thread 3 (both 2b'00) must be performed first. This is because for processors with more than 4 threads, such as SMT6 processors and SMT8 processors, the current mark bits of thread 1 and thread 3 may be 2b'10 and 2b'00 respectively. The current mark bits of thread 1 and thread 3 both need to be cleared to avoid labeling errors.

[0089] It should be noted that the instruction processing method provided by the embodiment of the present disclosure is applicable to all stages in the instruction scheduling process where resource conflicts exist, including but not limited to the renaming stage.

[0090] FIG6 shows a schematic structural diagram of an instruction processing device provided by at least one embodiment of the present disclosure.

[0091] As shown in FIG6 , the instruction processing apparatus 600 includes an acquisition module 610 and a scheduling module 620. The acquisition module 610 is configured to acquire inter-thread resource conflict information for multiple threads being processed in the processor to determine at least two threads with resource conflicts among the multiple threads. The scheduling module 620 is configured to determine candidate threads to be arbitrated for scheduling in the current operation cycle from the multiple threads, and to determine a target thread to be scheduled in the current operation cycle from the candidate threads, wherein the candidate threads do not simultaneously include at least two threads with resource conflicts.

[0092] For example, the scheduling module 620 is configured to select the determined candidate thread from a plurality of threads that are in a schedulable state in the current operation cycle.

[0093] For example, the scheduling module 620 is configured to enable the determined candidate thread to be further selected from a thread having a thread priority greater than a preset priority among the multiple threads.

[0094] For example, the scheduling module 620 is further configured to select a thread with a higher priority from among at least two threads having resource conflicts as a candidate thread.

[0095] For example, at least two threads having resource conflicts have resource conflicts for first-category resources in the processor, and the scheduling module 620 enables candidate threads to be arbitrated for scheduling in the current operation cycle based on allocation of the first-category resources.

[0096] The instruction processing apparatus 600 of the above embodiment further includes a conflict detection module 630. The conflict detection module 630 includes multiple counters and is configured to obtain inter-thread resource conflict information based on resource contention information between multiple threads recorded by the multiple counters within a first period of time. The embodiments of the present disclosure do not limit the implementation of the counters.

[0097] For example, the instruction processing apparatus 600 of the above embodiment further includes a marking module (not shown in FIG6 ). The marking module is configured to, after obtaining inter-thread resource conflict information of multiple threads being processed in the processor, mark the flag bits of at least two threads that have resource conflicts. For example, the marking module is further configured to clear the flag bits of the multiple threads before marking the flag bits of the threads that have resource conflicts.

[0098] For example, after marking the flag bit of the thread having the resource conflict, the conflict detection module 630 is further configured to clear multiple counters.

[0099] For example, the scheduling module 620 is further configured to determine candidate threads by using the mark bits corresponding to the plurality of threads, so that the candidate threads do not simultaneously include at least two threads having resource conflicts.

[0100] The instruction processing device or the modules therein of the above embodiments of the present disclosure may be implemented by hardware, software, firmware or any combination thereof, and the embodiments of the present disclosure are not limited thereto.

[0101] FIG7 shows a schematic structural diagram of another instruction processing device provided by at least one embodiment of the present disclosure.

[0102] As shown in Figure 7, the instruction processing device 700 includes a processing unit 720 and a memory 710. The memory 710 stores computer-readable instructions and is in communication with the processing unit 720. The processing unit 720 executes the computer-readable instructions stored in the memory 710 to perform the instruction processing method provided by any embodiment of the present disclosure.

[0103] For example, the memory 710 and the processing unit 720 can communicate with each other directly or indirectly. For example, in some examples, as shown in FIG7 , the instruction processing device 700 may further include a system bus 730, and the memory 710 and the processing unit 720 may communicate with each other via the system bus 730. For example, the processing unit 720 may access the memory 710 via the system bus 730. For example, in other examples, components such as the memory 710 and the processing unit 720 may communicate via a network on chip (NOC) connection.

[0104] For example, the processing unit 720 can control other components in the instruction processing device to perform the desired functions. The processing unit 720 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU). It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc.

[0105] For example, the memory 710 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc.

[0106] For example, the memory 710 may store one or more computer-readable instructions, and the processing unit 720 may execute the computer-readable instructions to implement various functions. The computer-readable storage medium may also store various applications and various data, such as instruction processing code and various data used and / or generated by the application.

[0107] For example, when some computer instructions stored in the memory 710 are executed by the processing unit 720 , one or more steps in the instruction processing method described above may be performed.

[0108] For example, as shown in FIG7 , the instruction processing apparatus 700 may further include an input interface 740 that allows external devices to communicate with the instruction processing apparatus 700. For example, the input interface 740 may be used to receive instructions from an external computer device, from a user, etc. The instruction processing apparatus 700 may further include an output interface 750 that interconnects the instruction processing apparatus 700 and one or more external devices. For example, the instruction processing apparatus 700 may output commands to the external device through the output interface 750.

[0109] It should be noted that the instruction processing device provided in the embodiments of the present disclosure is exemplary rather than restrictive. According to actual application requirements, the instruction processing device may also include other conventional components or structures. For example, in order to realize the necessary functions of the instruction processing device, those skilled in the art may set other conventional components or structures according to the specific application scenarios, and the embodiments of the present disclosure do not limit this.

[0110] At least one embodiment of the present disclosure further provides a processor, such as an SMT processor, which includes the instruction processing device provided by any embodiment of the present disclosure. The SMT processor can support a maximum number of threads, such as 2, 4, or 8, and can be a single-core or multi-core processor. For example, the processor core can adopt a microarchitecture such as X86, ARM, or RISC-V, and can include one or more levels of cache, although the embodiments of the present disclosure are not limited thereto.

[0111] At least one embodiment of the present disclosure further provides a computer-readable storage medium.

[0112] FIG8 is a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.

[0113] For example, as shown in FIG8 , the computer-readable storage medium 800 stores computer-readable instructions 810 . When the computer-readable instructions 810 are executed by a computer (including a processor), the instruction processing method provided by any embodiment of the present disclosure can be implemented.

[0114] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 800. Some of the computer-readable instructions stored on the computer-readable storage medium 800 may be, for example, instructions for implementing one or more steps in the above-mentioned instruction processing method.

[0115] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a flash memory, or any combination thereof, or other suitable storage media. For example, the computer-readable storage medium 800 may include the memory 710 in the instruction processing device 700 described above.

[0116] At least some embodiments of the present disclosure further provide an electronic device, the electronic device comprising the processor of any of the above embodiments. Figure 9 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0117] The electronic devices in the embodiments of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0118] The electronic device 900 shown in FIG9 is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0119] For example, as shown in Figure 9, in some examples, the electronic device 900 includes a processor 901, which may include the processor of any of the above-mentioned embodiments, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 902 or the program loaded from the storage device 908 into the random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the computer system are also stored. The processor 901, ROM 902 and RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0120] For example, the following components may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 908 including, for example, a magnetic tape, hard disk, etc.; and a communication device 909, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 910 as needed, so that computer programs read therefrom can be installed into the storage device 908 as needed. Although FIG. 9 shows the electronic device 900 including various devices, it should be understood that implementation or inclusion of all of the devices shown is not required. More or fewer devices may alternatively be implemented or included.

[0121] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 909 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0122] In addition to the above exemplary explanations, the following points should be explained:

[0123] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0124] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0125] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A method for processing an instruction, comprising: Obtaining inter-thread resource conflict information of a plurality of threads processed in the processor to determine at least two threads having resource conflicts among the plurality of threads; Determining candidate threads to be arbitrated for scheduling in a current operation cycle from the plurality of threads, wherein the candidate threads do not simultaneously include the at least two threads having resource conflicts; as well as A target thread to be scheduled in the current operation cycle is determined from the candidate threads.

2. The instruction processing method according to claim 1, wherein: The candidate thread is selected from the plurality of threads and is a thread that is in a schedulable state in the current operation cycle.

3. The instruction processing method according to claim 2, wherein: The candidate thread is further selected from threads having a thread priority higher than a preset priority among the multiple threads.

4. The instruction processing method according to claim 1 , further comprising: A thread with a higher priority is selected from the at least two threads having resource conflicts as the candidate thread.

5. The instruction processing method according to claim 1, wherein: The at least two threads having resource conflicts have the resource conflicts for first-category resources in the processor, and the candidate threads are arbitrated for scheduling in the current operation cycle based on allocation of the first-category resources.

6. The instruction processing method according to any one of claims 1 to 5, wherein: The obtaining of inter-thread resource conflict information of multiple threads processed in the processor includes: The inter-thread resource conflict information is obtained by using information about resource competition between the multiple threads recorded by multiple counters within a first time period.

7. The instruction processing method according to claim 6, further comprising: After obtaining the inter-thread resource conflict information of the plurality of threads processed in the processor, the flag bits of the at least two threads having the resource conflict are marked.

8. The instruction processing method according to claim 7, wherein: The candidate threads are determined by using the mark bits corresponding to the multiple threads, so that the candidate threads do not simultaneously include the at least two threads having the resource conflict.

9. The instruction processing method according to claim 7, further comprising: Before marking the flag bits of the threads having the resource conflict, the flag bits of the multiple threads are cleared.

10. The instruction processing method according to claim 7, comprising: After marking the flag bits of the at least two threads having the resource conflict, the multiple counters are cleared.

11. An instruction processing device, comprising: an acquisition module configured to acquire inter-thread resource conflict information of a plurality of threads processed in the processor to determine at least two threads having resource conflicts among the plurality of threads; as well as The scheduling module is configured to determine candidate threads to be arbitrated for scheduling in a current operation cycle from the multiple threads, and determine a target thread to be scheduled in the current operation cycle from the candidate threads, wherein the candidate threads do not simultaneously include the at least two threads having resource conflicts.

12. The instruction processing apparatus according to claim 11, wherein: The candidate thread is selected from the plurality of threads and is a thread that is in a schedulable state in the current operation cycle.

13. The instruction processing apparatus according to claim 12, wherein: The candidate thread is further selected from threads having a thread priority higher than a preset priority among the multiple threads.

14. The instruction processing apparatus according to claim 11, wherein: The scheduling module is further configured to select a thread with a higher priority from the at least two threads having resource conflicts as a candidate thread.

15. The instruction processing apparatus according to claim 11, wherein: The at least two threads having resource conflicts have resource conflicts for first-category resources in the processor; The scheduling module enables the candidate threads to be arbitrated for scheduling in the current operation cycle based on allocation of the first type of resources.

16. The instruction processing apparatus according to any one of claims 11 to 15, further comprising: The conflict detection module includes a plurality of counters and is configured to obtain the inter-thread resource conflict information through the information of resource competition between the plurality of threads recorded by the plurality of counters within a first time period.

17. The instruction processing apparatus according to claim 16, further comprising: The marking module is configured to mark the flag bits of the at least two threads having resource conflicts after obtaining the inter-thread resource conflict information of the multiple threads processed in the processor.

18. The instruction processing apparatus according to claim 17, wherein: The marking module is further configured to clear the mark bits of the multiple threads before marking the mark bits of the threads having the resource conflict.

19. The instruction processing apparatus according to claim 17, wherein: The conflict detection module is further configured to clear the multiple counters after marking the flag bits of the at least two threads having the resource conflict.

20. An instruction processing device, comprising a processing unit and a memory; wherein: The memory stores computer-readable instructions and is communicatively connected to the processing unit; The processing unit executes the computer-readable instructions stored in the memory to implement the instruction processing method according to any one of claims 1 to 10.

21. A processor comprising the instruction processing device according to any one of claims 11 to 20.

22. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the instruction processing method according to any one of claims 1 to 10 is implemented.

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