Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises a base substrate and multiple sub-pixels disposed on the base substrate. Each sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit comprises a driving transistor, a sensing transistor, and a storage capacitor. The storage capacitor comprises a first electrode plate and a second electrode plate, and an orthographic projection of the first electrode plate onto the base substrate at least partially overlaps with an orthographic projection of the second electrode plate onto the base substrate. The first electrode plate is coupled to a gate of the driving transistor. The second electrode plate is separately coupled to a second electrode of the driving transistor, a second electrode of the sensing transistor, and an anode of the light-emitting element. The display substrate further comprises an insulating layer, the insulating layer being located on the side of the first electrode plate facing away from the base substrate. The sensing transistor comprises a sensing active layer, and both the second electrode plate and the sensing active layer are located on a surface of the insulating layer facing away from the base substrate.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410370878.8 filed in China on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and the corresponding display quality requirements of display products are becoming increasingly higher. To meet more application scenarios and achieve better display quality, the structure of display products has become more complex. To achieve complex structural layouts within limited layout space, more film layers are required, and the corresponding film layer manufacturing process becomes more complicated. Therefore, how to simplify the production process of display products has become a technical problem that needs to be solved urgently.

[0005] Summary of the Invention

[0006] An object of the present disclosure is to provide a display substrate and a display device.

[0007] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0008] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of sub-pixels disposed on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit includes: a driving transistor, a sensing transistor, and a storage capacitor;

[0009] The storage capacitor includes a first plate and a second plate, wherein an orthographic projection of the first plate on the substrate at least partially overlaps with an orthographic projection of the second plate on the substrate; the first plate is coupled to the gate of the driving transistor; and the second plate is coupled to the second electrode of the driving transistor, the second electrode of the sensing transistor, and the anode of the light-emitting element, respectively.

[0010] The display substrate further includes an insulating layer, and the insulating layer is located on a side of the first electrode plate facing away from the base substrate;

[0011] The sensing transistor includes a sensing active layer, and the second electrode plate and the sensing active layer are both located on a surface of the insulating layer facing away from the base substrate.

[0012] Optionally, the display substrate further includes a conductive portion, and the conductive portion is located on a surface of the insulating layer facing away from the base substrate; the second electrode and the conductive portion are made of the same material;

[0013] The conductive portion is part of the sensing active layer; or, the conductive portion includes a portion independent of the sensing active layer.

[0014] Optionally, the second electrode plate and the conductive part form an integral structure.

[0015] Optionally, the sub-pixel driving circuit further includes a first conductive connecting portion;

[0016] When the conductive portion is part of the sensing active layer, the first conductive connection portion passes through the integrated structure and is coupled to the second electrode of the driving transistor; the first conductive connection portion is also coupled to the sidewall of the integrated structure at the penetration point.

[0017] Optionally, the sub-pixel driving circuit further includes a third conductive connection portion and a second conductive connection portion;

[0018] The third conductive connection portion is coupled to the second electrode plate and the second electrode of the driving transistor respectively; the first portion of the sensing active layer serves as the second electrode of the sensing transistor, and the first portion is overlapped on the third conductive connection portion; the second conductive connection portion is coupled to the third conductive connection portion, the first portion and the anode respectively;

[0019] The conductive portion includes the third conductive connection portion.

[0020] Optionally, the storage capacitor further includes a compensation plate, which is located on the side of the second plate facing away from the substrate, and the positive projection of the compensation plate on the substrate at least partially overlaps with the positive projection of the second plate on the substrate, and the compensation plate is coupled to the first level signal output end, and the compensation plate is set in the same layer and material as the gate of the sensing transistor.

[0021] Optionally, in a plurality of sub-pixel driving circuits located in the same row, the compensation plates included in the storage capacitors in the respective sub-pixel driving circuits are coupled to each other.

[0022] Optionally, the display substrate further includes a switching pattern, which is used to connect different functional patterns in the display substrate, and the switching pattern is provided in the same layer and material as the gate of the sensing transistor.

[0023] Optionally, the display substrate further includes a transfer pattern, which is used to connect different functional patterns in the display substrate, and the transfer pattern and the first conductive connection portion are provided in the same layer and the same material.

[0024] Optionally, the display substrate further includes a transfer pattern, which is used to connect different functional patterns in the display substrate, and the transfer pattern and the third conductive connection portion are provided in the same layer and the same material.

[0025] Optionally, the display substrate further includes a data line; the switching pattern includes a first switching pattern; the sub-pixel driving circuit further includes a data writing transistor, and the first electrode of the data writing transistor is coupled to the corresponding data line through the first switching pattern.

[0026] Optionally, the switching pattern includes a second switching pattern; the sub-pixel driving circuit further includes a data writing transistor; and the second electrode of the data writing transistor is coupled to the first electrode plate through the second switching pattern.

[0027] Optionally, the switching pattern includes a third switching pattern;

[0028] The display substrate further includes a first functional pattern and a second functional pattern, wherein the first functional pattern is located on a side of the driving active layer of the driving transistor facing the base substrate, and the second functional pattern is located on a side of the gate of the sensing transistor facing away from the base substrate; the first functional pattern is coupled to the second functional pattern via the third switching pattern.

[0029] Optionally, the sensing transistor includes an oxide transistor, and the sensing active layer includes an oxide active layer.

[0030] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0032] FIG1 is a circuit schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0033] FIG2 is a first cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0034] FIG3 is a second cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0035] FIG4 is a schematic planar layout diagram of three sub-pixel driving circuits corresponding to the cross-sectional view of FIG2 ;

[0036] FIG5 is a schematic diagram of the layout of the polysilicon active layer in FIG4 ;

[0037] FIG6 is a schematic diagram of the layout of the polysilicon active layer and the first gate metal layer in FIG4 ;

[0038] FIG7 is a schematic diagram of a layout in which an oxide active layer is added based on FIG6 ;

[0039] FIG8 is a schematic diagram of the layout of the oxide active layer in FIG7;

[0040] FIG9 is a schematic diagram of a layout in which a third gate metal layer is added on the basis of FIG7 ;

[0041] FIG10 is a schematic diagram of the layout of the first source and drain metal layer in FIG4 ;

[0042] FIG11 is a schematic diagram of the layout after adding a first source / drain metal layer in FIG9 ;

[0043] FIG12 is a schematic diagram of the layout of the first conductive layer in FIG4;

[0044] FIG13 is a schematic diagram of the layout after adding a first conductive layer in FIG11;

[0045] FIG14 is a schematic diagram of the layout of the second source and drain metal layer in FIG4;

[0046] FIG15 is a schematic diagram of a planar layout of a plurality of sub-pixel driving circuits distributed in an array corresponding to FIG4 ;

[0047] FIG16 is a schematic diagram of the layout of the first conductive layer in FIG15 ;

[0048] FIG17 is a schematic diagram of the layout of the polysilicon active layer and the first gate metal layer in FIG15 ;

[0049] FIG18 is a schematic diagram of a layout in which a first conductive layer is added to FIG17;

[0050] FIG19 is a schematic diagram of the layout of the oxide active layer in FIG15;

[0051] FIG20 is a schematic diagram of the layout of FIG18 with an oxide active layer added;

[0052] FIG21 is a schematic diagram of the layout of the third gate metal layer in FIG15;

[0053] FIG22 is a schematic diagram of the layout of FIG20 with a third gate metal layer added;

[0054] FIG23 is a schematic diagram of the layout of the first source and drain metal layer in FIG15;

[0055] FIG24 is a schematic diagram of the layout of FIG22 with a first source / drain metal layer added;

[0056] FIG25 is a schematic diagram of the layout of the second source / drain metal layer in FIG15 ;

[0057] FIG26 is a third cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0058] FIG27 is a fourth cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0059] FIG28 is a fifth cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0060] FIG29 is a sixth cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0061] FIG30 is a schematic planar layout diagram of three sub-pixel driving circuits corresponding to the cross-sectional view of FIG28 ;

[0062] FIG31 is a schematic diagram of the layout of the polysilicon active layer, the first gate metal layer, and the third conductive layer in FIG30;

[0063] FIG32 is a schematic diagram of the layout of the third conductive layer in FIG31;

[0064] FIG33 is a schematic diagram of the layout of FIG31 with an oxide active layer and a third gate metal layer added;

[0065] FIG34 is a schematic diagram of the layout of the first source / drain metal layer in FIG30 ;

[0066] FIG35 is a seventh cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0067] FIG36 is a schematic planar layout diagram of three sub-pixel driving circuits corresponding to the cross-sectional view of FIG35 ;

[0068] FIG37 is a schematic diagram of the layout of the second gate metal layer in FIG36;

[0069] FIG38 is a schematic diagram of the layout of the polysilicon active layer, the first gate metal layer, and the second gate metal layer in FIG36 ;

[0070] FIG39 is a schematic diagram of the layout of the third conductive layer in FIG36;

[0071] FIG40 is a schematic diagram of a layout in which a third conductive layer is added on the basis of FIG38;

[0072] FIG41 is a schematic diagram of a layout in which an oxide active layer is added based on FIG40;

[0073] FIG42 is a schematic diagram of the layout of the first source / drain metal layer in FIG36;

[0074] FIG43 is an eighth cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0075] FIG44 is a schematic planar layout diagram of three sub-pixel driving circuits corresponding to the cross-sectional view of FIG43 ;

[0076] FIG45 is a schematic diagram of the layout of the third gate metal layer in FIG44 . DETAILED DESCRIPTION

[0077] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0078] With the diversification of VR applications, demand for VR products is growing rapidly. As one of its core hardware components, display substrates require higher resolutions to achieve a greater number of pixel viewpoints and reproduce realistic scenes. The higher the resolution, the smaller the layout space occupied by sub-pixels. Consequently, the dimensions of each film layer in the display substrate must be significantly compressed. Masks are also required to avoid interference restrictions such as same-layer routing. Therefore, higher-resolution displays require more masks.

[0079] As shown in Figure 35, the display substrate generally includes a first conductive layer BS1, a first buffer layer Buf1, a second conductive layer BS2, a second buffer layer Buf2, a polycrystalline silicon active layer Poly, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a first interlayer insulating layer ILD1, a third conductive layer CM, an oxide active layer ACT, a third gate insulating layer GI3, a third gate metal layer Gate3, a second interlayer insulating layer ILD2, a first source and drain metal layer SD1, a first passivation layer PVX1, a second source and drain metal layer SD2, a planarization layer PLN, a second passivation layer PVX2, an anode layer Ano, a pixel defining layer PDL, a light-emitting functional layer, a cathode layer, and an encapsulation layer.

[0080] The mask process for making display substrates generally includes:

[0081] BS1 mask, that is, a mask process for forming the first conductive layer BS1.

[0082] BS2 mask, that is, a mask process for forming the second conductive layer BS2.

[0083] Poly mask is a mask process used to form the polysilicon active layer Poly.

[0084] Gate1 mask, that is, a mask process for forming the first gate metal layer Gate1.

[0085] GI2 mask, i.e., via mask, is used to form vias connecting the second gate metal layer Gate2 and the functional pattern located on the side thereof facing the substrate.

[0086] Gate2 mask, that is, a mask process for forming the second gate metal layer Gate2.

[0087] The CNT-CM mask, i.e., the via mask, is used to form vias connecting the third conductive layer CM and the functional pattern located on the side thereof facing the substrate.

[0088] CM mask, that is, a mask process for forming the third conductive layer CM.

[0089] ACT mask is a mask process used to form the oxide active layer ACT.

[0090] Gate3 mask is a mask process used to form the third gate metal layer Gate3.

[0091] The CNT-L mask, namely the via mask, is used to form vias connecting the first source / drain metal layer SD1 and the functional pattern located on the side thereof facing the substrate.

[0092] The CNT-O mask, namely the via mask, is used to form vias connecting the first source / drain metal layer SD1 and the functional pattern located on the side thereof facing the substrate.

[0093] SD1 mask, that is, a mask process for forming the first source / drain metal layer SD1.

[0094] The PVX1 mask, i.e., the via mask, is used to form vias on the first passivation layer PVX1 that connect the second source / drain metal layer SD2 and the functional pattern located on the side thereof facing the substrate.

[0095] SD2 mask, that is, a mask process for forming the second source / drain metal layer SD2.

[0096] PLN mask, also known as via mask, is used to form vias on the flat layer PLN.

[0097] PVX2 mask, that is, via mask, is used to form vias on the second passivation layer PVX2.

[0098] Ano mask is a mask process used to form the anode layer Ano.

[0099] The PDL mask, namely the via mask, is used to form pixel openings on the pixel definition layer (PDL).

[0100] Referring to FIG. 1 , FIG. 2 , and FIG. 4 to FIG. 14 , an embodiment of the present disclosure provides a display substrate, including: a base substrate 10 and a plurality of sub-pixels disposed on the base substrate 10 , wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit includes: a driving transistor M3 , a sensing transistor M2 , and a storage capacitor Cst ;

[0101] The storage capacitor Cst includes a first plate Cst1 and a second plate Cst2, wherein an orthographic projection of the first plate Cst1 on the substrate 10 at least partially overlaps with an orthographic projection of the second plate Cst2 on the substrate 10; the first plate Cst1 is coupled to the gate M3-g of the driving transistor M3; and the second plate Cst2 is coupled to the second electrode of the driving transistor M3, the second electrode of the sensing transistor M2, and the anode of the light-emitting element, respectively.

[0102] The display substrate further includes an insulating layer (such as a first interlayer insulating layer ILD1 ), which is located on a side of the first electrode plate Cst1 facing away from the base substrate 10 ;

[0103] The sensing transistor M2 includes a sensing active layer 42 . The second electrode Cst2 and the sensing active layer 42 are both located on a surface of the insulating layer facing away from the base substrate 10 .

[0104] It should be noted that FIG4 is a schematic planar layout diagram of three sub-pixel driving circuits corresponding to the cross-sectional view of FIG2 ; FIG5 is a schematic layout diagram of the polysilicon active layer in FIG4 ; FIG6 is a schematic layout diagram of the polysilicon active layer and the first gate metal layer in FIG4 ; FIG7 is a schematic layout diagram of FIG6 with an oxide active layer added; FIG8 is a schematic layout diagram of the oxide active layer in FIG7 ; FIG9 is a schematic layout diagram of FIG7 with a third gate metal layer added; FIG10 is a schematic layout diagram of the first source and drain metal layer in FIG4 ; and FIG11 is a schematic layout diagram of FIG9 after the first source and drain metal layer is added.

[0105] Figure 12 is a schematic diagram of the layout of the first conductive layer in Figure 4; Figure 13 is a schematic diagram of the layout after adding the first conductive layer in Figure 11; Figure 14 is a schematic diagram of the layout of the second source and drain metal layer in Figure 4.

[0106] Figure 15 is a schematic diagram of the planar layout of multiple sub-pixel driving circuits arranged in an array corresponding to Figure 4; the sub-pixel driving circuits in the same column in Figure 15 are symmetrically arranged. Figure 16 is a schematic diagram of the layout of the first conductive layer in Figure 15; Figure 17 is a schematic diagram of the layout of the polysilicon active layer and the first gate metal layer in Figure 15; Figure 18 is a schematic diagram of the layout with the first conductive layer added in Figure 17; Figure 19 is a schematic diagram of the layout of the oxide active layer in Figure 15; Figure 20 is a schematic diagram of the layout with the oxide active layer added in Figure 18; Figure 21 is a schematic diagram of the layout of the third gate metal layer in Figure 15; Figure 22 is a schematic diagram of the layout with the third gate metal layer added in Figure 20; Figure 23 is a schematic diagram of the layout of the first source and drain metal layer in Figure 15; Figure 24 is a schematic diagram of the layout with the first source and drain metal layer added in Figure 22; and Figure 25 is a schematic diagram of the layout of the second source and drain metal layer in Figure 15.

[0107] It's worth noting that the black dots in the accompanying figures represent connection holes between the structure formed by the first source / drain metal layer and the other underlying film layers. The black squares in the accompanying figures represent connection holes between the first and second transfer patterns and the other underlying film layers. The cross-hatched square holes in the accompanying figures represent connection holes between the second source / drain metal layer and the other underlying film layers.

[0108] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0109] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0110] The sub-pixel driving circuit has various structures. For example, as shown in FIG1 , a 3T1C (including 3 transistors and 1 capacitor) circuit structure is adopted, but the present invention is not limited thereto.

[0111] The display substrate includes a plurality of power lines VDD, a plurality of data lines DA, a plurality of sensing lines SE, a plurality of first scan lines GA1 and a plurality of second scan lines GA2.

[0112] The sub-pixel driving circuit includes a driving transistor M3, a sensing transistor M2, a data writing transistor M1 and a storage capacitor Cst.

[0113] The gate T1-g of the data writing transistor M1 is coupled to the corresponding first scan line GA1, the first electrode of the data writing transistor M1 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor M1 is coupled to the gate M3-g of the driving transistor M3.

[0114] The gate M3-g of the driving transistor M3 is coupled to the first plate Cst1 of the storage capacitor Cst. For example, the gate M3-g of the driving transistor M3 is multiplexed as the first plate Cst1 of the storage capacitor Cst. The first electrode of the driving transistor M3 is coupled to the corresponding power line VDD, and the second electrode of the driving transistor M3 is coupled to the anode of the light-emitting element. The cathode of the light-emitting element is coupled to the power signal input terminal VSS. The second plate Cst2 of the storage capacitor Cst is coupled to the anode of the light-emitting element.

[0115] A gate T2 - g of the sensing transistor M2 is coupled to the corresponding second scan line GA2 , a first electrode of the sensing transistor M2 is coupled to the corresponding sensing line SE, and a second electrode of the sensing transistor M2 is coupled to the anode of the light emitting element.

[0116] Exemplarily, the driving transistor M3 and the data writing transistor M1 include polysilicon transistors, and the sensing transistor M2 includes an oxide transistor, but is not limited thereto.

[0117] Exemplarily, the insulating layer is located on the side of the first electrode Cst1 facing away from the base substrate 10, and the second electrode Cst2 is located on the surface of the insulating layer facing away from the base substrate 10, so that the insulating layer serves as a dielectric layer between the first electrode Cst1 and the second electrode Cst2.

[0118] Exemplarily, the sensing transistor M2 includes a sensing active layer 42 , and the sensing active layer 42 includes an oxide active layer, such as an IGZO (Indium Gallium Zinc Oxide) active layer, but is not limited thereto.

[0119] In the related technical solution, the second electrode Cst2 of the storage capacitor Cst is made of an independent metal film layer, for example: the second gate metal layer often mentioned in the related technology, and after the second electrode Cst2 is made, at least one insulating film layer and an oxide active layer are formed in sequence.

[0120] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, the sensing transistor M2 is provided including a sensing active layer 42, and the second electrode Cst2 and the sensing active layer 42 are both located on the surface of the insulating layer facing away from the base substrate 10; this arrangement allows the second electrode Cst2 and the sensing active layer 42 to be manufactured on the same layer, which not only avoids the need to manufacture an insulating film layer (such as a second gate insulating layer GI2) between the second electrode Cst2 and the sensing active layer 42, but also allows the second electrode Cst2 and the conductive portion located on the surface of the insulating layer to be manufactured using the same material, so that the second electrode Cst2 and the conductive portion can be formed through the same patterning process, thereby further omitting the manufacturing process flow of the second gate metal layer GI2 as in the related art; therefore, the display substrate provided by the embodiment of the present disclosure effectively simplifies the manufacturing process flow and reduces the manufacturing cost of the display substrate.

[0121] As shown in Figures 4, 26 and 28, in some embodiments, the display substrate further includes a conductive portion, which is located on the surface of the insulating layer facing away from the base substrate 10; the second electrode Cst2 is made of the same material as the conductive portion; the conductive portion is part of the sensing active layer 42; or, the conductive portion includes a portion independent of the sensing active layer 42.

[0122] By setting the second electrode plate Cst2 and the conductive portion to be made of the same material, the second electrode plate Cst2 and the conductive portion can be formed in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0123] The aforementioned arrangement of the conductive portion as part of the sensing active layer 42 enables the second electrode Cst2 to be formed in the same patterning process as the sensing active layer 42. Furthermore, the surface of the insulating layer facing away from the base substrate 10 may no longer include other conductive portions (such as a third conductive layer CM) made of a material different from that of the sensing active layer 42, thereby further simplifying the process for fabricating other conductive portions on the surface of the insulating layer facing away from the base substrate 10. This arrangement is equivalent to eliminating three patterning process steps: the patterning process for independently fabricating the second electrode Cst2 (i.e., the Gate2 mask), the process for independently fabricating other conductive portions (i.e., the CM mask), and the via process (e.g., the CNT-CM mask) required to electrically connect the other conductive portions to the underlying structure (i.e., the structure located on the side of the other conductive portions facing the base substrate 10).

[0124] It should be noted that the sensing transistor M2 adopts a top-gate structure, and the sensing active layer 42 is conductively processed in the area not blocked by the gate, and the conductive portion of the sensing active layer 42 serves as the conductive portion.

[0125] The aforementioned arrangement of the conductive portion including a portion independent of the sensing active layer 42 allows the second electrode plate Cst2 and the conductive portion independent of the sensing active layer 42 to be formed in the same patterning process, effectively simplifying the manufacturing process and reducing the manufacturing cost of the display substrate. It is worth noting that the conductive portion including a portion independent of the sensing active layer 42 means that the conductive portion is made of a different material than the sensing active layer 42 and does not form an integral structure with the sensing active layer 42, but the conductive portion can be electrically connected to the sensing active layer 42.

[0126] As shown in FIG. 26 , in some embodiments, the second electrode plate Cst2 and the conductive portion are formed into an integral structure.

[0127] The second electrode plate Cst2 and the conductive part to be electrically connected thereto form an integral structure, which is beneficial for improving the electrical connection performance between the second electrode plate Cst2 and the conductive part.

[0128] As shown in Figures 2 and 26, in some embodiments, the sub-pixel driving circuit further includes a first conductive connection portion 51; when the conductive portion is part of the sensing active layer 42, the first conductive connection portion 51 passes through the integrated structure and is coupled to the second electrode of the driving transistor M3; the first conductive connection portion 51 is also coupled to the side wall of the integrated structure at the penetration point.

[0129] Exemplarily, the first conductive connection portion 51 is an integrated structure, and the first conductive connection portion 51 is provided in the same layer and with the same material as the first source / drain metal layer in the display substrate, but the present invention is not limited thereto.

[0130] Exemplarily, the second electrode plate Cst2 and the sensing active layer 42 form an integral structure, the first conductive connection portion 51 penetrates the integral structure in a direction perpendicular to the base substrate 10, one end of the first conductive connection portion 51 is coupled to the second electrode of the driving transistor M3 in a direction perpendicular to the base substrate 10, the other end of the first conductive connection portion 51 is coupled to the anode, and the first conductive connection portion 51 is also coupled to the side wall of the integral structure at the penetration point.

[0131] In more detail, before forming the first conductive connection portion 51, a via process is performed. In this via process, the insulating film layer located on the side of the sensing active layer 42 facing away from the base substrate 10 can be sequentially etched by over-etching, the integral structure formed by the sensing active layer 42 and the second electrode Cst2, and the insulating film layer located between the integral structure and the second electrode of the driving transistor M3. The second electrode of the driving transistor M3 can be formed by the driving active layer 43 in the driving transistor M3.

[0132] The above-mentioned arrangement enables the first conductive connection portion 51 to be formed through a single patterning process, which not only ensures that the first conductive connection portion 51 can electrically connect the second electrode of the driving transistor M3, the second electrode plate Cst2, the sensing active layer 42 and the anode together, but also helps to simplify the manufacturing process of the display substrate and reduce the manufacturing cost of the display substrate.

[0133] As shown in Figures 28 and 30 to 34, in some embodiments, the sub-pixel driving circuit also includes a third conductive connection part 53 and a second conductive connection part 52; the third conductive connection part 53 is respectively coupled to the second electrode Cst2 and the second electrode of the driving transistor M3; the first part of the sensing active layer 42 serves as the second electrode of the sensing transistor M2, and the first part is overlapped on the third conductive connection part 53; the second conductive connection part 52 is respectively coupled to the third conductive connection part 53, the first part and the anode; the conductive part includes the third conductive connection part 53.

[0134] It should be noted that Figure 30 is a schematic diagram of the planar layout of the three sub-pixel driving circuits corresponding to the cross-sectional view of Figure 28; Figure 31 is a schematic diagram of the layout of the polysilicon active layer, the first gate metal layer and the third conductive layer in Figure 30; Figure 32 is a schematic diagram of the layout of the third conductive layer in Figure 31; Figure 33 is a schematic diagram of the layout with an oxide active layer and a third gate metal layer added to Figure 31; and Figure 34 is a schematic diagram of the layout of the first source and drain metal layer in Figure 30.

[0135] Exemplarily, the second electrode plate Cst2 and the third conductive film layer form an integrated structure, but are not limited thereto.

[0136] Exemplarily, the third conductive film layer and the sensing active layer 42 are made of different materials, and the third conductive film layer and the sensing active layer 42 are formed in different patterning processes.

[0137] The second electrode Cst2 is set to be made of the same material as the conductive part, and the conductive part includes the third conductive connecting part 53, so that the second electrode Cst2 can be formed in the same composition process as the third conductive film layer, thereby effectively simplifying the composition process of the display substrate and reducing the production cost of the display substrate.

[0138] As shown in Figures 3, 27 and 29, in some embodiments, the storage capacitor Cst also includes a compensation plate Cst4, which is located on the side of the second plate Cst2 facing away from the base substrate 10, and the positive projection of the compensation plate Cst4 on the base substrate 10 at least partially overlaps with the positive projection of the second plate Cst2 on the base substrate 10. The compensation plate Cst4 is coupled to the first level signal output end, and the compensation plate Cst4 is arranged in the same layer and material as the gate T2-g of the sensing transistor M2.

[0139] Exemplarily, the voltage value of the first-level signal outputted by the first-level signal output terminal includes 0V, but is not limited thereto.

[0140] The gate T2-g of the sensing transistor M2 is located in the third gate metal layer, which has ample design space. Providing the compensation plate Cst4 and the gate T2-g of the sensing transistor M2 in the same layer and material can not only reduce the layout difficulty of the compensation plate Cst4, but also enable the compensation plate Cst4 and the gate T2-g of the sensing transistor M2 to be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process flow of the display substrate.

[0141] Furthermore, by arranging the orthographic projection of the compensation plate Cst4 on the base substrate 10 to at least partially overlap with the orthographic projection of the second plate Cst2 on the base substrate 10, and coupling the compensation plate Cst4 to the first level signal output terminal, a capacitor structure is formed between the compensation plate Cst4 and the second plate Cst2, thereby increasing the capacitance of the storage capacitor Cst. More specifically, the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst have a first capacitance C1, and the second plate Cst2 and the compensation plate Cst4 have a second capacitance C2. The first plate Cst1, the second plate Cst2, and the compensation plate Cst4 together form a parallel capacitor structure, thereby increasing the capacitance of the storage capacitor Cst to C1 + C2.

[0142] In some embodiments, in a plurality of sub-pixel driving circuits located in the same row, the compensation plates included in the storage capacitors in the respective sub-pixel driving circuits are coupled to each other.

[0143] Exemplarily, in the sub-pixel driving circuits of the same row, the compensation plates included in the storage capacitors in each sub-pixel driving circuit are formed into an integrated structure.

[0144] The above-mentioned setting method enables the compensation plates of multiple storage capacitors belonging to the same row of sub-pixel driving circuits to be electrically connected together, so that the compensation plates of multiple storage capacitors belonging to the same row of sub-pixel driving circuits can be coupled together to a first-level signal output terminal, without having to independently connect each of the compensation plates to the first-level signal output terminal, thereby better reducing the structural complexity of the display substrate and the difficulty of the layout of the display substrate.

[0145] As shown in Figures 2, 4 and 9, in some embodiments, the display substrate further includes a switching pattern (such as a first switching pattern 31, a second switching pattern 32 and a third switching pattern 33), which is used to connect different functional patterns in the display substrate. The switching pattern is set in the same layer and material as the gate T2-g of the sensing transistor M2.

[0146] Exemplarily, the transfer pattern connects at least two functional patterns, and the at least two functional patterns may both be located on the side of the transfer pattern facing the base substrate 10; or, a portion of the at least two functional patterns are located on the side of the transfer pattern facing the base substrate 10, and another portion of the at least two functional patterns are located on the side of the transfer pattern facing away from the base substrate 10; or, the at least two functional patterns may both be located on the side of the transfer pattern facing away from the base substrate 10.

[0147] The gate T2-g of the sensing transistor M2 is located in the third gate metal layer, which has ample design space. Providing the switching pattern and the gate T2-g of the sensing transistor M2 in the same layer and material not only reduces the layout difficulty of the switching pattern, but also enables the switching pattern and the gate T2-g of the sensing transistor M2 to be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process flow of the display substrate.

[0148] As shown in Figures 26 and 28, in some embodiments, the display substrate also includes a transfer graphic (such as the first transfer graphic 31 and the second transfer graphic 32 in Figure 26, and the second transfer graphic 32 in Figure 28), and the transfer graphic is used to connect different functional graphics in the display substrate, and the transfer graphic is set in the same layer and material as the first conductive connection part 51.

[0149] Exemplarily, the transfer pattern connects at least two functional patterns, and the at least two functional patterns may both be located on the side of the transfer pattern facing the base substrate 10; or, a portion of the at least two functional patterns are located on the side of the transfer pattern facing the base substrate 10, and another portion of the at least two functional patterns are located on the side of the transfer pattern facing away from the base substrate 10; or, the at least two functional patterns may both be located on the side of the transfer pattern facing away from the base substrate 10.

[0150] The transfer pattern and the first conductive connection portion 51 are provided in the same layer and material, so that the transfer pattern and the first conductive connection portion 51 can be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process of the display substrate.

[0151] As shown in Figures 28 and 32, in some embodiments, the display substrate also includes a transfer pattern (such as the first transfer pattern 31 and the third transfer pattern 33 in Figure 28), which is used to connect different functional patterns in the display substrate, and the transfer pattern is set in the same layer and material as the third conductive connection part 53.

[0152] Exemplarily, the transfer pattern connects at least two functional patterns, and the at least two functional patterns may both be located on the side of the transfer pattern facing the base substrate 10; or, a portion of the at least two functional patterns are located on the side of the transfer pattern facing the base substrate 10, and another portion of the at least two functional patterns are located on the side of the transfer pattern facing away from the base substrate 10; or, the at least two functional patterns may both be located on the side of the transfer pattern facing away from the base substrate 10.

[0153] The transfer pattern and the third conductive connection portion 53 are provided in the same layer and material, so that the transfer pattern and the third conductive connection portion 53 can be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process of the display substrate.

[0154] As shown in Figures 2, 26 and 28, in some embodiments, the display substrate further includes a data line DA; the switching pattern includes a first switching pattern 31; the sub-pixel driving circuit further includes a data writing transistor M1, and the first electrode of the data writing transistor M1 is coupled to the corresponding data line DA through the first switching pattern 31.

[0155] Exemplarily, the data writing transistor M1 includes a data writing active layer 41 .

[0156] Exemplarily, the first transfer pattern 31 is provided in the same layer and material as the gate T2-g of the sensing transistor M2; or, the first transfer pattern 31 is provided in the same layer and material as the first conductive connection portion 51; or, the first transfer pattern 31 is provided in the same layer and material as the third conductive connection portion 53.

[0157] As shown in Figures 2, 26 and 28, in some embodiments, the switching pattern includes a second switching pattern 32; the sub-pixel driving circuit also includes a data writing transistor M1; the second electrode of the data writing transistor M1 is coupled to the first electrode plate Cst1 through the second switching pattern 32.

[0158] Exemplarily, the second transfer pattern 32 is provided in the same layer and material as the gate T2-g of the sensing transistor M2; or, the second transfer pattern 32 is provided in the same layer and material as the first conductive connection portion 51; or, the second transfer pattern 32 is provided in the same layer and material as the third conductive connection portion 53.

[0159] As shown in Figures 2, 26 and 28, in some embodiments, the switching pattern includes a third switching pattern 33; the display substrate also includes a first functional pattern 21 and a second functional pattern 22, the first functional pattern 21 is located on the side of the driving active layer 43 of the driving transistor M3 facing the base substrate 10, and the second functional pattern 22 is located on the side of the gate T2-g of the sensing transistor M2 facing away from the base substrate 10; the first functional pattern 21 is coupled to the second functional pattern 22 through the third switching pattern 33.

[0160] Exemplarily, the third transfer pattern 33 is provided in the same layer and material as the gate T2-g of the sensing transistor M2; or, the third transfer pattern 33 is provided in the same layer and material as the first conductive connection portion 51; or, the third transfer pattern 33 is provided in the same layer and material as the third conductive connection portion 53.

[0161] It is worth noting that when the first transfer pattern 31 and the first conductive connection part 51 are set in the same layer and material, the second transfer pattern 32 and the first conductive connection part 51 are set in the same layer and material, and the third transfer pattern 33 and the first conductive connection part 51 are set in the same layer and material, the GI2 mask can be omitted, further simplifying the manufacturing process of the display substrate.

[0162] With the continuous development of display technology, in order to meet the needs of more application scenarios, the resolution of display products is getting higher and higher, and the layout space that sub-pixels can occupy is getting smaller and smaller. As the sub-pixel layout space decreases, the plate size of the storage capacitor included in the sub-pixel driving circuit in the sub-pixel also decreases synchronously, so there is a problem of the capacitance of the storage capacitor Cst being too small. However, a too small capacitance of the storage capacitor Cst can easily lead to the problem of the anode voltage not being able to be maintained during the light-emitting phase. At the same time, as the capacitance of the storage capacitor Cst decreases, the ratio of the capacitance of the parasitic capacitance to the storage capacitor Cst gradually increases, and the influence of the coupling crosstalk continues to change, which will further affect normal display. Therefore, how to improve the capacitance of the storage capacitor Cst in high-resolution display products has become an urgent problem to be solved.

[0163] As shown in Figures 35 to 42, an embodiment of the present disclosure further provides a display substrate, comprising a base substrate 10 and a plurality of sub-pixels disposed on the base substrate 10. The sub-pixels include a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a driving transistor M3 and a storage capacitor Cst. The second electrode of the driving transistor M3 is coupled to the anode of the light-emitting element.

[0164] The storage capacitor Cst includes a first plate Cst1, a second plate Cst2, and a third plate Cst3 stacked in sequence in a direction away from the base substrate 10, the first plate Cst1 is coupled to the third plate Cst3, the orthographic projection of the first plate Cst1 on the base substrate 10 and the orthographic projection of the second plate Cst2 on the base substrate 10 at least partially overlap, and the orthographic projection of the second plate Cst2 on the base substrate 10 and the orthographic projection of the third plate Cst3 on the base substrate 10 at least partially overlap; the first plate Cst1 is coupled to the gate M3-g of the driving transistor M3, and the second plate Cst2 is coupled to the second electrode of the driving transistor M3.

[0165] It should be noted that Figure 36 is a schematic diagram of the planar layout of the three sub-pixel driving circuits corresponding to the cross-sectional view of Figure 35; Figure 37 is a schematic diagram of the layout of the second gate metal layer in Figure 36; Figure 38 is a schematic diagram of the layout of the polysilicon active layer and the first gate metal layer and the second gate metal layer in Figure 36; Figure 39 is a schematic diagram of the layout of the third conductive layer in Figure 36; Figure 40 is a schematic diagram of the layout of adding a third conductive layer on the basis of Figure 38; Figure 41 is a schematic diagram of the layout of adding an oxide active layer on the basis of Figure 40; and Figure 42 is a schematic diagram of the layout of the first source and drain metal layer in Figure 36.

[0166] Exemplarily, the second electrode plate Cst2 is provided in the same layer and material as the second gate metal layer, but is not limited thereto. Exemplarily, the second gate metal layer may further include a first switching pattern 31 and a third switching pattern 33, wherein the first switching pattern 31 and the third switching pattern 33 are both used to couple different functional patterns in the display substrate; for example, when the sub-pixel driving circuit also includes a data write transistor M1, the first switching pattern 31 is used to couple the first electrode of the data write transistor M1 and the corresponding data line DA; the third switching pattern 33 is used to couple the first functional pattern 21 and the second functional pattern 22 in the display substrate.

[0167] Exemplarily, the third electrode plate Cst3 is formed of the same material as the third conductive layer, but is not limited thereto. Exemplarily, the third conductive layer may further include a second switching pattern 32, which is used to couple different functional patterns in the display substrate; for example, when the sub-pixel driving circuit also includes a data write transistor M1, the second switching pattern 32 is used to couple the second electrode of the data write transistor M1 to the first electrode plate Cst1.

[0168] Exemplarily, the third electrode plate Cst3 is coupled to the first electrode plate Cst1 through a via hole, and the via hole can be realized by a CM mask.

[0169] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, the storage capacitor Cst is provided to include a first electrode plate Cst1, a second electrode plate Cst2, and a third electrode plate Cst3 stacked in sequence. The first electrode plate Cst1 is coupled to the third electrode plate Cst3, which is equivalent to increasing the overlapping area between the electrodes in the storage capacitor Cst, thereby effectively improving the capacitance of the storage capacitor Cst. Moreover, by providing the third electrode plate Cst3 with the same layer and material as the third conductive layer, the third electrode plate Cst3 can be formed simultaneously with the third conductive layer in the same patterning process, thereby simplifying the manufacturing process of the display substrate while improving the capacitance of the storage capacitor Cst.

[0170] As shown in Figures 43 to 45, in some embodiments, the storage capacitor Cst also includes a compensation plate Cst4, which is located on the side of the third plate Cst3 facing away from the base substrate 10, and the positive projection of the compensation plate Cst4 on the base substrate 10 at least partially overlaps with the positive projection of the third plate Cst3 on the base substrate 10. The compensation plate Cst4 is coupled to the first level signal output end, and the compensation plate Cst4 is set in the same layer and material as the gate T2-g of the sensing transistor M2.

[0171] It should be noted that Figure 43 is the eighth cross-sectional schematic diagram of the display substrate provided in the embodiment of the present disclosure; Figure 44 is a planar layout schematic diagram of three sub-pixel driving circuits corresponding to the cross-sectional diagram of Figure 43; and Figure 45 is a layout schematic diagram of the third gate metal layer in Figure 44.

[0172] As shown in Figure 45, exemplarily, in multiple sub-pixel driving circuits located in the same row, the compensation plates Cst4 included in the storage capacitors Cst in each sub-pixel driving circuit are coupled; this method enables the compensation plates Cst4 of multiple storage capacitors Cst belonging to the sub-pixel driving circuit in the same row to be electrically connected together, so that the compensation plates Cst4 of multiple storage capacitors Cst belonging to the sub-pixel driving circuit in the same row can be coupled together to a first-level signal output terminal, and there is no need to independently connect each of the compensation plates Cst4 to the first-level signal output terminal, thereby better reducing the structural complexity of the display substrate and the difficulty of the layout of the display substrate.

[0173] The gate T2-g of the sensing transistor M2 is located in the third gate metal layer, which has ample design space. Providing the compensation plate Cst4 and the gate T2-g of the sensing transistor M2 in the same layer and material can not only reduce the layout difficulty of the compensation plate Cst4, but also enable the compensation plate Cst4 and the gate T2-g of the sensing transistor M2 to be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process flow of the display substrate.

[0174] Moreover, by setting the positive projection of the compensation plate Cst4 on the base substrate 10 to at least partially overlap with the positive projection of the third plate Cst3 on the base substrate 10, and coupling the compensation plate Cst4 to the first level signal output end, a capacitor structure can be formed between the compensation plate Cst4 and the third plate Cst3, thereby increasing the capacitance of the storage capacitor Cst.

[0175] It should be noted that the drawings corresponding to the embodiments in the present disclosure only illustrate the film layer diagrams that are different between this embodiment and other embodiments, and the film layer diagrams that are the same as other embodiments can be referenced in other embodiments.

[0176] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0177] The display device includes a high-resolution organic light-emitting diode display device, but is not limited thereto. The display device can be applied to VR / AR display technology.

[0178] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0179] In the display substrate provided in the above embodiment, the sensing transistor M2 is provided, including a sensing active layer 42, and the second electrode Cst2 and the sensing active layer 42 are both located on the surface of the insulating layer facing away from the base substrate 10. This arrangement allows the second electrode Cst2 and the sensing active layer 42 to be manufactured on the same layer, which not only avoids the need to manufacture an insulating film layer between the second electrode Cst2 and the sensing active layer 42, but also allows the second electrode Cst2 and the conductive portion located on the surface of the insulating layer to be manufactured using the same material, so that the second electrode Cst2 and the conductive portion can be formed through the same patterning process, thereby further omitting the manufacturing process flow of the second gate metal layer as in the related art. Therefore, the display substrate provided in the above embodiment effectively simplifies the manufacturing process flow and reduces the manufacturing cost of the display substrate.

[0180] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0181] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0182] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extended along the certain direction is greater than the length of the secondary part extended along other directions.

[0183] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0184] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0185] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0186] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0187] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0188] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels arranged on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit includes: a driving transistor, a sensing transistor and a storage capacitor; The storage capacitor includes a first plate and a second plate, wherein an orthographic projection of the first plate on the substrate at least partially overlaps with an orthographic projection of the second plate on the substrate; the first plate is coupled to the gate of the driving transistor; and the second plate is coupled to the second electrode of the driving transistor, the second electrode of the sensing transistor, and the anode of the light-emitting element, respectively. The display substrate further includes an insulating layer, and the insulating layer is located on a side of the first electrode plate facing away from the base substrate; The sensing transistor includes a sensing active layer, and the second electrode plate and the sensing active layer are both located on a surface of the insulating layer facing away from the base substrate.

2. The display substrate according to claim 1, wherein The display substrate further includes a conductive portion, which is located on a surface of the insulating layer facing away from the base substrate; the second electrode and the conductive portion are made of the same material; The conductive portion is part of the sensing active layer; or, the conductive portion includes a portion independent of the sensing active layer.

3. The display substrate according to claim 2, wherein: The second electrode plate and the conductive part are formed into an integral structure.

4. The display substrate according to claim 3, wherein: The sub-pixel driving circuit further includes a first conductive connection portion; When the conductive portion is part of the sensing active layer, the first conductive connection portion passes through the integrated structure and is coupled to the second electrode of the driving transistor; the first conductive connection portion is also coupled to the sidewall of the integrated structure at the penetration point.

5. The display substrate according to claim 2, wherein: The sub-pixel driving circuit further includes a second conductive connection portion and a third conductive connection portion; The third conductive connection portion is coupled to the second electrode plate and the second electrode of the driving transistor respectively; the first portion of the sensing active layer serves as the second electrode of the sensing transistor, and the first portion The second conductive connecting portion is respectively coupled to the third conductive connecting portion, the first portion and the anode; The conductive portion includes the third conductive connection portion. The display substrate according to claim 5 , wherein: The storage capacitor also includes a compensation plate, which is located on the side of the second plate facing away from the base substrate. The orthographic projection of the compensation plate on the base substrate at least partially overlaps with the orthographic projection of the second plate on the base substrate. The compensation plate is coupled to the first level signal output end, and the compensation plate is arranged in the same layer and material as the gate of the sensing transistor.

7. The display substrate according to claim 6, wherein: In a plurality of sub-pixel driving circuits located in the same row, the compensation plates included in the storage capacitors in the respective sub-pixel driving circuits are coupled to each other.

8. The display substrate according to claim 1, wherein: The display substrate further includes a switching pattern, which is used to connect different functional patterns in the display substrate. The switching pattern and the gate of the sensing transistor are provided in the same layer and material.

9. The display substrate according to claim 4, wherein: The display substrate further includes a transfer pattern, which is used to connect different functional patterns in the display substrate. The transfer pattern and the first conductive connection portion are provided in the same layer and the same material.

10. The display substrate according to claim 5, wherein: The display substrate further includes a transfer pattern, which is used to connect different functional patterns in the display substrate. The transfer pattern and the third conductive connection portion are provided in the same layer and the same material.

11. The display substrate according to any one of claims 8 to 10, wherein The display substrate further includes a data line; the transfer pattern includes a first transfer pattern; The sub-pixel driving circuit further includes a data writing transistor, a first electrode of which is coupled to the corresponding data line through the first switching pattern.

12. The display substrate according to any one of claims 8 to 10, wherein The transfer pattern includes a second transfer pattern; the sub-pixel driving circuit further includes a data writing transistor; the second electrode of the data writing transistor is coupled to the first electrode plate through the second transfer pattern.

13. The display substrate according to claim 8 or 10, wherein: The switching pattern includes a third switching pattern; The display substrate further includes a first functional pattern and a second functional pattern. The first functional pattern The second functional pattern is located on the side of the driving active layer of the driving transistor facing the substrate, and the second functional pattern is located on the side of the gate of the sensing transistor facing away from the substrate; the first functional pattern is coupled to the second functional pattern through the third switching pattern.

14. The display substrate according to claim 1, wherein The sensing transistor includes an oxide transistor, and the sensing active layer includes an oxide active layer.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

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