Low-cost and high-performance solar cell and manufacturing process therefor

Abstract

A low-cost and high-performance solar cell and a manufacturing process therefor, the solar cell comprising: a silicon wafer, a tunneling oxide layer formed on the silicon wafer and a doped polysilicon, wherein an N-type doped region and a P-type doped region are formed on the doped polysilicon, and there is intrinsic polysilicon in a gap between the N-type doped region and the P-type doped region; a semiconductor layer is formed on the doped polysilicon, and the material of the semiconductor layer comprises one layer or a combination of layers of TiO2, WO3, MoO3, TeO2 or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doped region, a P-type electrode is formed on the semiconductor layer corresponding to the P-type doped region, and the N-type electrode and the P-type electrode come into contact with the semiconductor layer. The low-cost and high-performance solar cell can use a low-cost metal paste and sinter same into an electrode, and has the advantages of low cost and high performance.

Description

A low-cost, high-performance solar cell and its manufacturing process Technical Field

[0001] The invention relates to the technical field of photovoltaic cells, and particularly discloses a low-cost, high-performance solar cell and a manufacturing process thereof. Background Art

[0002] Cost reduction and efficiency improvement have always been one of the most important goals in the commercialization of solar cell technology. Typically, solar cell technology uses silver paste and a rapid sintering process to form electrodes. Due to the excellent chemical stability, high conductivity, and low contact resistance between silver paste and silicon, most solar cell technologies still use silver as an electrode material. However, the high cost of silver has also led to an increase in the cost of solar cells.

[0003] In order to solve this problem, various electrode formation technologies using non-precious metal materials have been proposed, such as the patent (patent number US9293624B2) that introduces the technology of electroplating copper electrodes, and the patent (patent number WO2012 / 047404) that discloses a method of forming copper electrodes through a plating process. The patent (patent number US9293624B2) has the problem of forming contact holes and applying masks to prevent electrode materials from being plated in non-electrode forming areas through the technology of plating copper electrodes. In addition, in order to prevent the diffusion of copper, a protective layer needs to be coated on the upper and lower sides, so the process is more complicated and will lead to additional costs. In the patent for coating copper slurry (patent number WO2012 / 047404), the effect of partially using silver to reduce costs is not obvious. At the same time, since copper will oxidize, only low-temperature sintering can be performed. Compared with the high-temperature sintering process, the resistance of the copper electrode is higher under the same electrode design.

[0004] Currently, with the exception of PERC technology, most high-efficiency solar cell technologies (such as HJT, TopCon, and IBC) still use silver electrodes. However, even in PERC solar cell technology, aluminum paste is only used on the P-type electrode on the back side, limiting the potential for cost savings. For the N-type electrode, aluminum reacts with silicon to form P-type doping, making it difficult to apply.

[0005] In terms of back-contact solar cells using P-type silicon wafers, the patent (patent number US2023 / 0307573A1) describes a back-contact solar cell preparation technology similar to PERC technology, that is, using silver paste for the N-type electrode and aluminum paste for the P-type electrode. The patent (patent number US2023 / 0307573A1) is applied to the back-contact solar cell structure based on P-type silicon wafers. It is a PERC technology similar to that of the P-type electrode. Aluminum is used for the P-type electrode, but silver is still used for the N-type electrode, which has application limitations. It can be seen that these existing technologies still cannot completely replace silver paste, and it is difficult to effectively reduce the amount of silver used by partially applying silver paste.

[0006] In view of the above-mentioned defects in the prior art, there is an urgent need to provide a new low-cost and high-performance solar cell.

[0007] Summary of the Invention

[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a low-cost, high-performance solar cell and a manufacturing process thereof.

[0009] On the one hand, the present invention discloses a low-cost, high-performance solar cell, which adopts the following technical solution:

[0010] A low-cost, high-performance solar cell and its manufacturing process, comprising: a silicon wafer, a tunneling oxide layer formed on the silicon wafer, and doped polysilicon, wherein an N-type doping region and a P-type doping region are formed on the doped polysilicon, and intrinsic polysilicon is spaced between the N-type doping region and the P-type doping region; a semiconductor layer is formed on the doped polysilicon and the intrinsic polysilicon, and the material of the semiconductor layer includes a combination of one or more layers of TiO2, WO3, MoO3, TeO2 or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doping region, and a P-type electrode is formed on the semiconductor layer corresponding to the P-type doping region, and the N-type electrode and the P-type electrode are in contact with the semiconductor layer.

[0011] Preferably, the thickness of the doped polysilicon is 20 nm to 100 nm, and the thickness of the semiconductor layer is 10 nm to 100 nm.

[0012] Preferably, the semiconductor layer above the P-type doping region has the same thickness as or thinner than the semiconductor layer above the N-type doping region.

[0013] Preferably, the thickness of the semiconductor layer above the N-type doping region is 40-70 nm, and the thickness of the semiconductor layer above the P-type doping region is 20-70 nm.

[0014] Preferably, a metal alloy is formed between the contact surface of the semiconductor layer and the P-type electrode and / or the N-type electrode.

[0015] Preferably, the semiconductor layer contains 0-5 wt% of dopants, and the dopants include one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).

[0016] Preferably, the P-type electrode and / or the N-type electrode comprises Al, Ag, Cu or a mixture thereof.

[0017] Preferably, the P-type electrode and / or the N-type electrode are formed of aluminum paste, and the silicon content in the aluminum paste is 0-20 wt %.

[0018] Preferably, a passivation layer is also included.

[0019] Preferably, the passivation layer is formed on the semiconductor layer.

[0020] Preferably, the passivation layer is formed on the doped polysilicon and the intrinsic polysilicon, the semiconductor layer is formed on the passivation layer, and the semiconductor layer passes through the passivation layer and contacts the doped polysilicon.

[0021] Preferably, the material of the passivation layer is SiN x 、SiO x 、SiON x Or a combination of one or more layers of Al2O3.

[0022] On the other hand, the present invention discloses a low-cost, high-performance manufacturing process for solar cells, which adopts the following technical solutions:

[0023] A low-cost, high-performance solar cell manufacturing process comprises the following steps:

[0024] S1, forming a tunnel oxide layer and intrinsic polysilicon on a silicon wafer;

[0025] S2. Selectively implanting boron and phosphorus into the intrinsic polysilicon to form doped polysilicon, alternately forming N-type doped regions and P-type doped regions on the doped polysilicon, with intrinsic polysilicon remaining between the N-type doped region and the P-type doped region as isolation;

[0026] S3, forming a semiconductor layer on the doped polysilicon;

[0027] S4. Form an N-type electrode and a P-type electrode on the semiconductor layer, so that the N-type electrode contacts the semiconductor layer above the N-type doping region, and the P-type electrode contacts the semiconductor layer above the P-type doping region.

[0028] Preferably, in S2, boron and phosphorus are selectively implanted by ion implantation, printing and heat treatment of a doping paste, or using a mask and a doping diffusion furnace.

[0029] Preferably, in S3, the semiconductor layer above the P-type doped region is subjected to laser ablation treatment, or a metal alloy is formed on the semiconductor layer above the P-type doped region so that the semiconductor layer above the P-type doped region is thinner than the semiconductor layer above the N-type doped region.

[0030] Preferably, in S4, the N-type electrode and the P-type electrode are formed by simultaneously printing metal paste on the semiconductor layer and sintering, or the N-type electrode and the P-type electrode are formed by separately printing metal paste on the semiconductor layer and sintering.

[0031] Compared with the prior art, the present invention has at least the following beneficial effects:

[0032] 1. Application of low-cost electrode paste: When aluminum paste is used to form electrodes on traditional N-type polysilicon, there are problems such as P-type doping due to the reaction between aluminum and polysilicon, or aluminum diffusion in the polysilicon, which leads to a decrease in passivation properties. The present invention prevents the diffusion of aluminum into polysilicon through the semiconductor layer, while also having good contact resistance with aluminum, so low-cost metal electrodes such as aluminum can be used;

[0033] 2. Reduce the thickness of polysilicon: When traditional metal electrodes directly contact polysilicon, the diffusion and spike problems of metal ions make it difficult to reduce the thickness of polysilicon, so the thickness must be kept above a specific value. Therefore, it is difficult to reduce the parasitic absorption of light by the thick polysilicon layer, especially in the case of low current on the back side, which also hinders the improvement of double-sided efficiency. The present invention solves the above problems by forming a structure of a semiconductor layer on doped polysilicon, so that the metal electrode contacts the semiconductor layer instead of the doped polysilicon below, thereby reducing the thickness of the polysilicon. In addition, the larger band gap of the semiconductor layer can further reduce light absorption loss;

[0034] 3. Simple manufacturing process: The semiconductor layer mentioned in the present invention can be prepared using the same manufacturing process as doped polysilicon, can be processed in a low-temperature process, and has high-temperature stability. Therefore, it will not be affected by subsequent high-temperature processes. It can be prepared on the basis of the existing solar cell manufacturing process without adding additional processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of a low-cost, high-performance solar cell according to Examples 1-3;

[0036] FIG2 is a schematic diagram of step S1 of the manufacturing process of a low-cost, high-performance solar cell according to Example 1;

[0037] FIG3 is a schematic diagram of step S2 of the manufacturing process of a low-cost, high-performance solar cell according to Example 1;

[0038] FIG4 is a schematic diagram of step S3 of the manufacturing process of a low-cost, high-performance solar cell according to Example 1;

[0039] FIG5 is a schematic diagram of step S4 of the manufacturing process of the low-cost, high-performance solar cell of Example 1;

[0040] FIG6 is a schematic structural diagram of a low-cost, high-performance solar cell according to Example 4;

[0041] FIG7 is a schematic diagram of step S4 of the manufacturing process of a low-cost, high-performance solar cell according to Example 4;

[0042] FIG8 is a schematic diagram of another method of S4 of the manufacturing process of the low-cost, high-performance solar cell of Example 4;

[0043] FIG9 is a graph showing the backside light absorption reflectivity of different materials;

[0044] FIG10 is a graph showing the backside absorbance of different materials;

[0045] FIG11 is a graph showing the contact resistance characteristics of the doped polysilicon and semiconductor layers with the aluminum electrode;

[0046] FIG. 12 is a graph showing the PL intensity characteristics of photoluminescence detection of doped polysilicon.

[0047] Description of Figure Numbers:

[0048] 1. Tunneling oxide layer; 2. Intrinsic polysilicon; 3. P-type doped region; 4. N-type doped region; 5. Semiconductor layer; 6. Passivation layer; 7. P-type electrode; 8. N-type electrode. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] This invention is applied to a TBC structure using a tunneling oxide layer and doped polysilicon. The goal is to directly utilize conventional aluminum paste and sintering processes, allowing the technology to be used on existing electrode sintering processes. This patent simultaneously uses a semiconductor layer above both the P-type and N-type doped regions to prevent aluminum diffusion, allowing excellent metal contact to be achieved not only on the P-type electrode but also in the N-type doped region. By using low-cost aluminum paste and conventional sintering processes to form electrodes, high-efficiency and low-cost solar cells can be manufactured.

[0051] Example 1

[0052] As shown in Figure 1(a), in this embodiment, a low-cost, high-performance solar cell includes: a silicon wafer, a tunneling oxide layer 1, doped polysilicon, a semiconductor layer 5, and a passivation layer 6, which are sequentially formed on the silicon wafer. A P-type doped region 3 and an N-type doped region 4 are formed on the doped polysilicon, with intrinsic polysilicon 2 interposed between the P-type doped region 3 and the N-type doped region 4. A semiconductor layer 5 is formed entirely overlying the doped polysilicon and the intrinsic polysilicon, and the material of the semiconductor layer 5 is TiO2. A P-type electrode 7 is formed on the semiconductor layer 5 corresponding to the P-type doped region 3, and an N-type electrode 8 is formed on the semiconductor layer 5 corresponding to the N-type doped region 4. The P-type electrode 7 and the N-type electrode 8 are in contact with the semiconductor layer 5.

[0053] In this embodiment, referring to Figures 2-5, a low-cost, high-performance solar cell manufacturing process includes the following steps:

[0054] S1. Forming a tunnel oxide layer and intrinsic polysilicon: As shown in Figure 2, a tunnel oxide layer and intrinsic polysilicon are formed on the back side of the silicon wafer. The tunnel oxide layer is formed by heat treating the surface of the silicon wafer, and the thickness of the tunnel oxide layer is 1-2nm. The intrinsic polysilicon is formed by LPCVD deposition, and the thickness of the intrinsic polysilicon is 20nm. The tunnel oxide layer can also be formed on the silicon wafer by oxidation in a vacuum device or by a wet process. The intrinsic polysilicon can be deposited using methods such as PVD or PECVD, or implanted by a diffusion furnace, or prepared using a variety of other processes.

[0055] S2. Forming doped polysilicon: See Figure 3. Boron and phosphorus are selectively implanted on the intrinsic polysilicon through printing and heat treatment of the doping paste to form alternating P-type doping regions and N-type doping regions. Intrinsic polysilicon is left between the N-type doping region and the P-type doping region as isolation. In addition to being formed by printing and heat treatment of the doping paste, doped polysilicon can also be formed by ion implantation or by using a mask and a doping diffusion furnace.

[0056] S3. Forming a semiconductor layer: See Figure 4. TiO2 is formed as a semiconductor layer by PVD deposition on doped polysilicon and intrinsic polysilicon with a thickness of 60nm. The deposition process of the secondary conductor layer can also use vacuum deposition methods such as PECVD and ALD, or a slurry printing process. The semiconductor layer can be doped with other elements. The dopant can be one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O). The dopant content can be 0-5wt%. The semiconductor layer can also be TiO2 / TiO2 deposited outward in the doped polysilicon. x (Al-doped TiO x ), or a double-layer semiconductor layer composed of TiO2 / WO3, or TiO2 / MoO3, etc., the energy loss of charge collection and the reflectivity of light of the double-layer semiconductor layer are lower.

[0057] S4. Forming metal electrodes: See Figure 5. Aluminum paste is printed simultaneously on the semiconductor layer above the P-type doped region and the N-type doped region. P-type and N-type electrodes are then formed by rapid thermal processing. The P-type and N-type electrodes are in direct contact with the semiconductor layer and do not contact the doped polysilicon below. Depending on actual needs, the P-type and N-type electrodes can also be printed separately. The rapid thermal processing temperature is set to 920°C, and the peak temperature of the rapid thermal processing process can be between 840 and 920°C. The aluminum paste can contain silicon, and the silicon content can be between 0 and 20 wt%. A TiAl metal alloy is formed between the contact surface of the semiconductor layer and the N-type and P-type electrodes to prevent oxygen in the semiconductor layer from diffusing into the Al metal electrode.

[0058] Different from other commonly used materials for photovoltaic cells, such as TiN, TiON, and Ti, although they can also block the diffusion of Al or Cu metals, their performance in solar cells has the following problems:

[0059] 1. See Figure 9. Due to its high conductivity, it cannot be used in back-contact solar cells. Electrons collected from the N-type doped region can flow through the material and then recombine with holes from the P-type doped region, which will cause a huge current leakage.

[0060] 2. As shown in Figure 10, due to its high light reflectivity, its bifaciality is very low. Since most of the light is absorbed or reflected, the efficiency of the solar cell will be very low when shining light on the back side.

[0061] Therefore, the invention uses TiO2, WO3, MoO3, TeO2 or NiO as the semiconductor layer material for blocking Al diffusion, which has the advantages of low conductivity and light reflection / absorption rate, and is particularly suitable for double-sided light-receiving solar cells.

[0062] Example 2

[0063] The difference from Example 1 is that, as shown in FIG1(b), SiO is also deposited on the semiconductor layer 5. x As the passivation layer 6, the metal electrode passes through the passivation layer 6 and contacts the semiconductor layer 5. The material of the passivation layer can also be SiN x 、SiO x 、SiON x Or a combination of one or more layers of Al2O3, the passivation layer can form a stable surface layer to reduce electron recombination and surface reflection, thereby improving the efficiency of the solar cell.

[0064] Example 3

[0065] The difference from Example 2 is that, as shown in Figure 1(c), the semiconductor layer 5 and the passivation layer 6 are inverted. After the passivation layer 6 is deposited on the doped polysilicon and the intrinsic polysilicon, the passivation layer 6 is locally removed above the P-type doping region 3 and the N-type doping region 4 by laser to form a contact hole, and the semiconductor layer 5 is deposited on the entire surface of the passivation layer 6 so that the semiconductor layer 5 contacts the P-type doping region 3 and the N-type doping region 4 through the contact hole.

[0066] Example 4

[0067] The difference from the embodiment 1 is that, in S4 , as shown in FIG6 , the semiconductor layer 5 above the P-type doping region 3 is thinner than the semiconductor layer 5 above the N-type doping region 4 .

[0068] In this embodiment, as shown in FIG7 , the semiconductor layer on top of the polysilicon in the P-type doped region can be slightly thinned by laser ablation. The semiconductor layer above the P-type doped region is 40 nm, and the semiconductor layer above the N-type semiconductor is 60 nm. The laser in this embodiment is ultraviolet light with a wavelength of 355 nm and an energy density of 0.1 to 0.5 J / cm 2 , since ultraviolet laser has better selective absorption for the second semiconductor with a larger energy gap, ultraviolet laser is more suitable.

[0069] Alternatively, the semiconductor layer above the P-type doped region can be made thinner than the semiconductor layer above the N-type doped region by forming a metal alloy on the semiconductor layer above the P-type doped region. As shown in Figure 8, a thin TiO2 semiconductor layer is first formed on the polysilicon layer, and then Ti metal is simultaneously formed on top of the semiconductor layer. Only the first aluminum paste is printed above the P-type doped region and sintered, forming a TiAl metal alloy and a P-type electrode on the P-type doped region, while TiO2 is formed in other areas. A second aluminum paste is printed above the N-type doped region and sintered, thereby also making the semiconductor layer above the P-type doped region thinner than the semiconductor layer above the N-type doped region.

[0070] By adjusting the thickness of the semiconductor above the P-type doped region and the N-type doped region, the contact resistance of aluminum in the P-type doped region 3 can be optimized while preventing damage caused by aluminum diffusion in the N-type doped region 4. The specific research is as follows.

[0071] After research, it was found that the diffusion of aluminum in the tunnel oxide layer / doped polysilicon causes passivation damage to the tunnel oxide layer / doped polysilicon:

[0072] 1. Problems with aluminum doping in N-type doped polysilicon regions: Diffused aluminum causes Al doping in the polysilicon layer of the N-type doped region. Increasing Al doping ultimately converts N-type doping to P-type doping, resulting in a decrease in the N-type doping efficiency of the polysilicon. In contrast, P-type doped polysilicon does not have this problem because it has the same polarity as Al doping.

[0073] 2. The problem of Al further diffusing into the tunnel oxide layer: This will cause passivation loss to P-type and N-type doped polysilicon.

[0074] In this regard, the optimal thickness of the semiconductor layer corresponding to N-type doping and P-type doping is explored:

[0075] FIG11a) shows the contact resistance characteristics of the N-type doped polysilicon and semiconductor layer with the aluminum electrode, and FIG11b) shows the contact resistance characteristics of the P-type doped polysilicon and semiconductor layer with the aluminum electrode.

[0076] As shown in Figure 11a), in a dual-layer structure of N-type doped polysilicon and a semiconductor layer, aluminum exhibits excellent contact resistance. This resistance remains stable even with varying semiconductor layer thicknesses. This is because the tunneling oxide layer applied to the semiconductor layer has a good energy level match with the conduction band of the N-type doped polysilicon.

[0077] As shown in Figure 11b), in a double-layer structure of P-type doped polysilicon and semiconductor layers, the contact resistance decreases as the thickness decreases. This phenomenon is caused by the misalignment of the valence band energy levels of the polysilicon in the P-type doped region and the semiconductor layer. Below a certain thickness, the tunneling effect becomes the dominant effect of electrons passing through the semiconductor layer's energy band, thereby reducing the contact resistance. As mentioned earlier, the reason why aluminum paste and high-temperature sintering processes are difficult to apply to doped polysilicon is that 1) aluminum reacts with silicon to form P-type dopants, and 2) aluminum diffuses into the tunneling oxide layer below the doped polysilicon, destroying the passivation properties of the oxide film.

[0078] It can be seen that in the absence of passivation loss of doped polysilicon, the thinner the thickness of the semiconductor layer, the lower the contact resistivity. In addition, using materials such as TiO2 as the semiconductor layer, its band alignment is well matched with the polysilicon in the N-type doped region, thus having good electron collection (because its resistivity is not strongly dependent on the thickness of the semiconductor layer). For P-type doped polysilicon, holes can be collected by TiO2. Therefore, the TiO2 above the P-type doped region is thinner, resulting in a lower resistivity.

[0079] Figure 12 shows the measured results of the passivation reduction caused by aluminum diffusion in a dual-layer structure of doped polysilicon and a semiconductor layer. Photoluminescence (PL) measurement is a widely used technique in the solar cell industry to analyze changes in passivation properties. In this paper, it was used to analyze the passivation reduction caused by aluminum diffusion. The results in the figure are average PL intensities.

[0080] As shown in Figure 12, the decrease in PL intensity indicates a degradation of the passivation properties caused by aluminum diffusion. In particular, in the N-type doped polysilicon region, the PL intensity drops sharply, even with a relatively thick semiconductor layer. This is because aluminum diffusion and doping through the N-type polysilicon weaken the field passivation effect of the N-type doping. As can be seen in Figure 10, when the semiconductor layer thickness decreases to a certain range, the PL intensity for both P-type and N-type doped polysilicon shows a turn and remains constant.

[0081] Therefore, the present invention proposes an optimal range of semiconductor layer thickness conditions: the semiconductor layer thickness above the N-type doped region is 40 to 70 nm, and the semiconductor layer thickness above the P-type doped region is 20 to 70 nm. That is, within the optimal range of semiconductor layer thickness conditions, the polysilicon in the N-type doped region will not be doped by Al diffusion, and its passivation quality will not be reduced by P-type doping, resulting in a higher PL intensity, good passivation characteristics, and lower contact resistance with the Al metal electrode. In the thinner P-type doped region, Al diffuses into the polysilicon but does not diffuse into the tunneling oxide layer. Even if the P-type doped region is doped with Al, its passivation quality will not be reduced, and it will also have a lower contact resistance with the Al metal electrode. This allows the solar cell of the present invention to use low-cost slurry to form the metal electrode while also demonstrating excellent solar cell high performance.

[0082] The technical solution provided by the present invention is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A low-cost, high-performance solar cell, characterized in that: include: A silicon wafer, a tunneling oxide layer and doped polysilicon formed on the silicon wafer, wherein an N-type doped region and a P-type doped region are formed on the doped polysilicon, and intrinsic polysilicon is spaced between the N-type doped region and the P-type doped region; a semiconductor layer is formed on the doped polysilicon and the intrinsic polysilicon, and the material of the semiconductor layer includes a combination of one or more layers of TiO2, WO3, MoO3, TeO2 or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doped region, and a P-type electrode is formed on the semiconductor layer corresponding to the P-type doped region, and the N-type electrode and the P-type electrode are in contact with the semiconductor layer.

2. A low-cost, high-performance solar cell according to claim 1, characterized in that: The thickness of the doped polysilicon is 20 nm to 100 nm, and the thickness of the semiconductor layer is 10 nm to 100 nm.

3. A low-cost, high-performance solar cell according to claim 1, characterized in that: The semiconductor layer above the P-type doping region has the same thickness as or thinner than the semiconductor layer above the N-type doping region.

4. A low-cost, high-performance solar cell according to claim 1, characterized in that: The thickness of the semiconductor layer above the N-type doping region is 40 to 70 nm, and the thickness of the semiconductor layer above the P-type doping region is 20 to 70 nm.

5. A low-cost, high-performance solar cell according to claim 1, characterized in that: A metal alloy is formed between the contact surface of the semiconductor layer and the P-type electrode and / or the N-type electrode.

6. A low-cost, high-performance solar cell according to claim 1, characterized in that: The semiconductor layer contains 0-5 wt% of dopants, and the dopants include one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).

7. A low-cost, high-performance solar cell according to claim 1, characterized in that: The P-type electrode and / or the N-type electrode include Al, Ag, Cu or a mixture thereof.

8. The low-cost, high-performance solar cell according to claim 1, characterized in that: The P-type electrode and / or the N-type electrode are formed of aluminum paste, and the silicon content in the aluminum paste is 0-20 wt %.

9. The low-cost, high-performance solar cell according to claim 1, characterized in that: A passivation layer is also included, and the passivation layer is formed on the semiconductor layer.

10. The low-cost, high-performance solar cell according to claim 1, characterized in that: It also includes a passivation layer, the passivation layer is formed on the doped polysilicon and the intrinsic polysilicon, the semiconductor layer is formed on the passivation layer, the semiconductor layer passes through the passivation layer and contacts the doped polysilicon, and the material of the passivation layer is SiN x 、SiO x 、SiON x Or a combination of one or more layers of Al2O3.

11. The process for manufacturing a low-cost, high-performance solar cell according to any one of claims 1 to 10, characterized in that: The following steps are involved: S1, forming a tunnel oxide layer and intrinsic polysilicon on a silicon wafer; S2. Selectively implanting boron and phosphorus into the intrinsic polysilicon to form doped polysilicon, alternately forming N-type doped regions and P-type doped regions on the doped polysilicon, with intrinsic polysilicon remaining between the N-type doped region and the P-type doped region as isolation; S3, forming a semiconductor layer on the doped polysilicon; S4. Form an N-type electrode and a P-type electrode on the semiconductor layer, so that the N-type electrode contacts the semiconductor layer above the N-type doping region, and the P-type electrode contacts the semiconductor layer above the P-type doping region.

12. The low-cost, high-performance solar cell manufacturing process according to claim 11, characterized in that: In S2, boron and phosphorus are selectively implanted by ion implantation, printing and heat treatment of a doping paste, or using a mask and a doping diffusion furnace; In S3, the semiconductor layer above the P-type doped region is subjected to laser ablation, or a metal alloy is formed on the semiconductor layer above the P-type doped region so that the semiconductor layer above the P-type doped region is thinner than the semiconductor layer above the N-type doped region; In S4 , the N-type electrode and the P-type electrode are formed by simultaneously printing metal paste on the semiconductor layer and sintering, or the N-type electrode and the P-type electrode are formed by separately printing metal paste on the semiconductor layer and sintering.

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