Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises: a first conductive layer (001), a second conductive layer (002) and a third conductive layer (003), which are arranged on a base substrate in a stacked manner; and a sub-pixel driving circuit, which comprises a plurality of transistors. The display substrate further comprises a light-shielding layer (2), wherein the light-shielding layer (2) and the first conductive layer (001) are arranged on the same layer.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024, with application number 202410384694.7 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Transparent display panels, a new application that has emerged in recent years, have garnered significant attention. This technology has greatly expanded the scope and application scenarios of displays and provided convenience for people's lives. Currently, transparent display panels are mostly top-emitting. In top-emitting transparent display panels, the pixel light-emitting area and the pixel driver circuit overlap. However, in larger transparent display panels, the driver signal lines of the pixel driver circuit are designed to be wider. Wider driver signal lines occupy a larger area, which in turn reduces the transparent area and the transparency of the display panel.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] The present disclosure provides a display substrate, comprising a display area and a non-display area surrounding the display area, wherein the display area includes a transparent area and a non-transparent area; the display substrate further includes a base substrate and a plurality of pixel units and a plurality of signal traces arranged in an array on the base substrate; the pixel units include a plurality of sub-pixels and a plurality of sub-pixel driving circuits electrically coupled to the plurality of sub-pixels in a one-to-one correspondence; at least a portion of the plurality of signal traces is electrically coupled to the plurality of sub-pixel driving circuits and provides driving signals to the plurality of sub-pixel driving circuits;

[0007] The display substrate further includes a first conductive layer, a second conductive layer, and a third conductive layer stacked on the base substrate; the sub-pixel driving circuit includes a plurality of transistors, and the display substrate further includes a light shielding layer for shielding at least part of the plurality of transistors from light, the light shielding layer being provided on the same layer as the first conductive layer;

[0008] The first conductive layer includes at least one first signal line among the multiple signal lines, the second conductive layer includes at least one second signal line among the multiple signal lines, and the third conductive layer includes at least one third signal line among the multiple signal lines; the orthographic projection of the at least one first signal line on the substrate at least partially overlaps with the orthographic projection of the at least one second signal line and / or the at least one third signal line on the substrate.

[0009] The present disclosure also provides a display device, comprising the above-mentioned display substrate.

[0010] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0011] Summary of the Figures

[0012] FIG. 1A shows a schematic diagram of a pixel layout of an exemplary transparent display substrate.

[0013] FIG1B shows a schematic diagram of a pixel layout structure of an exemplary transparent display substrate.

[0014] FIG2A shows a schematic structural diagram of an exemplary display substrate provided by the present disclosure.

[0015] FIG2B shows a schematic diagram of an exemplary sub-pixel 010 driving circuit provided by the present disclosure.

[0016] FIG2C shows a schematic cross-sectional structure diagram of an exemplary display substrate provided by the present disclosure.

[0017] FIG2D shows a schematic cross-sectional structure diagram of multiple signal lines of an exemplary display substrate provided by the present disclosure.

[0018] FIG2E shows a schematic cross-sectional structure diagram of multiple signal lines of another exemplary display substrate provided by the present disclosure.

[0019] FIG3A shows a schematic diagram of a pixel layout of an exemplary display substrate according to an embodiment of the present disclosure.

[0020] FIG3B shows a schematic diagram of a pixel layout structure of an exemplary display substrate according to an embodiment of the present disclosure.

[0021] FIG3C shows a schematic cross-sectional structure diagram of an exemplary display substrate in an embodiment provided by the present disclosure.

[0022] 3D to 3K are schematic diagrams showing exemplary display substrate level graphics according to an embodiment of the present disclosure.

[0023] FIG4A shows a schematic diagram of a pixel layout of an exemplary display substrate in another embodiment provided by the present disclosure.

[0024] FIG4B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in another embodiment provided by the present disclosure.

[0025] FIG4C shows a schematic cross-sectional structure diagram of an exemplary display substrate in another embodiment provided by the present disclosure.

[0026] 4D to 4K are schematic diagrams showing exemplary display substrate level graphics according to another embodiment of the present disclosure.

[0027] FIG5A shows a schematic diagram of a pixel layout of an exemplary display substrate in another embodiment provided by the present disclosure.

[0028] FIG5B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in another embodiment provided by the present disclosure.

[0029] FIG5C shows a schematic cross-sectional structure diagram of an exemplary display substrate in another embodiment provided by the present disclosure.

[0030] 5D to 5K are schematic diagrams showing exemplary display substrate level graphics in yet another embodiment provided by the present disclosure.

[0031] FIG6A shows a schematic diagram of a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0032] FIG6B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0033] FIG6C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0034] 6D to 6K are schematic diagrams showing exemplary display substrate level graphics in yet another embodiment provided by the present disclosure.

[0035] FIG7A shows a schematic diagram of a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0036] FIG7B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0037] FIG7C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0038] 7D to 7K are schematic diagrams showing exemplary display substrate level graphics in yet another embodiment provided by the present disclosure.

[0039] FIG8A shows a schematic diagram of a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0040] FIG8B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0041] FIG8C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0042] 8D to 8K are schematic diagrams showing exemplary display substrate level graphics in yet another embodiment provided by the present disclosure.

[0043] FIG9A is a schematic diagram showing a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0044] FIG9B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0045] FIG9C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0046] 9D to 9K are schematic diagrams showing exemplary display substrate level graphics in yet another embodiment provided by the present disclosure.

[0047] Details

[0048] The specific embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate the present disclosure and are merely exemplary, but are not intended to limit the scope of the present disclosure. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other in any manner.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0050] In the top-emitting WOLED display panel, due to the overlapping design of the pixel light-emitting area and the pixel driving circuit, the space utilization rate is high, and it is easier to have a high pixel count (Pixels per inch, PPI) or a high aperture design, and it is easy to achieve a high transparency design in the transparent display panel. WOLED means that the pixel includes four sub-pixels of RGBW, among which the W sub-pixel (white light sub-pixel) is used to emit white light, so that the brightness of the pixel can be enhanced, thereby improving the brightness of the display panel. In other words, when the display panel has the same brightness, WOLED has lower power consumption because it has white light sub-pixels 010 to enhance the brightness. Compared with RGB OLED display panels, the WOLED display panel with the same resolution has W sub-pixels added to the WRGB pixels, making the pixel layout space more tight and more difficult, and posing greater challenges to the pixel aperture ratio and transparent area transmittance. In the current pixel design of transparent OLED display panels, the non-transparent area mainly occupies the pixel layout space by the pixel driving circuit wiring, driving TFT and pixel capacitor. In larger transparent display panels, due to their large size, the drive signal traces are typically designed to be wider, occupying a larger area and affecting the transparent area. FIG1A shows a schematic diagram of a pixel layout for an exemplary transparent display substrate. FIG1B shows a schematic diagram of a pixel layout structure for an exemplary transparent display substrate. Exemplarily, the transparent display substrate includes a base substrate 1 and a plurality of pixel units 01 and a plurality of signal lines arranged in an array on the base substrate 1; the pixel unit 01 includes a plurality of sub-pixels 010 and a plurality of sub-pixel 010 driving circuits coupled to the plurality of sub-pixels 010, and at least part of the plurality of signal lines is coupled to the plurality of sub-pixel 010 driving circuits and provides driving signals to the plurality of sub-pixel 010 driving circuits; the display substrate also includes a first conductive layer 001, a second conductive layer 002 and a third conductive layer 003 stacked on the base substrate 1; wherein the plurality of signal lines include four data lines, a scan line G1, a detection line Sense and two constant voltage lines, and the four data lines, the detection line Sense and the two constant voltage lines are all designed to be alternately arranged in the same layer vertically, and are manufactured using a single patterning process with the third conductive layer 003; the scan line G1 is designed horizontally, and is manufactured using a single patterning process with the second conductive layer 002. Since most of the multiple signal lines are arranged alternately on the same layer and the signal lines are designed to be wide, the signal lines will occupy a large area, reducing the transparent area and lowering the transparency of the display panel.

[0051] An embodiment of the present disclosure provides a display substrate, including a first conductive layer 001, a second conductive layer 002, and a third conductive layer 003 stacked on a base substrate 1; the sub-pixel 010 driving circuit includes a plurality of transistors, and the display substrate further includes a light-shielding layer 2 for at least partially shielding the plurality of transistors from light. The light-shielding layer 2 is arranged on the same layer as the first conductive layer 001. By arranging the light-shielding layer 2 and the first conductive layer 001 on the same layer, the thickness of the base substrate 1 can be reduced, and signal lines can also be arranged in the light-shielding layer 2, thereby reducing the area of ​​the transparent area a1 occupied by the signal lines and improving the transmittance. In one exemplary embodiment, multiple signal traces are arranged in multiple layers. For example, the first conductive layer 001 includes at least one first signal trace 0011 among the multiple signal traces, the second conductive layer 002 includes at least one second signal trace 0021 among the multiple signal traces, and the third conductive layer 003 includes at least one third signal trace 0031 among the multiple signal traces. The orthographic projection of the at least one first signal trace 0011 on the base substrate 1 at least partially overlaps with the orthographic projections of the at least one second signal trace 0021 and / or the at least one third signal trace 0031 on the base substrate 1. By arranging the multiple signal traces in three stacked conductive layers, an overlapping arrangement of the multiple signal traces can be achieved, reducing the area occupied by the signal traces and increasing the area of ​​the transparent area a1, thereby improving the transmittance of the display substrate.

[0052] FIG2A shows a schematic structural diagram of an exemplary display substrate provided by the present disclosure.

[0053] As shown in Figure 2A, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area b surrounding the display area, the display area including a transparent area a1 and a non-transparent area a2; the display substrate also includes a base substrate 1 and a plurality of pixel units 01 and a plurality of signal lines arranged in an array on the base substrate 1; the pixel unit 01 includes a plurality of sub-pixels 010 and a plurality of sub-pixel 010 driving circuits electrically coupled to the plurality of sub-pixels 010 in a one-to-one correspondence, and at least part of the plurality of signal lines is electrically coupled to the plurality of sub-pixel 010 driving circuits and provides driving signals to the plurality of sub-pixel 010 driving circuits.

[0054] In an exemplary embodiment, the plurality of sub-pixels 010 are arranged in a 2×2 arrangement of four sub-pixels 010, and the four sub-pixels 010 include white light sub-pixels 010. Exemplarily, the four sub-pixels 010 include RGBW (red, green, blue, and white), and the structure of the plurality of sub-pixel 010 driving circuits coupled to the four sub-pixels 010 in a one-to-one correspondence is consistent.

[0055] FIG2B shows a schematic diagram of an exemplary sub-pixel 010 driving circuit provided by the present disclosure.

[0056] As shown in Figure 2B , the sub-pixel 010 driving circuit is exemplarily a 3T1C circuit, i.e., the pixel circuit is composed of three transistors and one capacitor. T1 is the driving transistor, T2 is the data writing transistor, T3 is the detection transistor, and Cst is the storage capacitor Cst. Transistors T1, T2, and T3 are all N-type transistors.

[0057] Exemplarily, as shown in FIG2B , the sub-pixel 010 driving circuit includes a data writing module 0101 , a driving module 0102 , an energy storage module 0103 and a detection module 0104 ;

[0058] The data writing module 0101 is electrically connected to the scan line G1, the data line and the control end of the driving module 0102 respectively, and is configured to write the data voltage provided by the data line into the control end of the driving module 0102 under the control of the scan signal provided by the scan line G1.

[0059] In an exemplary embodiment, the data writing module 0101 includes a second transistor T2, a first electrode of the second transistor T2 being electrically connected to the data line, a control electrode of the second transistor T2 being electrically connected to the scan line G1, and a second electrode of the second transistor T2 being electrically connected to the control terminal of the driving module 0102. The second transistor T2 is configured to write a data voltage provided by the data line to the control terminal of the driving module 0102 under the control of a scan signal provided by the scan line G1.

[0060] The energy storage module 0103 is electrically connected to the control end of the driving module 0102 and is configured to store electrical energy.

[0061] In an exemplary embodiment, the energy storage module 0103 includes a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the control end of the driving module 0102, a second electrode of the storage capacitor Cst is connected to the second electrode of the driving module 0102, and the storage capacitor Cst is configured to store electrical energy.

[0062] The driving module 0102 is electrically connected to the first constant voltage line VDD and one end of the light-emitting element of the sub-pixel 010, and is configured to drive the light-emitting element under the control of the potential of the control end of the driving module 0102; the other end of the light-emitting element is electrically connected to the second constant voltage line VSS.

[0063] In an exemplary embodiment, the driving module 0102 includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the first constant voltage trace VDD, a second electrode of the first transistor T1 is electrically connected to one end of the light-emitting element, a control electrode of the first transistor T1 is electrically connected to the second electrode of the second transistor T2, and the first transistor T1 is configured to drive the light-emitting element under the control of the potential written by the receiving data writing module 0101, and the other end of the light-emitting element is electrically connected to the second constant voltage trace VSS.

[0064] The detection module 0104 is electrically connected to the scanning line G1, the detection line Sense, and the connection node between the driving module 0102 and the light-emitting element, and is configured to control the connection between the connection node and the detection line Sense under the control of the scanning signal.

[0065] In an exemplary embodiment, the detection module 0104 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to a connection point between the second electrode of the first transistor T1 and one end of the light-emitting element, a second electrode of the third transistor T3 is electrically connected to the detection trace Sense, and a control electrode of the third transistor T3 is electrically connected to the scan trace G1. The third transistor T3 is configured to control the connection between the connection point and the detection trace Sense under the control of a scan signal, so that the external circuit can obtain the potential of the driving module 0102 and provide a more stable driving signal for the driving module 0102.

[0066] FIG2C shows a schematic cross-sectional structure diagram of an exemplary display substrate provided by the present disclosure.

[0067] As shown in Figure 2C, the display substrate also includes a first conductive layer 001, a second conductive layer 002 and a third conductive layer 003 stacked on the base substrate 1; the sub-pixel 010 driving circuit includes a plurality of transistors, and the display substrate also includes a light-shielding layer 2 for at least partially shielding light from the plurality of transistors, and the light-shielding layer 2 is arranged on the same layer as the first conductive layer 001.

[0068] In an exemplary embodiment, as shown in FIG2C , the display substrate includes a light shielding layer 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate layer 6, an interlayer dielectric layer 7, a source / drain layer 8, a passivation layer 9, a planarization layer 10, a pixel electrode anode 11, a pixel defining layer 12, a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, a blocking dam 17, the blocking dam 17 being disposed on a side of the encapsulation layer 15 away from the base substrate 1, and further provided with a filler 16, a color filter 18, a black matrix 19, and glass 20. The black matrix 19 is disposed in the same layer as the color filter 18, and the blocking dam 17 is disposed on the sides of the filler 16 and the color filter 18 to block the filler 16. The light shielding layer 2 is disposed in the same layer as the first conductive layer 001, or the light shielding layer 2 serves as the first conductive layer 001, the second conductive layer 002 serves as the gate layer 6, and the third conductive layer 003 serves as the active layer 4. In this way, signal lines can be laid out on different conductive layers, enabling overlapping signal lines, reducing the area of ​​the transparent region a1 occupied by the signal lines, and improving transmittance. In an exemplary embodiment, the light shielding layer 2 can serve as the plate of the pixel storage capacitor Cst, and the light shielding layer 2 is made of a metal with low resistance.

[0069] As shown in FIG2C , the layers of the display substrate are partially connected by vias. In the following embodiments, vias can be used for connection, which is set according to actual needs and will not be described in detail in this disclosure. In an exemplary embodiment, the via design may include:

[0070] An ILD hole is etched in the interlayer dielectric layer 7 by an etching process. The ILD hole is used to connect the active layer 4 and the source-drain layer 8. For example, the through hole on the left side of the SD layer in FIG2C penetrates the ILD layer. An ILD semi-buried hole is etched in the ILD layer by an etching process. The ILD semi-buried hole is used for connecting the active layer 4, the source-drain layer 8 and the gate layer 6. For example, the two through holes on the right side of the SD layer in FIG2C penetrate the ILD layer and the buffer layer are ILD semi-buried holes. Alternatively, CNT / ILD sleeve holes and PVX / Resin sleeve holes may be included. The CNT / ILD sleeve holes and PVX / Resin sleeve holes may be a large hole on the outside and a small hole on the inside.

[0071] FIG2D shows a schematic cross-sectional structure diagram of multiple signal lines of an exemplary display substrate provided by the present disclosure.

[0072] FIG2E shows a schematic cross-sectional structure diagram of multiple signal lines of another exemplary display substrate provided by the present disclosure.

[0073] As shown in Figures 2D and 2E, the first conductive layer 001 includes at least one first signal line 0011 among the multiple signal lines, the second conductive layer 002 includes at least one second signal line 0021 among the multiple signal lines, and the third conductive layer 003 includes at least one third signal line 0031 among the multiple signal lines; the first signal line 0011, the second signal line 0021 and the third signal line 0031 each include a main body and a branch portion, the main body extends along a first direction, and the branch portion extends along a second direction, and the first direction is perpendicular to the second direction; the orthographic projection of the main body of the at least one first signal line 0011 on the base substrate 1 completely overlaps with the orthographic projection of the main body of the at least one second signal line 0021 and / or the at least one third signal line 0031 on the base substrate 1.

[0074] In an exemplary embodiment, at least one first signal line 0011 among the plurality of signal lines is fabricated with the first conductive layer 001 using a single patterning process, at least one second signal line 0021 among the plurality of signal lines is fabricated with the second conductive layer 002 using a single patterning process, and at least one third signal line 0031 among the plurality of signal lines is fabricated with the third conductive layer 003 using a single patterning process. Furthermore, the orthographic projection of the at least one first signal line 0011 on the base substrate 1 partially overlaps with the orthographic projections of the at least one second signal line 0021 and / or the at least one third signal line 0031 on the base substrate 1. Thus, multiple data lines can be fabricated with different conductive layers using a single patterning process, and multiple data lines can be arranged in an overlapping manner, thereby reducing the area occupied by the data lines, increasing the transparent area a1, and improving transmittance.

[0075] In an exemplary embodiment, as shown in FIG2D , at least one first signal trace 0011 may include a first data trace Data1, a fourth data trace Data4, and a detection trace Sense; at least one second signal trace 0021 may include a second signal trace 0021, a third signal trace 0031, and a second constant voltage trace VSS; and at least one third signal trace 0031 may include a first constant voltage trace VDD and a scan trace G1. The orthographic projection of at least one first signal trace 0011 in the first conductive layer 001 on the base substrate 1 at least partially overlaps with the orthographic projection of at least one third signal trace 0031 on the base substrate 1. For example, the orthographic projection of the main portion of at least one first signal trace 0011 in the first conductive layer 001 on the substrate 1 completely overlaps with the orthographic projection of the main portion of at least one third signal trace 0031 on the substrate 1, and the orthographic projection of the branch portion of at least one first signal trace 0011 in the first conductive layer 001 on the substrate 1 partially overlaps with the orthographic projection of the branch portion of at least one third signal trace 0031 on the substrate 1 (see FIG. 7B in yet another embodiment). It can be seen that the detection trace Sense in FIG. 2D overlaps with the first constant voltage trace VDD. In this way, the overlapping arrangement of some data traces reduces the area of ​​the transparent region a1 occupied by the data traces compared to an alternating arrangement of multiple data traces, thereby improving transmittance.

[0076] As shown in Figure 2E, at least one first signal line 0011 may include a first data line Data1, a second data line Data2, a third data line Data3, a fourth data line Data4 and a detection line Sense, and at least one third signal line 0031 may include a first constant voltage line VDD, a second constant voltage line VSS and a scan line G1. The orthographic projection of at least the first signal line 0011 in the first conductive layer 001 on the base substrate 1 at least partially overlaps with the orthographic projection of at least one third signal line 0031 on the base substrate 1. For example, the orthographic projection of the main portion Data01 of the first data trace Data1 and the second data trace Data2 on the substrate completely overlaps with the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD (or as shown in Figure 5H) on the substrate 1, while the orthographic projection of the branch portion Data02 of the first data trace Data1 and the second data trace Data2 on the substrate partially overlaps with the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the substrate 1, and the orthographic projection of the branch portion VDD02 of the first constant voltage trace VDD on the substrate 1 partially overlaps with the orthographic projection of the main portion Data01 of the first data trace Data1 and the second data trace Data2 on the substrate (that is, the branch portion VDD02 of the first constant voltage trace VDD is a signal trace coupled to the sub-pixel driving circuit). The orthographic projections of the main portion Data01 of the third data routing Data3 and the fourth data routing Data4 on the substrate substrate completely overlap with the orthographic projections of the main portion VSS01 of the second constant voltage routing VSS (or as shown in Figure 5H) on the substrate substrate 1, while the orthographic projections of the branch portion Data02 of the third data routing Data3 and the fourth data routing Data4 on the substrate substrate partially overlap with the orthographic projections of the main portion VSS01 of the second constant voltage routing VSS on the substrate substrate 1, and the orthographic projections of the branch portion VSS02 of the second constant voltage routing VSS on the substrate substrate 1 partially overlap with the orthographic projections of the main portion Data01 of the third data routing Data3 and the fourth data routing Data4 on the substrate substrate (that is, the branch portion VSS02 of the second constant voltage routing VSS is a signal routing coupled to the sub-pixel driving circuit) (as shown in Figure 5B in another embodiment). As can be seen in Figure 2E , the first and second data traces Data1 and Data2 overlap with the first constant voltage trace VDD, while the third and fourth data traces Data3 and Data4 overlap with the second constant voltage trace VSS. This overlapping arrangement of some data traces reduces the area of ​​the transparent region a1 occupied by the data traces compared to an alternating arrangement of multiple data traces, thereby improving transmittance.

[0077] One embodiment

[0078] FIG3A shows a schematic diagram of a pixel layout of an exemplary display substrate according to an embodiment of the present disclosure.

[0079] FIG3B shows a schematic diagram of a pixel layout structure of an exemplary display substrate according to an embodiment of the present disclosure.

[0080] As shown in FIG3A and FIG3B , along the extension direction of the main portion of the signal line, the four sub-pixels 010 share one detection line Sense, and two sub-pixels 010 form a group of four sub-pixels, which are respectively arranged on both sides of the detection line Sense; and / or,

[0081] The first constant voltage trace VDD and the second constant voltage trace VSS both extend along the first direction. The four sub-pixels 010 share one first constant voltage trace VDD and one second constant voltage trace VSS. The first constant voltage trace VDD is located on one side of the four sub-pixels 010, and the second constant voltage trace VSS is located on the other side of the four sub-pixels 010.

[0082] Exemplarily, the first direction includes the longitudinal direction. The first sub-pixel 101 and the third sub-pixel 103 form a first group, and the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction. The first group of sub-pixels 010 is arranged in the left area of ​​the detection trace Sense, and the second group of sub-pixels 010 is arranged in the right area of ​​the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS. The first constant voltage trace VDD and the second constant voltage trace VSS are respectively arranged on both sides of the four sub-pixels 010. Exemplarily, the first constant voltage trace VDD is arranged on the left side of the four sub-pixels 010, and the second constant voltage trace VSS is arranged on the right side of the four sub-pixels 010. In this way, the signal lines are arranged in close proximity to the sub-pixels 010, reducing the number of signal line traces and thereby reducing the area occupied by the signal lines, increasing the area of ​​the transparent region a1, and improving the transmittance.

[0083] As shown in Figures 3A and 3B, the orthographic projection of the at least one first signal trace 0011 on the base substrate 1 and the orthographic projection of the at least one second signal trace 0021 on the base substrate 1 are arranged alternately; and / or, the orthographic projection of the at least one first signal trace 0011 on the base substrate 1 and the orthographic projection of the at least one third signal trace 0031 on the base substrate 1 are arranged alternately.

[0084] Exemplarily, the at least one first signal line 0011 includes at least one of the first constant voltage line VDD, the second constant voltage line VSS, the data line, and the detection line Sense; the at least one third signal line 0031 includes the scan line G1. The four sub-pixels 010 include a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103 and a fourth sub-pixel 104; the sub-pixel 010 driving circuit corresponding to the first sub-pixel 101 includes a first data routing Data1, the sub-pixel 010 driving circuit corresponding to the second sub-pixel 102 includes a second data routing Data2, the sub-pixel 010 driving circuit corresponding to the third sub-pixel 103 includes a third data routing Data3, and the sub-pixel 010 driving circuit corresponding to the fourth sub-pixel 104 includes a fourth data routing Data4; the first data routing Data1, the second data routing Data2, the third data routing Data3 and the fourth data routing Data4 extend along the first direction, and the first data routing Data1 and the second data routing Data2 are located on one side of the four sub-pixels 010, and the third data routing Data3 and the fourth data routing Data4 are located on the other side of the four sub-pixels 010.

[0085] In this embodiment, at least one first signal line 0011 includes a first constant voltage line VDD, a second constant voltage line VSS, the data line, and the detection line Sense. Multiple first signal lines 0011 are alternately arranged and fabricated using a single patterning process with the first conductive layer 001. At least one third signal line 0031 includes a scan line G1. At least one of the multiple first signal lines 0011 can be fabricated using a single patterning process with the second conductive layer 002 and / or the third conductive layer 003. That is, at least one of the multiple first signal lines 0011 can be the second signal line 0021 and / or the third signal line 0031. Then, the orthographic projection of at least one first signal trace 0011 on the substrate 1 and the orthographic projection of at least one second signal trace 0021 on the substrate 1 are arranged alternately; and / or the orthographic projection of at least one first signal trace 0011 on the substrate 1 and the orthographic projection of at least one third signal trace 0031 on the substrate 1 are arranged alternately. For details, please refer to other embodiments below, and this embodiment will not be described in detail.

[0086] In an exemplary embodiment, the first data line Data1, the second data line Data2, the third data line Data3 and the fourth data bus extend in the longitudinal direction, the first sub-pixel 101 and the third sub-pixel 103 are the first group, the first data line Data1 and the second data line Data2 correspond to the first sub-pixel 101 and the third sub-pixel 103, and since the first group of sub-pixels 010 is set on the left side of the detection line Sense, the first data line Data1 and the second data line Data2 are set on the left side of the first group of sub-pixels 010. In this way, the first data line Data1 and the second data line Data2 are set adjacent to the corresponding sub-pixels 010, reducing the number of lines. The second sub-pixel 102 and the fourth sub-pixel 104 are grouped together. The third data traces Data3 and the fourth data traces Data4 correspond to the second sub-pixel 102 and the fourth sub-pixel 104. Since the second sub-pixel 010 is located to the right of the detection trace Sense, the third data traces Data3 and the fourth data traces Data4 are located to the right of the second sub-pixel 010. This places the third data traces Data3 and the fourth data traces Data4 close to the corresponding sub-pixels 010, reducing the number of traces. In one exemplary embodiment, the detection trace Sense is located in the middle of the non-display area b region a. The first sub-pixel 101 and the third sub-pixel 103 are grouped together and located to the left of the detection trace Sense. The second sub-pixel 102 and the fourth sub-pixel 104 are grouped together and located to the right of the detection trace Sense. The first sub-pixel 101 and the second sub-pixel 102 are symmetrically arranged, and the third sub-pixel 103 and the fourth sub-pixel 104 are symmetrically arranged. In this way, the signal line is arranged in close proximity to the sub-pixel 010, reducing the number of signal line traces, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving transmittance. At least one third signal trace 0031 includes a scan trace G1, which extends along a second direction, wherein the second direction includes a transverse direction, and the first direction is arranged perpendicular to the second direction. Because the first signal trace 0011 and the first conductive layer 001 are manufactured using a single patterning process, and the third signal trace 0031 and the third conductive layer 003 are manufactured using a single patterning process, multiple insulating layers are separated between the first signal trace 0011 and the third signal trace 0031, which can improve the yield rate of metal crossovers. When the yield rate is high enough, it can replace the repair design, thereby improving space utilization and increasing the area of ​​the transparent region a1.

[0087] FIG3C shows a schematic cross-sectional structure diagram of an exemplary display substrate in an embodiment provided by the present disclosure.

[0088] 3D to 3K are schematic diagrams showing exemplary display substrate level graphics according to an embodiment of the present disclosure.

[0089] As shown in Figures 3C and 3D, the first constant voltage trace VDD, the first data trace Data1, the second data trace Data2, the detection trace Sense, the third data trace Data3, the fourth data trace Data4 and the second constant voltage trace VSS are alternately arranged in sequence, and are manufactured with the first conductive layer 001 using a single patterning process (the signal trace is insulated from the first conductive layer 001) to form a pattern as shown in Figure 3D. A buffer layer 3 is formed above the plurality of signal traces, and an active layer 4 is formed above the buffer layer 3. A single patterning process is used to form a pattern as shown in FIG3E (pattern 41 in FIG3E). A gate insulating layer 5 is formed on the active layer 4. A second conductive layer 002 is formed on the gate insulating layer 5. A first constant voltage trace and a second constant voltage trace of the second layer are formed on the second conductive layer 002 (the signal trace is insulated from the second conductive layer 002). A single patterning process is used to form a pattern as shown in FIG3F (pattern 61 in FIG3F is the pattern of the second conductive layer 002). The first constant voltage trace and the second constant voltage trace of the second layer are overlapped with the first constant voltage signal and the second constant voltage trace of the first layer. In an exemplary embodiment, the constant voltage trace of the first layer is a constant voltage trace formed simultaneously with the first conductive layer 001, and the constant voltage trace of the second layer is a constant voltage trace formed simultaneously with the second conductive layer 002. In this embodiment, two layers of constant voltage traces are used to reduce trace resistance and thus reduce voltage drop on the trace. An interlayer dielectric layer 7 is made on the constant voltage trace of the second layer, and CNT opening is performed to form a pattern as shown in FIG3G (the pattern marked 71 in FIG3G ). A third conductive layer 003 and a scanning line are stacked on the interlayer dielectric layer 7 (the signal trace is insulated from the third conductive layer 003), and a one-time patterning process is used to form a pattern as shown in FIG3H (811 / 812 / 813 / 814 in FIG3H are all patterns of the third conductive layer 003). A passivation layer 9 and a flat layer 10 are stacked on the third conductive layer, and a one-time patterning process is used to form a pattern as shown in FIG3I (91 in FIG3I is the pattern of the passivation layer 9, and 10 to 1 are the patterns of the flat layer 10). A pixel electrode is made on the flat layer 10, and a one-time patterning process is used to form a pattern as shown in FIG3J (1 in FIG3J ). 11 pixel electrode pattern), a pixel defining layer 12 is made on the pixel electrode, and an etching process is adopted to form a pattern as shown in FIG3K (the blank area 121 in FIG3K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are sequentially stacked on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and a glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16.In this embodiment, the first constant voltage line VDD, the second constant voltage line VSS, the first data line Data1, the second data line Data2, the third data line Data3, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 by a single patterning process, and every two sub-pixels 010 in the four sub-pixels 010 are divided into a group, the four sub-pixels 010 share one detection line Sense, the first constant voltage line VDD and the second constant voltage line VSS, the detection line Sense is arranged between the four sub-pixels 010, the data lines are arranged adjacent to the corresponding sub-pixels 010, and the first constant voltage line VDD and the second constant voltage line VSS are arranged on both sides of the data lines, thereby saving the number of signal lines and reducing the space occupied by multiple signal lines, thereby increasing the transparent area a1 and improving the transmittance.

[0090] Another embodiment

[0091] FIG4A shows a schematic diagram of a pixel layout of an exemplary display substrate in another embodiment provided by the present disclosure.

[0092] FIG4B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in another embodiment provided by the present disclosure.

[0093] As shown in Figures 4A and 4B, along the extension direction of the main body of the signal line, the four sub-pixels 010 share one detection line Sense, and among the four sub-pixels 010, two sub-pixels 010 form a group and are respectively arranged on both sides of the detection line Sense; and / or, the first constant voltage line VDD and the second constant voltage line VSS both extend along the first direction, and the four sub-pixels 010 share one first constant voltage line VDD and one second constant voltage line VSS, the first constant voltage line VDD is located on one side of the four sub-pixels 010, and the second constant voltage line VSS is located on the other side of the four sub-pixels 010.

[0094] Exemplarily, the first direction includes the longitudinal direction. The four sub-pixels 010 include a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. The first sub-pixel 101 and the third sub-pixel 103 form a first group, and the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction. The first group of sub-pixels 010 is arranged to the left of the detection trace Sense, and the second group of sub-pixels 010 is arranged to the right of the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS. The first constant voltage trace VDD and the second constant voltage trace VSS are respectively arranged on either side of the four sub-pixels 010. Exemplarily, the first constant voltage trace VDD is arranged to the left of the four sub-pixels 010, and the second constant voltage trace VSS is arranged to the right of the four sub-pixels 010. In this way, the signal line is arranged close to the sub-pixel 010, which reduces the number of signal line routings, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving the transmittance.

[0095] As shown in Figures 4A and 4B, the orthographic projection of the at least one first signal trace 0011 on the base substrate 1 and the orthographic projection of the at least one second signal trace 0021 on the base substrate 1 are arranged alternately; and / or, the orthographic projection of the at least one first signal trace 0011 on the base substrate 1 and the orthographic projection of the at least one third signal trace 0031 on the base substrate 1 are arranged alternately.

[0096] In an exemplary embodiment, the at least one signal trace includes a constant voltage trace for providing a constant voltage signal; the at least one second signal trace 0021 includes the at least one second signal trace 0021 includes two second signal traces 0021 arranged in parallel, and the orthographic projections of the two second signal traces 0021 on the base substrate 1 are located within the orthographic projection of the constant voltage trace on the base substrate 1.

[0097] For example, as shown in FIG4B , at least one signal line further includes two data lines, and the orthographic projections of the two data lines on the substrate 1 are located within the orthographic projections of the constant voltage line on the substrate 1; the data line includes the second data line Data2 and the third data line Data3; the constant voltage line includes the first constant voltage line VDD and the second constant voltage line VSS; the at least one second signal line 0021 includes the first data line Data1 and the fourth data line Data4; the at least one third signal line 0031 includes the scan line G1, and the scan line G1 Extending along a second direction, the first direction is perpendicular to the second direction; the orthographic projection of the main portion Data01 of the first data trace Data1 on the base substrate 1 is located between the orthographic projection of the main portion Data01 of the second data trace Data2 and the main portion Data01 of the first constant voltage trace VDD on the base substrate 1; the orthographic projection of the main portion Data01 of the fourth data trace Data4 on the base substrate 1 is located between the orthographic projection of the main portion Data01 of the third data trace Data3 and the main portion Data01 of the second constant voltage trace VSS on the base substrate 1.

[0098] In this embodiment, at least one first signal line includes a first constant voltage trace VDD, a second data trace Data2, a third data trace Data3, and a second constant voltage trace VSS, which are alternately arranged in sequence. At least the second signal trace 0021 includes a first data trace Data1 and a fourth data trace Data4. At least the third signal trace 0031 includes a scan trace G1. The orthographic projections of the two data traces in the first conductive layer 001 on the base substrate 1 are located within the orthographic projections of the constant voltage traces on the base substrate 1. As can be seen in FIG4B , the main portions Data01 of the second data trace Data2 and the third data trace Data3 are located between the main portions VDD01 of the first constant voltage trace VDD and VSS01 of the second constant voltage trace VSS. The orthographic projections of the main portions of the two data traces in the second conductive layer 002 on the base substrate 1 are located within the orthographic projections of the main portions of the two constant voltage traces on the base substrate 1. It can be seen that the main parts Data03 of the first data line Data1 and the fourth data line Data4 in Figure 4B are located between the main part VDD01 of the first constant voltage line VDD and the main part VSS01 of the second constant voltage line VSS, and the main part Data01 of the first data line Data1 is located between the main part Data01 of the third data line Data3 and the main part VDD01 of the first constant voltage line VDD, and the main part Data03 of the fourth data line Data4 is located between the main part Data01 of the third data line Data3 and the main part VSS01 of the second constant voltage line VSS. In this way, the four data lines are compactly arranged with the four sub-pixels 010, reducing the occupied area of ​​the signal lines, increasing the transparent area a1, and improving the transmittance.

[0099] In an exemplary embodiment, the main portions of the first constant voltage trace VDD, the second data trace Data2, the third data trace Data3, and the second constant voltage trace VSS extend longitudinally, while the main portions of the first constant voltage trace VDD, the second data trace Data2, the third data trace Data3, and the second constant voltage trace VSS extend transversely. The second data trace Data2 corresponds to the third sub-pixel 103. Since the third sub-pixel 103 is located to the left of the detection trace Sense, the second data trace Data2 is positioned immediately to the left of the third sub-pixel 103. The third data trace Data3 corresponds to the second sub-pixel 102. Since the second sub-pixel 102 is located to the right of the detection trace Sense, the third data trace Data3 is positioned immediately to the right of the second sub-pixel 102. Since the four sub-pixels 010 share the first constant voltage trace VDD and the second constant voltage trace VSS, the first constant voltage trace VDD is positioned to the left of the second data trace Data2, and the second constant voltage trace VSS is positioned to the right of the third data trace Data3. This reduces the number of routing lines and the area occupied by the routing lines, while increasing the transparent area a1. At least the second signal routing line 0021 includes a first data routing line Data1 and a fourth data routing line Data4. The first data routing line Data1 and the fourth data routing line Data4 extend in the longitudinal direction. The first data routing line Data1 corresponds to the first sub-pixel 101. Since the second data routing line Data2 is located adjacent to the sub-pixel 010, the first data routing line Data1 and the second data routing line Data2 are located adjacent to each other. The fourth data routing line Data4 corresponds to the fourth sub-pixel 104. Since the third data routing line Data3 is located adjacent to the sub-pixel 010, the fourth data routing line Data4 is located adjacent to the third data routing line Data3. This allows the four data routing lines to be compactly arranged with the four sub-pixels 010, reducing the area occupied by the signal routing lines, increasing the transparent area a1, and improving transmittance. Because the first signal trace 0011 and the second signal trace 0021 are fabricated using a single patterning process on different conductive layers, the first data trace Data1 and the fourth data trace Data4 of the second signal trace 0021 are positioned above the first data trace Data1 and the fourth data trace Data4. This reduces the number of connections between the data traces and the corresponding sub-pixels 010 and increases the spacing between conductive layers on the same layer, improving substrate manufacturing yield. Since the spacing between different conductive layers can be designed to be smaller, more layout space is saved, which can increase the area ratio of the transparent area a1. At least one third signal trace 0031 includes a scan trace G1, which extends along a second direction, where the second direction includes a horizontal direction and the first direction is perpendicular to the second direction.Since the first signal trace 0011 and the first conductive layer 001 are manufactured using a single patterning process, the second signal trace 0021 and the second conductive layer 002 are manufactured using a single patterning process, and the third signal trace 0031 and the third conductive layer 003 are manufactured using a single patterning process, multiple insulating layers are provided between the first signal trace 0011, the second signal trace, and the third signal trace 0031. This can improve the yield rate of metal crossings. When the yield rate is high enough, the repair design can be replaced, thereby improving space utilization and increasing the area of ​​the transparent area a1.

[0100] FIG4C shows a schematic cross-sectional structure diagram of an exemplary display substrate in another embodiment provided by the present disclosure.

[0101] 4D to 4K are schematic diagrams showing exemplary display substrate level graphics according to another embodiment of the present disclosure.

[0102] As shown in Figures 4C and 4D, the first constant voltage trace VDD, the second data trace Data2, the detection trace Sense, the third data trace Data3 and the second constant voltage trace VSS are alternately arranged in sequence, and are manufactured using a single patterning process with the first conductive layer 001 (the signal trace is insulated from the first conductive layer 001). A buffer layer 3 is formed above the plurality of signal lines, and an active layer 4 is formed above the buffer layer 3. A single patterning process is used to form a pattern as shown in FIG4E (pattern 41 in FIG4E). A gate insulating layer 5 is formed on the active layer 4. A second conductive layer 002 is formed on the gate insulating layer 5. A first data line Data1, a second data line Data2, and a first constant voltage line and a second constant voltage line of the second layer (the signal lines are insulated from the second conductive layer 002) are formed on the second conductive layer 002. A single patterning process is used to form a pattern as shown in FIG4F (pattern 61 in FIG4F is the pattern of the second conductive layer 002), wherein the first constant voltage line and the second constant voltage line of the second layer are overlapped with the first constant voltage signal and the second constant voltage line of the first layer. In an exemplary embodiment, the constant voltage line of the first layer is a constant voltage line formed simultaneously with the first conductive layer 001, and the constant voltage line of the second layer is a constant voltage line formed simultaneously with the second conductive layer 002. In this embodiment, two layers of constant voltage wiring are used to reduce wiring resistance and thus reduce voltage drop on the wiring. An interlayer dielectric layer 7 is made on the constant voltage wiring of the second layer, and CNT openings are performed to form a pattern as shown in Figure 4G (such as the pattern labeled 71 in Figure 4G). A third conductive layer 003 and a scanning line are stacked on the interlayer dielectric layer 7 (the signal wiring is insulated from the third conductive layer 003), and a one-time composition process is used to form a pattern as shown in Figure 4H (811 / 812 / 813 / 814 in Figure 4H are all patterns of the third conductive layer 003), a passivation layer 9 and a flat layer 10 are stacked on the third conductive layer, and a one-time composition process is used to form a pattern as shown in Figure 4I (91 in Figure 4I is the pattern of the passivation layer 9, and 10 to 1 is the pattern of the flat layer 10), a pixel electrode is made on the flat layer 10, and a one-time composition process is used to form a pattern as shown in Figure 4J (such as the pattern in Figure 4J). 111 pixel electrode pattern), a pixel defining layer 12 is made on the pixel electrode, and an etching process is adopted to form a pattern as shown in Figure 4K (the blank area 121 in Figure 4K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are stacked in sequence on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16.In this embodiment, the first constant voltage line VDD, the second constant voltage line VSS, the second data line Data2, the third data line Data3 and the detection line Sense are manufactured with the first conductive layer 001 using a single patterning process, the first data line Data1 and the fourth data line Data4 are manufactured with the second conductive layer 002 using a single patterning process, and the scanning line G1 and the third conductive layer 003 are manufactured with a single patterning process. In addition, every two sub-pixels 010 in the four sub-pixels 010 are grouped together, and the four sub-pixels 010 share one detection line Sense, the first constant voltage line VDD and the second constant voltage line VSS. The detection line Sense is arranged between the four sub-pixels 010, and the data lines are arranged adjacent to the corresponding sub-pixels 010. The first constant voltage line VDD and the second constant voltage line VSS are respectively arranged on both sides of the data lines. This saves the number of signal lines and reduces the space occupied by multiple signal lines, thereby increasing the transparent area a1 and improving the transmittance. In an exemplary embodiment, multiple insulating layers are provided between the first signal line 0011, the second signal line, and the third signal line 0031, which can improve the yield of metal crossing. When the yield is high enough, the repair design can be replaced, thereby improving space utilization and increasing the area of ​​the transparent area a1.

[0103] Yet another embodiment

[0104] FIG5A shows a schematic diagram of a pixel layout of an exemplary display substrate in another embodiment provided by the present disclosure.

[0105] FIG5B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in another embodiment provided by the present disclosure.

[0106] As shown in Figures 5A and 5B, along the extension direction of the main body of the signal line, the four sub-pixels 010 share one detection line Sense, and among the four sub-pixels 010, two sub-pixels 010 form a group and are respectively arranged on both sides of the detection line Sense; and / or, the first constant voltage line VDD and the second constant voltage line VSS both extend along the first direction, and the four sub-pixels 010 share one first constant voltage line VDD and one second constant voltage line VSS, the first constant voltage line VDD is located on one side of the four sub-pixels 010, and the second constant voltage line VSS is located on the other side of the four sub-pixels 010.

[0107] Exemplarily, the first direction includes the longitudinal direction. Four sub-pixels 010 include a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. The first sub-pixel 101 and the third sub-pixel 103 form a first group, while the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction. The first group of sub-pixels 010 is disposed to the left of the detection trace Sense, while the second group of sub-pixels 010 is disposed to the right of the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS. The first constant voltage trace VDD and the second constant voltage trace VSS are disposed on either side of the four sub-pixels 010, respectively. Exemplarily, the first constant voltage trace VDD is disposed to the left of the four sub-pixels 010, while the second constant voltage trace VSS is disposed to the right of the four sub-pixels 010. In this way, the signal line is arranged close to the sub-pixel 010, which reduces the number of signal line routings, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving the transmittance.

[0108] As shown in Figures 5A and 5B, the orthographic projection of the at least one first signal trace 0011 on the substrate substrate 1 and the orthographic projection of the at least one second signal trace 0021 on the substrate substrate 1 are arranged alternately; and / or, the orthographic projection of the at least one first signal trace 0011 on the substrate substrate 1 and the orthographic projection of the at least one third signal trace 0031 on the substrate substrate 1 are arranged alternately.

[0109] Exemplarily, the at least one first signal trace 0011 includes the data trace and / or the detection trace Sense; the at least one third signal trace 0031 includes at least one of the scan trace G1, the first constant voltage trace VDD, and the second constant voltage trace VSS. The at least one first signal trace 0011 includes the first data trace Data1, the second data trace Data2, the third data trace Data3, and the fourth data trace Data4; the orthographic projections of the main portions Data01 of the first data trace Data1 and the second data trace Data2 on the base substrate 1 are located within the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the base substrate 1; the orthographic projections of the main portions of the third data trace Data3 and the fourth data trace Data4 on the base substrate 1 are located within the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS on the base substrate 1.

[0110] In an exemplary embodiment, as shown in FIG5B , at least one signal routing line further includes a first data routing line Data1, a second data routing line Data2, a third data routing line Data3, a fourth data routing line Data4, and a detection routing line Sense, and at least the third signal routing line 0031 includes a scan routing line G1, a first constant voltage routing line VDD, and a second constant voltage routing line VSS. The orthographic projections of the first data routing line Data1 and the second data routing line Data2 on the substrate substrate 1 partially overlap with the orthographic projection of the first constant voltage routing line VDD on the substrate substrate 1. As shown in FIG5B , the orthographic projections of the main parts of the first data routing line Data1 and the second data routing line Data2 on the substrate substrate 1 overlap with the orthographic projections of the main parts of the first data routing line Data1 and the second data routing line Data2 on the substrate substrate 1. The orthographic projection of the main portion VDD01 of a constant voltage trace VDD (or as can be seen in FIG5H ) ​​on the base substrate 1 completely overlaps, while the orthographic projection of the branch portion Data02 of the first data trace Data1 and the second data trace Data2 on the base substrate partially overlaps with the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the base substrate 1, and the orthographic projection of the branch portion VDD02 of the first constant voltage trace VDD on the base substrate 1 partially overlaps with the orthographic projection of the main portion Data01 of the first data trace Data1 and the second data trace Data2 on the base substrate (that is, the branch portion VDD02 of the first constant voltage trace VDD is a signal trace coupled to the sub-pixel driving circuit). The orthographic projections of the third data trace Data3 and the fourth data trace Data4 on the substrate 1 partially overlap with the orthographic projection of the second constant voltage trace VSS on the substrate 1. As shown in Figure 5B, the orthographic projections of the main portions Data01 of the third data trace Data3 and the fourth data trace Data4 on the substrate substrate completely overlap with the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS (or as shown in Figure 5H) on the substrate substrate 1, and the orthographic projections of the branch portions Data02 of the third data trace Data3 and the fourth data trace Data4 on the substrate substrate partially overlap with the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS on the substrate substrate 1, and the orthographic projections of the branch portions VSS02 of the second constant voltage trace VSS on the substrate substrate 1 partially overlap with the orthographic projections of the main portions Data01 of the third data trace Data3 and the fourth data trace Data4 on the substrate substrate (that is, the branch portions VSS02 of the second constant voltage trace VSS are signal traces coupled to the sub-pixel driving circuit). That is to say, the main portion Data01 of the first data trace Data1 and the second data trace Data2 and the main portion VDD01 of the first constant voltage trace VDD are overlapped, and the main portion Data01 of the third data trace Data3 and the fourth data trace Data4 and the main portion VSS01 of the second constant voltage trace VSS are overlapped. The specific structure can be seen in Figure 5B.Since the first data line Data1, the second data line Data2, the third data line Data3, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 using a single patterning process, the first constant voltage line VDD and the second constant voltage line VSS are manufactured with the third conductive layer 003 using a single patterning process, and the first signal line and the third signal line are manufactured with different conductive layers, the first constant voltage line VDD and the second constant voltage line VSS can be overlapped with the data lines, which can reduce the space occupied by the signal lines, increase the area of ​​the transparent area a1, and improve the transparency effect.

[0111] In an exemplary embodiment, the first constant voltage trace VDD, the first data trace Data1, the second data trace Data2, the third data trace Data3, the fourth data trace Data4, the detection trace Sense and the second constant voltage trace VSS extend in the longitudinal direction, the first data trace Data1 and the second data trace Data2 are arranged in parallel and are located on the left side of the detection trace Sense, the third data trace Data3 and the fourth data trace Data4 are arranged in parallel and are located on the right side of the detection trace Sense, in this way, the data trace corresponding to each sub-pixel 010 can be arranged adjacent to it, making the layout of the data traces compact, and making the four data traces compactly arranged with the four sub-pixels 010, reducing the occupied area of ​​the signal traces, increasing the transparent area a1, and improving the transmittance. Because the first data trace Data1, the second data trace Data2, the third data trace Data3, the fourth data trace Data4, and the detection trace Sense are fabricated in a single patterning process with the first conductive layer 001, and the first constant voltage trace VDD and the second constant voltage trace VSS are fabricated in a single patterning process with the third conductive layer 003, overlapping the data traces in the first conductive layer 001 and the data traces in the third conductive layer 003 can reduce the area occupied by the data traces, increase the area of ​​the transparent area a1, and improve transmittance. At least one third signal trace 0031 includes a scan trace G1, which extends along a second direction, where the second direction includes a transverse direction and the first direction is perpendicular to the second direction. Since the first signal trace 0011 and the first conductive layer 001 are manufactured using a single patterning process, the second signal trace 0021 and the second conductive layer 002 are manufactured using a single patterning process, and the third signal trace 0031 and the third conductive layer 003 are manufactured using a single patterning process, multiple insulating layers are provided between the first signal trace 0011, the second signal trace, and the third signal trace 0031. This can improve the yield rate of metal crossings. When the yield rate is high enough, the repair design can be replaced, thereby improving space utilization and increasing the area of ​​the transparent area a1.

[0112] FIG5C shows a schematic cross-sectional structure diagram of an exemplary display substrate in another embodiment provided by the present disclosure.

[0113] 5D to 5K are schematic diagrams showing exemplary display substrate level graphics according to yet another embodiment of the present disclosure.

[0114] As shown in Figures 5C and 5D , the first data trace Data1, the second data trace Data2, the detection trace Sense, the third data trace Data3, and the fourth data trace Data4 are patterned together with the first conductive layer 001 using a single patterning process (the signal traces are insulated from the third conductive layer 003), forming the pattern shown in Figure 5D . A buffer layer 3 is formed above the multiple signal traces, and an active layer 4 is formed above the buffer layer 3 using a single patterning process to form the pattern shown in Figure 5E (such as the pattern 41 in Figure 5E ). A gate insulating layer 5 is formed on the active layer 4, and a second conductive layer 002 is formed on the gate insulating layer 5 using a single patterning process to form the pattern shown in Figure 5F (such as the pattern 61 in Figure 5F is the pattern of the second conductive layer 002). An interlayer dielectric layer 7 is formed on the second conductive layer 002, and CNT openings are performed to form the pattern shown in Figure 5G (such as the pattern labeled 71 in Figure 5G ). A third conductive layer 003, a first constant voltage line VDD, a second constant voltage line VSS, and a scan line G1 are fabricated on the interlayer dielectric layer 7 (the signal line is insulated from the third conductive layer 003), the first constant voltage line VDD overlaps with the first data line Data1 and the second data line Data2, and the second constant voltage line VSS overlaps with the third data line Data3 and the fourth data line Data4. A single patterning process is used to form a pattern as shown in FIG5H (811 / 812 / 813 / 814 in FIG5H are all patterns of the third conductive layer 003). A passivation layer 9 and a planarization layer 10 are stacked on the signal lines, and a single patterning process is used to form a pattern as shown in FIG5I (91 in FIG5I is the pattern of the passivation layer 9, and 10-1 is the pattern of the planarization layer 10). A pixel electrode is fabricated on the planarization layer 10, and a single patterning process is used to form a pattern as shown in FIG5J (the pixel electrode pattern 111 in FIG5J). A pixel defining layer 12 is fabricated on the pixel electrode. An etching process is used to form a pattern as shown in Figure 5K (the blank area 121 in Figure 5K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are stacked in sequence on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16.In this embodiment, the first data line Data1, the second data line Data2, the third data line Data3, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 through a single patterning process, the first constant voltage line VDD and the second constant voltage line VSS and the scan line G1 are manufactured with the third conductive layer 003 through a single patterning process, and every two sub-pixels 010 in the four sub-pixels 010 are grouped together, the four sub-pixels 010 share one detection line Sense, the first constant voltage line VDD and the second constant voltage line VSS, the detection line Sense is arranged between the four sub-pixels 010, and the data lines are arranged adjacent to the corresponding sub-pixels 010, the first constant voltage line VDD is arranged to overlap with the first data signal line and the second data signal line, and the second constant voltage line VSS is arranged to overlap with the third signal line 0031 and the fourth signal line, thereby saving the space occupied by the signal lines, thereby increasing the transparent area a1 and improving the transmittance. In an exemplary embodiment, multiple insulating layers are provided between signal traces to improve the yield of metal crossing the traces. When the yield is high enough, the repair design can be replaced, thereby improving space utilization and increasing the area of ​​the transparent region a1.

[0115] Yet another embodiment

[0116] FIG6A shows a schematic diagram of a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0117] FIG6B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0118] As shown in Figures 6A and 6B, along the extension direction of the main body of the signal line, the four sub-pixels 010 share one detection line Sense, and among the four sub-pixels 010, two sub-pixels 010 form a group and are respectively arranged on both sides of the detection line Sense; and / or, the first constant voltage line VDD and the second constant voltage line VSS both extend along the first direction, and the four sub-pixels 010 share one first constant voltage line VDD and one second constant voltage line VSS, the first constant voltage line VDD is located on one side of the four sub-pixels 010, and the second constant voltage line VSS is located on the other side of the four sub-pixels 010.

[0119] Exemplarily, the first direction includes the longitudinal direction. Four sub-pixels 010 include a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. The first sub-pixel 101 and the third sub-pixel 103 form a first group, while the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction. The first group of sub-pixels 010 is disposed to the left of the detection trace Sense, while the second group of sub-pixels 010 is disposed to the right of the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS. The first constant voltage trace VDD and the second constant voltage trace VSS are disposed on either side of the four sub-pixels 010, respectively. Exemplarily, the first constant voltage trace VDD is disposed to the left of the four sub-pixels 010, while the second constant voltage trace VSS is disposed to the right of the four sub-pixels 010. In this way, the signal line is arranged close to the sub-pixel 010, which reduces the number of signal line routings, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving the transmittance.

[0120] As shown in Figures 6A and 6B, the orthographic projection of the at least one first signal trace 0011 on the substrate 1 and the orthographic projection of the at least one second signal trace 0021 on the substrate 1 are arranged alternately; and / or, the orthographic projection of the at least one first signal trace 0011 on the substrate 1 and the orthographic projection of the at least one third signal trace 0031 on the substrate 1 are arranged alternately.

[0121] Exemplarily, the at least one first signal trace 0011 includes the data trace and the detection trace Sense; the at least one second signal trace 0021 includes the first constant voltage trace VDD and the second constant voltage trace VSS; and the at least one third signal trace 0031 includes the scan trace G1. The at least one first signal trace 0011 includes the first data trace Data1, the second data trace Data2, the third data trace Data3, and the fourth data trace Data4; the orthographic projections of the main portions Data01 of the first data trace Data1 and the second data trace Data2 on the base substrate 1 are located within the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the base substrate 1; and the orthographic projections of the main portions of the third data trace Data3 and the fourth data trace Data4 on the base substrate 1 are located within the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS on the base substrate 1.

[0122] In an exemplary embodiment, as shown in FIG6B , at least one first signal trace 0011 further includes a first data trace Data1, a second data trace Data2, a third data trace Data3, a fourth data trace Data4, and a detection trace Sense; at least one second signal trace 0021 includes a first constant voltage trace VDD and a second constant voltage trace VSS; and at least one third signal trace 0031 includes a scan trace G1. The orthographic projections of the main portions Data01 of the first data trace Data1 and the second data trace Data2 on the substrate 1 partially overlap with the orthographic projections of the main portions VDD01 of the first constant voltage trace VDD on the substrate 1; and the orthographic projections of the main portions of the third data trace Data3 and the fourth data trace Data4 on the substrate 1 partially overlap with the orthographic projections of the main portions VSS01 of the second constant voltage trace VSS on the substrate 1. That is, the main portions of the first data traces Data1 and Data2 overlap with the main portion VSS01 of the first constant voltage trace VDD, and the main portions of the third data traces Data3 and Data4 overlap with the main portion VSS01 of the second constant voltage trace VSS. The branches of the data traces can overlap with the orthographic projections of the branches of the constant voltage traces on the substrate 1, or can be alternately arranged. Since the data lines are laid out on different layers, the branch portions of the signal traces have different lengths and positions, which can be set according to specific needs and will not be described in detail in this disclosure. The specific structure can be seen in Figure 6B. Since the first data line Data1, the second data line Data2, the third data line Data3, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 using a single patterning process, the first constant voltage line VDD and the second constant voltage line VSS are manufactured with the second conductive layer 002 using a single patterning process, and the first signal line and the third signal line are manufactured with different conductive layers, the first constant voltage line VDD and the second constant voltage line VSS can be overlapped with the data lines, which can reduce the space occupied by the signal lines, increase the area of ​​the transparent area a1, and improve the transparency effect.

[0123] In an exemplary embodiment, the first constant voltage trace VDD, the first data trace Data1, the second data trace Data2, the third data trace Data3, the fourth data trace Data4, the detection trace Sense and the second constant voltage trace VSS extend in the longitudinal direction, the first data trace Data1 and the second data trace Data2 are arranged in parallel and are located on the left side of the detection trace Sense, the third data trace Data3 and the fourth data trace Data4 are arranged in parallel and are located on the right side of the detection trace Sense, in this way, the data trace corresponding to each sub-pixel 010 can be arranged adjacent to it, making the layout of the data traces compact, and making the four data traces compactly arranged with the four sub-pixels 010, reducing the occupied area of ​​the signal traces, increasing the transparent area a1, and improving the transmittance. Because the first data traces Data1, Data2, Data3, Data4, and the detection trace Sense are fabricated in a single patterning process with the first conductive layer 001, and the first constant voltage trace VDD and the second constant voltage trace VSS are fabricated in a single patterning process with the second conductive layer 002, overlapping the data traces in the first conductive layer 001 and the data traces in the second conductive layer 002 can reduce the area occupied by the data traces, increase the area of ​​the transparent area a1, and improve transmittance. At least one third signal trace 0031 includes a scan trace G1, which extends along a second direction, where the second direction includes a transverse direction and the first direction is perpendicular to the second direction. Because the first signal trace 0011 and the first conductive layer 001 are fabricated using a single patterning process, the second signal trace 0021 and the second conductive layer 002 are fabricated using a single patterning process, and the third signal trace 0031 and the third conductive layer 003 are fabricated using a single patterning process, multiple insulation layers are placed between the first signal trace 0011, the second signal trace, and the third signal trace 0031. This improves the yield rate when metal traces cross over. When the yield rate is high enough, it can replace the repair design, thereby improving space utilization and increasing the area of ​​transparent area a1. The first constant voltage trace VDD and the second constant voltage trace VSS are fabricated using a single patterning process with the second conductive layer 002. Compared to using a single patterning process for the first constant voltage trace VDD, the second constant voltage trace VSS, and the scan signal trace with the third conductive layer 003, this reduces the space occupied by the first constant voltage trace VDD and the second constant voltage trace VSS crossing the scan signal trace layer, further increasing the area of ​​transparent area a1.

[0124] FIG6C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0125] 6D to 6K are schematic diagrams showing exemplary display substrate level graphics according to yet another embodiment of the present disclosure.

[0126] As shown in FIG. 6C and FIG. 6D , the first data trace Data1 , the second data trace Data2 , the detection trace Sense , the third data trace Data3 and the fourth data trace Data4 are alternately arranged in sequence and are manufactured using a single patterning process with the first conductive layer 001 . A buffer layer 3 is formed above the multiple signal lines, and an active layer 4 is formed above the buffer layer 3. A one-time patterning process is used to form a pattern as shown in Figure 6E (the pattern 41 in Figure 6E). A gate insulating layer 5 is formed on the active layer 4. A second conductive layer 002 is formed on the gate insulating layer 5. A one-time patterning process is used to form a pattern as shown in Figure 6F (the pattern 61 in Figure 6F is the pattern of the second conductive layer 002). A first constant voltage line VDD and a second constant voltage line VSS are formed and alternately arranged on the second conductive layer 002 (the signal line is insulated from the second conductive layer 002). The first constant voltage line VDD overlaps with the first data line Data1 and the second data line Data2, and the second constant voltage line VSS overlaps with the third data line Data3 and the fourth data line Data4. A one-time patterning process is used to form the pattern as shown in Figure 6F. An interlayer dielectric layer 7 is formed on the signal line, and CNT openings are performed to form a pattern as shown in Figure 6G (the pattern labeled 71 in Figure 6G). A third conductive layer 003 and a scanning line G1 are fabricated on the interlayer dielectric layer 7 (the scanning line G1 is insulated from the third conductive layer 003), and a single patterning process is used to form a pattern as shown in FIG6H (811 / 812 / 813 / 814 in FIG6H are all patterns of the third conductive layer 003). A passivation layer 9 and a flat layer 10 are stacked on the signal line, and a single patterning process is used to form a pattern as shown in FIG6I (91 in FIG6I is the pattern of the passivation layer 9, and 10-1 is the pattern of the flat layer 10). A pixel electrode is fabricated on the flat layer 10, and a single patterning process is used to form a pattern as shown in FIG6J (91 in FIG6I is the pattern of the passivation layer 9, and 10-1 is the pattern of the flat layer 10). 111 pixel electrode pattern), a pixel defining layer 12 is made on the pixel electrode, and an etching process is adopted to form a pattern as shown in Figure 6K (the blank area 121 in Figure 6K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are stacked in sequence on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and a glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16.In this embodiment, the first data trace Data1, the second data trace Data2, the third data trace Data3, the fourth data trace Data4, and the detection trace Sense are fabricated with the first conductive layer 001 using a single patterning process, the first constant voltage trace VDD and the second constant voltage trace VSS are fabricated with the second conductive layer 002 using a single patterning process, and the scan trace G1 is fabricated with the third conductive layer 003 using a single patterning process. Furthermore, every two sub-pixels 010 are grouped together, and the four sub-pixels 010 share a detection trace Sense, a first constant voltage trace VDD, and a second constant voltage trace VSS. The detection trace Sense is positioned between the four sub-pixels 010, and the data traces are positioned adjacent to the corresponding sub-pixels 010. The first constant voltage trace VDD overlaps with the first and second data signal traces, and the second constant voltage trace VSS overlaps with the third signal trace 0031 and the fourth signal trace. This reduces the space occupied by the signal traces, thereby increasing the transparent area a1 and improving transmittance. In one exemplary embodiment, multiple insulating layers are placed between signal traces to improve the yield of metal crossovers. When the yield is high enough, it can replace the repair design, thereby improving space utilization and increasing the area of ​​the transparent area a1. This embodiment is suitable for display panels with lower resolution or low refresh rate.

[0127] Yet another embodiment

[0128] FIG7A shows a schematic diagram of a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0129] FIG7B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0130] As shown in Figures 7A and 7B, the detection trace Sense, the first constant voltage trace VDD and the second constant voltage trace VSS all extend along the first direction, and the four sub-pixels 010 share one detection trace Sense, one first constant voltage trace VDD and one second constant voltage trace VSS. Among the four sub-pixels 010, two sub-pixels 010 form a group and are respectively arranged on both sides of the detection trace Sense. The at least one first signal trace 0011 includes the detection trace Sense; among the four sub-pixels 010, two sub-pixels 010 form a group and are respectively arranged on both sides of the first constant voltage trace VDD. The at least one third signal trace 0031 includes the first constant voltage trace VDD, and the orthographic projection of the main portion Sense01 of the detection trace Sense on the substrate 1 is located within the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the substrate 1.

[0131] Exemplarily, the first direction includes the longitudinal direction. The four sub-pixels 010 include a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. The first sub-pixel 101 and the third sub-pixel 103 form a first group, while the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction. The first group of sub-pixels 010 is located to the left of the detection trace Sense, while the second group of sub-pixels 010 is located to the right of the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS, wherein the first group of sub-pixels 010 are arranged in the left area of ​​the first constant voltage trace VDD, and the second group of sub-pixels 010 are arranged in the right area of ​​the first constant voltage trace VDD, and the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the substrate 1 is located within the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS on the substrate 1. In an exemplary embodiment, the main portion VDD01 of the first constant voltage trace VDD and the main portion Sense01 of the detection trace Sense are arranged in an overlapping manner. The branch portion of the data trace can be arranged in an overlapping manner with the orthographic projection portion of the branch portion of the constant voltage trace on the substrate 1, or can be arranged alternately. Since the data lines are arranged on different layers, the branch portions of the signal traces have different lengths and positions, which can be set according to specific needs and will not be described in detail in this disclosure. Since the four sub-pixels 010 share a first constant voltage line VDD, placing the first constant voltage line VDD between the four sub-pixels 010 can reduce the number of signal lines and the space occupied by the signal lines, thereby increasing the transparent area a1.

[0132] In one exemplary embodiment, as shown in Figures 7A and 7B, the orthographic projection of the at least one first signal trace 0011 on the substrate 1 is arranged alternately with the orthographic projection of the at least one second signal trace 0021 on the substrate 1; and / or the orthographic projection of the at least one first signal trace 0011 on the substrate 1 is arranged alternately with the orthographic projection of the at least one third signal trace 0031 on the substrate 1. The second constant voltage trace VSS is disposed on the right or left side of the four sub-pixels 010. This allows the signal lines to be placed in close proximity to the sub-pixels 010, reducing the number of signal line traces and, in turn, the area occupied by the signal lines, increasing the area of ​​the transparent region a1, and improving transmittance.

[0133] For example, as shown in Figures 7A and 7B, the at least one first signal trace 0011 includes the first data trace Data1, the fourth data trace Data4, and the detection trace Sense; the at least one second signal trace 0021 includes the second data trace Data2, the third data trace Data3, and the second constant voltage trace VSS; and the at least one third signal trace 0031 includes the first constant voltage trace VDD and the scan trace G1. In other words, the first data trace Data1, the fourth data trace Data4, and the detection trace Sense are fabricated with the first conductive layer 001 using a single patterning process; the second signal trace 0021 and the third signal trace 0031 are fabricated with the second conductive layer 002 using a single patterning process; and the first constant voltage trace VDD and the scan trace G1 are fabricated with the third conductive layer 003 using a single patterning process. Among them, the first constant voltage trace VDD, the first data trace Data1, the second data trace Data2, the third data trace Data3, the fourth data trace Data4, the detection trace Sense, and the second constant voltage trace VSS extend in the longitudinal direction. The first data trace Data1 and the second data trace Data2 are arranged in parallel and located to the left of the detection trace Sense, and the third data trace Data3 and the fourth data trace Data4 are arranged in parallel and located to the right of the detection trace Sense. In this way, the data trace corresponding to each sub-pixel 010 can be arranged adjacent to it, making the data trace layout compact. The four data traces are arranged closely with the four sub-pixels 010, reducing the area occupied by the signal traces, increasing the transparent area a1, and improving the transmittance. The second constant voltage trace VSS is arranged to the right or left of the four sub-pixels 010. In other words, it can be arranged to the left of the first data trace Data1 and the second data trace Data2, or to the right of the third data trace Data3 and the fourth data trace Data4. This allows the signal line to be placed in close proximity to the sub-pixel 010, reducing the number of signal line traces and, in turn, reducing the area occupied by the signal lines, increasing the area of ​​the transparent area a1, and improving transmittance. Furthermore, to conserve the area occupied by the signal traces, the first constant voltage trace VDD and the third conductive layer 003 are fabricated using a single patterning process, and the first constant voltage trace VDD and the detection trace Sense are arranged overlappingly. Since the four sub-pixels 010 share one first constant voltage trace VDD, placing the first constant voltage trace VDD between the four pixels can reduce the number of signal traces, reduce the space occupied by the signal traces, and increase the transparent area a1. In addition, the first constant voltage line VDD is set between the four sub-pixels 010 and can be directly electrically connected to the sub-pixel 010 driving circuits on both sides. In addition, the signal line connecting the first constant voltage line VDD and the sub-pixel 010 driving circuit has no cross-line and no via, thereby further reducing the space occupied by the signal line and increasing the area of ​​the transparent area a1.

[0134] As shown in Figures 7A and 7B, the at least one third signal line 0031 includes the scan line G1, and the scan line G1 is disconnected at the intersection with the first constant voltage line VDD or the second constant voltage line VSS located in the third conductive layer 003, and the scan line G1 disconnected in the third conductive layer 003 is electrically connected through the first auxiliary line G11 set in the second conductive layer 002.

[0135] In an exemplary embodiment, since the first constant voltage trace VDD and the third conductive layer 003 are manufactured using a one-time patterning process, and the scanning trace G1 is also manufactured using a one-time patterning process with the third conductive layer 003, the first constant voltage trace VDD and the scanning line are disconnected at the intersection, and the first auxiliary trace G11 of the second conductive layer 002 is used to achieve electrical connection. In this way, the first constant voltage trace VDD and the scanning trace G1 have no intersection, thereby avoiding a short circuit between the first constant voltage trace VDD and the scanning trace G1.

[0136] FIG7C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0137] 7D to 7K are schematic diagrams showing exemplary display substrate level graphics according to yet another embodiment of the present disclosure.

[0138] As shown in Figures 7C to 7K, the difference between the length of the branch portion of the at least one first signal trace 0011 and the length of the branch portion of the at least one second signal trace 0021 is less than the maximum value of the width of the main body of the at least one first signal trace 0011 and the at least one second signal trace 0021; and / or,

[0139] The difference between the length of the branch portion of the at least one first signal trace 0011 and the length of the branch portion of the at least one third signal trace 0031 is smaller than the maximum value of the widths of the main portions of the at least one first signal trace 0011 and the at least one third signal trace 0031 .

[0140] Exemplarily, the detection trace Sense includes a main portion extending along a first direction and a branch portion extending along a second direction. The first constant voltage trace VDD includes a main portion VDD01 extending along the first direction and a branch portion VDD02 extending along the second direction. The difference in length of the first constant voltage trace VDD along the second direction is less than the larger of the widths of the main portions of the first constant voltage trace VDD and the detection trace Sense. This can better optimize the patching space, increase the aperture ratio, and reduce trace impedance.

[0141] As shown in FIG. 7C and FIG. 7D , the first data trace Data1 , the detection trace Sense and the fourth data trace Data4 are patterned together with the first conductive layer 001 using a single patterning process to form a pattern as shown in FIG. 7D . A buffer layer 3 is formed above the multiple signal lines, and an active layer 4 is formed above the buffer layer 3, and a one-time composition process is used to form a pattern as shown in Figure 7E (the pattern 41 in Figure 7E), a gate insulating layer 5 is formed on the active layer 4, and a second conductive layer 002 is formed on the gate insulating layer 5, and a one-time composition process is used to form a pattern as shown in Figure 7F (the pattern 61 in Figure 7F is the pattern of the second conductive layer 002), a second data line Data2, a fourth data line Data4, a second constant voltage line VSS and a horizontally arranged first auxiliary line G11 (the signal line is insulated from the second conductive layer 002) are formed on the second conductive layer 002, and a one-time composition process is used to form the pattern as shown in Figure 7F, an interlayer dielectric layer 7 is formed on the signal line, and CNT openings are performed to form a pattern as shown in Figure 7G (the pattern labeled 71 in Figure 7G). A third conductive layer 003, a first constant voltage trace VDD, and a scan trace G1 are fabricated on the interlayer dielectric layer 7 (the signal trace is insulated from the third conductive layer 003), and a single patterning process is used to form a pattern as shown in FIG7H (811 / 812 / 813 / 814 in FIG7H are all patterns of the third conductive layer 003). A passivation layer 9 and a flat layer 10 are stacked on the signal trace, and a single patterning process is used to form a pattern as shown in FIG7I (91 in FIG7I is the pattern of the passivation layer 9, and 10-1 is the pattern of the flat layer 10). 7J (pixel electrode pattern 111 in FIG7J ) is formed on the flat layer 10, a pixel electrode is formed on the flat layer 10, and a one-time patterning process is used to form a pattern as shown in FIG7J (the pixel electrode pattern 111 in FIG7J ) is formed on the pixel electrode, and an etching process is used to form a pattern as shown in FIG7K (the blank area 121 in FIG7K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are sequentially stacked on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and a glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16. In this embodiment, the first data line Data1, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 by a single patterning process, the second data line Data2, the third data line Data3 and the second constant voltage line VSS are manufactured with the second conductive layer 002 by a single patterning process, and the first constant voltage line VDD and the scan line G1 are manufactured with the third conductive layer 003 by a single patterning process.Furthermore, every two sub-pixels 010 are grouped together, and the four sub-pixels 010 share a detection trace Sense, a first constant voltage trace VDD, and a second constant voltage trace VSS. The first constant voltage trace VDD and the detection trace Sense are arranged between the four sub-pixels 010, and the signal traces are arranged adjacent to the corresponding sub-pixels 010. The first constant voltage trace VDD and the detection trace Sense overlap, saving space occupied by the signal traces, thereby increasing the transparent area a1 and improving transmittance. In an exemplary embodiment, multiple insulating layers are provided between the signal traces to improve the yield rate when metal crosses the traces. When the yield rate is high enough, the repair design can be replaced, thereby improving space utilization and increasing the area of ​​the transparent area a1.

[0142] Yet another embodiment

[0143] FIG8A shows a schematic diagram of a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0144] FIG8B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0145] As shown in Figures 8A and 8B, along the extension direction of the main body of the signal line, the four sub-pixels 010 share one detection line Sense, and among the four sub-pixels 010, two sub-pixels 010 are grouped together and respectively arranged on both sides of the detection line Sense; and / or, the first constant voltage line VDD and the second constant voltage line VSS both extend along the first direction, and the four sub-pixels 010 share one first constant voltage line VDD and one second constant voltage line VSS, and the first constant voltage line VDD and the second constant voltage line VSS are located on the same side of the four sub-pixels 010 and are arranged overlappingly.

[0146] Exemplarily, the first direction includes the longitudinal direction. The first sub-pixel 101 and the third sub-pixel 103 form a first group, and the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The data trace, the detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction; the first group of sub-pixels 010 are arranged in the left area of ​​the detection trace Sense, and the second group of sub-pixels 010 are arranged in the right area of ​​the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS. The first constant voltage trace VDD and the second constant voltage trace VSS are both arranged on the same side of the four sub-pixels 010, and can be arranged on the left or the right. Exemplarily, the first constant voltage trace VDD and the second constant voltage trace VSS are both arranged on the right side of the four sub-pixels 010, and the first constant voltage trace VDD and the second constant voltage trace VSS are arranged overlapping. In this way, the signal line is arranged close to the sub-pixel 010, which reduces the number of signal line routings, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving the transmittance.

[0147] As shown in Figures 8A and 8B, the orthographic projection of the at least one first signal trace 0011 on the substrate substrate 1 and the orthographic projection of the at least one second signal trace 0021 on the substrate substrate 1 are arranged alternately; and / or, the orthographic projection of the at least one first signal trace 0011 on the substrate substrate 1 and the orthographic projection of the at least one third signal trace 0031 on the substrate substrate 1 are arranged alternately.

[0148] Exemplarily, the at least one first signal trace 0011 includes the first constant voltage trace VDD, the data trace and the detection trace Sense; the at least one second signal trace 0021 includes the second constant voltage trace VSS; the at least one third signal trace 0031 includes the scan trace G1; the orthographic projection of the main portion VDD01 of the first constant voltage trace VDD on the base substrate 1 is located within the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS on the base substrate 1.

[0149] In this embodiment, at least one first signal line 0011 includes a first constant voltage line VDD, the data line, and the detection line Sense. Multiple first signal lines 0011 are alternately arranged and fabricated using a single patterning process with the first conductive layer 001. At least one second signal line 0021 includes a second constant voltage line VSS, and at least one third signal line 0031 includes a scan line G1. Among them, the first data line Data1, the second data line Data2, the third data line Data3 and the fourth data bus extend in the longitudinal direction, the first sub-pixel 101 and the third sub-pixel 103 are the first group, the first data line Data1 and the second data line Data2 correspond to the first sub-pixel 101 and the third sub-pixel 103, and since the first group of sub-pixels 010 is set on the left side of the detection line Sense, the first data line Data1 and the second data line Data2 are set on the left side of the first group of sub-pixels 010. In this way, the first data line Data1 and the second data line Data2 are set close to the corresponding sub-pixel 010, reducing the number of lines. The second sub-pixel 102 and the fourth sub-pixel 104 are grouped together. The third data traces Data3 and the fourth data traces Data4 correspond to the second sub-pixel 102 and the fourth sub-pixel 104. Since the second sub-pixel 010 is located to the right of the detection trace Sense, the third data traces Data3 and the fourth data traces Data4 are located to the right of the second sub-pixel 010. This places the third data traces Data3 and the fourth data traces Data4 close to the corresponding sub-pixels 010, reducing the number of traces. In one exemplary embodiment, the detection trace Sense is located in the middle of the non-display area b region a. The first sub-pixel 101 and the third sub-pixel 103 are grouped together and located to the left of the detection trace Sense. The second sub-pixel 102 and the fourth sub-pixel 104 are grouped together and located to the right of the detection trace Sense. The first sub-pixel 101 and the second sub-pixel 102 are symmetrically arranged, and the third sub-pixel 103 and the fourth sub-pixel 104 are symmetrically arranged. In this way, the signal line is arranged in close proximity to the sub-pixel 010, reducing the number of signal line traces, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving transmittance. Since the data trace and the first constant voltage trace VDD are manufactured using a single patterning process with the first conductive layer 001, and the second constant voltage trace VSS is manufactured using a single patterning process with the second conductive layer 002, and the first constant voltage trace VDD and the second constant voltage trace VSS are manufactured using a non-continuous layer, to reduce the area occupied by the signal trace, the first constant voltage trace VDD and the second constant voltage trace VSS can be arranged overlappingly. In this way, the signal line is arranged in close proximity to the sub-pixel 010, reducing the number of signal line traces, thereby reducing the area occupied by the signal line, increasing the area of ​​the transparent region a1, and improving transmittance.At least one third signal trace 0031 includes a scan trace G1, which extends along a second direction, where the second direction includes a transverse direction, and the first direction is perpendicular to the second direction. Because the first signal trace 0011 and the first conductive layer 001 are fabricated using a single patterning process, and the third signal trace 0031 and the third conductive layer 003 are fabricated using a single patterning process, multiple insulating layers are placed between the first signal trace 0011 and the third signal trace 0031. This improves the yield rate of metal crossovers. When the yield rate is sufficiently high, it can replace a repair design, thereby improving space utilization, increasing the area of ​​the transparent area a1, and avoiding the problem of increased pixel driver loading.

[0150] As shown in Figures 8A and 8B, the driving modules of the four sub-pixel 010 driving circuits corresponding to the first sub-pixel 101, the second sub-pixel 102, the third sub-pixel 103 and the fourth sub-pixel 104 are connected to the first constant voltage trace VDD through the second auxiliary trace VDD10 located in the third conductive layer 003.

[0151] In this embodiment, the driving modules of the four sub-pixel 010 driving circuits corresponding to the first sub-pixel 101, the second sub-pixel 102, the third sub-pixel 103, and the fourth sub-pixel 104 are all disposed above the third conductive layer 003 and can be directly electrically connected to the third conductive layer 003. Because the first constant voltage trace VDD and the second conductive layer 002 are fabricated using a single patterning process, by electrically connecting the first constant voltage trace VDD and the second auxiliary trace VDD10 laid on the third layer to the driving modules of the four pixel circuits, winding wires can be avoided, the number of traces can be reduced, and the area occupied by the transparent region a1 can be reduced, thereby improving transparency.

[0152] FIG8C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0153] 8D to 8K are schematic diagrams showing exemplary display substrate level graphics according to yet another embodiment of the present disclosure.

[0154] As shown in Figures 8C and 8D, the first data line Data1, the second data line Data2, the detection line Sense, the third data line Data3, the fourth data line Data4 and the second constant voltage line VSS are manufactured with the first conductive layer 001 using a single patterning process (the signal line is insulated from the first conductive layer 001) to form the pattern shown in Figure 8D. A buffer layer 3 is formed above the multiple signal lines, and an active layer 4 is formed above the buffer layer 3. A one-time patterning process is used to form a pattern as shown in Figure 8E (such as the pattern 41 in Figure 8E). A gate insulating layer 5 is formed on the active layer 4, a second conductive layer 002 is formed on the gate insulating layer 5, and a first constant voltage line VDD is formed on the second conductive layer 002 (the signal line is insulated from the second conductive layer 002), so that the first constant voltage line VDD overlaps with the second constant voltage line VSS. A one-time patterning process is used to form a pattern as shown in Figure 8F (such as the pattern 61 in Figure 8F is the pattern of the second conductive layer 002). An interlayer dielectric layer 7 is formed on the constant voltage line, and CNT openings are performed to form a pattern as shown in Figure 8G (such as the pattern labeled 71 in Figure 8G). A third conductive layer 003, a scanning line and a second auxiliary line VDD10 are stacked on the interlayer dielectric layer 7 (the signal line is insulated from the third conductive layer 003), and a single patterning process is used to form a pattern as shown in FIG8H (811 / 812 / 813 / 814 in FIG8H are all patterns of the third conductive layer 003). A passivation layer 9 and a flat layer 10 are stacked on the third conductive layer, and a single patterning process is used to form a pattern as shown in FIG8I (91 in FIG8I is the pattern of the passivation layer 9, and 10-1 is the pattern of the flat layer 10). A pixel electrode is made on the flat layer 10, and a single patterning process is used to form a pattern as shown in FIG8J ( 8J ), a pixel defining layer 12 is made on the pixel electrode, and an etching process is adopted to form a pattern as shown in FIG8K (the blank area 121 in FIG8K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are sequentially stacked on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16.In this embodiment, the first constant voltage line VDD, the second constant voltage line VSS, the first data line Data1, the second data line Data2, the third data line Data3, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 by a single patterning process, and every two sub-pixels 010 in the four sub-pixels 010 are divided into a group, the four sub-pixels 010 share one detection line Sense, the first constant voltage line VDD and the second constant voltage line VSS, the detection line Sense is arranged between the four sub-pixels 010, and the data lines are arranged adjacent to the corresponding sub-pixels 010, and the first constant voltage line VDD and the second constant voltage line VSS are respectively arranged on both sides of the data lines, thereby saving the number of signal lines and reducing the space occupied by multiple signal lines, thereby increasing the transparent area a1 and improving the transmittance.

[0155] Yet another embodiment

[0156] FIG9A is a schematic diagram showing a pixel layout of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0157] FIG9B shows a schematic diagram of a pixel layout structure of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0158] As shown in Figures 9A and 9B, the detection trace Sense, the first constant voltage trace VDD and the second constant voltage trace VSS all extend along the first direction, and the four sub-pixels 010 share one detection trace Sense, one first constant voltage trace VDD and one second constant voltage trace VSS. Among the four sub-pixels 010, two sub-pixels 010 form a group and are respectively arranged on both sides of the detection trace Sense, and the at least one first signal trace 0011 includes the detection trace Sense.

[0159] Exemplarily, the first direction includes the longitudinal direction. The four sub-pixels 010 include a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. The first sub-pixel 101 and the third sub-pixel 103 form a first group, while the second sub-pixel 102 and the fourth sub-pixel 104 form a second group. The detection trace Sense, the first constant voltage trace VDD, and the second constant voltage trace VSS all extend in the longitudinal direction. The first group of sub-pixels 010 is located to the left of the detection trace Sense, while the second group of sub-pixels 010 is located to the right of the detection trace Sense. The four sub-pixels 010 share a first constant voltage trace VDD and a second constant voltage trace VSS, wherein the first group of sub-pixels 010 are arranged in the left area of ​​the second constant voltage trace VSS, and the second group of sub-pixels 010 are arranged in the right area of ​​the second constant voltage trace VSS, and the orthographic projection of the main portion VSS01 of the second constant voltage trace VSS on the substrate 1 is located within the orthographic projection of the main portion VSS01 of the first constant voltage trace VDD on the substrate 1. In an exemplary embodiment, the main portion VSS01 of the second constant voltage trace VSS and the main portion Sense01 of the detection trace Sense are arranged in an overlapping manner. The branch portion of the data trace can be arranged in an overlapping manner with the orthographic projection of the branch portion of the constant voltage trace on the substrate 1, or can be arranged alternately. Since the data lines are arranged on different layers, the branch portions of the signal traces have different lengths and positions, which can be set according to specific needs and will not be described in detail in this disclosure. Since the four sub-pixels 010 share one second constant voltage trace VSS, routing the second constant voltage trace VSS between the four sub-pixels 010 can reduce the number of signal traces and the space occupied by the signal traces, thereby increasing the transparent area a1.

[0160] In an exemplary embodiment, as shown in Figures 9A and 9B, the orthographic projection of the at least one first signal trace 0011 on the substrate 1 is arranged alternately with the orthographic projection of the at least one second signal trace 0021 on the substrate 1; and / or the orthographic projection of the at least one first signal trace 0011 on the substrate 1 is arranged alternately with the orthographic projection of the at least one third signal trace 0031 on the substrate 1. The first constant voltage trace VDD is disposed on the right or left side of the four sub-pixels 010. This allows the signal lines to be placed in close proximity to the sub-pixels 010, reducing the number of signal line traces and, in turn, reducing the area occupied by the signal lines, increasing the area of ​​the transparent region a1, and improving transmittance.

[0161] For example, as shown in Figures 9A and 9B, the at least one first signal trace 0011 includes the first data trace Data1, the fourth data trace Data4, and the detection trace Sense; the at least one second signal trace 0021 includes the second data trace Data2, the third data trace Data3, and the first constant voltage trace VDD; and the at least one third signal trace 0031 includes the second constant voltage trace VSS and the scan trace G1. In other words, the first data trace Data1, the fourth data trace Data4, and the detection trace Sense are fabricated with the first conductive layer 001 using a single patterning process; the second signal trace 0021 and the third signal trace 0031 are fabricated with the second conductive layer 002 using a single patterning process; and the second constant voltage trace VSS and the scan trace G1 are fabricated with the third conductive layer 003 using a single patterning process. Among them, the first constant voltage trace VDD, the first data trace Data1, the second data trace Data2, the third data trace Data3, the fourth data trace Data4, the detection trace Sense, and the second constant voltage trace VSS extend in the longitudinal direction. The first data trace Data1 and the second data trace Data2 are arranged in parallel and located to the left of the detection trace Sense, and the third data trace Data3 and the fourth data trace Data4 are arranged in parallel and located to the right of the detection trace Sense. In this way, the data trace corresponding to each sub-pixel 010 can be arranged adjacent to it, making the data trace layout compact. The four data traces are arranged closely with the four sub-pixels 010, reducing the area occupied by the signal traces, increasing the transparent area a1, and improving the transmittance. The first constant voltage trace VDD is arranged to the right or left of the four sub-pixels 010. In other words, it can be arranged to the left of the first data trace Data1 and the second data trace Data2, or to the right of the third data trace Data3 and the fourth data trace Data4. This allows the signal line to be placed in close proximity to the sub-pixel 010, reducing the number of signal line traces and, in turn, reducing the area occupied by the signal lines, increasing the area of ​​the transparent area a1, and improving transmittance. Furthermore, to save the area occupied by the signal traces, the second constant voltage trace VSS and the third conductive layer 003 are fabricated using a single patterning process, and the second constant voltage trace VSS and the detection trace Sense are arranged overlapping. Since the four sub-pixels 010 share one second constant voltage trace VSS, arranging the second constant voltage trace VSS between the four pixels can reduce the number of signal traces, reduce the space occupied by the signal traces, and increase the transparent area a1. In addition, the second constant voltage line VSS is arranged between the four sub-pixels 010 and can be directly electrically connected to the sub-pixel 010 driving circuits on both sides. In addition, the signal line connecting the second constant voltage line VSS and the sub-pixel 010 driving circuit has no cross-line and no via, thereby further reducing the space occupied by the signal line and increasing the area of ​​the transparent area a1.

[0162] As shown in Figures 9A and 9B, the at least one third signal line 0031 includes the scan line G1, and the scan line G1 is disconnected at the intersection with the second constant voltage line VSS or the first constant voltage line VDD located in the third conductive layer 003, and the scan line G1 disconnected in the third conductive layer 003 is electrically connected through the first auxiliary line G11 set in the second conductive layer 002.

[0163] In an exemplary embodiment, since the second constant voltage line VSS and the third conductive layer 003 are manufactured using a one-time patterning process, and the scanning line G1 is also manufactured using a one-time patterning process with the third conductive layer 003, the second constant voltage line VSS and the scanning line are disconnected at the intersection, and the first auxiliary line G11 of the second conductive layer 002 is used to achieve electrical connection. In this way, the second constant voltage line VSS and the scanning line G1 have no intersection, thereby avoiding a short circuit between the second constant voltage line VSS and the scanning line G1.

[0164] FIG9C shows a schematic cross-sectional structure diagram of an exemplary display substrate in yet another embodiment provided by the present disclosure.

[0165] 9D to 9K are schematic diagrams showing exemplary display substrate level graphics according to yet another embodiment of the present disclosure.

[0166] As shown in FIG. 9C and FIG. 9D , the first data trace Data1 , the detection trace Sense and the fourth data trace Data4 are patterned together with the first conductive layer 001 using a single patterning process to form a pattern as shown in FIG. 9D . A buffer layer 3 is formed above the multiple signal lines, and an active layer 4 is formed above the buffer layer 3, and a one-time composition process is used to form a pattern as shown in Figure 9E (the pattern 41 in Figure 9E), a gate insulating layer 5 is formed on the active layer 4, and a second conductive layer 002 is formed on the gate insulating layer 5, and a one-time composition process is used to form a pattern as shown in Figure 9F (the pattern 61 in Figure 9F is the pattern of the second conductive layer 002), a second data line Data2, a fourth data line Data4 and a first constant voltage line VDD and a horizontally arranged first auxiliary line G11 (the signal line is insulated from the second conductive layer 002) are formed on the second conductive layer 002, and a one-time composition process is used to form the pattern as shown in Figure 9F, an interlayer dielectric layer 7 is formed on the signal line, and CNT openings are performed to form a pattern as shown in Figure 9G (the pattern labeled 71 in Figure 9G). A third conductive layer 003, a second constant voltage line VSS and a scanning line G1 are fabricated on the interlayer dielectric layer 7 (the signal line is insulated from the third conductive layer 003), and a one-time patterning process is used to form a pattern as shown in FIG9H (811 / 812 / 813 / 814 in FIG9H are all patterns of the third conductive layer 003). A passivation layer 9 and a flat layer 10 are stacked on the signal line, and a one-time patterning process is used to form a pattern as shown in FIG9I (91 in FIG9I is the pattern of the passivation layer 9, and 10-1 is the pattern of the flat layer 10). A pixel electrode is fabricated on the flat layer 10, and a one-time patterning process is used to form a pattern as shown in FIG9J (FIG. 9J), a pixel defining layer 12 is made on the pixel electrode, and an etching process is adopted to form a pattern as shown in FIG9K (the blank area 121 in FIG9K is the etching area), and a semiconductor layer 13, a pixel electrode cathode 14, an encapsulation layer 15, and a blocking dam 17 are sequentially stacked on the pixel defining layer 12. A filler 16, a filter 18, a black matrix 19, a blocking dam 17, and a glass 20 are also provided on the side of the encapsulation layer 15 away from the base substrate 1. The black matrix 19 and the filter 18 are arranged in the same layer, and the blocking dam 17 is arranged on the side of the filler 16 and the filter 18 to block the filler 16. In this embodiment, the first data line Data1, the fourth data line Data4 and the detection line Sense are manufactured with the first conductive layer 001 using a single patterning process, the second data line Data2, the third data line Data3 and the first constant voltage line VDD are manufactured with the second conductive layer 002 using a single patterning process, and the second constant voltage line VSS and the scan line G1 are manufactured with the third conductive layer 003 using a single patterning process.Furthermore, every two sub-pixels 010 are grouped together, and the four sub-pixels 010 share a detection trace Sense, a first constant voltage trace VDD, and a second constant voltage trace VSS. The second constant voltage trace VSS and the detection trace Sense are arranged between the four sub-pixels 010, and the signal traces are arranged adjacent to the corresponding sub-pixels 010. The second constant voltage trace VSS and the detection trace Sense overlap, saving space occupied by the signal traces, thereby increasing the transparent area a1 and improving transmittance. In an exemplary embodiment, multiple insulating layers are provided between the signal traces to improve the yield rate when metal crosses the traces. When the yield rate is high enough, the repair design can be replaced, thereby improving space utilization and increasing the area of ​​the transparent area a1.

[0167] In summary, the present application provides a display substrate and a display device, wherein the display substrate includes a first conductive layer, a second conductive layer, and a third conductive layer stacked on a base substrate; a sub-pixel driving circuit includes a plurality of transistors, and the display substrate further includes a light-shielding layer for at least partially shielding the plurality of transistors from light. The light-shielding layer is provided on the same layer as the first conductive layer. By providing the light-shielding layer and the first conductive layer on the same layer, the thickness of the base substrate can be reduced, and signal traces can be arranged within the light-shielding layer, thereby reducing the area of ​​the transparent region occupied by the signal traces and improving the transmittance. The plurality of signal traces are arranged in different layers. For example, the first conductive layer includes at least one first signal trace among the plurality of signal traces, the second conductive layer includes at least one second signal trace among the plurality of signal traces, and the third conductive layer includes at least one third signal trace among the plurality of signal traces. The orthographic projection of the at least one first signal trace on the base substrate at least partially overlaps with the orthographic projections of the at least one second signal trace and / or the at least one third signal trace on the base substrate. By laying out multiple signal lines in the three stacked conductive layers, overlapping arrangement of multiple signal lines can be achieved, reducing the occupied area of ​​the signal lines, increasing the transparent area, and thus improving the transmittance of the display substrate.

[0168] The foregoing describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0169] For ordinary technicians in the field, the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples; under the thinking of the present disclosure, the above embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0170] Although the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description.For example, other memory architectures may use the discussed embodiments.

[0171] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: a display area and a non-display area surrounding the display area, the display area including a transparent area and a non-transparent area; the display substrate further including a base substrate and a plurality of pixel units and a plurality of signal traces arranged in an array on the base substrate; the pixel unit including a plurality of sub-pixels and a plurality of sub-pixel driving circuits electrically coupled to the plurality of sub-pixels in a one-to-one correspondence, at least part of the plurality of signal traces being electrically coupled to the plurality of sub-pixel driving circuits and providing driving signals to the plurality of sub-pixel driving circuits; The display substrate further includes a first conductive layer, a second conductive layer, and a third conductive layer stacked on the base substrate; the sub-pixel driving circuit includes a plurality of transistors, and the display substrate further includes a light shielding layer for shielding at least part of the plurality of transistors from light, the light shielding layer being provided on the same layer as the first conductive layer; The first conductive layer includes at least one first signal line among the multiple signal lines, the second conductive layer includes at least one second signal line among the multiple signal lines, and the third conductive layer includes at least one third signal line among the multiple signal lines; the first signal line, the second signal line, and the third signal line each include a main body and a branch portion, the main body extends along a first direction, and the branch portion extends along a second direction, and the first direction is perpendicular to the second direction; the orthographic projection of the main body of the at least one first signal line on the substrate completely overlaps with the orthographic projection of the main body of the at least one second signal line and / or the at least one third signal line on the substrate.

2. The display substrate according to claim 1, wherein The difference between the length of the branch portion of the at least one first signal line and the length of the branch portion of the at least one second signal line is smaller than the maximum width of the main body of the at least one first signal line and the at least one second signal line; and / or, A difference between the length of the branch portion of the at least one first signal line and the length of the branch portion of the at least one third signal line is smaller than a maximum value of widths of the main portions of the at least one first signal line and the at least one third signal line.

3. The display substrate according to claim 1, wherein The orthographic projection of the at least one first signal line on the substrate and the orthographic projection of the at least one second signal line on the substrate are arranged alternately; and / or, The orthographic projection of the at least one first signal line on the base substrate and the orthographic projection of the at least one third signal line on the base substrate are arranged alternately.

4. The display substrate according to claim 1, wherein: The at least one first signal trace comprises a constant voltage trace for providing a constant voltage signal; The at least one second signal trace comprises two second signal traces arranged in parallel, the orthographic projections of the two second signal traces on the base substrate being located within the orthographic projection of the constant voltage trace on the base substrate; and / or, The at least one third signal line includes two third signal lines arranged in parallel, and the orthographic projections of the two third signal lines on the base substrate are located within the orthographic projection of the constant voltage line on the base substrate.

5. The display substrate according to claim 1, wherein The pixel unit includes four sub-pixels arranged in a 2×2 pattern, and the four sub-pixels include white light sub-pixels. The display substrate according to claim 5 , wherein: The sub-pixel driving circuit includes at least one processor, and the at least one processor is configured to execute a data writing module, a driving module, an energy storage module and a detection module; The data writing module is electrically connected to the scan line, the data line and the control end of the driving module, and is configured to write the data voltage provided by the data line into the control terminal of the driving module under the control of the scan signal provided by the scan line. a control terminal of the drive module; The energy storage module is electrically connected to the control terminal of the driving module and is configured to store electrical energy; The driving module is electrically connected to the first constant voltage trace and one end of the light-emitting element of the sub-pixel, and is configured to drive the light-emitting element under the control of the potential of the control end of the driving module; the other end of the light-emitting element is electrically connected to the second constant voltage trace; The detection module is electrically connected to the scanning line, the detection line, and the connection node between the driving module and the light-emitting element, and is configured to control the connection between the connection node and the detection line under the control of the scanning signal.

7. The display substrate according to claim 6, wherein: Along the extension direction of the main body of the signal line, the four sub-pixels share one detection line, and two sub-pixels form a group of four sub-pixels, which are respectively arranged on both sides of the detection line; and / or, The four sub-pixels share one first constant voltage line and one second constant voltage line. The first constant voltage line is located on one side of the four sub-pixels, and the second constant voltage line is located on the other side of the four sub-pixels.

8. The display substrate according to claim 6 or 7, wherein: The at least one first signal line includes at least one of the first constant voltage line, the second constant voltage line, the data line, and the detection line; and the at least one third signal line includes the scan line.

9. The display substrate according to claim 7, wherein: The four sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel; the sub-pixel driving circuit corresponding to the first sub-pixel includes a first data routing line, the sub-pixel driving circuit corresponding to the second sub-pixel includes a second data routing line, the sub-pixel driving circuit corresponding to the third sub-pixel includes a third data routing line, and the sub-pixel driving circuit corresponding to the fourth sub-pixel includes a fourth data routing line; Along the extension direction of the main body of the signal line, the first data line and the second data line are located on one side of the four sub-pixels, and the third data line and the fourth data line are located on the other side of the four sub-pixels.

10. The display substrate according to claim 9, wherein: The at least one first signal line includes the data line and / or the detection line; the at least one third signal line includes at least one of the scan line, the first constant voltage line, and the second constant voltage line.

11. The display substrate according to claim 9, wherein: The at least one first signal line includes the data line and the detection line; the at least one second signal line includes the first constant voltage line and the second constant voltage line; and the at least one third signal line includes the scan line.

12. The display substrate according to claim 9, wherein: The at least one first signal line includes the data line and / or the detection line; the at least one third signal line includes the scan line, the first constant voltage line, and the second constant voltage line.

13. The display substrate according to any one of claims 10 to 12, wherein: The at least one first signal line includes the first data line, the second data line, the third data line and the fourth data line; The orthographic projections of the first data line and the second data line on the base substrate are located within the orthographic projection of the first constant voltage line on the base substrate; the orthographic projections of the third data line and the fourth data line on the base substrate are located within the orthographic projection of the second constant voltage line on the base substrate.

14. The display substrate according to claim 9, wherein: The at least one first signal line includes the second data line, the third data line, the first constant voltage line, and the second constant voltage line; the at least one second signal line includes the first data line and the fourth data line; the at least one third signal line includes the scan line, and the scan line extends along the second direction; The orthographic projection of the main portion of the first data wiring on the base substrate is located between the orthographic projections of the main portions of the second data wiring and the first constant voltage wiring on the base substrate; The orthographic projection of the main portion of the fourth data wiring on the base substrate is located between the orthographic projections of the main portions of the third data wiring and the second constant voltage wiring on the base substrate.

15. The display substrate according to claim 4, wherein Along the extension direction of the main portion of the signal trace, the four sub-pixels share one detection trace, one first constant voltage trace, and one second constant voltage trace; two sub-pixels form a group of four sub-pixels, respectively disposed on either side of the detection trace; and the at least one first signal trace includes the detection trace; Among the four sub-pixels, two sub-pixels form a group and are respectively arranged on both sides of the first constant voltage trace, the at least one third signal trace includes the first constant voltage trace, and the orthographic projection of the main portion of the detection trace on the base substrate is located within the orthographic projection of the main portion of the first constant voltage trace on the base substrate; or, Among the four sub-pixels, two sub-pixels form a group and are respectively arranged on both sides of the second constant voltage routing. The at least one third signal routing includes the second constant voltage routing. The orthographic projection of the main body of the detection routing on the base substrate is located within the orthographic projection of the main body of the second constant voltage routing on the base substrate.

16. The display substrate according to claim 15, wherein: The at least one third signal line includes the scan line, and the scan line is disconnected at the intersection with the first constant voltage line or the second constant voltage line located in the third conductive layer, and the scan line disconnected in the third conductive layer is electrically connected through the first auxiliary line arranged in the second conductive layer.

17. The display substrate according to claim 9, wherein: The at least one first signal routing includes the second constant voltage routing, the data routing and the detection routing; the at least one second signal routing includes the first constant voltage routing; the at least one third signal routing includes the scan routing; the orthographic projection of the main portion of the first constant voltage routing on the base substrate is located within the orthographic projection of the main portion of the second constant voltage routing on the base substrate.

18. The display substrate according to claim 17, wherein: The driving modules of the four sub-pixel driving circuits corresponding to the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are connected to the first constant voltage wiring via a second auxiliary wiring located on the third conductive layer.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

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