Image sensor with high dynamic range

Abstract

An image sensor includes a photoelectric conversion element that accumulates charge generated by incident radiation. An overflow transfer gate passes charge from the photoelectric conversion element to a charge accumulation structure in a first case when the accumulated charge in the photoelectric conversion element reaches a first threshold charge and in a second case in response to an active transfer gate signal. A digital circuit triggers a selective reset of the charge accumulation structure each time a charge accumulated in the charge accumulation structure reaches a second threshold charge during an exposure period.

Description

[0001] IMAGE SENSOR WITH HIGH DYNAMIC RANGE

[0002] The present disclosure relates to an image sensor with pixel circuits having a high dynamic range. In particular, the present disclosure relates to an image sensor with pixel circuits having a transfer gate between a photoelectric conversion element and a charge accumulation structure.

[0003] BACKGROUND

[0004] In solid-state imaging devices photoelectric conversion elements generate a photocurrent proportional to the radiation intensity received during an exposure period. The photocurrent gradually accumulates charge. After the exposure period, the accumulated charge is transferred to a floating diffusion, wherein a resulting potential of the floating diffusion is a function of the transferred accumulated charge. The floating diffusion is connected to the gate of a source follower which outputs an analog pixel signal in a readout period. A voltage level of the analog pixel signal is a function of the floating diffusion potential. The greater the capacitance of the floating diffusion, the wider the dynamic range of the pixel circuit but the lower the signal -to-noise ratio in low light conditions. Some high dynamic range (HDR) pixel circuits process in parallel the photocurrents of two photoelectric conversion elements having different sensitivities. Other HDR image sensors use two or more consecutive exposures with different exposure periods to generate a photocurrent that matches the capacitance of the floating diffusion.

[0005] SUMMARY

[0006] In HDR pixel circuits with two photoelectric conversion elements and in HDR image sensors using multiple exposures, the capacitance of the floating diffusion sets an upper limit above which different illumination intensities are indistinguishable.

[0007] The present disclosure mitigates such deficiencies of the prior art by allowing charge overflow from the saturated photoelectric conversion element into the floating diffusion and resetting the saturated floating diffusion. The number of resets of the floating diffusion during an exposure period can be counted.

[0008] Accordingly, an image sensor according to the present disclosure includes a photoelectric conversion element that accumulates charge generated by incident radiation. An overflow transfer gate passes charge from the photoelectric conversion element to a charge accumulation structure in a first case when the accumulated charge in the photoelectric conversion element reaches a first threshold charge, and in a second case in response to an active transfer gate signal. A control circuit triggers a selective reset of the charge accumulation structure each time a charge in the charge accumulation structure reaches a second threshold charge in an exposure period.

[0009] The overflow transfer gate facilitates charge overflow from the photoelectric conversion element to the charge accumulation structure. When the charge accumulation structure saturates, the control circuit triggers a selective self-reset of the charge accumulation structure. The charge on the photoelectric conversion element remains unaffected by the self-resetting of the charge accumulation structure. A pixel readout can obtain information about the received radiation intensity from the number of resets, the potential of the charge accumulation structure and the charge accumulated on the photoelectric conversion device at the end of an exposure period. The dynamic range of the image sensor is not limited by pixel internal capacitances but by the capacity of a digital counter.

[0010] BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0012] FIG. 1 is a simplified block diagram of a solid-state imaging device with theoretically infinite dynamic range in accordance with an embodiment of the present technology.

[0013] FIG. 2 is a simplified circuit diagram of a pixel circuit having a photoelectric conversion element, an overflow transfer gate, a charge accumulation structure and a digital circuit for resetting the charge accumulation structure and counting the resets in accordance with an embodiment of the present technology.

[0014] FIG. 3 is a simplified circuit diagram of a pixel circuit having a charge accumulation structure, a reset transistor and a digital circuit for controlling the reset transistor to reset the charge accumulation structure in accordance with an embodiment of the present technology.

[0015] FIG. 4 is a simplified circuit diagram of a pixel circuit having a digital circuit with a comparator circuit for obtaining a reset signal for resetting the charge accumulation structure in accordance with an embodiment of the present technology.

[0016] FIG. 5 is a simplified timing diagram for illustrating the operation principle of the pixel circuits in FIG. 2 to FIG. 4.

[0017] FIG. 6 is a circuit diagram of a digital circuit of a pixel circuit for obtaining a reset signal for resetting a charge accumulation structure in accordance with an embodiment of the present technology.

[0018] FIG. 7 is a simplified timing diagram for control signals and internal signals of the digital circuit of FIG. 6 during a reset period and a subsequent exposure period.

[0019] FIG. 8A shows a timing diagram illustrating the self-reset operation of a pixel circuit with the digital circuit illustrated in FIG. 6 in the low illumination case. FIG. 8B shows a timing diagram illustrating the self-reset operation of a pixel circuit with the digital circuit illustrated in FIG. 6 in the high illumination case.

[0020] FIG. 9 is a schematic perspective view of an image sensor with laminated structure including a top die with analog circuits and a bottom die with digital circuits in accordance with an embodiment.

[0021] FIG. 10 is a schematic flow chart for a readout of the pixel circuit of FIG. 4.

[0022] FIG. 11 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0023] FIG. 12 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 11.

[0024] DETAILED DESCRIPTION

[0025] Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

[0026] Connected electronic elements may be directly electrically connected through a direct, permanent low- resistive connection, e.g., through a conductive line or an ohmic contact. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to a gate of a FET controls by field effect the current flow in the load path between source and drain.

[0027] Active binary signals have an active voltage level. Inactive binary signals have an inactive voltage level. When the active voltage level of a binary signal is the logic high level, the inactive voltage level of the binary signal is the logic low level. When the active voltage level of a binary signal is the logic low level, the inactive voltage level of the binary signal is the logic high level.

[0028] Though in the following a technology for theoretically almost infinite dynamic range pixel circuits is discussed mainly in combination with four-transistor pixel circuits and a pixel readout scheme that uses the same analog-to-digital converter for all pixel circuits of a pixel column, other embodiments may provide pixel circuits with three, five or more FETs, and / or pixel readout schemes that use one analog-to-digital converter or pulse width modulator per pixel circuit. FIG. 1 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 includes an image sensor 70 and a signal processing unit 80. The image sensor 70 includes a pixel array 10, a column signal processing unit 20, a vertical scanning unit 30, a readout buffer memory 40 and a sensor controller 50.

[0029] The pixel array 10 includes a plurality of identical pixel circuits 100 with high dynamic range. Each pixel circuit 100 includes an analog circuit 110 and a digital circuit 160. The analog circuit 110 converts incident radiation into analog voltage signals and outputs analog voltage signals on an analog signal line 19. The digital circuit 160 receives an analog voltage signal from the analog circuit 110, resets the analog circuit 110 each time a reset condition is met and outputs digital pixel data indicating the number of resets per exposure period on a digital signal line 18. The digital pixel data may include a count signal that becomes active every time a reset is triggered in the exposure period.

[0030] The analog circuit 110 includes a photoelectric conversion element for converting radiation into a photocurrent and pixel transistors for controlling reset, exposure and readout. The photoelectric conversion elements of the pixel array 10 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column of photoelectric conversion elements form a pixel column. A subset of pixel circuits 100 assigned to the same row of photoelectric conversion elements form a pixel row. Each pixel circuit 100 can be identified by a unique pixel address. If the pixel circuits are grouped into a 2D matrix with pixel rows and pixel columns, each pixel circuit 100 can be identified by a unique combination of row address and column address.

[0031] The vertical scanning unit 30 generates pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control a forced pixel reset of the analog circuit 110 at the beginning or the end of an exposure period, a counter reset of the digital circuit 160, and a readout of illumination information from the analog circuit 110 to the analog signal lines 19 and from the digital circuit 160 to the digital signal lines 18.

[0032] The vertical scanning unit 30 controls all pixel circuits 100 of a selected group of pixel circuits 100 synchronously to output the analog pixel signals for a preset phase (reset signal, P phase) and a data phase (data signal, D phase) sequentially on the same analog signal line 19. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row, all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. In the following part of the description, “pixel row” is often referred to as an example of “group of pixel circuits” for simplicity. The vertical scanning unit 30 outputs the control signals for operation of the pixel transistors according to driver timing signals provided by the sensor controller 50.

[0033] The pixel circuits 100 of a pixel output group output the analog pixel signals to an analog signal line (vertical signal line) 19 and the digital pixel data to a digital signal line 18. Each pixel output group may include some pixel circuits 100 of one pixel column, all pixel circuits 100 of one pixel column, or some or all pixel circuits 100 of more than one pixel column. In the following part of the description, “pixel column” is often referred to as an example of “pixel output group” for simplicity.

[0034] The column signal processing unit 20 includes a column signal processing circuit 200 for each analog signal line 19, a voltage ramp generator 25 and a counter circuit 26. The column signal processing circuit 200 converts the analog pixel signals into digital pixel values, may preprocess the digital pixel values and outputs the digital pixel values or the preprocessed digital pixel values to the readout buffer memory 40. Each column signal processing circuit 200 includes amain constant current source 128, a comparator circuit 220, and a digital counting circuit 230.

[0035] The main constant current source 128 complements an amplifier transistor of the selected pixel circuit 100 to a source follower that outputs the analog pixel signals of a selected pixel circuit 100 to a first input of the comparator circuit 220 in a row readout period. The main constant current source 128 sinks a constant current.

[0036] The voltage ramp generator 25 outputs a voltage ramp signal in response to an active ramp enable signal. The voltage ramp signal falls from a high voltage level to a low voltage level continuously or in small steps. The voltage ramp signal is applied to the second inputs of the comparator circuits 220 in the row readout penods. The comparator circuit 220 outputs an active comparator output signal when the voltage level of the voltage ramp signal falls below the voltage level of the analog pixel signal applied to the first input of the comparator circuit 220.

[0037] The counter circuit 26 outputs a digital count value of a digital counter on a digital bus to data inputs of the digital counting circuits 230 in response to an active count enable signal. The active count enable signal and the active ramp enable signal have a predetermined temporal relationship to each other and to the start of the row readout period. The digital counting circuit 230 latches the current count value applied to the data inputs with a transition from an inactive comparator output signal to the active comparator output signal. The latched count value represents the digital pixel value of the analog pixel signal obtained from the pixel circuit 100 in the row readout period. The readout buffer memory 40 may store a digital value obtained from the digital pixel value and the digital pixel data.

[0038] The readout buffer memory 40 receives and temporarily stores the digital pixel values from the column signal processing unit 20 and the digital pixel data through the digital signal lines 18.

[0039] The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the vertical scanning unit 30. The sensor controller 50 generates column control signals for controlling the column signal processing unit 20 and may generate a readout control signal that controls the readout of the digital values from the readout buffer memory 40 to the signal processing unit 80 and / or to a digital interface. FIG. 2 shows an image sensor 70 that includes a photoelectric conversion element PD configured to accumulate charge generated by incident radiation. An overflow transfer gate 111 is configured to pass charge from the photoelectric conversion element PD to a charge accumulation structure FD in a first case when the accumulated charge in the photoelectric conversion element PD reaches a first threshold charge and in a second case in response to an active transfer gate signal TRG. A digital circuit 160 is configured to trigger a selective reset of the charge accumulation structure FD each time a charge accumulated in the charge accumulation structure FD reaches a second threshold charge in an exposure period.

[0040] A pixel circuit 100 includes the digital circuit 160 and an analog circuit 110 with the photoelectric conversion element PD and the charge accumulation structure FD. During the exposure periods, the accumulated charge in the photoelectric conversion element PD typically does not exceed the first threshold charge because the overflow charge flows into the charge accumulation structure FD, and the charge of the charge accumulation structure FD typically does not exceed or only slightly exceeds the second threshold charge due to a timely reset.

[0041] The photoelectric conversion element PD photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion element PD is a function of the intensity of the incident electromagnetic radiation. The photoelectric conversion element PD may include or consist of a photodiode with the photodiode anode electrically connected to a reference potential VSS, wherein the photoelectric conversion element converts electromagnetic radiation incident on a detection surface into a photocurrent by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and / or ultraviolet radiation. The amplitude of the photocurrent corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the photocurrent increases at least approximately linearly with increasing intensity of the detected electromagnetic radiation. The photocurrent changes the voltage at the photodiode cathode. For a pinned photodiode, the photodiode cathode can be depleted to a positive reset voltage before an exposure period and the photocurrent gradually decreases the voltage at the photodiode cathode during the exposure period. The charge on the photoelectric conversion element remains unaffected by the self-resetting of the charge accumulation structure FD.

[0042] The charge accumulation structure FD is suitable for accumulating charge and may include a capacitor electrode, a floating diffusion region or a combination of both. When a reset element 113 resets the charge accumulation structure FD, a potential of the charge accumulation structure FD with respect to the reference potential VSS is initialized with a reset potential. The reset potential may be equal or approximately equal to an analog supply voltage VDDH.

[0043] The overflow transfer gate 111 may be a FET-hke device that passes charge from the photoelectric conversion element PD to the charge accumulation structure FD when at least one of two conditions is met:

[0044] The first condition is an active transfer signal TRG applied to a gate of the overflow transfer gate 111. The active transfer signal TRG turns on the overflow transfer gate 111 and the charge accumulated by the photoelectric conversion element PD is completely or almost completely transferred to the charge accumulation structure FD.

[0045] The second condition is that the charge accumulated by the photoelectric conversion element PD reaches the first threshold charge. In such a case, the photoelectric conversion element PD is in saturation and the overflow transfer gate 111 transfers the excess charge to the charge accumulation structure FD regardless of whether the transfer signal TRG is active or inactive.

[0046] The electric potential heights of the overflow transfer gate 111 may be such that charge flows through the overflow transfer gate 111 when the photoelectric conversion element PD is saturated.

[0047] As in a lateral overflow integration capacitor (LOFIC) pixel, electrons generated in the photoelectric conversion element PD overflow into the charge accumulation structure FD node beyond the potential barrier of the overflow transfer gate 111 when the photoelectric conversion element PD is saturated.

[0048] In case the photoelectric conversion element PD is a photodiode with the photodiode anode electrically connected to the reference potential VSS, the photodiode cathode accumulates charge when receiving radiation. When the reset potential is the analog supply voltage VDDH, charge transferred from the photodiode cathode to the charge accumulation structure FD decreases the potential of the charge accumulation structure FD. The photocurrent of the photoelectric conversion element PD changes the potential in the positively pre-charged charge accumulation structure FD so that in an exposure period a floating diffusion potential VFD across the charge accumulation structure FD is a function of the photocurrent integrated over time, and, in the result, a function of the brightness (illumination intensity) sampled by the pixel circuit 100 in the exposure period.

[0049] An amplifier circuit 120 may be configured to output an analog pixel signal, wherein a voltage level of the analog pixel signal is a function of the charge accumulated in the charge accumulation structure FD.

[0050] The amplifier circuit 120 receives information about the potential of the charge accumulation structure FD and generates an analog pixel signal with an amplitude that is a function of the potential of the charge accumulation structure FD. The amplifier circuit 120 outputs an analog pixel signal to the digital circuit 160 at least in the exposure periods. The amplifier circuit 120 outputs an analog pixel signal to a readout circuit at least in readout periods. The readout circuit may be the column signal processing unit 20 of FIG. 1.

[0051] As illustrated in FIG. 3, the amplifier circuit 120 may include an amplifier transistor 121 and an auxiliary constant current source 125 connected to each other in a source follower configuration.

[0052] The charge accumulation structure FD is connected to the gate of the amplifier transistor 121. A potential at the gate of the amplifier transistor 121 is equal to the floating diffusion potential VFD. A load path between source and drain of the amplifier transistor 121 is electrically connected between the analog supply voltage VDDH and an amplifier node 129. The amplifier node 129 may be directly connected to the auxiliary constant current source 125. Alternatively, the amplifier node 129 is connectable to the auxiliary constant current source 125 at least for the exposure periods. For example, an auxiliary switch connects the amplifier node 129 to the auxiliary constant current source 125 in the exposure periods and disconnects the amplifier node 125 from the auxiliary constant current source 125 outside the exposure periods.

[0053] The auxiliary constant current source 125 may include a resistive structure and / or a FET with constant gate bias. The digital circuit 160 receives the analog pixel signal tapped from the amplifier node 129 at least in the exposure periods.

[0054] The charge accumulation structure FD may be configured to be reset in response to the analog pixel signal reaching a predefined reset threshold voltage.

[0055] The digital circuit 160 uses the analog pixel signal received from the amplifier circuit 120 to trigger a reset of the charge accumulation structure FD. The analog pixel signal reaches the predefined reset threshold voltage when the accumulated charge on the charge accumulation structure FD reaches the second threshold charge.

[0056] The pixel circuit 100 may include a first select switch 109 configured to connect the amplifier transistor 121 to an analog signal line 19 in response to an active analog select signal ASEL.

[0057] The first select switch 109 connects the amplifier transistor 121 to the analog signal line 19 in the readout periods and disconnects the amplifier transistor 121 from the analog signal line 19 outside the readout periods. A second select switch 169 may connect the digital circuit 160 to a digital signal line 18 in response to an active digital select signal DSEL.

[0058] The image sensor 70 may include a main constant current source 128 configured to be in a source follower configuration with the amplifier transistor 121 in a readout period.

[0059] The amplifier node 129 is connectable to the main constant current source 128 at least for the readout periods. The main constant current source 128 may include a resistive structure and / or a FET with constant gate bias, by way of example. The analog signal line 1 receives the analog pixel signal tapped from the amplifier node 129 at least in the readout periods.

[0060] The pixel circuit 100 may include a reset transistor 105 configured to reset a potential of the charge accumulation structure FD in response to an active reset signal received from the digital circuit (160).

[0061] The reset transistor 105 is an embodiment of the reset element 113 of FIG. 2. The reset transistor 105 is an n channel FET with a load path electrically connected between the analog supply voltage VDDH and the charge accumulation structure FD. A gate of the reset transistor 105 receives a reset signal RST that may be partially derived from the analog pixel signal output by the amplifier circuit 120.

[0062] The digital circuit 160 may be configured to output an active reset signal RST when a charge accumulated in the charge accumulation structure FD reaches the second threshold charge. For example, the digital circuit 160 outputs an active reset signal RST when the potential of the charge accumulation structure FD reaches the predefined reset threshold voltage.

[0063] In addition to the self-reset controlled by the charge accumulated in the charge accumulation structure FD, the digital circuit 160 may output an active reset signal on the same signal line in response to a forced reset signal VS RST received from the vertical scanning unit 30 of FIG. 1.

[0064] As illustrated in FIG. 4, a digital circuit 160 of the image sensor 70 may include a comparator circuit 170 configured to receive an analog pixel signal having a voltage level that is a function of the charge accumulated in the charge accumulation structure FD and output an active comparator output signal when the analog pixel signal reaches a reset threshold voltage corresponding to the second threshold charge.

[0065] The comparator circuit 170 may include an amplifier element 173 and an autozero element 174 configured to short-circuit input and output of the amplifier element 173 in response to an active autozeroing signal AZ.

[0066] The comparator circuit 170 is part of the digital circuit 160 and includes an amplifier element 173. The analog pixel signal CM IN is passed through a first capacitive element 171 to an input of the amplifier element 173. A threshold voltage signal CMTHR changing between a low voltage level and the reset threshold voltage is passed through a second capacitive element 172 to the input of the amplifier element 173. The comparator circuit 170 outputs an active comparator output signal CM OUT when the analog pixel signal CM IN exceeds the threshold voltage signal CMTHR.

[0067] The autozero element 174 may be a p channel FET with the gate receiving the autozeroing signal AZ. The autozeroing signal AZ is active during an autozeroing period preceding the exposure period. By feeding back the amplifier output voltage to the amplifier input, the amplifier element 173 nulls its own inherent offset voltage directly before the exposure period.

[0068] The digital circuit 160 of the image sensor 70 may further include a reset latch circuit 161 configured to output the active reset signal RST in response to receiving an active comparator output signal CM OUT.

[0069] The reset latch circuit 161 can combine the comparator output signal CM OUT with the forced reset signal VS RST from the vertical scanner unit 30 of FIG. 1 to allow the same reset transistor to be used fora forced reset for initialization before exposure and a self-reset during exposure. The reset latch circuit 161 is reset after outputting an active reset signal RST of sufficient pulse width. The reset latch circuit 161 can be selfresetting, can be reset when the comparator output signal changes from the active voltage level to the inactive voltage level, and / or through a further control signal, for example in response to an external pulse control signal. A level shifter 165 adapts the voltage level of the reset signal RST output by the reset latch circuit 161 to a voltage level matching the analog supply voltage VDDH used in the pixel circuits 100 if the digital circuit 160 uses a logic supply voltage VDDL that is different from the analog supply voltage VDDH. A count latch circuit 166 outputs an active count signal CNT every time the comparator output signal CM OUT inverts. An external counter computes a digital count value from the active count signals CNT received during the same exposure period.

[0070] The image sensor 70 may further include a count circuit 180configured to increase a reset count each time a charge accumulated in the charge accumulation structure FD reaches the second threshold charge during an exposure period.

[0071] The count circuit 180 receives the count signal CNT output by the count latch circuit 166. The count circuit 180 includes a binary counter, wherein an internal counter value of the binary counter is increased each time the analog pixel signal reaches the predefined reset threshold voltage and the comparator output signal changes to the active level. The count circuit 180 may have a capacity of at least two or four and may output digital count data representing the reset count in a serial or parallel binary format, or as a digital multilevel signal. The count circuit 180 may be integrated in the digital circuit 160 or may be provided outside the digital circuit 160. For example, the count circuit 180 may be integrated in the column signal processing unit 20 or the readout buffer memory 40 of FIG. 1.

[0072] A read signal READ controls a second select switch 169. The read signal READ is an example of the digital select signal DSEL of FIG. 3. When the read signal READ is active, the second select switch 169 connects the output of the count latch circuit 166 with the digital signal line(s) 18 and passes the count signal CNT to the digital signal line(s) 18.

[0073] FIG. 5 illustrates the operation of the pixel circuits 100 described with reference to the preceding figures. The height of the columns in the top row indicates the amount of charge accumulated by the photoelectric conversion device PD during a single exposure at successive points in time tO to tl2. The height of the columns in the middle row indicates the amount of charge accumulated in the charge accumulation structure FD at the points in time tO to tl2. The numbers in the bottom row indicate the number of self-resets for the charge accumulation structure FD at the respective points in time tO to tl2.

[0074] When radiation incidents onto the pixel circuit, the charge in the photoelectric conversion device PD increases steadily until the charge reaches the first threshold charge TH1 at t3. The overflow mechanism from the photoelectric conversion device PD to the charge accumulation structure FD is activated, and the overflowing charge increases the charge in the charge accumulation structure FD until the charge in the charge accumulation structure FD reaches the second threshold charge TH2 att6. The charge accumulation structure FD is reset and the number of self-resets is increased by one. The charge accumulation in the charge accumulation structure FD, the resetting of the charge accumulation structure FD and the increase of the number of self-resets are repeated for the remainder of the exposure period. At the end of the exposure period at tl2, the received radiation intensity can be computed from the charges accumulated in the photoelectric conversion device PD and in the charge accumulation region FD at 112 and the number of self-resets at tl2.

[0075] FIG. 6 shows further details of an example for the digital circuit 160 of FIG. 4. The amplifier element 173 is a p channel FET with the load path electrically connected between the logic supply voltage VDDL and a comparator output node 179. A NAND gate 162 masks the comparator output signal CM OUT with a first clock signal CLK1.

[0076] The reset latch 161 receives the NAND-gated comparator output signal CM OUT at a first input Al, a second clock signal CLK2 at a second input A2 and the forced reset signal VS RST at a reset input. The reset latch 161 outputs complementary signals at a first output VO and a second output XVO. A level shift circuit 165 receives the complementary signals output on the first output VO and the second output XVO and converts the signal amplitude to a signal amplitude matching the analog supply voltage VDDH.

[0077] The count latch circuit 166 receives the NAND-gated comparator output signal CM OUT at a second input A2 and a third clock signal CLK at a first input Al and outputs a count signal CNT every time the amplifier element 173 inverts.

[0078] The second select switch 169 includes a pass transistor (transmission gate) that is controlled by the read signal READ and the inverted read signal XREAD. In response to an active read signal READ, the second select switch 169 connects the output of the count latch circuit 166 with the digital signal line 18.

[0079] A first n channel FET 178 is an example for the constant current source 125 illustrated in FIG. 4. The gate of the first n channel FET 178 receives a first constant bias voltage NB 1. The first n channel FET 178 drives the current for the pixel source follower that further includes the amplifier transistor 121 of FIG. 4. The gate of a second n channel FET 179 receives a second constant bias voltage NB2. The second n channel FET 179 drives the tail current for the amplifier element 173.

[0080] The vertical scanning unit 30 of FIG 1 controls the transfer gate signal TRG, the forced reset signal VS RST, the autozeroing signal AZ, the threshold voltage signal CMTHR, the read signal READ, a first clock signal CLK1, and a second clock signal CLK2 according to the time chart illustrated in FIG. 7.

[0081] The transfer gate signal TRG, the forced reset signal VS RST, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 have active high level. The autozeroing signal AZ has active low level. Rising edges of the third clock signal CLK3 may be triggered by the comparator output signal CM OUT becoming active.

[0082] In a reset period between tO and tl, synchronously active transfer gate and forced reset signals TRG, VS RST initialize the charge on the floating electrode of the photoelectric conversion element PD and the charge accumulation structure FD with the analog supply voltage VDDH. Simultaneously with the transfer gate signal TRG and the forced reset signal VS RST, the active autozeroing signal initializes the comparator circuit 170. Simultaneously with the transfer gate signal TRG and the forced reset signal VS RST, the third clock signal CLK3 becomes active.

[0083] The first and second clock signals CLK1, CLK2 are pulsed signals that provide an external pulse control for the self-reset and the count signal CNT. The first clock signal CLK1 and the second clock signal CLK2 become synchronously active. The pulse width of the first clock signal CLK1 is shorter than the pulse width of the second clock signal CLK2. The first clock signal CLK1 samples the comparator output signal at predefined points in time. The second clock signal CLK2 resets the reset latch circuit 161 at predefined points in time.

[0084] At tl, the exposure period starts with the transfer gate signal TRG and the forced reset signal VS RST becoming inactive. The voltage across the photoelectric conversion element PD begins to decrease according to the illumination conditions. The potential of the charge accumulation structure FD drops by the threshold voltage AMPvt of the amplifier transistor 121.

[0085] At t2, the photoelectric conversion element PD saturates and excess charge overflows into the charge accumulation structure FD, wherein the potential of the charge accumulation structure FD begins to drop according to the illumination conditions.

[0086] At t5 the charge accumulation structure FD saturates and the comparator output signal CM OUT changes to the active level. When the comparator output signal CM OUT is active, the rising edge of the first clock signal active CLK1 triggers a selective self-reset between t5 and t6. The first clock signal CLK1 samples the comparator output signal. The second clock signal CLK2 resets the reset latch circuit 161 accordingly.

[0087] For the self-reset the transfer gate signal TRG is decoupled from the reset signal RST such that the transfer gate signal TRG remains inactive between t5 and t6. The charge on the photoelectric conversion element PD remains unaffected by the self-resetting of the charge accumulation structure FD. A further self-reset occurs between t9 and tlO.

[0088] In FIG. 8A and FIG. 8B, the lines 801 show the variation over time of the voltage across the photoelectric conversion device PD and the lines 802 show the variation over time of the potential of the charge accumulation structure FD during an exposure time under different illumination conditions.

[0089] For FIG. 8B the photocurrent is five times the photocurrent for FIG. 8A.

[0090] FIG. 9 shows an image sensor 70 that includes atop die 910 and a bottom die 920. The analog circuits 110 with the photoelectric conversion devices PD are formed in the top die 910. The digital circuits 160 are formed in the bottom die 910. The analog circuits 110 and the digital circuits 160 are arranged in two congruent two-dimensional matrices with columns and rows, such that each analog circuit 110 is directly above the digital circuit 160 of the same pixel circuit 100. For each pixel circuit 100, chip-to-chip connections 915 pass the analog pixel signal CM IN from the top die 910 to the bottom die 920 and the reset signal RST from the bottom die 920 to the top die 910.

[0091] As illustrated in FIG. 1, the image sensor 70 includes a readout circuit 20 configured to convert the analog pixel signal passed to the analog signal line 19 in a readout period into a digital pixel value.

[0092] The readout circuit 20 may be assigned to one single pixel circuit 100 or to a group of pixel circuits 100. For example, the readout circuit 20 may be a column readout circuit consecutively connectable to all pixel circuits 100 of a pixel row as illustrated in FIG. 1. Alternatively, the readout circuit 20 may be assigned to one single pixel circuit 100, wherein the readout circuits 20 may be formed in the bottom tie 920 of FIG. 9 or in an additional tie (not illustrated), and wherein each readout circuit 20 is connectable to the pixel circuits 100 in the top tie 910 and the bottom tie 920 through one or more chip-to-chip connections. As illustrated in FIG. 1, the image sensor 70 further includes a sensor controller 50.

[0093] The sensor controller 50 is configured to control the overflow transfer gate 111 and a reset of the charge accumulation structure FD to sequentially perform a differential double sampling of the charge accumulation structure FD and a correlated double sampling of the photoelectric conversion device PD.

[0094] The differential double sampling and the correlated double sampling may share a common preset phase.

[0095] FIG. 10 illustrates an example for a readout process for a pixel circuit of any of the image sensors described with reference to the preceding figures.

[0096] For a first phase 961, the charge accumulation structure FD has accumulated the charge overflowing from the photoelectric conversion element PD during an exposure. At the end of the exposure, the readout circuit converts the analog pixel signal representing an FD data signal (FD D-phase) into a first digital value Dphase 1.

[0097] For the second phase 962, the charge accumulation structure FD is reset. After reset, charge is generated by noise and accumulated by the charge accumulation structure FD. The readout circuit converts the analog pixel signal representing an FD reset signal (FD P-phase) into a second digital value Pphase.

[0098] For the third phase 963, the overflow transfer gate 111 is turned on and the charge previously accumulated by the photoelectric conversion element PD is transferred to the charge accumulation structure FD. The readout circuit converts the analog pixel signal representing a PD data signal (PD D-phase) into a third digital value Dphase2.

[0099] In an independent fourth phase 964, the number NSR of self-resets is read from the pixel counter assigned to the pixel circuit. With pd _cf representing a conversion factor for the photoelectric conversion element PD, fd cf representing a conversion factor for the charge accumulation structure FD, and fd fw representing a full capacity of the charge accumulation structure, the readout circuit or a further downstream unit may obtain a final pixel value PW according to equation # 1 :

[0100] #1: PW = fd_cf*(Dphasc l-Pphasc) + pd_cf*(Dphase2-Pphase) + fd_fw*NSR

[0101] According to other examples, the readout of the charge of the photoelectric conversion element PD can be omitted when the number NSR of self-resets is greater zero.

[0102] FIG. 11 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

[0103] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 11, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0104] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0105] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of vanous kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0106] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0107] The imaging section 12031 may be or may include an image sensor according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and / or invisible light such as infrared rays or the like.

[0108] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

[0109] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0110] In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0111] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030. The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 11, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

[0112] FIG. 12 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0113] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0114] Incidentally, FIG. 12 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0115] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor according to the embodiments of the present disclosure.

[0116] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

[0117] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0118] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images ofthe imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0119] The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor according to the embodiments of the present disclosure, a high dynamic range can be achieved. Flickering traffic lights can be safely detected.

[0120] Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology. The image sensor according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, an image sensor according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

[0121] Specifically, in the field of image reproduction, the image sensor according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including an image sensor according to the embodiments may be integrated in an m-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

[0122] In the field of home appliances, the image sensor according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the image sensor according to the embodiments may be integrated in home appliances such as TV receivers, refngerators, and air conditioners and / or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the image sensor according to the embodiments may be integrated in any type of sensor, e.g., a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

[0123] In the field of security, the image sensor according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, an image sensor according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, an image sensor according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the image sensor can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

[0124] The present technology can also be configured as described below:

[0125] [1] An image sensor, including: a photoelectric conversion element (PD) configured to accumulate charge generated by incident radiation; a charge accumulation structure (FD) and an overflow transfer gate (111) configured to pass charge from the photoelectric conversion element (PD) to the charge accumulation structure (FD) in a first case when the accumulated charge in the photoelectric conversion element (PD) reaches a first threshold charge and in a second case in response to an active transfer gate signal; and a digital circuit (160) configured to trigger a reset of the charge accumulation structure (FD) each time a charge accumulated in the charge accumulation structure (FD) reaches a second threshold charge during an exposure period.

[0126] [2] The image sensor according to [1], wherein electric potential heights of the overflow transfer gate (111) are such that charge flows through the overflow transfer gate (111) when the photoelectric conversion element (PD) is saturated.

[0127] [3] The image sensor according to [1] or [2], further including: an amplifier circuit (120) configured to output an analog pixel signal, wherein a voltage level of the analog pixel signal is a function of the charge accumulated in the charge accumulation structure (FD).

[0128] [4] The image sensor according to [3], wherein the amplifier circuit (120) includes an amplifier transistor (121) and an auxiliary constant current source (125) connected to each other in a source follower configuration.

[0129] [5] The image sensor according to [1] to [4], wherein the charge accumulation structure (FD) is configured to be reset in response to the analog pixel signal reaching a predefined reset threshold voltage.

[0130] [6] The image sensor according to [3] to [5], further including: a first select switch (109) configured to connect the amplifier transistor (121) to an analog signal line (19) in response to an active analog select signal.

[0131] [7] The image sensor according to [4], further including: a main constant current source (128) configured to be in a source follower configuration with the amplifier transistor (121) in a readout period.

[0132] [8] The image sensor according to [1] to [7], further including: a reset transistor (105) configured to reset a potential of the charge accumulation structure (FD) in response to an active reset signal received from the digital circuit (160).

[0133] [9] The image sensor according to [8], wherein the digital circuit (160) is configured to output the active reset signal when a charge accumulated in the charge accumulation structure (FD) reaches the second threshold charge.

[0134]

[0010] The image sensor according to [1] to [9], wherein the digital circuit (160) includes a comparator circuit (170) configured to receive an analog pixel signal having a voltage level being a function of the charge accumulated in the charge accumulation structure (FD), and output an active comparator output signal when the analog pixel signal reaches a reset threshold voltage corresponding to the second threshold charge.

[0135]

[0011] The image sensor according to

[0010] , wherein the comparator circuit (170) includes an amplifier element (173) and an autozero element (174) configured to short-circuit input and output of the amplifier element (173) in response to an active autozeroing signal.

[0012] The image sensor according to [8] to [9], wherein the digital circuit (160) includes a reset latch circuit (161) configured to output the active reset signal in response to receiving an active comparator output signal.

[0136]

[0013] The image sensor according to [1] to

[0012] , further including: a count circuit (180) configured to increase a reset count each time a charge accumulated in the charge accumulation structure (FD) reaches the second threshold charge during an exposure period.

[0014] The image sensor according to [6], further including: a readout circuit (20) configured to convert the analog pixel signal passed to the analog signal line (19) in a readout period into a digital pixel value.

[0137]

[0015] The image sensor according to [1] to

[0014] , further including: a sensor controller (50) configured to control the overflow transfer gate (111) and a reset of the charge accumulation structure (FD) to sequentially perform a differential double sampling of the charge accumulation structure (FD) and a correlated double sampling of the photoelectric conversion device (PD).

[0138]

[0016] The image sensor according to [1] to

[0015] , wherein the differential double sampling and the correlated double sampling share a common preset phase..

Claims

CLAIMS1. An image sensor, comprising a photoelectric conversion element configured to accumulate charge generated by incident radiation; a charge accumulation structure and an overflow transfer gate configured to pass charge from the photoelectric conversion element to the charge accumulation structure in a first case when the accumulated charge in the photoelectric conversion element reaches a first threshold charge and in a second case in response to an active transfer gate signal; and a digital circuit configured to trigger a reset of the charge accumulation structure each time a charge accumulated in the charge accumulation structure reaches a second threshold charge during an exposure period.

2. The image sensor according to claim 1, further comprising: wherein electric potential heights of the overflow transfer gate are such that charge flows through the overflow transfer gate when the photoelectric conversion element is saturated.

3. The image sensor according to claim 1, further comprising: an amplifier circuit configured to output an analog pixel signal, wherein a voltage level of the analog pixel signal is a function of the charge accumulated in the charge accumulation structure.

4. The image sensor according to claim 3, wherein the amplifier circuit comprises an amplifier transistor and an auxiliary constant current source connected to each other in a source follower configuration.

5. The image sensor according to claim 1, wherein the charge accumulation structure is configured to be reset in response to the analog pixel signal reaching a predefined reset threshold voltage.

6. The image sensor according to claim 3, further comprising: a first select switch configured to connect the amplifier transistor to an analog signal line in response to an active analog select signal.

7. The image sensor according to claim 4, further comprising: a main constant current source configured to be in a source follower configuration with the amplifier transistor in a readout period.

8. The image sensor according to claim 1, further comprising: a reset transistor configured to reset a potential of the charge accumulation structure in response to an active reset signal received from the digital circuit.

9. The image sensor according to claim 8, wherein the digital circuit is configured to output the active reset signal when a charge accumulated in the charge accumulation structure reaches the second threshold charge.

10. The image sensor according to claim 1, wherein the digital circuit comprises a comparator circuit configured to receive an analog pixel signal having a voltage level being a function of the charge accumulated in the charge accumulation structure, and output an active comparator output signal when the analog pixel signal reaches a reset threshold voltage corresponding to the second threshold charge.

11. The image sensor according to claim 10, wherein the comparator circuit comprises an amplifier element and an autozero element configured to short-circuit input and output of the amplifier element in response to an active autozeroing signal.

12. The image sensor according to claim 8, wherein the digital circuit comprises a reset latch circuit configured to output the active reset signal in response to receiving an active comparator output signal.

13. The image sensor according to claim 1, further comprising: a count circuit configured to increase a reset count each time a charge accumulated in the charge accumulation structure reaches the second threshold charge during an exposure period.

14. The image sensor according to claim 6, further comprising: a readout circuit configured to convert the analog pixel signal passed to the analog signal line in a readout period into a digital pixel value.

15. The image sensor according to claim 1, further comprising: a sensor controller configured to control the overflow transfer gate and a reset of the charge accumulation structure to sequentially perform a differential double sampling of the charge accumulation structure and a correlated double sampling of the photoelectric conversion device.

16. The image sensor according to claim 15, wherein the differential double sampling and the correlated double sampling share a common preset phase.

Images