Sensor and method

Abstract

A capacitive touch sensor comprising an array of pixels, each pixel comprising a capacitive sensing electrode; a sense voltage-controlled impedance, VCI; and electrostatic discharge, ESD, protection circuitry comprising a first ESD conduction path between a control terminal of the sense VCI and a first protection voltage; and a second ESD conduction path between a second protection voltage and the control terminal of the sense VCI.

Description

[0001] Sensor and Method

[0002] Technical Field

[0003] The present disclosure relates to the field of sensors and methods of sensing. In particular, the present disclosure may relate to the field of capacitive sensors, such as capacitive touch sensors, as well as methods of operating such sensors.

[0004] Background

[0005] Capacitive sensors, such as for biometric sensing, typically include an array of sensor pixels. Each pixel includes a capacitive sensing electrode which is designed to couple, capacitively, with a conductive object in proximity of that electrode. By determining an indication of the capacitance associated with that electrode, it is possible to infer a distance of separation between the electrode and the portion of the conductive object which is close to (e.g. above) that electrode. By obtaining this information over a spatial area large enough to contain a user’s fingerprint, a series of ridges and valleys for the user’s skin can be detected from the capacitance values. The ridges will be regions where the skin is closer to the electrode, and the valleys will be regions where the skin is further away. The distribution of ridges and valleys for the user’s fingerprint can then be used to identify the user, as the distribution of ridges and valleys in a user’s fingerprint will be unique.

[0006] It remains desirable to provide improved capacitive sensors of this type.

[0007] Summary

[0008] Aspects of the disclosure are set out in the independent claims and optional features are set out in the dependent claims. Aspects of the disclosure may be provided in conjunction with each other, and features of one aspect may be applied to other aspects.

[0009] In an aspect, there is provided a capacitive touch sensor comprising an array of pixels, each pixel comprising: a capacitive sensing electrode; a sense voltage-controlled impedance, VCI; and electrostatic discharge, ESD, protection circuitry comprising: a first ESD conduction path between a control terminal of the sense VCI and a first protection voltage; and a second ESD conduction path between a second protection voltage and the control terminal of the sense VCI. Embodiments may provide a capacitive touch sensor in which the pixels of the sensor array are protected against ESD. For instance, each pixel in the sensor array may include ESD protection circuitry to prevent that pixel, and in particular the sense VCI of that pixel, against ESD. Protecting the pixel (e.g. the sense VCI) against damage due to ESD may improve the reliability and longevity of the pixel and thus the sensor. In turn, this may provide an improved capacitive touch sensor.

[0010] The ESD protection circuitry may be configured to inhibit a voltage at the control terminal of the sense VCI extending beyond a threshold range of permitted values. For example, the first ESD conduction path may be responsible for inhibiting the voltage at the control terminal of the sense VCI going above an upper voltage value. Likewise, the second ESD conduction path may be responsible for inhibiting the voltage at the control terminal of the sense VCI going below a lower threshold value. For example, first protection voltage may be a higher value (e.g. a more positive value) than the second protection voltage. The first protection voltage may be provided by a high voltage line (or ‘rail’) of the sensor array. The second protection voltage may be provided by a low voltage line (or ‘rail’) of the sensor array. Additionally, or alternatively, the first and / or second protection voltages may be provided by other voltage connections within the pixel, such as to one or more sources of voltage which are additionally used for other purposes in the pixel (in addition to ESD protection).

[0011] The first ESD conduction path may comprise a one-way conduction path from the control terminal of the sense VCI to the first protection voltage. For example, the first ESD conduction path may be arranged to permit current to flow from the control terminal of the sense VCI to the first protection voltage (e.g. in the event that the voltage at said control terminal exceeds a threshold value), but to inhibit current from flowing from the first protection voltage to said control terminal. The one-way conduction path may comprise a transistor. For example, the transistor may be arranged to provide a diode (e.g. it may be a diode-connected transistor).

[0012] The ESD protection circuitry may be configured to allow current to flow from the control terminal of the sense VCI to the first protection voltage in the event that a voltage at said control terminal is greater than an upper threshold voltage. For example, the first protection voltage may be a positive voltage (e.g. it may comprise a connection to a source of a positive voltage). The upper threshold voltage may be a positive voltage. The pixel may be configured so that current flow from the control terminal to the source of the positive voltage (e.g. a ‘high’ voltage) in the event that the voltage at the control terminal is more positive than the upper threshold voltage. The upper threshold voltage may be based on the first protection voltage. For example, the ESD protection circuitry may be configured to allow current to flow toward the first protection voltage (e.g. the source of high voltage) once the voltage of the control terminal exceeds the first protection voltage (e.g. the high voltage). Current may flow once the voltage difference from the control terminal of the sense VCI to the first protection voltage (e.g. the high voltage) is sufficiently large to render any components therebetween, such as a diode or transistor, electrically conductive.

[0013] The ESD protection circuitry may be configured to allow current to flow to the control terminal of the sense VCI from the second protection voltage in the event that a voltage at said control terminal is below a lower threshold voltage. The second protection voltage may be zero or negative. For example, the source of the second protection voltage may comprise a negative voltage source (or an electrical ground). The lower threshold voltage may be a negative voltage or it may be zero. The pixel may be configured so that current is allowed to flow to the control terminal from the second protection voltage (e.g. the source of ‘low’ voltage) in the event that the voltage at the control terminal is more negative than the second protection voltage. Current may flow once the voltage difference from the second protection voltage (e.g. the low voltage) to the control terminal of the sense VCI is sufficiently large to render any components therebetween, such as a diode or transistor, electrically conductive.

[0014] The sensor may be configured to set a voltage at the control terminal of the sense VCI to a selected value prior to operating that sense VCI. For example, the sensor may be configured to pre-charge the control terminal of the sense VCI, e.g. to a selected (e.g. known) voltage. The sensor may be configured to set the voltage of the control terminal sense VCI to the selected value before using that sense VCI to output a read-out signal. The read-out signal may be indicative of a proximity to the capacitive sensing electrode of a conductive object to be sensed. The pixel may comprise a bias VCI. A conductive channel of the bias VCI may be connected between a bias voltage and the control terminal of the sense VCI. The bias VCI and bias voltage may be configured to reset the voltage at the control terminal of the sense VCI to the selected value. A control terminal of the bias VCI may be connected to a gate line for one or more other pixels of the array. The control terminal of the bias VCI may be connected to a gate line for another row of pixels in the array, such as the preceding row of pixels in the array (e.g. the row which is to be activated prior).

[0015] The bias voltage may provide the second protection voltage. The connection of the bias voltage to the control terminal of the sense VCI via the conductive channel of the bias VCI may provide the second ESD conduction path. The lower threshold voltage may be based on a voltage of a control terminal of the bias VCI. The lower threshold voltage may be based on an ‘off’ voltage for a gate line connected to that control terminal. For example, in the event that a voltage difference between the voltage at the control terminal of the bias VCI and the voltage at the control terminal of the sense VCI (e.g. a gate-source voltage for the bias VCI) is above a threshold level (e.g. a switch-on voltage forthat VCI), the conductive channel of the bias VCI may become electrically conductive (e.g. thereby to connect the second protection voltage - the bias voltage - to the control terminal of the sense VCI).

[0016] The second ESD conduction path may comprise a one-way conduction path from the second protection voltage to the control terminal of the sense VCI. The one-way conduction path may comprise a transistor and / or a diode, such as a diode-connected transistor.

[0017] A conductive channel of the sense VCI may be selectively connectable to a reference voltage. The reference voltage may provide the first protection voltage. The pixel may comprise a select VCI. A conductive channel of the select VCI may be connected between the conductive channel of the sense VCI and the reference voltage. A control terminal of the select VCI may be connected to a gate line for that pixel.

[0018] The capacitive touch sensor may comprise a capacitive biometric skin contact sensor. The capacitive biometric skin contact sensor may be configured to detect the difference between ridges and valleys in a user’s fingerprint for biometric identification of the user. The pixel may comprise a reference capacitor. A first plate of the reference capacitor may be connected to a gate line for said pixel. A second plate of the reference capacitor may be connected to the control terminal of the sense VCI and the capacitive sensing electrode.

[0019] The conductive channel of the sense VCI may be connected to a read-out line for the pixel. The first protection voltage may be selected based on a voltage of the read-out line for the pixel. For example, the first protection voltage may be selected to be within a threshold amount of the voltage of the read-out line for the pixel, e.g. the first protection voltage may be larger than the read-out line voltage but not vastly larger. The first protection voltage may be selected so that a difference between the first protection voltage and the voltage of the read-out line for the pixel is below an amount associated with damaging the sense VCI. For example, a maximum voltage across the sense VCI (e.g. a maximum gate-source voltage) may correspond to a difference between the first protection voltage and the read-out line voltage. At least one of these voltages may be selected so that the difference is below an amount likely to damage the sense VCI.

[0020] The first protection voltage may be positive, and / or the second protection voltage may be zero or negative. For example, the ESD protection circuitry may be configured to provide both positive and negative ESD protection.

[0021] In an aspect, there is provided a capacitive touch sensor comprising an array of pixels, each pixel comprising: a capacitive sensing electrode; a sense voltage-controlled impedance, VCI; and electrostatic discharge, ESD, protection circuitry comprising an ESD conduction path between a control terminal of the sense VCI and a high voltage source.

[0022] In an aspect, there is provided a method of controlling operation of a capacitive touch sensor, wherein the touch sensor comprises an array of pixels, each pixel comprising: (i) a capacitive sensing electrode, and (ii) a sense voltage-controlled impedance, VCI, and wherein the method comprises: connecting a control terminal of the sense VCI to a first protection voltage to provide electrostatic discharge, ESD, protection for the sense VCI; and connecting the control terminal of the sense VCI to a second protection voltage to provide ESD protection for the sense VCI.

[0023] Figures

[0024] Some examples of the present disclosure will now be described, by way of example only, with reference to the figures, in which:

[0025] Fig. 1 is a schematic diagram of a portion of a capacitive sensor.

[0026] Fig. 2 is a schematic diagram of a portion of a capacitive sensor.

[0027] Fig. 3 is a schematic diagram of a portion of a capacitive sensor.

[0028] Fig. 4 is a schematic diagram illustrating a capacitive touch sensor comprising an array of pixels.

[0029] In the drawings like reference numerals are used to indicate like elements.

[0030] Specific Description

[0031] Embodiments of the present disclosure relate to a capacitive touch sensor which is designed to provide electrostatic discharge (‘ESD’) protection for the capacitive sensor pixels of that sensor. For this, each sensor pixel includes ESD protection circuitry. The ESD protection circuitry provides conduction paths for directing current to or from the pixel to prevent against an ESD event. Each pixel includes a sense transistor and a capacitive sensing electrode. The sense transistor is configured to output a read-out signal indicative of the effective capacitance of the capacitive sensing electrode. The ESD protection circuitry is configured to protect the sense transistor against an ESD event. The ESD protection circuitry of each pixel connects a gate region of the sense transistor of that pixel to one or more protection voltages, such as a high and low protection voltage, for directing current to or from said protection voltage(s) to protect against an ESD event. The ESD protection circuitry is designed so that this current flow will occur, as required, once a voltage at the gate region of the sense transistor is no longer within a selected voltage range.

[0032] Examples of capacitive sensors will now be described with reference to the Figs. Each of the three Figs, shows a different design for the capacitive sensing pixel, but with each of these pixel designs including ESD protection circuitry for protecting components of the pixel. Reference will first be made to Fig. 1 .

[0033] Fig. 1 shows a portion of a capacitive sensor. One sensor pixel 100 is shown in Fig. 1.

[0034] The sensor pixel 100 includes a voltage-controlled impedance and a capacitive sensing electrode 110. The voltage-controlled impedance is shown as a thin film transistor (‘TFT’) 130. The voltage-controlled impedance has a control terminal, which is shown as the gate region 132 of the TFT 130. From hereon in, the TFT 130 will be referred to as ‘Sense TFT’ 130.

[0035] The pixel 100 includes ESD protection circuitry. For this, there is a first ESD conduction path 12 and a second ESD conduction path 22. The first ESD conduction path 12 is connected to a first protection voltage, which is shown as a high voltage line 10 (or ‘rail’). The second ESD conduction path 22 is connected to a second protection voltage, which is shown as a low voltage line 20 (or ‘rail’).

[0036] The pixel 100 is connected to a gate line 102 and a read-out line 104. The pixel 100 may include an optional reference capacitor 120 (as shown in Fig 1).

[0037] Five voltages are shown in Fig. 1 (these are shown in italicised text). V+ is the first protection voltage (i.e. of the high voltage line 10). V- is the second protection voltage (i.e. of the low voltage line 20). Vgate is the voltage of the control terminal of the voltage-controlled impedance (i.e. the gate voltage of sense TFT 130). refis a reference voltage to be provided to the pixel 100. Vread-out is a voltage of the read-out line 104.

[0038] The gate region 132 of the sense TFT 130 is connected to the capacitive sensing electrode 110. The gate region 132 may also be connected to a second plate of the reference capacitor 120. A first plate of the reference capacitor 120 may be connected to the gate line 102 for that pixel 100.

[0039] The ESD protection circuitry provides connections between the gate region 132 of the sense TFT 130 and the first and second protection voltages (the high and low voltage lines, respectively, in the example of Fig. 1). The first ESD conduction path 12 connects the gate region 132 of the sense TFT 130 to the high voltage line 10 (\ / +). The second ESD conduction path 22 connects the low voltage line 20 (V-) to the gate region 132 of the sense TFT 130.

[0040] In Fig. 1 , a diode is shown in each of the first ESD conduction path 12 and the second ESD conduction path 22. For the first ESD conduction path 12, an anode of the diode is connected to the gate region 132 of the sense TFT 130, and the cathode of the diode is connected to the high voltage line 10 (\ / +). For the second ESD conduction path 22, a cathode of the diode is connected to the gate region 132 of the sense TFT 130, and the anode of the diode is connected to the low voltage line 20 (V-).

[0041] A conductive channel of the sense TFT 130 couples a reference voltage source (Vref) to the read-out line 104 for that pixel 100. The conductive channel of the sense TFT 130 may be connected directly, or indirectly (e.g. via one or more other electrical components), to the reference voltage source Vref). The read-out line 104 is connected to read-out input circuitry of the sensor.

[0042] The ESD protection circuitry is configured to provide ESD protection for the pixel 100. In particular, the ESD protection circuitry is configured to provide ESD protection for the sense TFT 130. For this, the ESD protection circuitry is configured to inhibit a voltage (Vgate) at the gate region 132 of the sense TFT 130 from being outside a selected voltage range. The ESD protection circuitry is arranged to enable current to flow through a respective ESD conduction path in response to the voltage (Vgate) at the gate region 132 of the sense TFT 130 extending beyond the selected voltage range.

[0043] The first ESD conduction path 12 provides a one-way conduction path from the gate region 132 of the sense TFT 130 to the high voltage line 10. The first ESD conduction path 12 is arranged to permit current to flow, from the gate region 132 of the sense TFT 130 to the high voltage line 10, in the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 exceeds an upper threshold value. In the example of Fig. 1 , the upper threshold voltage value comprises the voltage (\ / +) of the high voltage line 10. In the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 exceeds the voltage (\ / +) of the high voltage line 10, the diode in the first ESD conduction path 12 will become electrically conductive (e.g. because its anode voltage will exceed its cathode voltage). In turn, current may then flow across the diode from the gate region 132 of the sense TFT 130 to the high voltage line 10, thereby to reduce the voltage (Vgate) at the gate region 132 of the sense TFT 130. Current will continue to flow until the voltage (Vgate) at the gate region 132 of the sense TFT 130 is at or below its upper threshold value, e.g. until it is at or below the voltage (\ / +) of the high voltage line 10.

[0044] The second ESD conduction path 22 provides a one-way conduction path from the low voltage line 20 to the gate region 132 of the sense TFT 130. The second ESD conduction path 22 is arranged to permit current to flow, from the low voltage line 20 to the gate region 132 of the sense TFT 130, in the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 is below a lower threshold value. In the example of Fig. 1 , the lower threshold voltage value comprises the voltage (V-) of the low voltage line 20. In the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 drops below the voltage (V-) of the low voltage line 20, the diode in the second ESD conduction path 22 will become electrically conductive (e.g. because its anode voltage will exceed its cathode voltage). In turn, current may then flow across the diode from the low voltage line 20 to the gate region 132 of the sense TFT 130, thereby to increase the voltage (Vgate) at the gate region 132 of the sense TFT 130. Current will continue to flow until the voltage (Vgate) at the gate region 132 of the sense TFT 130 is at or above its upper threshold value, e.g. until it is at or above the voltage (V-) of the low voltage line 20.

[0045] In other words, the ESD protection circuitry is configured to retain the voltage (Vgate) of the gate region 132 of the sense TFT 130 within a threshold voltage range. The threshold voltage range is the range of voltage between the voltage (V-) of the low voltage line 20, and the voltage (\ / +) of the high voltage line 10. As such, the ESD protection circuitry is arranged to inhibit the voltage (Vgate) from getting too high or too low.

[0046] As will be appreciated in the context of the present disclosure, the range of acceptable voltage values for the voltage (Vgate) at the gate region 132 of the sense TFT 130 may be chosen based on one or more properties of the sensor pixel circuitry itself. For example, the range may be selected based on operating conditions of the sense TFT 130, e.g. so that it is not caused to operate at voltage values which may be harmful to that TFT. In the example of Fig. 1 , the voltage (\ / +) of the high voltage line 10 is more positive than the voltage (V-) of the low voltage line 20. For example, V+ may be positive and V- may be negative. Alternatively, both could be positive or both could be negative. As will be appreciated in the context of the present disclosure, the two ESD conduction paths and the two respective protection voltages enable a range of acceptable values to be controlled for the voltage (Vgate) at the gate region 132 of the sense TFT 130, and what the particular values are for this range may be controlled accordingly depending on the properties of the sensor pixel 100 and the sensing circuitry.

[0047] As one example, the voltage (\ / +) of the high voltage line 10 may be selected to be higher than the voltage (Vread-out) of the read-out line 104. That way, the voltage Vgate) of the gate region 132 of the sense TFT 130 is permitted to be greater than the voltage (Vread-out) of the read-out line 104, thereby to enable the gate-source voltage for the sense TFT 130 to be positive (with the source region of the sense TFT 130 being connected to the read-out line 104). In turn, this may permit a read-out signal to be output from the sense TFT 130 to the read-out line 104. The voltage (\ / +) of the high voltage line 10 may be selected to be within a threshold amount of the voltage Vread-out) of the read-out line 104, thereby to inhibit the gate-source voltage of the sense TFT 130 exceeding a threshold amount, e.g. where that threshold amount is selected to inhibit damage occurring to the sense TFT 130 due to a magnitude of its gate-source voltage.

[0048] The capacitance of the capacitive sensing electrode 110 depends on the proximity, to the capacitive sensing electrode 110, of a conductive surface of an object to be sensed. Thus, an indication of a capacitance of the capacitive sensing electrode 110 may provide an indication of the proximity of that surface to the capacitive sensing electrode 110.

[0049] To active the sensor pixel 100, the sensor is configured to apply a gate drive signal to that pixel 100. For this, the gate line 102 for that pixel 100 will be activated (e.g. driven to a high voltage). In the example pixel 100 of Fig. 1 , the gate drive signal will be applied to the first plate of the reference capacitor 120. The second plate of the reference capacitor 120 is connected to the capacitive sensing electrode 110 and the gate region 132 of the sense TFT 130 such that, when the gate drive signal is applied to the first plate of the reference capacitor 120, the relative division of that voltage between that sensing electrode 110 and the reference capacitor 120 provides an indication of the proximity of the surface of that conductive object to the capacitive sensing electrode 110. This division of the control voltage provides an indicator voltage at the connection between the second plate of the reference capacitor 120 and the capacitive sensing electrode 110. The gate region 132 of the sense TFT 130 is connected to this connection between the second plate and the capacitive sensing electrode 110 so that the indicator voltage is applied to the gate region 132 of the sense TFT 130. The sense TFT 130 is arranged to provide an output from the pixel 100 (in the form of a read-out signal) which indicates proximity of the conductive object. The ESD protection circuitry is configured to provide ESD protection for the sense TFT 130 irrespective of whether the pixel 100 is activated or not.

[0050] In operation, to obtain a read-out signal from the pixel 100, a gate drive signal is applied to the gate line 102, and thus to the first plate of the reference capacitor 120. A voltage applied to the gate region 132 of the sense TFT 130 will therefore depend on the gate drive voltage and the proximity of the conductive object to be sensed to the capacitive sensing electrode 110. The source voltage of the sense TFT 130 will correspond to a voltage (Vread-out) of the readout line 104. A gate-source voltage across the sense TFT 130 will therefore vary in dependence on the effective capacitance of the capacitive sensing electrode 110 (i.e. of the proximity of the conductive object to the capacitive sensing electrode 110). A magnitude of the read-out current output from the sense TFT 130 will therefore provide an indication of the proximity of this conductive object to the capacitive sensing electrode 110. Read-out circuitry of the sensor may process such received read-out currents to digitise this information. For example, biometric sensing may be performed based on data obtained across the array. This process of activating pixels and then leaving pixels inactive until a subsequent measurement is obtained may continue to provide the desired capacitive sensing.

[0051] At any stage during operation of the sensor, the ESD protection circuitry will provide ESD protection for the sensor pixel 100. At any point in time, the sensor may be subject to voltages which are outside the selected voltage range for that pixel 100. For example, a static charge may build up on a user’s finger due to contact with a static generating surface (e.g. rubbing certain materials), and this may be discharged into the sensor by the user trying to contact the sensor (e.g. for biometric finger sensing). In which case, this may act as a capacitive divider in which a greater charge on the capacitive sensing electrode is divided onto the gate region 132 of the sense TFT 130 (e.g. injected on Vgate). The ESD protection circuity will provide ESD protection to address this static charge applied to the sensor. Operation in the two modes of ESD protection will be described in turn.

[0052] In a first (‘high’) mode, the pixel 100 will receive a large positive voltage. In which case, as the voltage (Vgate) exceeds the upper threshold amount, the first ESD conduction path 12 will become electrically conductive, thereby to connect the gate region 132 of the sense TFT 130 to the high voltage line 10. As already explained, by the voltage (Vgate) at the gate region 132 of the sense TFT 130 exceeding the voltage (\ / +) of the high voltage line 10, the diode in the first ESD conduction path 12 will become electrically conductive, thereby to allow current to flow from the gate region 132 of the sense TFT 130 to the high voltage line 10. In turn, this will permit the voltage (Vgate) at the gate region 132 of the sense TFT 130 to be reduced to a value at or below the upper threshold. At which point, the diode may no longer be electrically conductive, as the voltage (Vgate) at the gate region 132 of the sense TFT 130 will be below the upper threshold voltage (i.e. V+).

[0053] In a second (‘low’) mode, the pixel 100 will receive a large negative voltage. In which case, as the voltage (Vgate) will be below the lower threshold amount, the second ESD conduction path 22 will become electrically conductive, thereby to connect the low voltage line 20 to the gate region 132 of the sense TFT 130. As already explained, by the voltage (Vgate) at the gate region 132 of the sense TFT 130 dropping below the voltage (V-) of the low voltage line 20, the diode in the second ESD conduction path 22 will become electrically conductive, thereby to allow current to flow from the low voltage line 20 to the gate region 132 of the sense TFT 130. In turn, this will permit the voltage (Vgate) at the gate region 132 of the sense TFT 130 to be increased to a value at or above the lower threshold. At which point, the diode may no longer be electrically conductive, as the voltage (Vgate) at the gate region 132 of the sense TFT 130 will be above the lower threshold voltage (i.e. \ / -).

[0054] In either mode, the ESD protection circuitry prevents the voltage at the gate region 132 of the sense TFT 130 moving outside a selected range. This may provide protection for the sense TFT 130. In turn, this may enable greater reliability and longevity for such a sensor, as operation of the sense TFT 130 may be much less likely to be compromised or damaged due to any voltages it received which were outside of the selected range of allowable voltages for that sense TFT 130.

[0055] Another example of a capacitive sensor with ESD protection will now be described with reference to Fig. 2. In the example of Fig. 2, the pixel 100 includes additional components, and some of these components which perform other functions for operation of the sensor pixel 100 may also provide components of the ESD protection circuitry.

[0056] Fig. 2 shows a portion of a capacitive sensor. One sensor pixel 100 is shown in Fig. 2.

[0057] The sensor pixel 100 of Fig. 2 includes a number of similar components to those shown in Fig. 1 and described above. For the sake of brevity, these will not be described in detail again here. Of note, the pixel 100 of Fig. 2 is connected to a gate line 102 and a read-out line 104, and the pixel 100 includes a reference capacitor 120, a capacitive sensing electrode 110 and a sense TFT 130 (with gate region 132).

[0058] The pixel 100 includes additional voltage-controlled impedances. In this example, these are all TFTs. For this, the sensor pixel 100 also includes a select TFT 140 (with gate region 142) and a bias TFT 150 (with gate region 152). A protection TFT 180 is also included in the pixel 100.

[0059] Also shown in Fig. 2 is another gate line 101 for the sensor array. This is referred to as ‘Gate N-1 with the gate line 102 connected to the pixel 100 referred to as ‘Gate N’. However, it will be appreciated from the following description that the choice of Gate N-1 is not limiting, it could be another gate line for a preceding row to the row of the pixel 100 shown.

[0060] For the sensor pixel 100 of Fig. 2, at least some of the components which are used to provide the ESD protection circuitry are also used to provide additional functionality for the pixel itself. For example, components which provide active pixel functionality (e.g. biasing or selecting) may be used as well for ESD protection functionality. As such, the provision of ESD protection in the pixel 100 of Fig. 2 is achieved efficiently, as only a small amount of additional componentry is required (in this example, that is just the protection transistor and the connection path for that transistor).

[0061] As with the pixel 100 of Fig. 1 , the pixel 100 of Fig. 2 includes ESD protection circuitry which comprises a first ESD conduction path 12 and a second ESD conduction path 22. The first ESD conduction path 12 comprises the protection transistor. The first ESD conduction path 12 utilises a voltage (Vref) of the reference voltage source as the first protection voltage. The second ESD conduction path 22 comprises the bias TFT 150. The second ESD conduction path 22 utilises a voltage (Vb / as) of the bias TFT 150 as the second protection voltage.

[0062] As such, fewer voltages are shown in Fig. 2 than in Fig. 1. These are: (i) Vgate - the gate voltage for the sense TFT 130, (ii) Vref- the reference voltage for the pixel 100, which also provides the first protection voltage, (iii) Vbias - the biasing voltage for the pixel 100, which also provides the second protection voltage, and (iv) Vread-out - the voltage of the read-out line 104.

[0063] As with Fig. 1 , for the pixel 100 of Fig. 2, the ESD protection circuitry provides connections between the gate region 132 of the sense TFT 130 and the first and second protection voltages. For Fig. 2, the first protection voltage comprises the reference voltage (Vref), and the second protection voltage comprises the bias voltage Vbias).

[0064] The first ESD conduction path 12 connects the gate region 132 of the sense TFT 130 to the reference voltage (Vref). A conductive channel of the protection TFT 180 is connected between the gate region 132 of the sense TFT 130 and a source of the reference voltage (Vref). As described in more detail below, the protection TFT 180 is arranged to provide a oneway conduction path from the gate region 132 of the sense TFT 130 to the source of the reference voltage. In Fig. 2, the protection TFT 180 is connected to provide a diode, e.g. it is a diode-connected TFT. For this, the gate and drain regions of the protection TFT 180 are shorted (e.g. connected to each other), and these are both connected to the gate region 132 of the sense TFT 130. The source region of the protection TFT 180 is connected to the source of the reference voltage Vref).

[0065] The second ESD conduction path 22 connects the bias voltage (Vbias) to the gate region 132 of the sense TFT 130. A conductive channel of the bias TFT 150 is connected between a source of the bias voltage (Vb / as) and the gate region 132 of the sense TFT 130. As described in more detail below, a control terminal (e.g. gate region 152) of the bias TFT 150 is connected to a controllable voltage source for selectively activating the bias TFT 150 to pre-charge the gate region 132 of the sense TFT 130 prior to obtaining a read-out signal from that pixel 100. For example, the gate region 152 of the bias TFT 150 may be connected to another gate line for the sensor array (in the example of Fig. 2, this is shown as the preceding gate line 101 to the gate line 102 which is connected to the pixel 100). A source region of the bias TFT 150 is connected to the gate region 132 of the sense TFT 130. A drain region of the bias TFT 150 is connected to the source of the bias voltage (Vb / as).

[0066] A conductive channel of the select TFT 140 is connected between the source of the reference voltage Vref) and the conductive channel of the sense TFT 130. The control terminal (i.e. gate region 142) of the select TFT 140 is connected to the gate line 102 for that pixel 100. The drain region of the select TFT 140 is connected to the source of the reference voltage (Vref). The source region of the select TFT 140 is connected to the drain region of the sense TFT 130. The source region of the sense TFT 130 is connected to the read-out line 104 for the pixel 100.

[0067] As with Fig. 1 , the first plate of the reference capacitor 120 is connected to the gate line 102 for that pixel 100.

[0068] The gate region 132 of the sense TFT 130 is therefore connected to the drain and gate regions of the protection TFT 180, the capacitive sensing electrode 110, the source region of the bias TFT 150 and the second plate of the reference capacitor 120.

[0069] The underlying functionality for the ESD protection circuitry in the pixel 100 of Fig. 2 is similar to that of Fig. 1. That is, the ESD protection circuitry is configured to provide ESD protection for the sense TFT 130. For this, the ESD protection circuitry is configured to enable current to flow through a respective ESD conduction path in response to the voltage (Vgate) at the gate region 132 of the sense TFT 130 being above an upper threshold voltage or below a lower threshold voltage.

[0070] The conductive channel of the protection TFT 180 provides a selective connection between the gate region 132 of the sense TFT 130 and the reference voltage (Vref). The conductive channel of the bias TFT 150 provides a selective connection between the bias voltage (Vbias) and the gate region 132 of the sense TFT 130.

[0071] The first ESD conduction path 12 provides a one-way conduction path from the gate region 132 of the sense TFT 130 to the reference voltage (Vref). The first ESD conduction path 12 is arranged to permit current to flow, from the gate region 132 of the sense TFT 130 to the source of the reference voltage (Vref), in the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 exceeds an upper threshold value. The upper threshold voltage value corresponds to the reference voltage (Vref). In the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 exceeds the upper threshold voltage (e.g. which is based on the reference voltage Vref), the protection TFT 180 will become electrically conductive to permit current to flow through its conductive channel from the gate region 132 of the sense TFT 130 to the source of the reference voltage (e.g. because the voltage at its gate region, i.e. Vgate from the sense TFT 130, will exceed the voltage at its source, i.e. Vref, thereby rendering the conductive channel electrically conductive). In turn, current may flow through the conductive channel of the protection TFT 180 from the gate region 132 of the sense TFT 130 to the source of the reference voltage (Vref), thereby to reduce the voltage (Vgate) at the gate region 132 of the sense TFT 130. Current will continue to flow until the voltage (Vgate) at the gate region 132 of the sense TFT 130 is at or below the upper threshold value, e.g. until the gate-source voltage for the protection TFT 180 is insufficient to render the conductive channel therethrough electrically conductive.

[0072] The second ESD conduction path 22 provides a one-way conduction path from the bias voltage (Vbias) to the gate region 132 of the sense TFT 130. The second ESD conduction path 22 is arranged to permit current to flow, from the source of the bias voltage ( bias) to the gate region 132 of the sense TFT 130, in the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 is below a lower threshold value. The lower threshold voltage value corresponds to a voltage at the gate region 152 of the bias TFT 150. In the event that the voltage (Vgate) at the gate region 132 of the sense TFT 130 drops below the lower threshold value (e.g. which corresponds to the voltage at the gate region 152 of the bias TFT 150), the conductive channel through the bias TFT 150 will become electrically conductive to permit current to flow therethrough from the source of the bias voltage (Vbias) to the gate region 132 of the sense TFT 130 (e.g. because the voltage at the gate-source voltage for the bias TFT 150 is positive). In turn, the current will flow from Vbias to the gate region 132 of the sense TFT 130 to increase the voltage (Vgate) at the gate region 132 of the sense TFT 130. Current will continue to flow until the voltage Vgate) at the gate region 132 of the sense TFT 130 is at or above its upper threshold value, e.g. until the gate-source voltage for the bias TFT 150 is insufficient to render the conductive channel therethrough electrically conductive.

[0073] In other words, the ESD protection circuitry is configured to retain the voltage Vgate) of the gate region 132 of the sense TFT 130 within a threshold voltage range. The threshold voltage range is from a lower voltage which is based on the gate voltage for the bias TFT 150 and an upper voltage which is based on the reference voltage (Vref). The apparatus is arranged so that, should the voltage (Vgate) of the gate region 132 of the sense TFT 130 exceed the upper threshold voltage, the protection TFT 180 will become electrically conductive, and should Vgate drop below the lower threshold voltage, the bias TFT 150 will become electrically conductive. As will be appreciated in the context of the present disclosure, the upper and lower threshold voltages may not be exactly the voltages which are they are described as “corresponding to” above. The precise value for the upper / lower threshold voltages may also take into account additional resistances in the circuitry, as well as any additional voltage required to switch ‘on’ the respective TFTs for conducting current accordingly.

[0074] As such, the reference voltage (Vref) and the bias voltage (Vbias) may provide the first and second protection voltages, respectively.

[0075] The reference voltage is selectively connectable to the sense TFT 130 (to its conductive channel) via the select TFT 140. The bias voltage is selectively connectable to the sense TFT 130 (to its gate region 132) via the bias TFT 150. These two voltages (Vref and Vbias) also provide additional functionality for the pixel 100, as do their selective connections to the sense TFT 130. As described in more detail below, the bias TFT 150 and Vbias are used for biasing the pixel 100, and the select TFT 140 and Vref are used for selectively activating the pixel 100. Thus, these components which are used to provide ESD protection functionality are also used to provide additional active pixel functionality.

[0076] The bias voltage (Vbias) and the bias TFT 150 are configured to preset the voltage (Vgate) at the gate region 132 of the sense TFT 130 to a selected value. For this, the gate region 152 of the bias TFT 150 is connected to a controllable voltage source. The voltage source may selectively activate the bias TFT 150. For example, by driving the gate region 152 of the bias TFT 150 to a chosen voltage which is higher than Vgate, the bias TFT 150 will become electrically conductive, thereby to permit current to flow from the source of bias voltage (Vb / as) to the gate region 132 of the sense TFT 130. In turn, this current flow from Vbias will cause Vgate to be pre-charged to a set value. That value will be determined based on the voltage at the gate region 152 of bias TFT 150. The sensor may be configured to selectively control (e.g. vary) the bias TFT 150 gate voltage, thereby to selectively control Vgate for the sense TFT 130.

[0077] The gate region 152 of the bias TFT 150 may be connected to a gate line for another row of pixels in the sensor array, such as the gate line 101 for the preceding row of pixels. As such, when said gate line 101 is activated (e.g. when a voltage is applied to that gate line 101 to activate one or more pixels connected to that gate line 101 to output a read-out signal) a voltage will also be applied to the gate region 152 of the bias TFT 150. As such, the sensor is configured to pre-charge the sense TFT 130 of the pixel 100 to its selected voltage while another row of pixels are being activated. Then, after the pre-charge has finished (and the other row of pixels have output their read-out signals), the pixel 100 may subsequently be activated, and the starting voltage for Vgate will be a known value, thereby improving the sensitivity and reliability for any read-out signals output from the pixel 100.

[0078] In other words, the pixel 100 is arranged so that current may flow through the bias TFT 150 from Vbias to the gate region 132 of the sense TFT 130 in response to either: the gate region 152 of the bias TFT 150 being activated to pre-charge the gate region 132 of the sense TFT 130, or an ESD event occurring in which the voltage Vgate) at the gate region 132 of the sense TFT 130 drops below its lower threshold value. As will be appreciated, the configuration of the bias TFT 150 and Vbias is such that ESD protection may be provided when the bias TFT 150 is activated for pre-charge or when it is not activated (e.g. as in either scenario, the gate-source voltage across the bias TFT 150 may be sufficiently high to render the conductive channel of that TFT electrically conductive).

[0079] The select TFT 140 is arranged to selectively connect the conductive channel of the sense TFT 130 to Vref. The conductive channel of the select TFT 140 separates the conductive channel of the sense TFT 130 from Vref. The select TFT 140 is configured to selectively inhibit the sense TFT 130 from outputting a read-out signal to the read-out line 104. For example, in case Vgate was sufficiently elevated relative to the source voltage for the sense TFT 130 (Vread-out) even while the pixel 100 was inactive, the drain region of the sense TFT 130 would not be connected to Vrefdue to the select TFT 140 being non-conductive. In turn, this prevents the sense TFT 130 from outputting unwanted signals.

[0080] The gate region 142 of the select TFT 140 is connected to the gate line 102 for the pixel 100 so that, in response to the pixel 100 being activated and thus the gate line 102 for that pixel 100 being driven to an activating voltage, the select TFT 140 will become electrically conductive, thereby to connect the conductive channel of the sense TFT 130 to Vref (e.g. so that the sense TFT 130 may output a read-out signal to the read-out line 104).

[0081] In other words, the select TFT 140 provides a selective connection between the reference voltage (Vref) and the conductive channel of the sense TFT 130. The reference voltage (Vref) may therefore be used when outputting a read-out signal from the sense TFT 130. Additionally, the reference voltage (Vref) may also be used as the first protection voltage, e.g. so that current flows from the gate region 132 of the sense TFT 130 to Vref in the event of an ESD event occurring.

[0082] The sensor may be configured to pre-charge the gate region 132 of the sense TFT 130 to a voltage which is below Vref. For example, the pre-charge voltage may be selected so that, in response to the pixel 100 being activated and an effective capacitive measurement obtained using the capacitive sensing electrode 110, a maximum expected value for Vgate will still be below Vref. Also, the pre-charge voltage may be selected so that the maximum expected value for Vgate is within a threshold amount of Vread-out to inhibit a gate-source voltage across the sense TFT 130 exceeding a threshold amount.

[0083] The ESD protection circuitry is configured to provide ESD protection for the sense TFT 130 irrespective of whether the pixel 100 is activated or not.

[0084] In operation, prior to obtaining a read-out signal from the pixel 100, the pixel 100 will first be pre-charged. For this, while a gate drive signal is applied to another gate line in the array (e.g. the preceding gate line 101), this gate drive signal is also applied to the gate region 152 of the bias TFT 150. This activates the bias TFT 150 and renders its conductive channel electrically conductive. Current may therefore flow between Vbias and the gate region 132 of the sense TFT 130 to pre-charge the sense TFT 130 to a selected value for Vgate. Subsequently, the gate drive signal will no longer be applied to the gate line connected to the gate region 152 of the bias TFT 150 and the bias TFT 150 will no longer be electrically conductive.

[0085] A read-out signal is then obtained from the pre-charged pixel 100. For this, a gate drive signal is applied to the gate line 102, and thus to the first plate of the reference capacitor 120 and the gate region 142 of the select TFT 140. By applying the gate drive signal to the select TFT 140, the conductive channel of the select TFT 140 will become electrically conductive, thereby to electrically connect Vref to the conductive channel of the sense TFT 130. As the drain region of the sense TFT 130 is thus connected to receive current, the sense TFT 130 may output a read-out signal.

[0086] The voltage (Vgate) applied to the gate region 132 of the sense TFT 130 will depend on the gate drive voltage and the proximity of the conductive object to be sensed to the capacitive sensing electrode 110, as well as the pre-charge value for Vgate. The source voltage of the sense TFT 130 will correspond to a voltage (Vread-out) of the read-out line 104. A gate-source voltage across the sense TFT 130 will therefore vary in dependence on the effective capacitance of the capacitive sensing electrode 110 (i.e. of the proximity of the conductive object to the capacitive sensing electrode 110). A magnitude of the read-out current output from the sense TFT 130 will therefore provide an indication of the proximity of this conductive object to the capacitive sensing electrode 110.

[0087] At any stage during operation of the sensor, the ESD protection circuitry will provide ESD protection for the sensor pixel 100. At any point in time, the sensor may be subject to voltages which are outside the selected voltage range for that pixel 100.

[0088] In the first (‘high’) mode, the pixel 100 receives a large positive voltage. In which case, as the voltage Vgate) at the gate region 132 of the sense TFT 130 exceeds the upper threshold amount, the first ESD conduction path 12 will become electrically conductive, thereby to connect the gate region 132 of the sense TFT 130 to Vref. As already explained, by the voltage Vgate) at the gate region 132 of the sense TFT 130 exceeding the upper threshold value, the protection TFT 180 (in the first ESD conduction path 12) will become electrically conductive (e.g. due to its gate voltage exceeding its source voltage - Vref), thereby to allow current to flow from the gate region 132 of the sense TFT 130 to Vref. In turn, this will permit the voltage (Vgate) at the gate region 132 of the sense TFT 130 to be reduced to a value at or below the upper threshold. At which point, the protection TFT 180 may no longer be electrically conductive, as the voltage (Vgate) at the gate region 132 of the sense TFT 130 will be below the upper threshold voltage.

[0089] In the second (‘low’) mode, the pixel 100 will receive a large negative voltage. In which case, as the voltage (Vgate) will be below the lower threshold amount, the second ESD conduction path 22 will become electrically conductive, thereby to connect Vbias to the gate region 132 of the sense TFT 130. As already explained, by the voltage (Vgate) at the gate region 132 of the sense TFT 130 dropping below the gate voltage of the bias TFT 150, the conductive channel of the bias TFT 150 (in the second ESD conduction path 22) will become electrically conductive, thereby to allow current to flow from Vbias to the gate region 132 of the sense TFT 130. In turn, this will permit the voltage Vgate) at the gate region 132 of the sense TFT 130 to be increased to a value at or above the lower threshold. At which point, the bias TFT 150 may no longer be electrically conductive, as the voltage Vgate) at the gate region 132 of the sense TFT 130 will be above the lower threshold voltage.

[0090] In either mode, the ESD protection circuitry prevents the voltage at the gate region 132 of the sense TFT 130 moving outside a selected range.

[0091] Another example pixel 100 will now be described with reference to Fig. 3.

[0092] Fig. 3 shows a portion of a capacitive sensor. One sensor pixel 100 is shown in Fig. 3.

[0093] The sensor pixel 100 of Fig. 3 includes a number of similar components to those shown in Figs. 1 and 2, and as described above. For the sake of brevity, these will not be described in detail again here. Of note, the pixel 100 of Fig. 3 differs from the pixel 100 of Fig. 2 in that it includes an additional TFT (‘Reset TFT’ 160), and the bias TFT 150 is arranged in a different manner. The remaining components of the pixel 100 of Fig. 3 operate in the same manner as already described and so will not be described again.

[0094] As already mentioned, the pixel 100 of Fig. 3 includes an additional voltage-controlled impedance, which again is in the form of a TFT. This is reset TFT 160 (with gate region 162).

[0095] The gate region 162 of the reset TFT 160 is connected to a controllable voltage source, such as the gate line for another row of pixels in the array (e.g. the preceding gate line 101). A conductive channel of the reset TFT 160 is connected between the first and second plates of the reference capacitor 120.

[0096] For the bias TFT 150, the conductive channel is connected to the gate region 132 of the sense TFT 130 (as in Fig. 2). However, for the pixel 100 of Fig. 3, the bias TFT 150 is arranged to provide a one-way conduction path from Vbias to the gate region 132 of the sense TFT 130. That is, the bias TFT 150 may be diode-connected. As shown in Fig. 3, for this, the gate and drain regions of the bias TFT 150 are connected to each (e.g. they are shorted), as well as being connected to Vbias. The source region of the bias TFT 150 is connected to the gate region 132 of the sense TFT 130.

[0097] The conductive channel of the reset TFT 160 provides a selective connection between the two plates of the reference capacitor 120. In response to the reset TFT 160 being activated (e.g. with a signal applied to its gate region 162), the conductive channel of the reset TFT 160 will be electrically conductive. In turn, this acts to short the reference capacitor 120 (e.g. to electrically connect its two plates), thereby to reset the voltage across this capacitor to zero. In other words, the reset TFT 160 is selectively operable to reset the voltage across the reference capacitor 120 to a selected value (e.g. zero). The sensor may be configured to reset the reference capacitor 120 prior to obtaining a read-out signal from that pixel 100.

[0098] The conductive channel of the bias TFT 150 provides a connection between Vbias and the gate region 132 of the sense TFT 130. The bias TFT 150 is arranged to provide a one-way conduction path for current to flow from Vbias to the gate region 132 of the sense TFT 130. For example, this current may flow in the event that the gate-source voltage across the bias TFT 150 is sufficiently high to activate the TFT. For example, if Vbias is greater than the voltage at the source region of the bias TFT 150 (e.g. Vgate for the sense TFT 130).

[0099] The ESD protection circuitry for the pixel 100 of Fig. 3 is similar to that for the pixel 100 of Fig. 2. Notably, the first ESD conduction path 12 (from the gate region 132 of the sense TFT 130 to Vref via the protective TFT) is the same as in Fig. 2.

[0100] The second ESD conduction path 22 is similar, but not identical, to that of Fig. 2. For this, the second ESD conduction path 22 is from Vbias to the gate region 132 of the sense TFT 130. As already mentioned, the bias TFT 150 provides a one-way conduction path from Vbias to the gate region 132 of the sense TFT 130, and so this acts to provide ESD protection. That is, in the event that the voltage Vgate) at the gate region 132 of the sense TFT 130 is below the lower threshold value, the bias TFT 150 will be electrically conductive to permit current to flow from Vbias to the gate region 132 of the sense TFT 130 (e.g. thereby to increase Vgate). In other words, the pixel 100 is arranged to inhibit the voltage (Vgate) at the gate region 132 of the sense TFT 130 from dropping below a threshold voltage (e.g. which corresponds to Vbias).

[0101] The bias TFT 150 also provides additional functionality to that of the second ESD conduction path 22. That is, the bias TFT 150 is configured to pre-charge the voltage (Vgate) at the gate region 132 of the sense TFT 130 to a selected and known value prior to any read-out being taken. The arrangement of the one-way conductive path for the bias TFT 150 may provide anti-kickback protection, in that Vgate will not be affected by a kickback voltage across a TFT which is being turned off, as current may continue to flow across the bias TFT 150 to ensure that Vgate is at the selected value.

[0102] As with the arrangement shown in Fig. 2, the pixel 100 is designed so that at least some of the componentry which provides the ESD protection circuitry also provides additional functionality for the pixel 100.

[0103] In operation, prior to obtaining a read-out signal, the pixel 100 will first be reset. For this, the gate region 162 of the reset TFT 160 will be activated to render the reset TFT 160 electrically conductive, thereby shorting the reference capacitor 120 so that the voltage across this is zero. After this, the reset TFT 160 will no longer be activated, and current will flow through the bias TFT 150 to pre-charge the gate region 132 of the sense TFT 130 to a selected voltage. The pixel 100 is then ready to obtain a read-out signal. Operation of this is the same as that described above in relation to Fig. 2, and so will not be described again here. Likewise, operation of the pixel 100 to provide the first ESD protection (e.g. against higher voltages) will not be described again.

[0104] For the second (‘low’) ESD protection, the bias TFT 150 provides a one-way conduction path from Vbias to the gate region 132 of the sense TFT 130. Therefore, whenever the voltage Vgate) at the gate region 132 of the sense TFT 130 gets sufficiently low (e.g. at an ESD event), the gate-source voltage across the bias TFT 150 will be sufficiently high that the bias TFT 150 will be activated, thereby rendering its conductive channel electrically conductive. In turn, current may then flow from Vbias to the gate region 132 of the sense TFT 130 to restore Vgate to a value within its threshold range.

[0105] Fig. 4 shows a plan view of a capacitive touch sensor 1000 comprising an array of sensor pixels 100. The capacitive sensing electrode 110 of each sensor pixel 100 is also shown. The sensor pixels 100 may correspond to any of the sensor pixels 100 described herein in relation to Figs. 1 to 3. For simplicity, other components of the sensor 1000 including those in each sensor pixel 100 (such as other components shown in Figs. 1 to 3) are not shown in Fig. 4 but may nonetheless be present.

[0106] The sensor 1000 contains a plurality of rows of sensor pixels 100 and a plurality of columns of sensor pixels 100. Each sensor pixel 100 may provide its own sensing area on the sensor 1000 (i.e. each sensor pixel 100 may be configured to provide sensing for a subset of the total area of the sensor 1000). The capacitive sensing electrode 110 of each sensor pixel 100 may take up a majority of the area of its sensor pixel 100 (when viewed in plan). By increasing the area covered by a capacitive sensing electrode 110, a greater amount of charge may be stored on that electrode 110. The area covered by each individual electrode 110 may also be limited so that the spatial resolution of the capacitive sensor may be sufficiently high to provide biometric sensing (e.g. for identifying contours of a user’s skin).

[0107] It is to be appreciated in the context of the present disclosure that the examples described herein and shown in the figures are not to be considered limiting. These examples are intended to show the functionality for the claimed subject-matter. It will be appreciated in the context of the present disclosure that alternative approaches for implementing the claimed subject-matter may be adopted. For instance, in the examples described herein, all voltage- controlled impedances are shown as TFTs. However, this need not be the case. For example, other types of VCIs may be employed, such as other semiconductor devices, transistors etc. Similarly, while either diodes or diode-connected transistors have been shown for providing selective connections between the gate region 132 of the sense TFT 130 and the protection voltages, it will be appreciated that other arrangements could be used. For example, any suitable arrangement which may provide the desired current flow, e.g. one-way conduction or conduction to / from the gate region 132 of the sense TFT in the event that Vgate is outside the threshold range.

[0108] Likewise, it will be appreciated in the context of the present disclosure that the example values for the selected voltage range for the select TFT 130 should not be considered limiting. For example, the ‘high’ voltage could be negative or zero (rather than positive) and / or the ‘low’ voltage could be positive (rather than negative or zero). It will be appreciated by one of skill in the art in the context of the present disclosure that the particular choice of operating voltage levels and semiconductor components may be varied to adjust these operating parameters. For example, polarity could be reversed for the relevant voltage values. As another example, one or both of the ESD conduction paths may comprise two (or more) diodes in series. For example, the inclusion of a second diode in one or both of these ESD conduction paths may inhibit leakage in normal operation. Additionally or alternatively, a channel resistance of the diodes (e.g. for TFT 180) may be selected to inhibit leakage. Irrespective of the particular values chosen, a range of permitted values for Vgate may be defined which inhibit breakdown of the sense TFT 130 due to ESD, e.g. due to gate-source voltage of the sense TFT 130 getting too large. Similarly, any of the other voltages may be chosen to be at a value which inhibits this breakdown (e.g. Vread-out or Vref) may be chosen based on an understanding of the values to be employed for Vgate. Also, it is to be appreciated that the particular choice for the connection to the first and second protection voltages should not be considered limiting. Any suitable protection voltage could be used. For example, this could be a fixed or a varying voltage. For example, the protection voltages may be chosen based on the desired operating range for the sense TFT and / or the protection voltages may be selected based on available voltage connections (e.g. lines) which already exist in the sensor (e.g. for other purposes than ESD protection).

[0109] Also, it will be appreciated that transistors may require a certain amount of gate-source voltage before they are activated (e.g. and become electrically conductive). Likewise, it is to be appreciated that there may some reduction in voltage due to electrical resistance within the circuitry. As a result, where comparisons have been mentioned between two different voltages for providing selective connections, it will be appreciated that this is not an exact comparison between the two voltages. Instead, this may take into account potential sources of voltage loss between different regions of the pixel and / or sensor. For example, where it is mentioned that current will flow from / to the gate region of the sense TFT in the event that the voltage at the gate region is above / below another value (e.g. where Vgate is greater than V+ or Vref, and / or where Vgate is less than V- or Vbias), it will be appreciated that this is not a direct comparison of these voltages. Instead, that current may flow assuming the gate-source voltage of any intervening transistors is sufficiently high to activate the conductive channel of that transistor. Likewise, it may be that there is some drop in voltage between these points arising from electrical resistances in that region.

[0110] It will be appreciated from the discussion above that the examples shown in the figures are merely exemplary, and include features which may be generalised, removed or replaced as described herein and as set out in the claims. The function of one or more of the elements shown in the drawings may be further subdivided, and / or distributed throughout apparatus of the disclosure.

[0111] As will be appreciated by the skilled reader in the context of the present disclosure, each of the examples described herein may be implemented in a variety of different ways. Any feature of any aspects of the disclosure may be combined with any of the other aspects of the disclosure. For example, method aspects may be combined with apparatus aspects, and features described with reference to the operation of particular elements of apparatus may be provided in methods which do not use those particular types of apparatus. In addition, each of the features of each of the examples is intended to be separable from the features which it is described in combination with, unless it is expressly stated that some other feature is essential to its operation. Each of these separable features may of course be combined with any of the other features of the examples in which it is described, or with any of the other features or combination of features of any of the other examples described herein. Furthermore, equivalents and modifications not described above may also be employed without departing from the invention.

[0112] Other examples and variations of the disclosure will be apparent to the skilled addressee in the context of the present disclosure.

Claims

Claims1 . A capacitive touch sensor comprising an array of pixels, each pixel comprising: a capacitive sensing electrode; a sense voltage-controlled impedance, VCI; and electrostatic discharge, ESD, protection circuitry comprising: a first ESD conduction path between a control terminal of the sense VCI and a first protection voltage; and a second ESD conduction path between a second protection voltage and the control terminal of the sense VCI.

2. The sensor of claim 1 , wherein the first ESD conduction path comprises a one-way conduction path from the control terminal of the sense VCI to the first protection voltage.

3. The sensor of claim 2, wherein the one-way conduction path comprises a transistor, optionally a transistor arranged to provide a diode.

4. The sensor of any preceding claim, wherein the ESD protection circuitry is configured to allow current to flow from the control terminal of the sense VCI to the first protection voltage in the event that a voltage at said control terminal is greater than an upper threshold voltage.

5. The sensor of claim 4, wherein the upper threshold voltage is based on the first protection voltage.

6. The sensor of any preceding claim, wherein the ESD protection circuitry is configured to allow current to flow to the control terminal of the sense VCI from the second protection voltage in the event that a voltage at said control terminal is below a lower threshold voltage.

7. The sensor of any preceding claim, wherein the sensor is configured to set a voltage at the control terminal of the sense VCI to a selected value prior to operating that sense VCI.

8. The sensor of any preceding claim, wherein the pixel comprises a bias VCI, and wherein a conductive channel of the bias VCI is connected between a bias voltage and the control terminal of the sense VCI.

9. The sensor of claim 8, wherein a control terminal of the bias VCI is connected to a gate line for one or more other pixels of the array, optionally wherein the control terminal of the biasVCI is connected to a gate line for another row of pixels in the array.

10. The sensor of claim 8 or 9, wherein the bias voltage provides the second protection voltage.

11. The sensor of claim 10, wherein the connection of the bias voltage to the control terminal of the sense VCI via the conductive channel of the bias VCI provides the second ESD conduction path.

12. The sensor of claim 10 or 11 , as dependent on claim 6, wherein the lower threshold voltage is based on a voltage of a control terminal of the bias VCI and / or the bias voltage, optionally wherein the lower threshold voltage is based on an ‘off’ voltage for a gate line connected to that control terminal.

13. The sensor of any of claims 3 to 9, wherein the second ESD conduction path comprises a one-way conduction path from the second protection voltage to the control terminal of the sense VCI.

14. The sensor of any preceding claim, wherein a conductive channel of the sense VCI is selectively connectable to a reference voltage.

15. The sensor of claim 14, wherein the reference voltage provides the first protection voltage.

16. The sensor of any preceding claim 14 or 15, wherein the pixel comprises a select VCI, and wherein a conductive channel of the select VCI is connected between the conductive channel of the sense VCI and the reference voltage.

17. The sensor of claim 16, wherein a control terminal of the select VCI is connected to a gate line for that pixel.

18. The sensor of any preceding claim, wherein the pixel comprises a reference capacitor.

19. The sensor of claim 18, wherein a first plate of the reference capacitor is connected to a gate line for said pixel.

20. The sensor of claim 18 or 19, wherein a second plate of the reference capacitor isconnected to the control terminal of the sense VCI and the capacitive sensing electrode.21 . The sensor of any preceding claim, wherein the conductive channel of the sense VCI is connected to a read-out line for the pixel.

22. The sensor of claim 21 , wherein the first protection voltage is selected based on a voltage of the read-out line for the pixel.

23. The sensor of any preceding claim, wherein the first protection voltage is positive, and / or the second protection voltage is zero or negative.

24. A capacitive touch sensor comprising an array of pixels, each pixel comprising: a capacitive sensing electrode; a sense voltage-controlled impedance, VCI; and electrostatic discharge, ESD, protection circuitry comprising an ESD conduction path between a control terminal of the sense VCI and a high voltage source.

25. A method of controlling operation of a capacitive touch sensor, wherein the touch sensor comprises an array of pixels, each pixel comprising: (i) a capacitive sensing electrode, and (ii) a sense voltage-controlled impedance, VCI, and wherein the method comprises: connecting a control terminal of the sense VCI to a first protection voltage to provide electrostatic discharge, ESD, protection for the sense VCI; and connecting the control terminal of the sense VCI to a second protection voltage to provide ESD protection for the sense VCI.

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