Laminated ceramic capacitor and method for manufacturing same

Abstract

The present invention comprises: preparing an intermediate laminate (10r); pressing the intermediate laminate (10r) in the lamination direction; irradiating the pressed intermediate laminate (10r) with laser light from one side in the lamination direction to form a plurality of through-holes (Vh) in the intermediate laminate (10r); filling each of the plurality of through-holes (Vh) with a conductive paste to form a plurality of unfired via conductors; forming an unfired laminate by laminating a ceramic green sheet, which is the remainder of a second outer layer part, on an intermediate surface (M) positioned on the other side in the lamination direction in the intermediate laminate (10r) on which the plurality of unfired via conductors are formed; pressing the unfired laminate in the lamination direction; and firing the unfired laminate. In the pressed intermediate laminate (10r), a first shortest distance (T1) from a first conductive pattern (130r) positioned closest to a first main surface (101) positioned on one side in the lamination direction in the intermediate laminate (10r) among a plurality of conductive patterns to the first main surface (101) is longer than a second shortest distance (T2) from a second conductive pattern (120r) positioned closest to the intermediate surface (M) among the plurality of conductive patterns to the intermediate surface (M), and a dimension of the second shortest distance (T2) is 2-6 μm.

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

[0002] Japanese Patent Laid-Open Publication No. 2021-48261 (Patent Document 1) is a prior art document disclosing a multilayer capacitor. The multilayer capacitor described in Patent Document 1 includes a laminate, a plurality of first external electrodes, a plurality of second external electrodes, a plurality of first via conductors, and a plurality of second via conductors. In the laminate, a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked. The plurality of first external electrodes and the plurality of second external electrodes are formed on the outer surface of the laminate. The plurality of first via conductors electrically connect the first external electrode and the plurality of first internal electrodes. The plurality of second via conductors electrically connect the second external electrode and the plurality of second internal electrodes. A through hole is formed in the second internal electrode, and the first via conductor passes through the through hole while being insulated from the second internal electrode. A through hole is formed in the first internal electrode, and the second via conductor passes through the through hole while being insulated from the first internal electrode.

[0003] In the method for manufacturing a multilayer capacitor described in Patent Document 1, a laser beam is irradiated onto an unsintered green sheet laminate to form through holes into which a conductive paste that becomes the first via conductor and the second via conductor is filled.

[0004] Japanese Patent Application Laid-Open No. 2021-48261

[0005] When the through holes to be filled with conductive paste that will become the first and second via conductors are tapered, the first and second via conductors also have tapered shapes.

[0006] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a multilayer ceramic capacitor and a manufacturing method thereof that can prevent the first via conductor and the second via conductor from becoming tapered.

[0007] A method for manufacturing a multilayer ceramic capacitor according to the present invention includes preparing an intermediate laminate comprising a plurality of ceramic green sheets, each of which is coated with a conductive paste to form a plurality of conductive patterns and which will become inner layer portions, and a plurality of ceramic green sheets which will become part of a first outer layer portion and a second outer layer portion; pressing the intermediate laminate in a stacking direction; irradiating the pressed intermediate laminate with laser light from one side of the stacking direction to form a plurality of through holes in the intermediate laminate; filling each of the plurality of through holes with conductive paste to form a plurality of unsintered via conductors; stacking a ceramic green sheet which will become the remainder of the second outer layer portion on an intermediate surface located on the other side of the stacking direction of the intermediate laminate on which the plurality of unsintered via conductors have been formed, to form an unsintered laminate; pressing the unsintered laminate in the stacking direction; and firing the unsintered laminate. In the pressed intermediate laminate, a first shortest distance from a first conductive pattern, which is located closest to a first main surface located on one side of the stacking direction in the intermediate laminate, to the first main surface is longer than a second shortest distance from a second conductive pattern, which is located closest to the intermediate surface, to the intermediate surface, among the plurality of conductive patterns, and the dimension of the second shortest distance is 2 μm or more and 6 μm or less.

[0008] According to the present invention, it is possible to prevent the first via conductor and the second via conductor from becoming tapered.

[0009] 1 is a plan view of a multilayer ceramic capacitor according to an embodiment of the present invention, as seen from the first main surface side; FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, as seen from the direction of the arrows along line II-II; FIG. 3 is a flowchart showing a manufacturing method of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 4 is a cross-sectional view showing a state in which a pressed intermediate laminate is irradiated with laser light to form through holes; FIG. 5 is a cross-sectional view showing an intermediate laminate according to Comparative Example 1, in which through holes for via conductors are formed by setting the side of the unsintered outer layer portion with a thinner minimum thickness as the laser light incident side and setting the minimum thickness dimension of the unsintered outer layer portion on the emission side to be greater than 6 μm; FIG. 6 is a cross-sectional view showing an intermediate laminate according to Comparative Example 2, in which through holes for via conductors are formed by setting the side of the unsintered outer layer portion with a thicker minimum thickness as the laser light incident side and setting the minimum thickness dimension of the unsintered outer layer portion on the emission side to be greater than 6 μm; FIG. 7 is an enlarged image of the periphery of a first via conductor in the cross section of a multilayer ceramic capacitor according to an example; FIG. 8 is an enlarged image of the periphery of a first via conductor in the cross section of a multilayer ceramic capacitor according to a first example of Comparative Example 1; 1 is an enlarged image of the periphery of a second via conductor on a first main surface of a multilayer ceramic capacitor according to a first example of Comparative Example 1. 2 is an enlarged image of the periphery of a first via conductor in a cross section of a multilayer ceramic capacitor according to a second example of Comparative Example 1. 3 is an enlarged image of the periphery of a first via conductor on a first main surface of a multilayer ceramic capacitor according to a second example of Comparative Example 1.

[0010] A multilayer ceramic capacitor and a method for manufacturing the same according to an embodiment of the present invention will now be described with reference to the drawings. In the following description of the embodiment, the same or corresponding parts in the drawings will be designated by the same reference numerals, and description thereof will not be repeated.

[0011] Fig. 1 is a plan view of a multilayer ceramic capacitor according to an embodiment of the present invention, seen from a first main surface side, and Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, seen from the direction of the arrows along line II-II.

[0012] As shown in FIGS. 1 and 2, a multilayer ceramic capacitor 100 according to one embodiment of the present invention includes a laminate 10, a plurality of first via conductors 140, and a plurality of second via conductors 150.

[0013] As shown in Figure 2, the laminate 10 includes a plurality of first internal electrode layers 120 and a plurality of second internal electrode layers 130 stacked alternately in the stacking direction with dielectric layers 110 sandwiched between them, and has a first main surface 101 and a second main surface 102 located on the opposite side of the first main surface 101 in the stacking direction.

[0014] The dielectric layer 110 may be made of any material, such as a ceramic material containing BaTiO, CaTiO, SrTiO, SrZrO, or CaZrO as a main component. A minor component selected from the group consisting of a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to the main component in a smaller amount than the main component.

[0015] The laminate 10 may have any shape. In this embodiment, the laminate 10 has a rectangular parallelepiped shape as a whole. A rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of a rectangular parallelepiped are rounded, but has six surfaces and can be considered as a rectangular parallelepiped as a whole. Therefore, the laminate 10 has a first main surface 101, a second main surface 102, a first side surface 103, a second side surface 104, a third side surface 105, and a fourth side surface 106.

[0016] The first side surface 103 to the fourth side surface 106 of the laminate 10 constitute four side surfaces of the surface of the laminate 10 other than the first main surface 101 and the second main surface 102. That is, the laminate 10 further has the first side surface 103 to the fourth side surface 106, which are four side surfaces connecting the first main surface 101 and the second main surface 102. The first side surface 103 faces the second side surface 104, and the third side surface 105 faces the fourth side surface 106. In this embodiment, the first side surface 103 to the fourth side surface 106 of the laminate 10 are orthogonal to the first main surface 101 and the second main surface 102, respectively, but they do not have to be orthogonal.

[0017] The dimensions of the laminate 10 are arbitrary, but for example, when viewed from the first main surface 101 side, the vertical dimension of the rectangle can be 0.3 mm to 3.0 mm, the horizontal dimension can be 0.3 mm to 3.0 mm, and the dimensions in the stacking direction of the dielectric layers 110, the first internal electrode layers 120 and the second internal electrode layers 130 can be 50 μm to 200 μm. The dimension of the laminate 10 in the stacking direction refers to the maximum thickness of the laminate 10.

[0018] Each of the plurality of first internal electrode layers 120 and the plurality of second internal electrode layers 130 has a rectangular outer shape. As shown in Fig. 2, each of the plurality of first internal electrode layers 120 has a plurality of first through holes 120h formed therein for inserting a plurality of second via conductors 150 therethrough. Each of the plurality of second internal electrode layers 130 has a plurality of second through holes 130h formed therein for inserting a plurality of first via conductors 140 therethrough.

[0019] The material of the first internal electrode layer 120 and the second internal electrode layer 130 is arbitrary, and for example, contains a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals, as a main component. The first internal electrode layer 120 and the second internal electrode layer 130 may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 110. In that case, the ratio of the common material contained in the first internal electrode layer 120 and the second internal electrode layer 130 is, for example, 20 vol % or less.

[0020] The thickness of each of the first internal electrode layers 120 and the second internal electrode layers 130 is arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode layers 120 and the second internal electrode layers 130 is arbitrary, but can be, for example, about 10 layers or more and 150 layers or less in total.

[0021] As shown in Fig. 2, the laminate 10 includes an inner layer portion E, a first outer layer portion 111, and a second outer layer portion 112. In the inner layer portion E, opposing portions of the first internal electrode layer 120 and the second internal electrode layer 130 are stacked in the stacking direction. The first outer layer portion 111 is adjacent to the inner layer portion E in the stacking direction and constitutes the first main surface 101. The second outer layer portion 112 is adjacent to the inner layer portion E in the stacking direction and constitutes the second main surface 102. Each of the first outer layer portion 111 and the second outer layer portion 112 is composed of a dielectric layer 110.

[0022] The plurality of first via conductors 140 are provided inside the laminate 10 and are electrically connected to the plurality of first internal electrode layers 120. The plurality of first via conductors 140 are inserted through second through holes 130h formed in each of the plurality of second internal electrode layers 130 and are insulated from the plurality of second internal electrode layers 130. As shown in Fig. 1 , in this embodiment, the plurality of first via conductors 140 are arranged in a zigzag pattern along the sides of the first main surface 101 when viewed from the stacking direction. The first internal electrode layer 120 is electrically connected to four first via conductors 140 arranged in two rows.

[0023] The plurality of second via conductors 150 are provided inside the laminate 10 and are electrically connected to the plurality of second internal electrode layers 130. The plurality of second via conductors 150 are inserted through first through holes 120h formed in each of the plurality of first internal electrode layers 120 and are insulated from the plurality of first internal electrode layers 120. In this embodiment, the plurality of second via conductors 150 are arranged in a zigzag pattern along the sides of the first main surface 101 when viewed from the stacking direction. The first via conductors 140 and the second via conductors 150 are arranged side by side in a matrix. The second internal electrode layer 130 is electrically connected to five second via conductors 150. In this embodiment, the total number of the first via conductors 140 and the second via conductors 150 is nine, but this total is not limited to nine.

[0024] Each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is provided inside the laminate 10 in a manner extending in the stacking direction from the first main surface 101 to the second main surface 102 of the laminate 10. In other words, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed on the first main surface 101 of the laminate 10, but is not exposed on the second main surface 102.

[0025] Specifically, a first end face T on the first main surface 101 side of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed to the first main surface 101. A second end face B on the second main surface 102 side of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is covered by the second outer layer portion 112. This makes it possible to prevent a short circuit from occurring between the multilayer ceramic capacitor 100 and an electronic component arranged on the second main surface 102 side.

[0026] By arranging the plurality of first via conductors 140 and the plurality of second via conductors 150 alternately in a zigzag pattern as described above, magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 100. Note that the arrangement of the first via conductors 140 and the second via conductors 150 is not limited to the arrangement described above.

[0027] The first via conductor 140 and the second via conductor 150 are substantially cylindrical in shape. The maximum diameter of each of the first via conductor 140 and the second via conductor 150 is, for example, 20 μm or more and 70 μm or less. The pitch between adjacent first via conductors 140 and second via conductors 150, more specifically, the distance between the centers of the first via conductors 140 and second via conductors 150, is, for example, approximately 50 μm or more and 500 μm or less.

[0028] 2 , the ratio of the maximum diameter Dt of the first end face T to the maximum diameter Db of the second end face B of each of the first via conductors 140 and the second via conductors 150 is 0.95 or more and 1.1 or less. That is, each of the first via conductors 140 and the second via conductors 150 satisfies the relationship 0.95≦Dt / Db≦1.1.

[0029] The material of the first via conductor 140 and the second via conductor 150 is arbitrary, and for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals, can be used.

[0030] A plurality of external electrodes connected to the first via conductors 140 and the second via conductors 150 may be formed on the first main surface 101. The material of the external electrodes is arbitrary. For example, the external electrodes are plated electrodes formed by a plating process using a rotary plating method. Examples of materials that constitute the plated electrodes include Cu, Ni, and Sn. The plated electrodes may be composed of a single layer or multiple layers. The external electrodes may be formed by firing a metal paste applied to the first main surface 101. The metal paste may contain a glassy inorganic material as a co-material.

[0031] Here, a method for manufacturing the multilayer ceramic capacitor 100 according to one embodiment of the present invention will be described.

[0032] 3 is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention. As shown in FIG. 3, first, an intermediate laminate is prepared (S1) in which a plurality of ceramic green sheets, each of which is coated with a conductive paste and has a plurality of conductive patterns formed thereon, that will become inner layer portions E, and a plurality of ceramic green sheets that will become parts of first outer layer portions 111 and second outer layer portions 112 are laminated together.

[0033] Specifically, a conductive paste that will become the first internal electrode layer 120 and the second internal electrode layer 130 is applied by screen printing or the like to the ceramic green sheets that will become the internal layer portion E, thereby forming a conductive pattern. The ceramic green sheets that will become part of the first external layer portion 111 and the second external layer portion 112 are not coated with the conductive paste.

[0034] Next, the intermediate laminate is pressed from both sides in the stacking direction (S2). In this embodiment, the intermediate laminate is pressed from both sides in the stacking direction with a resin film such as a PET (polyethylene terephthalate) film disposed on both a first main surface located on one side in the stacking direction of the intermediate laminate and an intermediate surface located on the other side in the stacking direction of the intermediate laminate.

[0035] 4 is a cross-sectional view showing a state in which through-holes are formed in the pressed intermediate laminate by irradiating the intermediate laminate with laser light, in which the PET film is not shown.

[0036] 4 , in the pressed intermediate laminate 10r, a first shortest distance T1 from a first conductive pattern 130r, which is located closest to the first main surface 101 located on one side of the stacking direction of the intermediate laminate 10r, among the plurality of conductive patterns, to the first main surface 101 is longer than a second shortest distance T2 from a second conductive pattern 120r, which is located closest to the intermediate surface M, among the plurality of conductive patterns, to the intermediate surface M, and the dimension of the second shortest distance T2 is 2 μm or more and 6 μm or less. In this embodiment, the dimension of the first shortest distance T1 is 8 μm or more and 12 μm or less.

[0037] That is, the minimum thickness dimension of the unsintered first outer layer portion 111r composed of the unsintered dielectric layer 110r is 8 μm or more and 12 μm or less, and the minimum thickness dimension of the part 112r of the unsintered second outer layer portion composed of the unsintered dielectric layer 110r is 2 μm or more and 6 μm or less.

[0038] 3 and 4, the pressed intermediate laminate 10r is irradiated with laser light from one side in the lamination direction by a laser light irradiation device 1 to form via conductor through holes Vh at positions in the intermediate laminate 10r where the first via conductors 140 and the second via conductors 150 are to be formed (S3). That is, in this embodiment, in the intermediate laminate 10r, the side with the thickest minimum thickness of the unsintered outer layer portion is the incident side of the laser light, and the dimension of the minimum thickness of the unsintered outer layer portion on the output side is 2 μm to 6 μm.

[0039] Figure 5 is a cross-sectional view showing an intermediate laminate of Comparative Example 1, in which the side with the thinner minimum thickness of the unsintered outer layer portion is the incident side of the laser light, and the dimension of the minimum thickness of the unsintered outer layer portion on the output side is larger than 6 μm to form a through hole for a via conductor.

[0040] Since a conductive pattern primarily composed of metal has a higher thermal conductivity than an unsintered dielectric layer 110r primarily composed of ceramic material, the heat generated by laser light irradiation spreads more easily, and the area removed by laser ablation (opening area) is larger for the conductive pattern than for the unsintered dielectric layer 110r.

[0041] Furthermore, when the minimum thickness dimension of the unsintered dielectric layer 110r located on the exit side, where the energy amount of the laser light is relatively small compared to the entrance side, where the energy amount of the laser light is relatively large, becomes larger than 6 μm due to the difference in focal depth, the through hole formed in the unsintered dielectric layer 110r located on the exit side begins to become tapered.

[0042] Therefore, as shown in Figure 5, in the intermediate laminate 10r of Comparative Example 1, in which the via conductor through hole Vh is formed with the intermediate surface M side, which is the side with the thinner minimum thickness of the unsintered outer layer portion, as the incident side of the laser light, the maximum diameter D2 of the via conductor through hole Vh at the intermediate surface M is larger than in this embodiment, and the via conductor through hole Vh in the portion formed in the unsintered first outer layer portion 111r becomes tapered.

[0043] Figure 6 is a cross-sectional view showing an intermediate laminate of Comparative Example 2, in which the side with the thicker minimum thickness of the unsintered outer layer portion is the incident side of the laser light, and the dimension of the minimum thickness of the unsintered outer layer portion on the output side is made larger than 6 μm to form a through hole for a via conductor.

[0044] As shown in FIG. 6, when the minimum thickness of the portion 112r of the unsintered second outer layer portion on the emission side is greater than 6 μm, the through holes Vh for via conductors formed in the portion 112r of the unsintered second outer layer portion are tapered.

[0045] In this embodiment, the minimum thickness dimension of the unfired first outer layer portion 111r located on the incident side where the energy amount of the laser light is relatively large is made larger than the minimum thickness dimension of the portion 112r of the unfired second outer layer portion located on the exit side where the energy amount of the laser light is relatively small, and the minimum thickness dimension of the portion 112r of the unfired second outer layer portion is made 2 μm or more and 6 μm or less.This prevents the maximum diameter D1 of the via conductor through hole Vh on the first main surface 101 from becoming too large, and prevents the via conductor through hole Vh in the portion formed in the portion 112r of the unfired second outer layer portion from becoming tapered due to the short distance from the conductive pattern on the exit side to the intermediate plane M.

[0046] As a result, the ratio of the maximum diameter D1 of the through hole Vh for a via conductor at the first main surface 101 to the maximum diameter D2 of the through hole Vh for a via conductor at the midplane M can be set to 0.95 or more and 1.1 or less. In other words, it is possible to prevent the through hole Vh for a via conductor from becoming tapered.

[0047] As shown in FIG. 3, the through holes for via conductors are filled with a conductive paste that will become first via conductors 140 and second via conductors 150, thereby forming unfired via conductors (S4).

[0048] Next, a ceramic green sheet that will become the remainder of the second outer layer portion 112 is laminated on the intermediate surface M of the intermediate laminate 10r to form an unsintered laminate (S5). This blocks one end of the via conductor through hole Vh on the second main surface 102 side. At this time, the conductive paste that will become the first via conductors 140 and the second via conductors 150 and the ceramic green sheet that will become the remainder of the second outer layer portion 112 may be in contact with each other or may be spaced apart from each other.

[0049] Next, the unfired laminate is pressed from both sides in the stacking direction (S6). In this embodiment, the unfired laminate is pressed from both sides in the stacking direction with a resin film such as a PET film disposed on both a first main surface located on one side in the stacking direction of the unfired laminate and a second main surface located on the other side in the stacking direction of the unfired laminate.

[0050] Next, the green laminate is fired (S7), which sinters both the dielectric material contained in the ceramic green sheets and the conductive material contained in the conductive paste.

[0051] The multilayer ceramic capacitor 100 is manufactured by the above manufacturing method. In the multilayer ceramic capacitor 100, the difference between the minimum thickness of the first outer layer portion 111 and the minimum thickness of the second outer layer portion 112 is preferably 2 μm or less. When external electrodes are formed, a conductive paste that will become the external electrodes may be applied before firing, or the external electrodes may be formed by plating after firing.

[0052] 2 , in the multilayer ceramic capacitor 100 according to this embodiment, the ratio of the maximum diameter Dt of the first end face T to the maximum diameter Db of the second end face B in each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is 0.95 or more and 1.1 or less. That is, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 satisfies the relationship 0.95≦Dt / Db≦1.1.

[0053] This prevents the first via conductors 140 and the second via conductors 150 from becoming tapered, thereby preventing cracks from occurring in the dielectric layer 110 around the first via conductors 140 and the second via conductors 150. This in turn improves the mechanical durability and moisture resistance reliability of the first outer layer portion 111 and the second outer layer portion 112. Furthermore, since the diameter of the via conductor through hole Vh can be set small, the area of ​​the opposing portions of the first internal electrode layer 120 and the second internal electrode layer 130 facing each other can be increased, thereby increasing the capacitance of the multilayer ceramic capacitor 100.

[0054] Hereinafter, multilayer ceramic capacitors according to an example, a first example of comparative example 1, and a second example of comparative example 1 will be described. The multilayer ceramic capacitors according to the examples were manufactured by the method for manufacturing the multilayer ceramic capacitor 100 according to the present embodiment, as described above with reference to FIGS. 3 and 4. The method for manufacturing the multilayer ceramic capacitor according to the first example of comparative example 1 differs from the method for manufacturing the multilayer ceramic capacitor according to the examples only in the respect that has been described above with reference to FIG. 5. The method for manufacturing the multilayer ceramic capacitor according to the second example of comparative example 1 differs from the method for manufacturing the multilayer ceramic capacitor according to the first example of comparative example 1 only in that the incident output of the laser light from the laser light irradiation device 1 is large.

[0055] Fig. 7 is an enlarged image of the periphery of a first via conductor in a cross section of a multilayer ceramic capacitor according to an example. Fig. 8 is an enlarged image of the periphery of a first via conductor on a first main surface of a multilayer ceramic capacitor according to an example. The enlarged images shown in Fig. 7 and subsequent figures were taken using a digital microscope (VHX-8000) manufactured by Keyence Corporation.

[0056] 7, in this example, Dt / Db=0.996, which satisfies the relationship 0.95≦Dt / Db≦1.1. As shown in FIG. 8, in this example, no cracks were observed in dielectric layer 110 of first outer layer portion 111 around first via conductor 140.

[0057] Fig. 9 is an enlarged image of the periphery of the second via conductor in the cross section of the multilayer ceramic capacitor according to the first example of Comparative Example 1. Fig. 10 is an enlarged image of the periphery of the second via conductor on the first main surface of the multilayer ceramic capacitor according to the first example of Comparative Example 1.

[0058] 9, in the first example of Comparative Example 1, Dt / Db=0.733, which does not satisfy the relationship 0.95≦Dt / Db≦1.1. As shown in FIG. 10, in the first example of Comparative Example 1, cracks C were observed in dielectric layer 110 of first outer layer portion 111 around second via conductor 150.

[0059] Fig. 11 is an enlarged image of the periphery of a first via conductor in a cross section of the multilayer ceramic capacitor according to the second example of Comparative Example 1. Fig. 12 is an enlarged image of the periphery of the first via conductor on the first main surface of the multilayer ceramic capacitor according to the second example of Comparative Example 1.

[0060] 11, in the second example of Comparative Example 1, Dt / Db=0.506, which does not satisfy the relationship 0.95≦Dt / Db≦1.1. As shown in FIG. 12, in the second example of Comparative Example 1, many cracks C were observed in dielectric layer 110 of first outer layer portion 111 around first via conductor 140.

[0061] From the above results, it was confirmed that the multilayer ceramic capacitor of this embodiment and the examples prevents the first via conductor 140 and the second via conductor 150 from becoming tapered, thereby preventing cracks from occurring in the dielectric layer 110 around the first via conductor 140 and the second via conductor 150.

[0062] In the above-described embodiments and examples, configurations that can be combined may be combined with each other.

[0063] The embodiments and examples disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0064] 1 Laser light irradiation device, 10 Laminate, 10r Intermediate laminate, 100 Multilayer ceramic capacitor, 101 First main surface, 102 Second main surface, 103 First side surface, 104 Second side surface, 105 Third side surface, 106 Fourth side surface, 110 Dielectric layer, 110r Unfired dielectric layer, 111, 111r First outer layer portion, 112 Second outer layer portion, 112r Part of unfired second outer layer portion, 120 First internal electrode layer, 120h First through hole, 120r Second conductive pattern, 130 Second internal electrode layer, 130h Second through hole, 130r First conductive pattern, 140 First via conductor, 150 Second via conductor, B Second end surface, C Crack, D1, D2, Db, Dt Maximum diameter, E Internal layer portion, M Intermediate surface, T First end surface, T1 First shortest distance, T2 Second shortest distance, Vh Through hole for via conductor.

Claims

1. A method for manufacturing an unfired laminate, comprising: preparing an intermediate laminate comprising a plurality of ceramic green sheets, each of which is coated with a conductive paste and has a plurality of conductive patterns formed thereon, and a plurality of ceramic green sheets, each of which is to form an inner layer portion, stacked together; pressing the intermediate laminate in a stacking direction; irradiating the pressed intermediate laminate with a laser beam from one side of the stacking direction to form a plurality of through holes in the intermediate laminate; filling each of the plurality of through holes with conductive paste to form a plurality of unfired via conductors; stacking a ceramic green sheet, which is to form the remainder of the second outer layer portion, on an intermediate surface, located on the other side of the stacking direction, of the intermediate laminate on which the plurality of unfired via conductors have been formed, to form an unfired laminate; pressing the unfired laminate in the stacking direction; and firing the pressed unfired laminate; a first shortest distance from a first conductive pattern, which is closest to a first main surface located on one side of the stacking direction in the intermediate laminate, to the first main surface of the pressed intermediate laminate is longer than a second shortest distance from a second conductive pattern, which is closest to the intermediate surface of the pressed intermediate laminate, to the intermediate surface, and the dimension of the second shortest distance is 2 μm or more and 6 μm or less.

2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the dimension of the first shortest distance is 8 μm or more and 12 μm or less.

3. A method for manufacturing a multilayer ceramic capacitor as set forth in claim 1 or claim 2, wherein, by firing the unsintered laminate, the plurality of unsintered via conductors become a plurality of via conductors, and the ratio of the maximum diameter of the first end face of one of the plurality of via conductors in the stacking direction to the maximum diameter of the second end face of the other of the plurality of via conductors is 0.95 or more and 1.1 or less.

4. A laminate including a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction with dielectric layers sandwiched therebetween, the laminate having a first main surface and a second main surface located on the opposite side of the first main surface in the stacking direction; a plurality of first via conductors provided inside the laminate and electrically connected to the plurality of first internal electrode layers; and a plurality of second via conductors provided inside the laminate and electrically connected to the plurality of second internal electrode layers, the laminate including an inner layer portion in which opposing portions of the first internal electrode layers and the second internal electrode layers are stacked in the stacking direction, a first outer layer portion adjacent to the inner layer portion in the stacking direction and constituting the first main surface, and a second outer layer portion adjacent to the inner layer portion in the stacking direction and constituting the second main surface, a first end face on the first main surface side of each of the plurality of first via conductors and the plurality of second via conductors is exposed to the first main surface, a multilayer ceramic capacitor, wherein a second end face on the second main surface side of each of the plurality of first via conductors and the plurality of second via conductors is covered by the second outer layer portion, and a ratio of a maximum diameter of the first end face to a maximum diameter of the second end face of each of the plurality of first via conductors and the plurality of second via conductors is 0.95 or more and 1.1 or less.

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