Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor in which the occurrence of structural defects can be suppressed.　A multilayer ceramic capacitor 1 comprises: an inner layer portion 11 including a plurality of dielectric layers 14 and a plurality of inner electrodes 15 stacked alternately; a laminate 2 having a first main surface AA and a second main surface AB relative to a stacking direction T, a first lateral surface BA and a second lateral surface BB relative to a width direction W orthogonal to the stacking direction T, and a first end surface CA and a second end surface CB relative to a length direction L orthogonal to the stacking direction T and the width direction W; a pair of external electrodes 3 respectively disposed on the end surfaces C; and an insulating member 7. The insulating member 7 is disposed on a ridgeline 5, which is the boundary line between a main surface A and a lateral surface B that are adjacent to each other.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors have been known that include a laminate in which multiple dielectric layers and internal electrodes are alternately stacked, and external electrodes provided on both end surfaces of the laminate. Multilayer ceramic capacitors have been widely used in recent years in electronic devices essential to people's lives and daily lives, such as electric vehicles, medical devices, and mobile phones. For this reason, improving and ensuring the quality of multilayer ceramic capacitors has become an urgent task. In particular, the need for multilayer ceramic capacitors that can function normally even when subjected to physical shocks has been increasing year by year.

[0003] Japanese Patent Application Laid-Open No. 2018-148117

[0004] However, conventional multilayer ceramic capacitors may have angular portions, such as portions where the main surfaces and side surfaces of the laminate intersect (so-called ridges), which poses a problem that chipping or cracking of the laminate is likely to occur at the angular portions when the multilayer ceramic capacitor is subjected to external physical impact.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of structural defects.

[0006] In order to solve the above problems, the multilayer ceramic capacitor of the present invention comprises a laminate having an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of internal electrodes, a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction, a pair of external electrodes arranged on each end surface, and an insulating member, wherein the insulating member is arranged on a ridge line that is a boundary line between the main surfaces and the side surfaces that are adjacent to each other.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of structural defects.

[0008] 1 is a schematic perspective view of a multilayer ceramic capacitor according to a first embodiment. FIG. 1 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 1 is a cross-sectional view taken along line III-III of FIG. 1. FIG. 2 is a view for explaining ridgelines, showing a WT cross section passing through the center in the longitudinal direction of the laminate. FIG. 3 is a schematic perspective view of a laminate, showing ridgelines. FIG. 4 is a schematic perspective view of a multilayer ceramic capacitor according to a second embodiment. FIG. 5 is a cross-sectional view taken along line VII-VII of FIG. 6. FIG. 7 is a schematic perspective view of a multilayer ceramic capacitor according to a third embodiment. FIG. 8 is a cross-sectional view taken along line IX-IX of FIG.

[0009] First Embodiment A multilayer ceramic capacitor 1 according to a first embodiment of the present invention will now be described with reference to FIGS.

[0010] (Multilayer Ceramic Capacitor 1) As shown in Figure 1, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a so-called two-terminal structure. The multilayer ceramic capacitor 1 includes a laminate 2 and a pair of external electrodes 3. The laminate 2 is substantially rectangular and has six outer surfaces. The laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are stacked, and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T.

[0011] In this specification, the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the width direction W. The direction perpendicular to both the width direction W and the stacking direction T is referred to as the length direction L.

[0012] A cross section parallel to the stacking direction T and the length direction L is referred to as an "LT cross section." A cross section parallel to the stacking direction T and the width direction W is referred to as a "WT cross section." The cross section in FIG. 2 is an LT cross section passing through the center of the multilayer ceramic capacitor 1 in the width direction W. The cross section in FIG. 3 is a WT cross section passing through the center of the multilayer ceramic capacitor 1 in the length direction L.

[0013] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T are referred to as the first main surface AA and the second main surface AB, a pair of outer surfaces extending in the stacking direction T and on both sides in the width direction W are referred to as the first side surface BA and the second side surface BB, and a pair of outer surfaces extending in the stacking direction T and on both sides in the length direction L are referred to as the first end surface CA and the second end surface CB.

[0014] The first main surface AA and the second main surface AB may be collectively referred to as "main surfaces A." The first side surface BA and the second side surface BB may be collectively referred to as "side surfaces B." The first end surface CA and the second end surface CB may be collectively referred to as "end surfaces C." The boundary line between adjacent main surfaces A and side surfaces B is referred to as "ridge line 5." The ridge line 5 will be described in detail later.

[0015] 2 and 3, the inner layer portion 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0016] The dielectric layer 14 is formed of dielectric ceramic particles having a perovskite structure, with a perovskite compound containing, for example, Ba and Ti as the main component. At least one of Si, Mg, and Ba may be added as an additive to these main components. The additive is present between the ceramic particles. The dimension T of the dielectric layer 14 in the stacking direction is, for example, 0.2 μm or more and 10 μm or less.

[0017] The internal electrodes 15 are formed by sintering a conductive paste containing a metal powder that serves as a conductor, an organic solvent, a binder, and a dispersant on the dielectric layer 14. Metals such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, and Au can be used as the metal powder that serves as a conductor. These metals may also be compounds containing these metal elements or alloys with other metals. The dimension T of the internal electrodes 15 in the stacking direction is not particularly limited, but may be, for example, 0.05 μm or more and 1.5 μm or less.

[0018] The internal electrode 15 includes a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A are exposed only at the first end face CA. The second internal electrodes 15B are exposed only at the second end face CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately.

[0019] The first internal electrode 15A has a first opposing portion 15Aa and a first lead portion 15Ab. The first opposing portion 15Aa is a portion of the first internal electrode 15A that faces the second internal electrode 15B adjacent to it in the stacking direction T. The first opposing portion 15Aa is located in the center between the end faces C. The first lead portion 15Ab is a portion of the first internal electrode 15A that is led out from the first opposing portion 15Aa toward the first end face CA. The first lead portion 15Ab is exposed at the first end face CA.

[0020] The second internal electrode 15B has a second opposing portion 15Ba and a second lead portion 15Bb. The second opposing portion 15Ba is a portion of the second internal electrode 15B that faces the adjacent first internal electrode 15A (first opposing portion 15Aa). The second opposing portion 15Ba is located in the center between the end faces C. The second lead portion 15Bb is a portion of the second internal electrode 15B that is led from the second opposing portion 15Ba toward the second end face CB. The second lead portion 15Bb is exposed at the second end face CB.

[0021] The first internal electrode 15A and the second internal electrode 15B may be collectively referred to as "internal electrodes 15." The first opposing portion 15Aa and the second opposing portion 15Ba may be collectively referred to as "opposing portion 15a."

[0022] The laminate 2 also has an effective layer portion 10 consisting of each opposing portion 15a and a portion of each dielectric layer 14 sandwiched between adjacent opposing portions 15a. The effective layer portion 10 is the portion where the capacitance of the multilayer ceramic capacitor 1 is formed.

[0023] (Outer layer portion 12) The outer layer portion 12 is made of a dielectric ceramic material mainly composed of, for example, BaTiO3, CaTiO3, SrTiO3, CaZrO3, etc. The outer layer portion 12 contains a glass component. The dimension T of the outer layer portion 12 in the stacking direction is not particularly limited, but is, for example, 10 μm or more and 80 μm or less. Note that no internal electrode 15 is disposed in the outer layer portion 12.

[0024] (External electrodes 3) Each external electrode 3 is disposed on each end face C. Each external electrode 3 covers not only the end face C but also part of the main face A and part of the side face B. Each external electrode 3 is disposed on each end of the ridge line 5 in the longitudinal direction L. Either the first internal electrode 15A or the second internal electrode 15B is connected to each external electrode 3. The external electrode 3 includes a base electrode layer 31 formed in contact with the surface of the laminate 2, and a plating layer 32 disposed on the base electrode layer 31.

[0025] The base electrode layer 31 is a baking layer containing, for example, a conductive metal such as Cu (copper) and glass. The baking layer contains glass and a metal. The glass contains, for example, at least one element selected from the group consisting of B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains, for example, at least one element selected from the group consisting of Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au. The baking layer may be a single layer or may be formed of multiple layers. The maximum thickness of the baking layer is preferably 10 μm or more and 50 μm or less.

[0026] The base electrode layer 31 may be, for example, a resin layer or a thin film layer. When the base electrode layer 31 is a resin layer, the resin layer contains, for example, conductive particles and a thermosetting resin. The resin layer may be formed directly on the laminate 2 without a baked layer therebetween, or may be formed on the laminate 2 with a baked layer therebetween. The resin layer may be formed directly on each main surface A and each side surface B without a baked layer therebetween, or may be formed on each main surface A and each side surface B with a baked layer therebetween. The resin layer may be a single layer, or may be formed of multiple layers. The maximum thickness of the resin layer is preferably 10 μm or more and 150 μm or less.

[0027] When the base electrode layer 31 is a thin film layer, the thin film layer is formed of metal particles deposited in a layer shape, and the thickness of the thin film layer is set to 1 μm or less.

[0028] The plating layer 32 contains at least one metal selected from the group consisting of, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au. The plating layer 32 may be formed of multiple layers. The plating layer 32 has, for example, a first plating layer 321 disposed on the base electrode layer 31 and a second plating layer 322 disposed on the first plating layer 321.

[0029] The first plating layer 321 is preferably a Ni (nickel) plating layer, which can prevent the base electrode layer 31 from being corroded by solder when the multilayer ceramic capacitor 1 is mounted on a circuit board (not shown).

[0030] The second plating layer 322 is preferably a Sn (tin) plating layer, which can improve the wettability of solder when mounting the multilayer ceramic capacitor 1 on a circuit board, thereby facilitating mounting the multilayer ceramic capacitor 1 on a circuit board.

[0031] The thickness of each plating layer 32 is preferably 0.5 μm or more and 10 μm or less.

[0032] (Ridge line 5 of laminate 2) Here, the ridge line 5 will be described in detail with reference to Fig. 4 and Fig. 5. Fig. 4 is a diagram showing a WT cross section of the laminate 2 passing through the center of the laminate 2 in the longitudinal direction L (i.e., a fourth reference cross section CS4 described later).

[0033] As shown in Fig. 4, in the WT cross section of the laminate 2, a virtual line extending parallel to the width direction W and tangent to the first main surface AA is defined as a "first main surface side virtual line LA1". In the WT cross section of the laminate 2, a virtual line extending parallel to the width direction W and tangent to the second main surface AB is defined as a "second main surface side virtual line LA2". In the WT cross section of the laminate 2, a virtual line extending parallel to the stacking direction T and tangent to the first side surface BA is defined as a "first side surface side virtual line LB1". In the WT cross section of the laminate 2, a virtual line extending parallel to the stacking direction T and tangent to the second side surface BB is defined as a "second side surface side virtual line LB2".

[0034] In the WT cross section of the laminate 2, a virtual line connecting the intersection of the first main surface side virtual line LA1 and the second side surface side virtual line LB2 and the intersection of the second main surface side virtual line LA2 and the first side surface side virtual line LB1 is defined as a "first diagonal line DL1." In the WT cross section of the laminate 2, a virtual line connecting the intersection of the first main surface side virtual line LA1 and the first side surface side virtual line LB1 and the intersection of the second main surface side virtual line LA2 and the second side surface side virtual line LB2 is defined as a "second diagonal line DL2."

[0035] In the WT cross section of the laminate 2, of the intersections between the first diagonal line DL1 and the surface of the laminate 2, the point closer to the first main surface AA is defined as the "first reference point P1," and the point closer to the second main surface AB is defined as the "third reference point P3." In the WT cross section of the laminate 2, of the intersections between the second diagonal line DL2 and the surface of the laminate 2, the point closer to the first main surface AA is defined as the "second reference point P2," and the point closer to the second main surface AB is defined as the "fourth reference point P4."

[0036] As shown in FIG. 5 , the WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 0:10 is defined as the "first reference cross section CS1." The WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 1:3 is defined as the "second reference cross section CS2." The WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 1:2 is defined as the "third reference cross section CS3." The WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 1:1 is defined as the "fourth reference cross section CS4." The WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 2:1 is defined as the "fifth reference cross section CS5." The WT cross section at a position spaced apart by the distance of the WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 3:1 is defined as the "sixth reference cross section CS6." The WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 10:0 is defined as the "seventh reference cross section CS7."

[0037] In this specification, the term "cross section" is not limited to a surface that appears when an object is cut, but also includes a WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 0:10, and a WT cross section at a position where the ratio of the distance from one end of the laminate 2 in the length direction L to the distance from the other end of the laminate 2 in the length direction L is 10:0. The first reference cross section CS1, the second reference cross section CS2, the third reference cross section CS3, the fourth reference cross section CS4, the fifth reference cross section CS5, the sixth reference cross section CS6, and the seventh reference cross section CS7 may be collectively referred to as "each reference cross section CS."

[0038] The "first ridge line 51" is a line extending along the surface of the laminate 2 and passing through the first reference point P1 on the first reference cross section CS1, the first reference point P1 on the second reference cross section CS2, the first reference point P1 on the third reference cross section CS3, the first reference point P1 on the fourth reference cross section CS4, the first reference point P1 on the fifth reference cross section CS5, the first reference point P1 on the sixth reference cross section CS6, and the first reference point P1 on the seventh reference cross section CS7. The first ridge line 51 is a boundary line between the first main surface AA and the second side surface BB. The first main surface AA and the second side surface BB are separated by the first ridge line 51.

[0039] The "second ridge line 52" is a line extending along the surface of the laminate 2 and passing through the second reference point P2 on the first reference cross section CS1, the second reference point P2 on the second reference cross section CS2, the second reference point P2 on the third reference cross section CS3, the second reference point P2 on the fourth reference cross section CS4, the second reference point P2 on the fifth reference cross section CS5, the second reference point P2 on the sixth reference cross section CS6, and the second reference point P2 on the seventh reference cross section CS7. The second ridge line 52 is a boundary line between the first main surface AA and the second side surface BB. The first main surface AA and the second side surface BB are separated by the first ridge line 51.

[0040] The "third ridge line 53" is a line extending along the surface of the laminate 2 and passing through the third reference point P3 on the first reference cross section CS1, the third reference point P3 on the second reference cross section CS2, the third reference point P3 on the third reference cross section CS3, the third reference point P3 on the fourth reference cross section CS4, the third reference point P3 on the fifth reference cross section CS5, the third reference point P3 on the sixth reference cross section CS6, and the third reference point P3 on the seventh reference cross section CS7. The third ridge line 53 is a boundary line between the second main surface AB and the first side surface BA. The second main surface AB and the first side surface BA are separated by the third ridge line 53.

[0041] The "fourth ridge line 54" is a line extending along the surface of the laminate 2 and passing through the fourth reference point P4 on the first reference cross section CS1, the fourth reference point P4 on the second reference cross section CS2, the fourth reference point P4 on the third reference cross section CS3, the fourth reference point P4 on the fourth reference cross section CS4, the fourth reference point P4 on the fifth reference cross section CS5, the fourth reference point P4 on the sixth reference cross section CS6, and the fourth reference point P4 on the seventh reference cross section CS7. The fourth ridge line 54 is a boundary line between the first side surface BA and the first main surface AA. The first side surface BA and the first main surface AA are separated by the fourth ridge line 54.

[0042] The first ridge line 51, the second ridge line 52, the third ridge line 53, and the fourth ridge line 54 may be collectively referred to as "ridge line 5." The first reference cross section CS1 also corresponds to the first end face CA. The seventh reference cross section CS7 also corresponds to the second end face CB. The ridge lines 5 each connect the first end face CA and the second end face CB.

[0043] Furthermore, a region of the first main surface AA that is closer to the first ridge line 51 than 3% of the width direction W dimension of the first main surface AA and a region of the second side surface BB that is closer to the first ridge line 51 than 3% of the stacking direction T dimension of the first side surface BA are defined as a "first ridge line surrounding region 61." A region of the first main surface AA that is closer to the second ridge line 52 than 3% of the width direction W dimension of the first main surface AA and a region of the first side surface BA that is closer to the second ridge line 52 than 3% of the stacking direction T dimension of the first side surface BA are defined as a "second ridge line surrounding region 62." A region of the first side surface BA whose distance from the third ridge line 53 is less than 3% of the dimension of the first side surface BA in the stacking direction T, and a region of the second main surface AB whose distance from the third ridge line 53 is less than 3% of the dimension of the width direction W of the second main surface AB, are defined as a "third ridge line surrounding region 63." A region of the second main surface AB whose distance from the fourth ridge line 54 is less than 3% of the dimension of the width direction W of the second main surface AB, and a region of the first side surface BA whose distance from the fourth ridge line 54 is less than 3% of the dimension of the first side surface BA in the stacking direction T are defined as a "fourth ridge line surrounding region 64."

[0044] The first ridgeline surrounding region 61, the second ridgeline surrounding region 62, the third ridgeline surrounding region 63, and the fourth ridgeline surrounding region 64 may be collectively referred to as the "ridgeline surrounding region 6."

[0045] The "width direction W dimension of the first main surface AA" is the length of the shortest line segment that extends along the surface of the laminate 2 in the WT cross section and connects the first ridge line 51 and the second ridge line 52. The "width direction W dimension of the second main surface AB" is the length of the shortest line segment that extends along the surface of the laminate 2 in the WT cross section and connects the third ridge line 53 and the fourth ridge line 54. The "stacking direction T dimension of the first side surface BA" is the length of the shortest line segment that extends along the surface of the laminate 2 in the WT cross section and connects the second ridge line 52 and the third ridge line 53. The "stacking direction T dimension of the second side surface BB" is the length of the shortest line segment that extends along the surface of the laminate 2 in the WT cross section and connects the fourth ridge line 54 and the first ridge line 51.

[0046] (Insulating Member 7) The multilayer ceramic capacitor 1 also includes an insulating member 7. The insulating member 7 is arranged on the ridge line 5, which is the boundary line between the adjacent main surface A and side surface B. The insulating member 7 has a first insulating member 71 arranged on the first ridge line 51, a second insulating member 72 arranged on the second ridge line 52, a third insulating member 73 arranged on the third ridge line 53, and a fourth insulating member 74 arranged on the fourth ridge line 54. In each drawing, the insulating member 7 is indicated by dot hatching. The insulating member 7 may also be arranged to cover the external electrodes 3 arranged on the ridge lines 5.

[0047] The first insulating member 71, the second insulating member 72, the third insulating member 73, and the fourth insulating member 74 are each thin film-shaped, and more specifically, have a rectangular strip shape extending in the length direction L.

[0048] The first insulating member 71 is disposed, for example, over the entire area of ​​the portion of the first ridge 51 where the external electrode 3 is not disposed. The first insulating member 71 is disposed over a part of the first main surface AA on the first ridge 51 side and a part of the first side surface BA on the first ridge 51 side. The first insulating member 71 covers, for example, the entire first ridge peripheral region 61.

[0049] The second insulating member 72 is disposed, for example, over the entire area of ​​the second ridge line 52 where no external electrode 3 is disposed. The second insulating member 72 is disposed over a part of the first side surface BA on the second ridge line 52 side and a part of the second main surface AB on the second ridge line 52 side. The second insulating member 72 covers, for example, the entire second ridge line peripheral region 62.

[0050] The third insulating member 73 is disposed, for example, over the entire area of ​​the portion of the third ridge 53 where the external electrode 3 is not disposed. The third insulating member 73 is disposed over a part of the second main surface AB on the third ridge 53 side and a part of the second side surface BB on the third ridge 53 side. The third insulating member 73 covers, for example, the entire third ridge peripheral region 63.

[0051] The fourth insulating member 74 is disposed, for example, over the entire area of ​​the portion of the fourth ridge line 54 where no external electrodes 3 are arranged. Therefore, the insulating member 7 is disposed over the entire area of ​​the portion of the ridge line 5 where no external electrodes 3 are arranged. The fourth insulating member 74 is disposed over a portion of the second side surface BB on the fourth ridge line 54 side and a portion of the first main surface AA on the fourth ridge line 54 side. The fourth insulating member 74 covers, for example, the entire fourth ridge line peripheral region 64.

[0052] The first insulating member 71 and the fourth insulating member 74 are spaced apart. The first insulating member 71 and the second insulating member 72 are spaced apart. The second insulating member 72 and the third insulating member 73 are spaced apart. The third insulating member 73 and the fourth insulating member 74 are spaced apart. The laminate 2 has exposed portions 8 which are regions of each of the main surfaces A and each of the side surfaces B where neither the external electrodes 3 nor the insulating members 7 are arranged.

[0053] The exposed portion 8 has a first exposed portion 81 formed on the first main surface AA, a second exposed portion 82 formed on the first side surface BA, a third exposed portion 83 formed on the second main surface AB, and a fourth exposed portion 84 formed on the second side surface BB.

[0054] The first exposed portion 81 is, for example, in a plan view, a substantially rectangular region surrounded by the first insulating member 71, the fourth insulating member 74, and the external electrodes 3. The second exposed portion 82 is, for example, in a plan view, a substantially rectangular region surrounded by the first insulating member 71, the second insulating member 72, and the external electrodes 3. The third exposed portion 83 is, for example, in a plan view, a substantially rectangular region surrounded by the second insulating member 72, the third insulating member 73, and the external electrodes 3. The fourth exposed portion 84 is, for example, in a plan view, a substantially rectangular region surrounded by the third insulating member 73, the fourth insulating member 74, and the external electrodes 3.

[0055] The area ratio of the exposed portion 8 to the area of ​​the region on each of the main surfaces A and side surfaces B where the external electrodes 3 are not disposed is preferably 10% or more and 90% or less.

[0056] The insulating member 7 is made of, for example, a resin. However, the material is not limited to this, and the insulating member 7 may be made of, for example, a ceramic or an oxidized metal component.

[0057] The insulating member 7 preferably contains various low-conductivity materials as its main component. The insulating member 7 preferably contains an insulating resin as its main component. The insulating resin may be, for example, an epoxy resin or a phenolic resin. In this specification, the term "main component of the insulating member" refers to the component with the largest weight percentage among the components constituting the insulating member 7.

[0058] It is more preferable that the insulating member 7 contains an elastic material as a main component. Examples of the elastic material include epoxy resin, phenol resin, acrylic resin, etc. Alternatively, the insulating member 7 may be made of a flexible insulating resin material.

[0059] The thickness of the insulating member 7 is preferably 5 μm or more and 150 μm or less. Note that the "thickness of the insulating member 7" refers to the distance between the intersection of an imaginary line passing through the ridge line 5 on which the insulating member 7 is located and another ridge line 5 that is not adjacent to the imaginary line 5 in the WT cross section and the outer surface of the insulating member 7 and the intersection of the imaginary line with the outer surface of the laminate 2.

[0060] (Method for Manufacturing the Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of the first embodiment will be described.

[0061] (Internal electrode pattern forming process) First, a ceramic green sheet is prepared by forming a ceramic slurry into a sheet shape. A pattern of the internal electrodes 15 is printed on the ceramic green sheet using a conductive paste. This results in a ceramic green sheet for an inner layer portion on which the internal electrodes 15 are arranged. The pattern of the internal electrodes 15 is formed by printing, for example, screen printing, gravure printing, letterpress printing, or the like.

[0062] (Laminating Process) Next, the ceramic green sheets for the inner layer portions are laminated. The ceramic green sheets for the inner layer portions are laminated so that the internal electrode patterns are shifted by half a pitch between adjacent sheets in the length direction L. Next, ceramic green sheets for the outer layer portions, which will become the outer layer portions 12, are laminated on both sides of the laminated ceramic green sheets in the lamination direction T. The ceramic green sheets for the outer layer portions are thermocompression bonded to the ceramic green sheets for lamination. This produces a mother block.

[0063] Each outer layer portion 12 may be formed by laminating a plurality of ceramic green sheets or by a single ceramic green sheet. The components contained in the ceramic green sheets for the inner layer portion and the components contained in the ceramic green sheets for the outer layer portion may be the same or different.

[0064] (Mother Block Cutting Process) Next, the mother block is divided along cutting lines corresponding to the dimensions of the laminate. The mother block is cut, for example, in the length direction L and the width direction W. This results in multiple rectangular blocks (referred to as "laminated chips").

[0065] (Laminate Firing Step) Next, the laminated chip is heated at a predetermined firing temperature in a nitrogen atmosphere for a predetermined time, thereby obtaining the laminate 2.

[0066] (Base electrode layer forming process) Next, a base electrode layer 31 is formed on each end surface C of the laminate 2. When the base electrode layer 31 is a baked layer, a conductive paste containing glass and metal is applied onto the laminate 2. When the base electrode layer 31 is a resin layer, a conductive paste containing conductive particles and a thermosetting resin is applied onto the laminate 2. When the base electrode layer 31 is a thin film layer, the thin film layer is formed on the laminate 2 by a thin film formation method such as sputtering or vapor deposition.

[0067] Each base electrode layer 31 is formed, for example, to cover each end face C, each main face A, each side face B, and a part of each ridge 5 on the end face C side. However, this is not limitative, and each base electrode layer 31 may be disposed only on each end face C.

[0068] (Base electrode layer baking process) Next, the laminate 2 on which the base electrode layer 31 has been formed is heated in a nitrogen atmosphere at a predetermined baking temperature for a predetermined time. This bakes the base electrode layer 31 onto the laminate 2. Note that the laminate baking process and the base electrode layer baking process may be performed simultaneously after the material for the base electrode layer 31 has been placed on the laminate chip. Furthermore, if the base electrode layer 31 is a thin film layer, the base electrode layer baking process is not performed.

[0069] (Plating Process) Next, a plating layer 32 is formed on the base electrode layer 31. A first plating layer 321 is formed on the surface of the base electrode layer 31. Next, a second plating layer 322 is formed on the surface of the first plating layer 321. The first plating layer 321 is formed by, for example, Ni plating. The second plating layer 322 is formed by, for example, Sn plating. The first plating layer 321 and the second plating layer 322 are formed sequentially by, for example, electrolytic plating. As a result, an external electrode 3 is formed on each end face C of the laminate 2.

[0070] (Insulating Member Forming Process) Next, a material for the insulating member 7 is applied to the surface of the multilayer ceramic capacitor 1. The material for the insulating member 7 is, for example, a thermosetting resin (e.g., epoxy resin). The material for the insulating member 7 is applied, for example, to each of the ridge lines 5. Next, a heat treatment is performed on the multilayer ceramic capacitor 1. This hardens the thermosetting resin, and the insulating member 7 is formed on the multilayer ceramic capacitor 1.

[0071] The process of applying the material for the insulating member 7 to the multilayer ceramic capacitor 1 and curing it may be repeated multiple times in the same location. Furthermore, the material for the insulating member 7 is not limited to thermosetting resin. The material for the insulating member 7 may be, for example, a photocurable resin. In this case, light of a predetermined wavelength (e.g., ultraviolet light) is irradiated onto the photocurable resin applied to the ridge lines 5, etc. Radicals and cations are generated in the photocurable resin. The photocurable resin is cured by radical polymerization or cationic polymerization. As a result, the insulating member 7 is formed on the multilayer ceramic capacitor 1. Furthermore, the order in which the plating process and the insulating member forming process are performed may be changed as appropriate.

[0072] As a result of the above, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0073] (Experimental Example) Using the above-described manufacturing method, multilayer ceramic capacitors were fabricated as samples of experimental examples and comparative examples. The area of ​​each exposed portion 8 was different for each experimental example. When manufacturing the multilayer ceramic capacitor of the comparative example, the insulating member forming step was omitted. The multilayer ceramic capacitor of the comparative example did not include the insulating member 7. For each experimental example and comparative example, the area of ​​the exposed portion 8 was measured, and the incidence of structural defects in the multilayer ceramic capacitor and the change in temperature over time of the laminate surface were observed for each experimental example and comparative example.

[0074] 1. Manufacturing of Multilayer Ceramic Capacitor As a sample of an experimental example, a multilayer ceramic capacitor having the structure shown in Figures 1 to 5 was manufactured using the manufacturing method according to the first embodiment. The main specifications of the multilayer ceramic capacitor are as follows:

[0075] Dimensions of multilayer ceramic capacitor: L x W x T = 1.0 mm x 0.5 mm x 0.4 mm Dielectric layer material (main component): BaTiO3 Rated voltage: 6.3 V

[0076] 2. Evaluation Next, the prepared samples were measured and evaluated according to the following methods.

[0077] (Area of ​​Exposed Portions) Each principal surface A and each side surface B was observed using an optical microscope, and images of each principal surface A and each side surface B were obtained. The obtained images were analyzed using image processing software to measure the area of ​​the portion of the first principal surface AA where the external electrodes 3 were not arranged, the area of ​​the portion of the second principal surface AB where the external electrodes 3 were not arranged, the area of ​​the portion of the first side surface BA where the external electrodes 3 were not arranged, the area of ​​the portion of the second side surface BB where the external electrodes 3 were not arranged, the area of ​​the first exposed portion 81, the area of ​​the second exposed portion 82, the area of ​​the third exposed portion 83, and the area of ​​the fourth exposed portion 84. The insulating member 7 and the exposed portions 8 can be distinguished based on their respective colors.

[0078] In addition, the area ratio of the first exposed portion 81 to the area of ​​the region of the first main surface AA where the external electrode 3 is not arranged (sometimes referred to as the "first exposed portion area ratio"), the area ratio of the second exposed portion 82 to the area of ​​the region of the second main surface AB where the external electrode 3 is not arranged (sometimes referred to as the "second exposed portion area ratio"), the area ratio of the third exposed portion 83 to the area of ​​the region of the first side surface BA where the external electrode 3 is not arranged (sometimes referred to as the "third exposed portion area ratio"), and the area ratio of the fourth exposed portion 84 to the area of ​​the region of the second side surface BB where the external electrode 3 is not arranged (sometimes referred to as the "fourth exposed portion area ratio") were calculated.

[0079] The first exposed portion area ratio was a value obtained by multiplying the value obtained by dividing the area of ​​the first exposed portion 81 by the area of ​​the region of the first main surface AA where the external electrode 3 was not arranged by 100. The second exposed portion area ratio was a value obtained by dividing the area of ​​the second exposed portion 82 by the area of ​​the region of the second main surface AB where the external electrode 3 was not arranged by 100. The third exposed portion area ratio was a value obtained by dividing the area of ​​the third exposed portion 83 by the area of ​​the region of the first side surface BA where the external electrode 3 was not arranged by 100. The fourth exposed portion area ratio was a value obtained by multiplying the value obtained by dividing the area of ​​the fourth exposed portion 84 by the area of ​​the region of the second side surface BB where the external electrode 3 was not arranged by 100.

[0080] The area ratio of each exposed portion 8 to the area of ​​the region of each principal surface A and each side surface B where the external electrode 3 was not arranged (sometimes referred to as the "total exposed portion area ratio") was calculated. The total exposed portion area ratio was determined by multiplying the value obtained by dividing the total area of ​​the first exposed portion 81, the area of ​​the second exposed portion 82, the area of ​​the third exposed portion 83, and the area of ​​the fourth exposed portion 84 by the total area of ​​the region of the first principal surface AA where the external electrode 3 is not arranged, the area of ​​the region of the second principal surface AB where the external electrode 3 is not arranged, the area of ​​the region of the first side surface BA where the external electrode 3 is not arranged, and the area of ​​the region of the second side surface BB where the external electrode 3 is not arranged by 100.

[0081] The first exposed portion area ratio, the second exposed portion area ratio, the third exposed portion area ratio, the fourth exposed portion area ratio, and the overall exposed portion area ratio may be collectively referred to as "each exposed portion area ratio."

[0082] (Rate of occurrence of structural defects) For each experimental example and comparative example, 100 multilayer ceramic capacitors were prepared as samples. Each sample was dropped from a height of 3 m. After the drop, the samples were observed using an optical microscope. For each sample, the presence or absence of structural defects such as cracks on each ridge 5 was confirmed. Samples with structural defects on the ridge 5 were designated as samples with structural defects.

[0083] For each of the experimental examples and comparative examples, the number of samples with structural defects was divided by the total number of samples (i.e., 100). The obtained results were used as the incidence rate of structural defects for each of the experimental examples and comparative examples.

[0084] (Temperature change of laminate surface) For each experimental example and comparative example, 100 multilayer ceramic capacitors were prepared as samples. A voltage was applied to each sample. The voltage was 6.3 V. The application time was 200 hours. Next, each sample was placed in an environment of 25°C, and the surface temperature of the laminate 2 was measured over time. When measuring the surface temperature of the laminate 2, the temperatures of each main surface A and each side surface B were measured using a thermograph. The average of the obtained values ​​was taken as the surface temperature of the laminate 2 at that time. The measurement was terminated when the surface temperature of the laminate 2 reached 25°C.

[0085] The value obtained by subtracting the surface temperature of the laminate 2 at the start of the measurement from the surface temperature of the laminate 2 at the end of the measurement (i.e., 25°C) and dividing the result by the time (minutes) from the start of the measurement to the end of the measurement was defined as the "temperature change rate (°C / min)." The temperature change rate was calculated for each sample. The average value of the temperature change rate was calculated for each example and comparative example. The obtained value was defined as the temperature change rate for each example and comparative example.

[0086] (Evaluation Method) Among the experimental examples and comparative examples, samples with a structural defect occurrence rate of 1% or less were judged to be "good." Among the experimental examples and comparative examples, samples with a structural defect occurrence rate of 0% and a temperature change rate of -5°C / min or less were judged to be "excellent." Among the experimental examples and comparative examples, samples with a structural defect occurrence rate of more than 1% were judged to be "poor."

[0087] 3. Measurement Results Table 1 shows the exposed area ratio (%), structural defect occurrence rate (%), temperature change rate (°C / min), and evaluation results for each experimental example and comparative example.

[0088]

[0089] As shown in Table 1, the evaluation results were poor when the overall exposed area ratio was 100%, good when the overall exposed area ratio was 95% and when the overall exposed area ratio was between 0% and 5%, and excellent when the overall exposed area ratio was between 10% and 90%.

[0090] This revealed that by setting the overall exposed area ratio to 10% or more and 90% or less, it is possible to improve heat dissipation while suppressing structural defects.

[0091] The first exposed portion area ratio, the second exposed portion area ratio, the third exposed portion area ratio, and the fourth exposed portion area ratio do not all need to be the same, and may be different from one another.

[0092] (Effects of First Embodiment) According to this embodiment, the following effects can be obtained.

[0093] According to this embodiment, the multilayer ceramic capacitor 1 includes an insulating member 7. The insulating member 7 is disposed on a ridge line 5 that is a boundary line between the main surface A and the side surface B that are adjacent to each other.

[0094] According to this configuration, the insulating member 7 can absorb impacts acting on the multilayer ceramic capacitor 1. The ridges 5 are covered with the insulating member 7. This allows the insulating member 7 to absorb impacts acting on the ridges 5, thereby suppressing the occurrence of structural defects on the ridges 5. Therefore, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of structural defects.

[0095] According to this embodiment, the laminate 2 has exposed portions 8 which are regions of each of the main surfaces A and each of the side surfaces B where neither the external electrodes 3 nor the insulating members 7 are arranged.

[0096] If the surface of the laminate 2 is covered with the insulating member 7, there is a risk that heat will easily build up inside the laminate 2. With this configuration, heat from the laminate 2 is suitably released from the exposed portion 8, thereby improving the heat dissipation performance of the multilayer ceramic capacitor 1.

[0097] According to this embodiment, the area ratio of the exposed portions 8 to the area of ​​the regions of each main surface A and each side surface B where the external electrodes 3 are not arranged is 10% or more and 90% or less.

[0098] According to this configuration, it is possible to improve heat dissipation while suppressing the occurrence of structural defects.

[0099] According to this embodiment, the insulating member 7 preferably contains an insulating resin as a main component.

[0100] According to this configuration, the occurrence of a short circuit via the insulating member 7 can be suitably suppressed.

[0101] According to this embodiment, the insulating member 7 is disposed over the entire area of ​​the ridge line 5 where no external electrodes 3 are disposed.

[0102] According to this configuration, the occurrence of structural defects at the ridge line 5 can be more suitably suppressed.

[0103] Furthermore, according to this embodiment, it is more preferable that the insulating member 7 contains an elastic material as a main component.

[0104] According to this configuration, the insulating member 7 can more effectively absorb external impacts, and can therefore more effectively mitigate impacts acting on the ridge line 5. This makes it possible to more effectively suppress the occurrence of structural defects in the ridge line 5.

[0105] According to this embodiment, the thickness of the insulating member 7 is preferably 5 μm or more and 150 μm or less.

[0106] According to this configuration, the thickness of the insulating member 7 is 5 μm or more, which makes it possible to sufficiently absorb impacts acting on the ridge lines 5. This makes it possible to sufficiently suppress the occurrence of structural defects in the ridge lines 5. Furthermore, the thickness of the insulating member 7 is 150 μm or less, which makes it possible to suppress the material of the insulating member 7 from sagging from the surface of the laminate 2 due to its own weight when the insulating member 7 is formed.

[0107] Second Embodiment Next, a multilayer ceramic capacitor 1 according to a second embodiment of the present invention will be described with reference to Fig. 6 and Fig. 7. The following description will focus on differences from the first embodiment, and the same components as those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

[0108] 6 and 7 , in the second embodiment, the laminate 2 has a pair of side margins 13 arranged to sandwich the inner layer portion 11 and each outer layer portion 12 in the width direction W. The side margins 13 are formed, for example, from the same material as the dielectric layer 14 and the outer layer portions 12. However, the material of the side margins 13 is not limited to this. The dimension in the width direction W of each side margin 13 is, for example, 2 μm or more and 40 μm or less.

[0109] An imaginary boundary plane BS is an imaginary plane extending parallel to the stacking direction T and the length direction L and contacting the effective layer portion 10 in the width direction W. The "side margin boundary portion 17" is a portion of each principal surface A whose distance in each direction of the width direction W from the portion intersecting with the imaginary boundary plane BS is 3% or less of the dimension in the width direction W of the laminate 2. The side margin boundary portion 17 is the boundary portion between the outer layer portion 12 and the side margin portion 13. Note that each external electrode 3 is disposed on each end of the side margin boundary portion 17 in the length direction L.

[0110] The side margin boundary 17 has a first side margin boundary 171 located in the area on the second side BB side of the first main surface AA, a second side margin boundary 172 located in the area on the first side BA side of the first main surface AA, a third side margin boundary 173 located in the area on the first side BA side of the second main surface AB, and a fourth side margin boundary 174 located in the area on the second side BB side of the second main surface AB.

[0111] The insulating member 7 is disposed on the side margin boundary 17. The first insulating member 71 extends onto the first side margin boundary 171. The first insulating member 71 covers the entire portion of the first side margin boundary 171 where no external electrodes 3 are arranged. The second insulating member 72 extends onto the second side margin boundary 172. The second insulating member 72 covers the entire portion of the second side margin boundary 172 where no external electrodes 3 are arranged. The third insulating member 73 extends onto the third side margin boundary 173. The third insulating member 73 covers the entire portion of the third side margin boundary 173 where no external electrodes 3 are arranged. The fourth insulating member 74 extends onto the fourth side margin boundary 174. The fourth insulating member 74 covers the entire area of ​​the fourth side margin boundary portion 174 where no external electrodes 3 are arranged.

[0112] The main component of the insulating member 7 is preferably a water-repellent resin. The water-repellent resin is, for example, a polymer having a hydrophobic group. Examples of the hydrophobic polymer include acrylic resin, polyester resin, and silicone resin. It is more preferable that the hydrophobic group is exposed on the surface of the insulating member 7.

[0113] (Method for Manufacturing Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of the second embodiment will be described. Differences from the method for manufacturing the multilayer ceramic capacitor 1 of the first embodiment will be described.

[0114] In the mother block cutting process of the second embodiment, the mother block is cut along the longitudinal direction L so that the internal electrode patterns are cut. On each surface of the obtained laminated chip facing the width direction W, the conductive paste that will become the first internal electrode 15A and the conductive paste that will become the second internal electrode 15B are exposed. On one of the surfaces of the laminated chip facing the longitudinal direction L, only the conductive paste that will become the first internal electrode 15A is exposed, and on the other surface, only the conductive paste that will become the second internal electrode 15B is exposed.

[0115] The method for manufacturing a multilayer ceramic capacitor according to the second embodiment includes a side margin forming step. The side margin forming step is performed after the mother block cutting step. In the side margin forming step, for example, multiple ceramic green sheets that will become the side margins are stacked. Next, the ceramic green sheets that will become the side margins are pressed against the surfaces of the laminated chip that face the width direction W. The ceramic green sheets that will become the side margins are punched out by the laminated chip. This forms a layer that will become the side margins 13 in the laminated chip. In a similar manner, a layer that will become the side margins 13 is also formed on the other surface of the laminated chip that faces the width direction W.

[0116] The ceramic green sheet to be the side margin portion may be one sheet or a plurality of sheets may be stacked. Furthermore, the components contained in the ceramic green sheet to be the side margin portion 13 may be the same as or different from the components contained in the ceramic green sheet for the inner layer portion.

[0117] Next, the laminated chip on which the layer that will become the side margin portion 13 is formed is subjected to the laminate firing process and subsequent processes. The laminate firing process and subsequent processes are performed in substantially the same manner as in the manufacturing method of the multilayer ceramic capacitor 1 of the first embodiment. However, in the insulating member forming process of the second embodiment, the material of the insulating member 7 is applied not only onto the ridge line 5 but also onto the side margin boundary portion 17.

[0118] (Effects of Second Embodiment) According to this embodiment, the following effects can be obtained.

[0119] According to this embodiment, the laminate 2 has a pair of outer layer portions 12 arranged to sandwich the inner layer portion 11 in the stacking direction T, and a pair of side margin portions 13 arranged to sandwich the inner layer portion 11 and each outer layer portion 12 in the width direction W. The insulating member 7 is arranged on a side margin boundary portion 17, which is the boundary portion between the outer layer portion 12 and the side margin portion 13.

[0120] The side margin boundary 17 is likely to be a path for moisture to penetrate into the laminate 2. With this configuration, the side margin boundary 17 is covered with the insulating member 7. This makes it possible to prevent moisture from penetrating into the laminate 2 through the side margin boundary 17, thereby improving moisture resistance reliability. Furthermore, it is possible to improve moisture resistance reliability while suppressing the occurrence of structural defects.

[0121] Furthermore, according to this embodiment, the main component of the insulating member 7 is preferably a water-repellent resin.

[0122] According to this configuration, the insulating member 7 can repel moisture, and therefore, the penetration of moisture into the inside of the laminate 2 through the side margin portion 13 can be more suitably suppressed.

[0123] Third Embodiment Next, a multilayer ceramic capacitor 1 according to a third embodiment of the present invention will be described with reference to Fig. 8 and Fig. 9. The following description will focus on differences from the third embodiment, and the same components as those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

[0124] The direction in which the external electrodes 3 are lined up is referred to as the “electrode line-up direction,” the direction in which the external electrodes 3 are spaced apart within the electrode line-up direction is referred to as the “electrode separation direction,” and the direction in which the external electrodes 3 are close to each other within the electrode line-up direction is referred to as the “electrode proximity direction.” The electrode line-up direction is the length direction L.

[0125] 8 and 9 , the boundary line between the laminate 2 and the end of the external electrode 3 on the electrode proximity direction side is referred to as the "electrode boundary line 18." The boundary line between the first main surface AA and the end of the external electrode 3 on the electrode proximity direction side is referred to as the "first electrode boundary line 181," the boundary line between the first side surface BA and the end of the external electrode 3 on the electrode proximity direction side is referred to as the "second electrode boundary line 182," the boundary line between the second main surface AB and the end of the external electrode 3 on the electrode proximity direction side is referred to as the "third electrode boundary line 183," and the boundary line between the second side surface BB and the end of the external electrode 3 on the electrode proximity direction side is referred to as the "fourth electrode boundary line 184."

[0126] In the third embodiment, no plating layer 32 is disposed on the electrode-approaching direction end of each base electrode layer 31. Therefore, the electrode-approaching direction end of each external electrode 3 is the electrode-approaching direction end of each base electrode layer 31. The electrode boundary line 18 is the boundary line between the laminate 2 and the electrode-approaching direction end of each base electrode layer 31.

[0127] In the third embodiment, the insulating member 7 is disposed on the electrode boundary line 18. In other words, the insulating member 7 is disposed across the laminate 2 and the end of the base electrode layer 31 on the electrode-approaching direction side. The first insulating member 71 extends continuously from above the first ridge line 51 onto each base electrode layer 31. The second insulating member 72 extends continuously from above the second ridge line 52 onto each base electrode layer 31. The third insulating member 73 extends continuously from above the third ridge line 53 onto each base electrode layer 31. The fourth insulating member 74 extends continuously from above the fourth ridge line 54 onto each base electrode layer 31. The insulating member 7 contacts, for example, the end of each plating layer 32 on the electrode-approaching direction side.

[0128] In this specification, the phrase "insulating member 7 is disposed on the ridge line" includes not only the case where insulating member 7 is disposed directly on ridge line 5, but also the case where insulating member 7 is disposed indirectly on ridge line 5. For example, the case where insulating member 7 is disposed on ridge line 5 via external electrode 3 is also included in the case where insulating member 7 is disposed on ridge line 5.

[0129] The insulating member 7 has a fifth insulating member 75 connecting the first insulating member 71 and the second insulating member 72, a sixth insulating member 76 connecting the second insulating member 72 and the third insulating member 73, a seventh insulating member 77 connecting the third insulating member 73 and the fourth insulating member 74, and an eighth insulating member 78 connecting the fourth insulating member 74 and the first insulating member 71.

[0130] The fifth insulating members 75 are provided in pairs in the length direction L. One of the fifth insulating members 75 connects the end of the first insulating member 71 on the first end face CA side to the end of the second insulating member 72 on the first end face CA side. The other of the fifth insulating members 75 connects the end of the first insulating member 71 on the second end face CB side to the end of the second insulating member 72 on the second end face CB side. Each fifth insulating member 75 is disposed on the first electrode boundary line 181. Each fifth insulating member 75 has a rectangular strip shape extending in the width direction W. On the first main surface AA, the first insulating member 71, the second insulating member 72, and each fifth insulating member 75 form a substantially square ring. The first electrode boundary line 181 is entirely covered by the first insulating member 71, the second insulating member 72, and each fifth insulating member 75.

[0131] The sixth insulating members 76 are provided in pairs in the length direction L. One of the sixth insulating members 76 connects the end of the second insulating member 72 on the first end face CA side to the end of the third insulating member 73 on the first end face CA side. The other of the sixth insulating members 76 connects the end of the second insulating member 72 on the second end face CB side to the end of the third insulating member 73 on the second end face CB side. Each sixth insulating member 76 is disposed on the second electrode boundary line 182. Each sixth insulating member 76 has a rectangular strip shape extending in the width direction W. On the second side face BB, the second insulating member 72, the third insulating member 73, and each sixth insulating member 76 form a substantially square ring. The second electrode boundary line 182 is entirely covered by the second insulating member 72, the third insulating member 73, and each sixth insulating member 76.

[0132] The seventh insulating members 77 are provided in pairs in the length direction L. One of the seventh insulating members 77 connects the end of the third insulating member 73 on the first end face CA side to the end of the fourth insulating member 74 on the first end face CA side. The other of the seventh insulating members 77 connects the end of the third insulating member 73 on the second end face CB side to the end of the fourth insulating member 74 on the second end face CB side. Each of the seventh insulating members 77 is disposed on the third electrode boundary line 183. Each of the seventh insulating members 77 has a rectangular strip shape extending in the width direction W. On the second main surface AB, the third insulating member 73, the fourth insulating member 74, and each of the seventh insulating members 77 form a substantially square ring. The third electrode boundary line 183 is entirely covered by the third insulating member 73, the fourth insulating member 74, and each of the seventh insulating members 77.

[0133] The eighth insulating members 78 are provided in pairs in the length direction L. One of the eighth insulating members 78 connects the end of the fourth insulating member 74 on the first end face CA side to the end of the first insulating member 71 on the first end face CA side. The other of the fifth insulating members 75 connects the end of the fourth insulating member 74 on the second end face CB side to the end of the first insulating member 71 on the second end face CB side. Each of the eighth insulating members 78 is disposed on the fourth electrode boundary line 184. Each of the eighth insulating members 78 has a rectangular band shape extending in the width direction W. On the first side face BA, the fourth insulating member 74, the first insulating member 71, and each of the eighth insulating members 78 form a substantially square ring. The fourth electrode boundary line 184 is entirely covered by the fourth insulating member 74, the first insulating member 71, and each of the eighth insulating members 78.

[0134] The insulating member 7 is disposed over the entire area on the electrode boundary line 18. The surface of each base electrode layer 31 is covered over the entire area by the plating layer 32 and the insulating member 7. The insulating member 7 does not easily stick to the plating layer 32, but easily sticks to the base electrode layer 31. By disposing the insulating member 7 directly on the base electrode layer 31, the insulating member 7 can be more reliably fixed to the external electrode 3. Note that, if the insulating member 7 can be sufficiently fixed to the base electrode layer 31, the insulating member 7 may extend over the plating layer 32. If the plating layer 32 can be sufficiently fixed to the base electrode layer 31, the plating layer 32 may extend over the insulating member 7.

[0135] The laminate 2 of the third embodiment may have a side margin portion 13, similar to the laminate 2 of the second embodiment. In this case, the insulating member 7 is preferably disposed on the side margin boundary portion 17.

[0136] (Method for Manufacturing Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of the third embodiment will be described. Differences from the method for manufacturing the multilayer ceramic capacitor 1 of the first embodiment will be described.

[0137] The insulating member forming step of the third embodiment is performed after the base electrode layer firing step. In the insulating member forming step, the raw material of the insulating member 7 is applied onto the ridge line 5 and the electrode boundary line 18. The raw material of the insulating member 7 is placed on the end of each base electrode layer 31 on the electrode approaching side.

[0138] The plating step in the third embodiment is performed, for example, after the insulating member forming step. In the plating step, a plating layer is formed on a portion of the surface of each base electrode layer 31 where the insulating member 7 is not disposed. The plating layer 32 is adjacent to the insulating member 7. The plating layer may extend slightly onto the insulating member 7.

[0139] The plating step of the third embodiment may be performed before the insulating member forming step. In this case, in the plating step, the plating layer 32 is disposed only on a portion of each base electrode layer 31 in the electrode separation direction, and is not disposed on the end of each base electrode layer 31 in the electrode approach direction. This makes it possible to dispose the insulating member 7 on the end of each base electrode layer 31 in the electrode approach direction in the insulating member forming step. Note that the insulating member 7 may extend slightly above the plating layer 32.

[0140] (Effects of Third Embodiment) According to this embodiment, the following effects can be obtained.

[0141] According to this embodiment, the direction in which the external electrodes 3 are arranged is defined as the electrode arrangement direction, the direction in which the external electrodes approach each other within the electrode arrangement direction is defined as the electrode proximity direction, and the boundary line between the laminate 2 and the end of the external electrode 3 on the electrode proximity direction side is defined as the electrode boundary line 18. The insulating member 7 is arranged on the electrode boundary line 18.

[0142] The electrode boundaries 18 are likely to act as a path for moisture to penetrate into the inside of the laminate 2. With this configuration, the electrode boundaries 18 are covered with the insulating member 7. This makes it possible to prevent moisture from penetrating into the inside of the laminate 2 through the electrode boundaries 18. Furthermore, it is possible to improve moisture resistance reliability while suppressing the occurrence of structural defects.

[0143] According to this embodiment, the insulating member 7 is disposed over the entire area of ​​the electrode boundary line 18 .

[0144] This configuration can more effectively prevent moisture from penetrating into the interior of the laminate 2 through the electrode boundary line 18 .

[0145] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0146] In each of the above embodiments, the laminate 2 has a substantially rectangular parallelepiped shape, but the shape of the laminate 2 is not limited to this. The laminate 2 may have, for example, a rounded ridgeline peripheral region 6 or an inclined ridgeline peripheral region 6. By making the ridgeline peripheral region 6 rounded or an inclined ridgeline peripheral region 6, the occurrence of structural defects at the ridgeline 5 can be suppressed. Therefore, it is preferable that the ridgeline peripheral region 6 be rounded. The laminate 2 can be rounded by, for example, barrel polishing.

[0147] Furthermore, even if the ridge line 5 is angular, the occurrence of structural defects at the ridge line 5 can be sufficiently suppressed by disposing the insulating member 7 on the ridge line 5. In other words, by disposing the insulating member 7 on the ridge line 5, the occurrence of structural defects can be suppressed without polishing the laminate 2 or the like.

[0148] In the above-described embodiments, the insulating member 7 is disposed over the entire area of ​​the ridge line 5, but this is not limited to this. The insulating member 7 may be disposed only on a portion of the ridge line 5. However, the configurations of the above-described embodiments are preferred because they can more suitably suppress the occurrence of structural defects on the ridge line 5.

[0149] In the above embodiments, each external electrode 3 covers not only each end face C but also part of each main face A and part of each side face B, but this is not limited to this. Each external electrode 3 may be arranged, for example, only on each end face C. Each external electrode 3 does not have to be arranged on each end of the ridge line 5 in the length direction L. When the external electrode 3 is not arranged on the ridge line 5, it is preferable that the insulating member 7 is arranged over the entire area of ​​the ridge line 5. This makes it possible to suppress the occurrence of structural defects on the ridge line 5.

[0150] In the above-described embodiments, the first insulating member 71, the second insulating member 72, the third insulating member 73, and the fourth insulating member 74 each have a rectangular strip shape, but this is not limited thereto. The first insulating member 71, the second insulating member 72, the third insulating member 73, and the fourth insulating member 74 may each have, for example, a wavy or arc shape, and their shapes are not limited as long as they cover the ridge line 5. Furthermore, the shape of the exposed portion 8 is not particularly limited. The exposed portion 8 is not an essential component. However, it is preferable that the exposed portion 8 have the configuration of the above-described embodiments in order to more effectively dissipate heat from the laminate 2.

[0151] In the second embodiment, the insulating member 7 is disposed on the side margin boundary 17. However, in a configuration in which the laminate 2 has a side margin 13, the insulating member 7 does not necessarily have to be disposed on the side margin boundary 17. It is sufficient that the insulating member 7 is disposed at least on the ridge line 5. However, the configuration of the second embodiment is preferable in that it can improve moisture resistance reliability.

[0152] The present invention also includes the following combinations:

[0153] <1> A multilayer ceramic capacitor comprising: a laminate having an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of inner electrodes; first and second main surfaces opposing each other in a stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes arranged on each end surface; and an insulating member, wherein the insulating member is arranged on a ridge line that is a boundary line between the main surfaces and the side surfaces that are adjacent to each other.

[0154] <2> The multilayer ceramic capacitor according to claim 1, wherein the laminate has exposed portions on the main surfaces and the side surfaces where neither the external electrodes nor the insulating members are arranged.

[0155] <3> The multilayer ceramic capacitor according to claim 2, wherein the area ratio of the exposed portions to the area of ​​the regions of the main surfaces and the side surfaces where the external electrodes are not disposed is 10% or more and 90% or less.

[0156] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the insulating member contains an insulating resin as a main component.

[0157] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the insulating member is disposed over the entire area of ​​the portion of the ridge line where the external electrodes are not disposed.

[0158] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the laminate has outer layer portions arranged to sandwich the inner layer portions in the stacking direction, and side margin portions arranged to sandwich the inner layer portions and each of the outer layer portions in the width direction, and the insulating member is arranged on a side margin boundary portion that is a boundary portion between the outer layer portions and the side margin portions.

[0159] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the direction in which the external electrodes 3 are arranged is defined as an electrode arrangement direction, the direction in which the external electrodes approach each other in the electrode arrangement direction is defined as an electrode proximity direction, and the boundary line between the laminate and the end of each external electrode on the electrode proximity direction side is defined as an electrode boundary line, and the insulating member is arranged on the electrode boundary line.

[0160] <8> The multilayer ceramic capacitor according to <7>, wherein the insulating member is disposed over the entire area of ​​the electrode boundary line.

[0161] REFERENCE SIGNS LIST 1 multilayer ceramic capacitor 2 laminate 3 external electrode 5 ridge line 7 insulating member 8 exposed portion 12 outer layer portion 13 side margin portion 14 dielectric layer 15 internal electrode 17 side margin boundary portion 18 electrode boundary line AA first main surface AB second main surface BA first side surface BB second side surface CA first end surface CB second end surface

Claims

1. A multilayer ceramic capacitor comprising: a laminate having an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of internal electrodes; first and second main surfaces opposing each other in the stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes arranged on each end surface; and an insulating member, wherein the insulating member is arranged on a ridge line that is a boundary line between the adjacent main surfaces and side surfaces.

2. The multilayer ceramic capacitor according to claim 1, wherein the laminate has exposed portions on each of the main surfaces and each of the side surfaces where neither the external electrodes nor the insulating members are arranged.

3. The multilayer ceramic capacitor according to claim 2, wherein the area ratio of the exposed portions to the area of ​​the regions of each of the main surfaces and each of the side surfaces where the external electrodes are not disposed is 10% or more and 90% or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the insulating member contains an insulating resin as a main component.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the insulating member is disposed over the entire area of ​​the ridge line where the external electrodes are not disposed.

6. A multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the laminate has outer layer portions arranged to sandwich the inner layer portions in the stacking direction, and side margin portions arranged to sandwich the inner layer portions and each of the outer layer portions in the width direction, and the insulating member is arranged on a side margin boundary portion that is a boundary portion between the outer layer portions and the side margin portions.

7. A multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the direction in which the external electrodes 3 are lined up is defined as the electrode arrangement direction, the direction in which the external electrodes approach each other within the electrode arrangement direction is defined as the electrode proximity direction, and the boundary line between the laminate and the end of each external electrode on the electrode proximity direction side is defined as an electrode boundary line, and the insulating member is arranged on the electrode boundary line.

8. The multilayer ceramic capacitor according to claim 7, wherein the insulating member is disposed over the entire area of ​​the electrode boundary line.

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