Signal processing device

Abstract

Combining multiple antenna arrays may degrade transmission / reception performance in some cases. The present invention provides a signal processing device for interconverting between two polarizations, which are modulated with different data and which are orthogonal to each other in the direction of oscillation, and a first signal and a second signal that correspond to the two polarizations. The signal processing device comprises: a first antenna array and a second antenna array each including a plurality of antennas, each antenna having a first feed point and a second feed point; a first signal circuit electrically connected to the plurality of first feed points of the first antenna array; a second signal circuit electrically connected to the plurality of second feed points of the first antenna array; a third signal circuit electrically connected to the plurality of first feed points of the second antenna array; a fourth signal circuit electrically connected to the plurality of second feed points of the second antenna array; a first select circuit that selectively connects one of either a node of a first signal or a node of a second signal to the first signal circuit and the other to the second signal circuit; and a second select circuit that selectively connects one of either a node of a first signal or a node of a second signal to the third signal circuit and the other to the fourth signal circuit.

Description

signal processing device

[0001] The present disclosure relates to a signal processing device.

[0002] Patent Document 1 discloses a method of combining multiple antenna arrays.

[0003] International Publication WO2022 / 176646

[0004] When combining multiple antenna arrays, if a specific antenna array is rotated relative to the other antenna arrays, the polarized waves radiated from the specific antenna may become noise, resulting in a decrease in transmission and reception performance.

[0005] a second antenna array including a plurality of antennas, each having a first feed point and a second feed point; a first signal circuit electrically connecting the plurality of first feed points of the first antenna array; a second signal circuit electrically connecting the plurality of second feed points of the first antenna array; a third signal circuit electrically connecting the plurality of first feed points of the second antenna array; a fourth signal circuit electrically connecting the plurality of second feed points of the second antenna array; a first selection circuit selectively connecting one of a node of the first signal and a node of the second signal to the first signal circuit and the other to the second signal circuit; and a second selection circuit selectively connecting one of the node of the first signal and the node of the second signal to the third signal circuit and the other to the fourth signal circuit.

[0006] The transmission and reception performance of the signal processing device can be improved.

[0007] FIG. 1 is a schematic diagram showing the configuration of a signal processing device according to the present embodiment. FIG. 2 is a schematic diagram showing the configuration of a signal processing device according to the present embodiment. FIG. 3 is a schematic diagram showing the configuration of a signal processing device according to the present embodiment. FIG. 4 is a plan view showing an example configuration of an antenna array. FIG. 5 is a cross-sectional view showing an example configuration of an antenna array. FIG. 6 is a schematic diagram showing the configuration of a signal processing device. FIG. 7 is a cross-sectional view showing the configuration of a signal processing device. FIG. 8 is a plan view showing the configuration of a connector. FIG. 9 is a plan view showing signal allocation to connectors. FIG. 10 is a plan view showing an example combination of a plurality of antenna arrays. FIG. 11 is a schematic diagram showing the configuration of a signal processing device. FIG. 12 is a plan view showing an example combination of a plurality of antenna arrays. FIG. 13 is a cross-sectional view showing the configuration of a signal processing device. FIG. 14 is a schematic diagram showing the configuration of a signal processing device.

[0008] 1 to 3 are schematic diagrams showing the configuration of a signal processing device according to this embodiment. FIG. 4 is a plan view showing an example of the configuration of an antenna array. FIG. 5 is a cross-sectional view showing an example of the configuration of an antenna array. As shown in FIGS. 1 to 3, a signal processing device 10 is a signal processing device that converts between two types of polarized waves modulated with different data and having orthogonal vibration directions, two types of polarized waves modulated with different data and having orthogonal vibration directions, and a first signal S1 and a second signal S2 corresponding to the two types of polarized waves. The signal processing device includes a first antenna array T1 including a plurality of antennas JA, JB, JC, and JD (hereinafter referred to as JA to JD), each having a first feed point P1 and a second feed point P2, a second antenna array T2 including a plurality of antennas JA to JD, each having a first feed point P1 and a second feed point P2, and a second antenna array T3 including a plurality of antennas JA to JD, each having a first feed point P1 and a second feed point P2, and a third antenna array T4 electrically connected to the plurality of first feed points P1 of the first antenna array T1. The signal processing device 10 includes a first signal circuit C1, a second signal circuit C2 electrically connected to the plurality of second feed points P2 of the first antenna array T1, a third signal circuit C3 electrically connected to the plurality of first feed points P1 of the second antenna array T2, a fourth signal circuit C4 electrically connected to the plurality of second feed points P2 of the second antenna array T2, a first selection circuit X1 selectively connecting one of a node U1 of the first signal S1 and a node U2 of the second signal S2 to the first signal circuit C1 and the other to the second signal circuit C2, and a second selection circuit X2 selectively connecting one of the node U1 of the first signal S1 and the node U2 of the second signal S2 to the third signal circuit C3 and the other to the fourth signal circuit C4. The signal processing device 10 may include a control unit CS that controls the first and second selection circuits X1 and X2 and the first to fourth signal circuits C1 to C4.

[0009] In the signal processing device 10, the transmission and reception performance can be improved by controlling the first and second selection circuits X1 and X2 in accordance with the relative positions of the first antenna array T1 and the second antenna array T2.

[0010] As shown in FIGS. 4 and 5 , the first antenna array T1 includes a substrate ST, a ground conductor MG on the substrate ST, an insulating film ZF on the ground conductor MG, and radiating elements MA, MB, MC, and MD (hereinafter referred to as MA to MD) on the insulating film ZF. The ground conductor MG and the radiating elements MA to MD may be rectangular (e.g., square) metal films. The first antenna array T1 includes an antenna JA including the radiating element MA and the ground conductor MG, an antenna JB including the radiating element MB and the ground conductor MG, an antenna JC including the radiating element MC and the ground conductor MG, and an antenna JD including the radiating element MD and the ground conductor MG, and the multiple antennas JA to JD are aligned in a first direction D1. For each of the multiple antennas JA to JD, a first feed point P1 is located between the antenna center and a side parallel to the first direction D1, and a second feed point P2 is located between the antenna center and a side parallel to the second direction D2 (a direction perpendicular to D1).

[0011] The oscillation direction (polarization direction) of the polarized wave radiated when power is fed to the first feed point P1 may be the second direction D2, and the oscillation direction (polarization direction) of the polarized wave radiated when power is fed to the second feed point P2 may be the first direction D1. The second antenna array T2 has the same structure as the first antenna array T1, and when the second antenna array T2 is rotated 90 degrees with respect to the first antenna array T1 (FIGS. 1 to 3), the oscillation direction (polarization direction) of the polarized wave radiated when power is fed to the first feed point P1 may be the first direction D1, and the oscillation direction (polarization direction) of the polarized wave radiated when power is fed to the second feed point P2 may be the second direction D2.

[0012] 1 and 2, the first signal circuit C1 includes amplifiers 18 and 19, a mixer M1, a first phase adjustment circuit (phase shifters 1A to 1D), amplifiers 5A to 5D, and amplifiers 6A to 6D. The amplifiers 18 and 19 are connected to a first selection circuit X1. The amplifiers 5A to 5D and amplifiers 6A to 6D are connected to a first antenna array T1. Specifically, the amplifiers 5A and 6A are connected to a first feed point P1 of the antenna JA, the amplifiers 5B and 6B are connected to a first feed point P1 of the antenna JB, the amplifiers 5C and 6C are connected to a first feed point P1 of the antenna JC, and the amplifiers 5D and 6D are connected to a first feed point P1 of the antenna JD.

[0013] 1 and 2, the second signal circuit C2 includes amplifiers 28 and 29, a mixer M2, a second phase adjustment circuit (phase shifters 2A to 2D), amplifiers 7A to 7D, and amplifiers 8A to 8D. The amplifiers 28 and 29 are connected to the first selection circuit X1. The amplifiers 7A to 7D and 8A to 8D are connected to the first antenna array T1. Specifically, the amplifiers 7A and 8A are connected to the second feed point P2 of the antenna JA, the amplifiers 7B and 8B are connected to the second feed point P2 of the antenna JB, the amplifiers 7C and 8C are connected to the second feed point P2 of the antenna JC, and the amplifiers 7D and 8D are connected to the second feed point P2 of the antenna JD.

[0014] As shown in FIGS. 1 and 3, the third signal circuit C3 includes amplifiers 38 and 39, a mixer M3, a third phase adjustment circuit (phase shifters 3A to 3D), amplifiers 5A to 5D, and amplifiers 6A to 6D. The amplifiers 38 and 39 are connected to the second selection circuit X2. The amplifiers 5A to 5D and 6A to 6D are connected to the second antenna array T2. Specifically, the amplifiers 5A and 6A are connected to the first feed point P1 of the antenna JA, the amplifiers 5B and 6B are connected to the first feed point P1 of the antenna JB, the amplifiers 5C and 6C are connected to the first feed point P1 of the antenna JC, and the amplifiers 5D and 6D are connected to the first feed point P1 of the antenna JD.

[0015] As shown in FIGS. 1 and 3, the fourth signal circuit C4 includes amplifiers 48 and 49, a mixer M4, a fourth phase adjustment circuit (phase shifters 4A to 4D), amplifiers 7A to 7D, and amplifiers 8A to 8D. The amplifiers 48 and 49 are connected to the second selection circuit X2. The amplifiers 7A to 7D and 8A to 8D are connected to the second antenna array T2. Specifically, the amplifiers 7A and 8A are connected to the second feed point P2 of the antenna JA, the amplifiers 7B and 8B are connected to the second feed point P2 of the antenna JB, the amplifiers 7C and 8C are connected to the second feed point P2 of the antenna JC, and the amplifiers 7D and 8D are connected to the second feed point P2 of the antenna JD.

[0016] The first signal S1 may be an intermediate frequency signal or a baseband signal, and similarly, the second signal S2 may be an intermediate frequency signal or a baseband signal. Each of the first to fourth signal circuits C1 to C4 may include a mixer (M1 to M4) that mixes a local oscillator signal LO with the intermediate frequency signal or the baseband signal. For example, the mixer M1 of the first signal circuit C1 may be disposed in a signal path between the first selection circuit X1 and the first antenna array T1. For example, in the first signal circuit C1, the mixer M1 may be connected to multiple signal paths, and each signal path may include a phase shifter 1A and amplifiers 5A and 6A located between the mixer M1 and the first feeding point P1.

[0017] 6 is a schematic diagram showing the configuration of a signal processing device. As shown in FIG. 6, when the first selection circuit X1 connects the node U1 of the first signal S1 to the first signal circuit C1 and the node U2 of the second signal S2 to the second signal circuit C2, the transmission function is as follows.

[0018] A first signal S1 (IF signal or baseband signal) is input to a mixer M1 via an amplifier 18. The mixer M1 multiplies the first signal S1 by an up-conversion LO signal (local oscillator signal) to output a high-frequency signal. This high-frequency signal is branched into four: the first branch signal is supplied to a first feed point P1 of an antenna JA via a phase shifter 1A and an amplifier 5A; the second branch signal is supplied to a first feed point P1 of an antenna JB via a phase shifter 2A and an amplifier 5B; the third branch signal is supplied to a first feed point P1 of an antenna JC via a phase shifter 1C and an amplifier 5C; and the fourth branch signal is supplied to a first feed point P1 of an antenna JD via a phase shifter 1D and an amplifier 5D. This causes a polarized wave corresponding to the first signal S1 to be radiated from the first antenna array T1 (antennas JA to JD). The LO signal may be converted into a desired integer multiple frequency signal by a frequency multiplier circuit (harmonic generating circuit) 85 and an amplifier 95, and this integer multiple frequency signal may be input to the mixer M1.

[0019] The second signal S2 (IF signal or baseband signal) is input to the mixer M2 via the amplifier 28. The mixer M2 multiplies the second signal S2 by an up-conversion LO signal (local oscillator signal) to output a high-frequency signal. This high-frequency signal is branched into four: the first branch signal is supplied to the first feed point P2 of the antenna JA via a phase shifter 2A and an amplifier 7A; the second branch signal is supplied to the second feed point P2 of the antenna JB via a phase shifter 2B and an amplifier 7B; the third branch signal is supplied to the second feed point P2 of the antenna JC via a phase shifter 2C and an amplifier 7C; and the fourth branch signal is supplied to the second feed point P2 of the antenna JD via a phase shifter 2D and an amplifier 7D. This causes the first antenna array T1 (antennas JA to JD) to radiate a polarized wave corresponding to the second signal S2. The LO signal may be converted into a desired integer multiple frequency signal by a frequency multiplier circuit (harmonic generating circuit) 85 and an amplifier 95, and this integer multiple frequency signal may be input to the mixer M2.

[0020] The receiving function in the case of Figure 6 is as follows. The high-frequency signal received by antenna JA is input to mixer M1 via first feed point P1, amplifier 6A, and phase shifter 1A. The high-frequency signal received by antenna JB is input to mixer M1 via first feed point P1, amplifier 6B, and phase shifter 1B. The high-frequency signal received by antenna JC is input to mixer M1 via first feed point P1, amplifier 6C, and phase shifter 1C. The high-frequency signal received by antenna JD is input to mixer M1 via first feed point P1, amplifier 6D, and phase shifter 1D. Mixer M1 multiplies the high-frequency signal by a down-conversion LO signal (local oscillator signal) to output an intermediate frequency signal or baseband signal. This intermediate frequency signal (IF signal) or baseband signal is extracted as a first signal S1 from first selection circuit X1.

[0021] The high-frequency signal received by antenna JA is input to mixer M2 via second feed point P2, amplifier 8A, and phase shifter 2A. The high-frequency signal received by antenna JB is input to mixer M2 via second feed point P2, amplifier 8B, and phase shifter 2B. The high-frequency signal received by antenna JC is input to mixer M2 via second feed point P2, amplifier 8C, and phase shifter 2C. The high-frequency signal received by antenna JD is input to mixer M2 via second feed point P2, amplifier 8D, and phase shifter 2D. Mixer M2 multiplies the high-frequency signal by a down-conversion LO signal (local oscillator signal) to output an intermediate frequency signal or baseband signal, and this intermediate frequency signal (IF signal) or baseband signal is extracted as second signal S2 from first selection circuit X1.

[0022] As shown in FIG. 1 , in the signal processing device 10, m (e.g., m = 4) antennas may be arranged in a first direction D1 and n (e.g., n = 1) antennas may be arranged in a second direction D2 perpendicular to the first direction D1, where m is an integer equal to or greater than 2 and n is a natural number smaller than m. The second antenna array T2 may have n (e.g., n = 1) antennas arranged in the first direction D1 and m (e.g., m = 4) antennas arranged in the second direction D2. The first antenna array T1 and the second antenna array T2 may have the same structure, and the second antenna array T2 may be rotated 90° relative to the first antenna array T1. The first antenna array T1 and the second antenna array T2 may be arranged on the same plane.

[0023] 7 and 8 are schematic diagrams showing the configuration of a signal processing device. As shown in FIG. 8, the first antenna array T1 and the second antenna array T2 have the same structure, and when the second antenna array T2 is rotated 90° relative to the first antenna array T1, the first selection circuit X1 may input the first signal S1 to the first signal circuit C1 and the second signal S2 to the second signal circuit C2, and the second selection circuit X2 may input the first signal S1 to the fourth signal circuit C4 and the second signal S2 to the third signal circuit C3, as shown in FIGS. 6 to 8. In this way, the antenna vibration direction corresponding to the first signal S1 of the antenna array T1 and the antenna vibration direction corresponding to the second signal S2 of the antenna array T2 are orthogonal to each other, preventing them from becoming parallel (causing noise to each other).

[0024] As shown in Figures 2 and 3 and Figures 6 and 7, the first signal circuit C1 may include a first phase adjustment circuit including a plurality of phase shifters 1A to 1D, the second signal circuit C2 may include a second phase adjustment circuit including a plurality of phase shifters 2A to 2D, the third signal circuit C3 may include a third phase adjustment circuit including a plurality of phase shifters 3A to 3D, and the fourth signal circuit C4 may include a fourth phase adjustment circuit including a plurality of phase shifters 4A to 4D.

[0025] 1, one of the third phase adjustment circuits (3A to 3D) and the fourth phase adjustment circuits (4A to 4D) may shift the phase by 180°, while the other may not. For example, the third phase adjustment circuits (3A to 3D) of the third signal circuit C3 may not shift the phase, while the fourth phase adjustment circuits (4A to 4D) of the fourth signal circuit C4 may shift the phase by 180°. The first phase adjustment circuits (1A to 1D) of the first signal circuit C1 and the second phase adjustment circuits (2A to 2D) of the second signal circuit C2 may not shift the phase.

[0026] Fig. 9 is a cross-sectional view showing the configuration of a signal processing device. Fig. 10 is a plan view showing the configuration of a connector. Fig. 11 is a plan view showing signal allocation of the connector. As shown in Fig. 9, the first antenna array T1 and the second antenna array T2 may be connected by a connector Y on the same plane. A connector 21 may be arranged on the lower surface (back surface) of the first antenna array T1, and the connector 21 may be electrically connected to the distribution plate DS via a connector 31, a wiring W, a connector 41, and a connector 51. The connectors 31 and 41 may be connected to both sides of the wiring W. The connector 51 may be arranged on the upper surface of the distribution plate DS.

[0027] An RFIC 11 including first and second signal circuits C1 and C2 and a first selection circuit X1, a power supply IC 90, and a connector 21 electrically connected to the RFIC 11 are mounted on the lower surface (rear surface) of the first antenna array T1, and first and second signals S1 and S2, an LO signal, and the like may be input / output between the distribution plate DS and the RFIC 11. Similarly, an RFIC 12 including third and fourth signal circuits C3 and C4 and a second selection circuit X2, a power supply IC, and a connector 22 electrically connected to the RFIC 12 are mounted on the lower surface (rear surface) of the second antenna array T2, and first and second signals S1 and S2, an LO signal, and the like may be input / output between the distribution plate DS and the RFIC 12. A connector 52 electrically connected to the connector 22 via wiring may be disposed on the upper surface of the distribution plate DS.

[0028] As shown in FIGS. 10 and 11 , the connector 51 (first connector) and the connector 52 (second connector) may have the same signal assignments for each pin. In assignment type 101 of FIG. 11 , IF2 (second signal S2) is assigned to pin a, GND to pin b, Ctrl1 (control signal) to pin c, GND to pin d, VDD to pin e, GND to pin f, GND to pin g, Ctrl2 (control signal) to pin h, GND to pin i, and IF1 (first signal S1) and an LO signal to pin j. Assignment type 101 is an example, and assignment types 102 to 104 may also be used. For example, each control signal (Ctrl and Ctrl2) in the RFIC 11 may be input from the control unit CS to the first and second signal circuits C1 and C2 and the first and second selection circuits X1 and X2, etc.

[0029] 12 is a plan view showing an example of a combination of multiple antenna arrays. As shown in Fig. 12, a second antenna array T2 (1 x 4 antennas) rotated 90 degrees counterclockwise and a sixth antenna array T6 (1 x 4 antennas) rotated 90 degrees clockwise may be arranged adjacent to a first antenna array T1 (4 x 1 antennas), a third antenna array T3 (4 x 1 antennas), a fourth antenna array T4 (4 x 1 antennas), and a fifth antenna array T5 (4 x 1 antennas) arranged in the second direction D2.

[0030] If the wavelength of the two types of polarized waves radiated or absorbed from the antenna array is λ, one antenna JD included in the first antenna array T1 and one antenna JA included in the second antenna array T2 may be adjacent to each other in the first direction D1 with a pitch PT of half the wavelength (λ / 2).

[0031] In the first antenna array T1, two adjacent antennas (e.g., antennas JC and JD) in the first direction D1 may be spaced apart at a pitch PT of half a wavelength (λ / 2). When the wavelengths of the two polarized waves are different, one of the wavelengths may be designed as λ.

[0032] 13 and 14 are schematic diagrams showing the configuration of a signal processing device. As shown in Fig. 12 and 13, the signal processing device 10 may include a third antenna array T3 including a plurality of antennas each having a first feed point P1 and a second feed point P2, a fifth signal circuit C5 electrically connected to the plurality of first feed points P1 of the third antenna array T3, a sixth signal circuit C6 electrically connected to the plurality of second feed points P2 of the third antenna array T3, and a third selection circuit X3 selectively inputting one of the first signal S1 and the second signal S2 to the fifth signal circuit C5 and the other to the sixth signal circuit C6. In the third antenna array T3, m antennas (e.g., m=4) may be arranged in the first direction D1 and n antennas (e.g., n=1) may be arranged in the second direction D2, and as shown in FIG. 14, the third selection circuit X3 may connect the node U1 of the first signal S1 to the fifth signal circuit C5 and the node U2 of the second signal S2 to the sixth signal circuit C6.

[0033] 15 is a plan view showing an example of a combination of multiple antenna arrays. As shown in FIG. 15, the first antenna array T1 and the third antenna array T3 may have the same structure, and the third antenna array T3 may be arranged rotated 180 degrees relative to the first antenna array T1. In this case, as shown in FIG. 14, the fifth signal circuit C5 may include a fifth phase adjustment circuit including a plurality of phase shifters (15A to 15D), and the sixth signal circuit C6 may include a sixth phase adjustment circuit including a plurality of phase shifters (16A to 16D), and the fifth phase adjustment circuits (15A to 15D) and the sixth phase adjustment circuits (16A to 16D) may each shift the phase by 180 degrees.

[0034] 16 is a cross-sectional view showing the configuration of the signal processing device. As shown in Fig. 16, the RFIC 11 and the distribution plate DS may be electrically connected by directly fitting a connector 21, which is arranged on the back surface of the first antenna array T1 and electrically connected to the RFIC 11, to a connector 51 on the distribution plate DS without using wiring.

[0035] 17 and 18 are schematic diagrams showing the configuration of a signal processing device. As shown in FIG. 17, when a mixed signal of a first signal S1 and an LO signal (see FIG. 11) is input to the RFIC 11, the first signal S1 and the LO signal may be separated by a separation circuit 88, and only the first signal S1 may be input to the first selection circuit X1. The LO signal is input to a frequency multiplication circuit (harmonic generating circuit) 85. As shown in FIG. 18, in the first signal circuit C1, a phase shifter 91 may be disposed between the mixer M1 and a first phase adjustment circuit including a plurality of phase shifters (1A-1D). In this case, the phase shifter 91 can perform phase setting for four branches. Similarly, in the second signal circuit C2, a phase shifter 92 may be disposed between the mixer M2 and a second phase adjustment circuit including a plurality of phase shifters (2A-2D).

[0036] The above-described embodiments are intended to be illustrative and explanatory, and not limiting, and many variations will be apparent to those skilled in the art based on these examples and descriptions.

[0037] (Cross-reference to related applications) This application is incorporated herein by reference in its entirety by reference to Japanese Patent Application No. 2024-053882.

[0038] 10 Signal processing device 11 RFIC 12 RFIC X1 First selection circuit X2 Second selection circuit C1 First signal circuit C2 Second signal circuit C3 Third signal circuit C4 Fourth signal circuit CS Control unit JA to JD Antenna P1 First feeding point P2 Second feeding point T1 First antenna array T2 Second antenna array

Claims

1. A signal processing device that converts between two types of polarized waves modulated with different data and vibrating in orthogonal directions, and a first signal and a second signal corresponding to the two types of polarized waves, comprising: a first antenna array including a plurality of antennas, each having a first feed point and a second feed point; a second antenna array including a plurality of antennas, each having a first feed point and a second feed point; a first signal circuit electrically connecting the plurality of first feed points of the first antenna array; a second signal circuit electrically connecting the plurality of second feed points of the first antenna array; a third signal circuit electrically connecting the plurality of first feed points of the second antenna array; a fourth signal circuit electrically connecting the plurality of second feed points of the second antenna array; and a first selection circuit selectively connecting one of a node of the first signal and a node of the second signal to the first signal circuit and the other to the second signal circuit. a second selection circuit that selectively connects one of the first signal node and the second signal node to the third signal circuit and the other to the fourth signal circuit.

2. A signal processing device as described in claim 1, wherein m is an integer greater than or equal to 2 and n is a natural number smaller than m, the first antenna array has m antennas arranged in a first direction and n antennas arranged in a second direction perpendicular to the first direction, and the second antenna array has n antennas arranged in the first direction and m antennas arranged in the second direction.

3. The signal processing device according to claim 2, wherein the first antenna array and the second antenna array have the same structure, and the second antenna array is arranged rotated 90° relative to the first antenna array.

4. The signal processing device according to claim 2, wherein the first selection circuit inputs the first signal to the first signal circuit and the second signal to the second signal circuit, and the second selection circuit inputs the first signal to the fourth signal circuit and the second signal to the third signal circuit.

5. The signal processing device according to claim 1, wherein said first antenna array and said second antenna array are arranged on the same plane.

6. A signal processing device according to claim 2, wherein one antenna included in the first antenna array and one antenna in the second antenna array are adjacent to each other in the first direction at a pitch of λ / 2, where λ is the wavelength of the two types of polarized waves.

7. A signal processing device according to claim 6, wherein two adjacent antennas in said first antenna array in said first direction are arranged at a pitch of half a wavelength.

8. The signal processing device of claim 2, comprising: a third antenna array including a plurality of antennas each having a first feed point and a second feed point; a fifth signal circuit electrically connecting the plurality of first feed points of said third antenna array; a sixth signal circuit electrically connecting the plurality of second feed points of said third antenna array; and a third selection circuit selectively inputting one of the first signal node and the second signal node to said fifth signal circuit and the other to said sixth signal circuit.

9. The signal processing device according to claim 8, wherein said third antenna array has m antennas arranged in said first direction and n antennas arranged in said second direction.

10. The signal processing device according to claim 8, wherein said third selection circuit inputs said first signal to said fifth signal circuit and said second signal to said sixth signal circuit.

11. The signal processing device according to claim 2, wherein the first signal circuit includes a first phase adjustment circuit including a plurality of phase shifters, the second signal circuit includes a second phase adjustment circuit including a plurality of phase shifters, the third signal circuit includes a third phase adjustment circuit including a plurality of phase shifters, and the fourth signal circuit includes a fourth phase adjustment circuit including a plurality of phase shifters.

12. The signal processing device according to claim 11, wherein one of the third phase adjustment circuit and the fourth phase adjustment circuit shifts the phase by 180°, and the other does not shift the phase.

13. The signal processing device according to claim 12, wherein the first phase adjustment circuit and the second phase adjustment circuit do not shift the phase.

14. The signal processing device according to claim 9, wherein the first antenna array and the third antenna array have the same structure, and the third antenna array is arranged rotated 180 degrees relative to the first antenna array.

15. The signal processing device according to claim 14, wherein the fifth signal circuit includes a fifth phase adjustment circuit including a plurality of phase shifters, the sixth signal circuit includes a sixth phase adjustment circuit including a plurality of phase shifters, and the fifth phase adjustment circuit and the sixth phase adjustment circuit each shift the phase by 180°.

16. A signal processing device according to any one of claims 1 to 15, comprising a first connector electrically connected to the first signal circuit and the first selection circuit, and a second connector electrically connected to the second signal circuit and the second selection circuit, wherein the first and second connectors have the same signal assignments for each pin.

17. A signal processing device according to any one of claims 1 to 15, wherein the first signal is an intermediate frequency signal or a baseband signal.

18. The signal processing device according to claim 17, wherein each of the first to fourth signal circuits includes a mixer that mixes a local oscillator signal with an intermediate frequency signal or a baseband signal.

19. The signal processing device according to claim 18, wherein the mixer of the first signal circuit is disposed in a signal path between the first selection circuit and the first antenna array.

20. The signal processing device according to claim 18, wherein in the first signal circuit, the mixer is connected to a plurality of signal paths, and each signal path includes a phase shifter and an amplifier located between the mixer and the first feeding point.

21. A signal processing device according to any one of claims 1 to 15, comprising an RFIC including the first selection circuit and the first and second signal circuits, and an RFIC including the second selection circuit and the third and fourth signal circuits.

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