Optical detection device and electronic apparatus

Abstract

[Problem] To prevent deterioration of the image quality of a captured image when an FD link is performed. [Solution] An optical detection device comprises: a plurality of pixels that each have a photoelectric conversion element; and signal lines that are individually provided to each pixel group including two or more pixels sharing a floating diffusion region among the plurality of pixels, and that transmit a pixel signal of all or a part of the pixels included in the corresponding pixel group.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to photodetection devices and electronic devices.

[0002] A technology (hereinafter referred to as FD link) that connects the floating diffusion regions of multiple pixels to increase the capacity that can store the charge obtained by photoelectric conversion is known (see Patent Document 1). The FD link can reduce the conversion efficiency when converting the charge obtained by photoelectric conversion into voltage, thereby increasing the dynamic range.

[0003] International Publication No. 2020 / 095544

[0004] However, in the FD link described in Patent Document 1, the diffusion layer connecting some of the amplifier transistors and the select transistors becomes floating. A parasitic capacitance is formed between this diffusion layer and the floating diffusion layer connected to the gate of the amplifier transistor. When the amplifier transistor transitions from the floating state of the diffusion layer to the on state, the gate voltage of the amplifier transistor rises due to the influence of the parasitic capacitance. This increases the potential of the signal line connected to the source of the select transistor, which may cause degradation of image quality, such as the appearance of black lines in captured images.

[0005] Therefore, the present disclosure provides a photodetector and electronic equipment that prevent degradation of the image quality of captured images when performing FD linking.

[0006] In order to solve the above problems, according to the present disclosure, there is provided a photodetection device including: a plurality of pixels each having a photoelectric conversion element; and a signal line provided for each pixel group including two or more of the plurality of pixels that share a floating diffusion region, the signal line transmitting pixel signals of all or some of the pixels included in the corresponding pixel group.

[0007] When the floating diffusion regions of all the pixels included in the pixel group are shared, the signal line may transmit pixel signals at a voltage level corresponding to the combined charge of the charges photoelectrically converted by all the pixels, and when the floating diffusion regions of all the pixels included in the pixel group are not shared, the signal line may transmit the pixel signals of the two or more pixels included in the pixel group with a time lag.

[0008] The pixel groups may include: a plurality of first pixel groups each generated by dividing the plurality of pixels and including two or more of the pixels sharing a floating diffusion region; and a second pixel group including two or more of the first pixel groups, and the signal line may be provided for each second pixel group to transmit pixel signals of all or some of the pixels included in the corresponding second pixel group.

[0009] When the floating diffusion region of all the pixels included in the second pixel group is shared, the signal line may transmit a pixel signal that combines the charges photoelectrically converted by all the pixels, and when the floating diffusion region of all the pixels included in the second pixel group is not shared, the signal line may transmit the pixel signals for each of the two or more first pixel groups included in the second pixel group with a time lag.

[0010] A plurality of the signal lines corresponding to a plurality of the second pixel groups may be arranged in one direction.

[0011] The pixel array may include a transfer transistor provided for each of the plurality of pixels, and a reset transistor, a conversion efficiency switching transistor, an amplification transistor, and a selection transistor provided for each of the first pixel groups, and all of the selection transistors included in the corresponding second pixel groups may be connected to the signal line.

[0012] When the floating diffusion region is shared by all the pixels included in the second pixel group corresponding to the signal line, all the selection transistors connected to the signal line may be turned on.

[0013] When the floating diffusion region is not shared by all of the pixels included in the second pixel group corresponding to the signal line, the plurality of selection transistors connected to the signal line may be sequentially turned on.

[0014] For each of the second pixel groups, all of the conversion efficiency switching transistors included in the second pixel group may be turned on, thereby sharing all of the floating diffusion regions included in the second pixel group.

[0015] The plurality of conversion efficiency switching transistors, the plurality of reset transistors, the plurality of amplification transistors, and the plurality of selection transistors included in the second pixel group corresponding to the signal line may be arranged symmetrically on both sides of the direction in which the signal line extends.

[0016] The pixel array may include a first transistor group arranged along a first direction and including all of the reset transistors and the conversion efficiency switching transistors included in the second pixel group; and a second transistor group arranged along the first direction and spaced apart from the first transistor group in a second direction intersecting the first direction, including all of the amplification transistors and the selection transistors included in the second pixel group.

[0017] The pixel may include a plurality of first transistor groups and a plurality of second transistor groups that are alternately arranged and spaced apart in the second direction, and the photoelectric conversion elements and the floating diffusion regions of the plurality of pixels may be arranged between the first transistor groups and the second transistor groups that are adjacent to each other in the second direction.

[0018] The plurality of amplification transistors and the selection transistors included in the second pixel group corresponding to the signal line, and the plurality of reset transistors and the plurality of conversion efficiency switching transistors included in the corresponding second pixel group may be arranged in a direction inclined from the first direction and the second direction relative to the plurality of photoelectric conversion elements included in the corresponding second pixel group.

[0019] The plurality of amplification transistors and the selection transistors included in the second pixel group corresponding to the signal line, and the plurality of reset transistors and the plurality of conversion efficiency switching transistors included in the corresponding second pixel group may be arranged on both sides of the plurality of photoelectric conversion elements included in the corresponding second pixel group, sandwiched between them.

[0020] The second pixel groups may include: a plurality of first pixel columns arranged along the first direction and spaced apart in a second direction intersecting the first direction, each having a plurality of the pixels; a plurality of second pixel columns arranged along the first direction between the plurality of first pixel columns arranged in the second direction, each having a plurality of the pixels; and the first transistor group or the second transistor group may be arranged between the first pixel column and the second pixel column adjacent to each other in the second direction.

[0021] The first pixel group may include the same or different numbers of pixels in a first direction and a second direction that intersect with each other.

[0022] The second pixel group may include the same or different numbers of pixels in a first direction and a second direction that intersect with each other.

[0023] At least some of the pixels included in the plurality of pixels may have two sub-pixels that detect a phase difference.

[0024] According to the present disclosure, there is provided an electronic device including: the photodetector described above; and a processing unit that performs predetermined image processing on image data generated based on pixel signals detected by the photodetector.

[0025] 5 is a block diagram of an electronic device including a photodetector according to an embodiment of the present disclosure. FIG. 6 is a schematic perspective view showing an example of a photodetector according to the present disclosure having a two-layer stacked structure. FIG. 7 is a schematic perspective view showing an example of a photodetector according to the present disclosure having a three-layer structure. FIG. 8 is a block diagram showing the overall configuration of a photodetector according to the present disclosure. FIG. 9 is a circuit diagram of a pixel circuit connected to a second pixel group. FIG. 10 is a circuit diagram of a pixel circuit according to a comparative example. FIG. 11 is a diagram explaining a problem of the pixel circuit according to the comparative example shown in FIG. 5. FIG. 12 is a potential diagram of a pixel circuit according to a comparative example. FIG. 13 is a diagram explaining a decrease in frame rate. FIG. 14 is a diagram showing a pixel layout of a photodetector according to the present embodiment. FIG. 15 is a diagram showing a second pixel group including two first pixel groups aligned in a first direction. FIG. 16 is a diagram showing an example in which each pixel included in the first pixel group is composed of two phase difference detection pixels. FIG. 17 is a diagram showing an example in which vertical signal lines are arranged in a first direction. FIG. 18 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0026] Hereinafter, embodiments of a light detection device and electronic equipment will be described with reference to the drawings. The following description will focus on the main components of the light detection device and electronic equipment, but the light detection device and electronic equipment may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0027] 1 is a block diagram of an electronic device 30 including a photodetector 1 according to an embodiment of the present disclosure. The electronic device 30 has a function of generating an image according to the luminance of incident light. The electronic device 30 in FIG. 1 includes the photodetector 1, an imaging lens 31, an image processing unit 32, a recording unit 33, and a control unit 34. The electronic device 30 can be applied to various electronic devices, such as a surveillance camera or a camera mounted on an industrial robot, or a camera for general use, but the specific use and configuration of the electronic device 30 are arbitrary.

[0028] The imaging lens 31 collects incident light and guides it to the photodetector 1. The photodetector 1 captures an image of the incident light. The photodetector 1 causes light within a predetermined wavelength range, such as visible light or infrared light, to be incident on multiple pixels, performing photoelectric conversion, and accumulating charges in a floating diffusion region according to the amount of incident light. The charges accumulated in the floating diffusion region are converted into voltage, generating pixel signals with voltage levels according to the amount of incident light. The photodetector 1 generates image data frame by frame based on the pixel signals of each pixel.

[0029] The photodetector 1 according to this embodiment has a plurality of pixels for detecting gradation information or luminance information, and may also include pixels for an Event Vision Sensor (EVS) that detects a change in the amount of incident light as an event.

[0030] The image processing unit 32 performs predetermined image processing such as color or brightness adjustment, image compression, image recognition, tracking, or analysis on the image data generated by the light detection device 1. The image data processed by the image processing unit 32 is recorded in the recording unit 33, for example.

[0031] The recording unit 33 records the image data output from the light detection device 1 or the image processing unit 32. The recording unit 33 may be disposed in a server connected via a network. In the electronic device 30 according to this embodiment, at least one of the image processing unit 32 and the recording unit 33 in FIG. 1 can be omitted.

[0032] The control unit 34 controls the operation of the light detection device 1. Although not specifically shown in FIG.

[0033] (Two-Layer Stacking) The photodetector 1 according to the present disclosure can be realized as a stacked chip. FIG. 2A is a schematic perspective view illustrating an example of a two-layer stacked photodetector 1 according to the present disclosure. The photodetector 1 in FIG. 2A includes a first substrate SB1 disposed on the light incident surface side and a second substrate SB2 stacked on the first substrate SB1. For example, a photoelectric conversion element for each pixel is disposed on the first substrate SB1. This specification mainly describes an example in which the photoelectric conversion element is a photodiode. Peripheral circuits (e.g., transfer transistors, etc.) for the photodiode may also be disposed on the first substrate SB1. Multiple transistors for generating event signals are disposed on the second substrate SB2. The first substrate SB1 and the second substrate SB2 are bonded and transmit signals, for example, via a copper-copper connection (CCC). Alternatively, the first substrate SB1 and the second substrate SB2 may be bonded using vias or bumps other than CCC. In this specification, the first substrate SB1 may be referred to as a pixel chip, and the second substrate SB2 may be referred to as a logic chip.

[0034] (Three-Layer Stacking) The photodetector 1 according to the present disclosure can be configured by stacking three or more substrates. FIG. 2B is a schematic perspective view showing an example of a three-layer structure of the photodetector 1 according to the present disclosure. FIG. 2B shows an example of a stacked structure of the photodetector 1 including a first substrate SB1, a second substrate SB2, and a third substrate SB3. The first substrate SB1 is provided with a photoelectric conversion element for each pixel. The second substrate SB2 is provided with, for example, a pixel transistor. The third substrate SB3 is provided with, for example, a signal processing circuit.

[0035] The circuit elements and the like arranged on the first substrate SB1, the second substrate SB2, and the third substrate SB3 are arbitrary and may be combined in any desired manner.

[0036] Fig. 3 is a block diagram showing the overall configuration of the photodetector 1 according to the present disclosure. The photodetector 1 shown in Fig. 3 shows the block configuration of a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0037] The photodetector device 1 in FIG. 3 includes a pixel array section 2 and a peripheral circuit section 3 .

[0038] The pixel array unit 2 has a plurality of pixels 4 arranged two-dimensionally in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. Each pixel 4 has a photoelectric conversion element, a floating diffusion region, a transfer transistor, a pixel transistor, etc. This embodiment is characterized in that two or more pixels 4 can share a floating diffusion region.

[0039] A plurality of row selection lines LS and a plurality of vertical signal lines VSL are arranged in the pixel array section 2. One of the row selection lines LS and one of the vertical signal lines VSL are connected to each pixel 4. The plurality of row selection lines LS extend in a first direction X and are arranged at intervals in a second direction Y. The plurality of vertical signal lines VSL extend in the second direction Y and are arranged at intervals in the first direction X.

[0040] The peripheral circuit section 3 has a row selection section 5 , a constant current source section 6 , an analog-to-digital conversion section 7 , a horizontal transfer scanning section 8 , a signal processing section 9 , a timing control section 10 , and a reference signal generation section 11 .

[0041] The row selection unit 5 sequentially drives a plurality of row selection lines LS. The row selection unit 5 includes a shift register and an address decoder (not shown). The row selection unit 5 performs readout scanning and sweep-out scanning. In readout scanning, the row selection lines LS are sequentially driven. Pixel signals corresponding to charges photoelectrically converted in each pixel 4 on the driven row selection line LS are output to the corresponding vertical signal line VSL. In sweep-out scanning, the row selection line LS of the readout row is driven before the start of an exposure period that is performed before the start of readout scanning, thereby discharging the charges of each pixel 4.

[0042] The constant current source unit 6 has a plurality of current sources connected to a plurality of vertical signal lines VSL. Each current source has, for example, a MOS transistor, and supplies a bias current to each vertical signal line VSL.

[0043] The analog-to-digital converter 7 converts the pixel signals on the vertical signal lines VSL into digital signals. The analog-to-digital converter 7 has a comparator, a counter, and a latch (not shown in FIG. 3) for each of the vertical signal lines VSL.

[0044] Each comparator compares the pixel signal on the corresponding vertical signal line VSL with the reference signal generated by the reference signal generation unit 11. Each counter stops counting when the pixel signal and the reference signal match in the corresponding comparator. Each latch holds the count value when the corresponding counter stops counting. A digital signal is generated by analog-to-digital conversion of the pixel signal based on the count value held in the latch.

[0045] The horizontal transfer scanning unit 8 controls the transfer of the digital signals converted from analog to digital by the analog to digital conversion unit 7. The horizontal transfer scanning unit 8 includes a shift register, an address decoder, and the like.

[0046] The signal processing unit 9 generates image data for each frame based on the digital signal of each pixel 4 transferred by the horizontal transfer scanning unit 8. For example, the signal processing unit 9 performs digital signal processing such as correction of vertical line defects and point defects, and adjustment of brightness and gradation levels.

[0047] The timing control unit 10 generates various timing signals, clock signals, control signals, etc., and uses these signals to drive and control the row selection unit 5, constant current source unit 6, reference signal generation unit 11, analog-to-digital conversion unit 7, horizontal transfer scanning unit 8, and signal processing unit 9, etc.

[0048] The photodetector 1 according to this embodiment is characterized in that a floating diffusion region is shared by a first pixel group IG1 including two or more pixels 4, and a floating diffusion region is shared by each second pixel group IG2 including two or more first pixel groups IG1, and pixel signals from all or some of the pixels 4 included in the corresponding second pixel group IG2 are transmitted via a single signal line provided for each second pixel group IG2. Hereinafter, the signal line may be referred to as a vertical signal line VSL.

[0049] In this way, in the photodetection device 1 according to this embodiment, when each of the multiple vertical signal lines VSL shares the floating diffusion regions of all the pixels 4 included in the second pixel group IG2, it transmits a pixel signal that combines the charges photoelectrically converted in all the pixels 4, and when each of the multiple vertical signal lines VSL does not share the floating diffusion regions of all the pixels 4 included in the second pixel group IG2, it transmits the pixel signals of each of the two or more first pixel groups IG1 included in the second pixel group IG2 with a time lag.

[0050] The vertical signal lines VSL corresponding to the second pixel groups IG2 are arranged in one direction, for example. The second pixel groups IG2, the first pixel groups IG1 included in the second pixel groups IG2, and the pixel transistors connected to the second pixel groups IG2 are arranged in the direction in which the vertical signal lines VSL extend.

[0051] 4 is a circuit diagram of a pixel circuit 20 connected to the second pixel group IG2 in the photodetector 1 according to this embodiment. In the pixel circuit 20 in Fig. 4, a floating diffusion region FD is shared by a first pixel group IG1 including four pixels 4, and the floating diffusion region FD is shared by a second pixel group IG2 including two first pixel groups IG1.

[0052] Of the two first pixel groups IG1 included in the second pixel group IG2, one first pixel group IG1 has four photodiodes PD0 to PD3 and four transfer transistors TRG0 to TRG3, and the other first pixel group IG1 has four photodiodes PD4 to PD7 and four transfer transistors TRG4 to TRG7.

[0053] The four floating diffusion regions FD0 connected to one end (e.g., sources) of the four transfer transistors TRG0 to TRG3 are connected to each other and shared. Similarly, the four floating diffusion regions FD1 connected to one end (e.g., sources) of the four transfer transistors TRG4 to TRG7 are connected to each other and shared.

[0054] 4 , one of the two first pixel groups IG1 includes a floating diffusion region FD0, a reset transistor RST0, a conversion efficiency switching transistor FDG0, an amplifier transistor AMP0, and a select transistor SEL0, while the other first pixel group IG1 includes a floating diffusion region FD1, a reset transistor RST1, a conversion efficiency switching transistor FDG1, an amplifier transistor AMP1, and a select transistor SEL1. The sources of the two select transistors SEL0 and SEL1 are connected to a common vertical signal line VSL0. In this way, all of the select transistors SEL0 and SEL1 included in the corresponding second pixel group IG2 are connected to the vertical signal line VSL0.

[0055] When performing FD linking, the two floating diffusion regions FD0, FD1 of the two first pixel groups IG1 are connected. To achieve this, the drains of the conversion efficiency switching transistors FDG0, FDG1 are connected to each other. The source of the conversion efficiency switching transistor FDG0 is connected to the floating diffusion region FD0, and the source of the conversion efficiency switching transistor FDG1 is connected to the floating diffusion region FD1. By turning on both the conversion efficiency switching transistors FDG0, FDG1, the floating diffusion regions FD0, FD1 are connected and shared.

[0056] The drain of the reset transistor RST0 is connected to the power supply voltage VDD node, and the source is connected to the floating diffusion region FD0. The drain of the reset transistor RST1 is connected to the power supply voltage VDD node, and the source is connected to the floating diffusion region FD1.

[0057] The gate of the amplifier transistor AMP0 is connected to the floating diffusion region FD0. The drain of the amplifier transistor AMP0 is connected to the power supply voltage VDD node, and the source is connected to the drain of the select transistor SEL0. The source of the select transistor SEL0 is connected to the vertical signal line VSL0.

[0058] The gate of the amplifier transistor AMP1 is connected to the floating diffusion region FD1. The drain of the amplifier transistor AMP1 is connected to the power supply voltage VDD node, and the source is connected to the drain of the select transistor SEL1. The source of the select transistor SEL1 is connected to the vertical signal line VSL0.

[0059] 4, when FD link is performed in the pixel circuit 20, both of the conversion efficiency switching transistors FDG0 and FDG1 are turned on, which connects the two floating diffusion regions FD0 and FD1 of the two first pixel groups IG1, and the second pixel group IG2 shares the floating diffusion regions FD0 and FD1.

[0060] 4, when FD link is performed in the pixel circuit 20, both of the two select transistors SEL0 and SEL1 are turned on. As a result, a pixel signal having a voltage level corresponding to the combined charge of the charges in the two floating diffusion regions FD0 and FD1 is supplied to the vertical signal line VSL0. In this way, when the floating diffusion regions of all the pixels included in the second pixel group IG2 corresponding to the signal line are shared, all of the select transistors SEL0 and SEL1 connected to the vertical signal line VSL0 are turned on.

[0061] Although only one vertical signal line VSL0 is shown in FIG. 4, the other vertical signal lines VSL also have the same configuration.

[0062] 4, when FD link is not performed, the conversion efficiency switching transistors FDG0 and FDG1 are turned off. As a result, the two floating diffusion regions FD0 and FD1 are no longer connected. In this state, when one of the selection transistors SEL0 and SEL1 is turned on, a pixel signal of a voltage level corresponding to the charge of one of the floating diffusion regions FD0 and FD1 is supplied to the vertical signal line VSL0.

[0063] In this way, when FD link is performed, the two conversion efficiency switching transistors FDG0 and FDG1 are both turned on, and the two selection transistors SEL0 and SEL1 are both turned on, so that a pixel signal with a voltage level corresponding to the combined charge resulting from photoelectric conversion in the two first pixel groups IG1 is supplied to the vertical signal line VSL0. When FD link is not performed, the two conversion efficiency switching transistors FDG0 and FDG1 are both turned off, and the two selection transistors SEL0 and SEL1 are alternately turned on. As a result, pixel signals with voltage levels corresponding to the charge resulting from photoelectric conversion in the two first pixel groups IG1 are supplied to the vertical signal line VSL0 with a time lag.

[0064] Fig. 5 is a circuit diagram of a pixel circuit 20a according to a comparative example. Similar to Fig. 4, the pixel circuit 20a according to the comparative example has a first pixel group IG1 including four pixels 4 sharing a floating diffusion region, and a second pixel group IG2 including two first pixel groups IG1 sharing a floating diffusion region. In Fig. 5, circuit elements common to Fig. 4 are assigned the same reference numerals.

[0065] 5 , a floating diffusion region FD0, a reset transistor RST0, a conversion efficiency switching transistor FDG0, an amplification transistor AMP0, and a selection transistor SEL0 are provided for one of the two first pixel groups IG1, and a floating diffusion region FD1, a reset transistor RST1, a conversion efficiency switching transistor FDG1, an amplification transistor AMP1, and a selection transistor SEL1 are provided for the other first pixel group IG1. The source of the selection transistor SEL0 is connected to a vertical signal line VSL0, and the source of the selection transistor SEL1 is connected to a vertical signal line VSL1.

[0066] When performing FD link in the pixel circuit 20a according to the comparative example, both of the conversion efficiency switching transistors FDG0 and FDG1 are turned on, and one of the selection transistors SEL0 and SEL1 is turned on and the other is turned off. For example, when the selection transistor SEL0 is turned on and the selection transistor SEL1 is turned off, a pixel signal having a voltage level corresponding to the combined charge of the eight pixels 4 included in the corresponding second pixel group IG2 is supplied to the vertical signal line VSL0. When the selection transistor SEL0 is turned off and the selection transistor SEL1 is turned on, a pixel signal having a voltage level corresponding to the combined charge of the eight pixels 4 included in the corresponding second pixel group IG2 is supplied to the vertical signal line VSL1.

[0067] In the pixel circuit 20a according to the comparative example, when the selection transistor is turned off, the diffusion layer connecting the drain of the selection transistor and the source of the amplification transistor becomes floating. The following describes the problems that arise when this diffusion layer becomes floating.

[0068] FIG. 6 is a diagram explaining the problem with the pixel circuit 20 a according to a comparative example shown in FIG. 5 , and FIG. 7 is a potential diagram of the pixel circuit 20 a according to a comparative example. FIG. 6 shows an example in which three floating diffusion regions FD in three pixels 4 arranged in the second direction Y are connected to perform FD linking. The right side of FIG. 6 shows the pixel 4 targeted for FD linking in the current horizontal line period, and the left side of FIG. 6 shows the pixel 4 targeted for FD linking in the previous horizontal line period. The right side of FIG. 6 shows an example in which the top row is the driving row and three floating diffusion regions FD in a total of three pixels 4 in the downward direction, including the pixel 4 in the top row, are connected to perform FD linking. The left side of FIG. 6 shows an example in which the second row from the top is the driving row and three floating diffusion regions FD in a total of three pixels 4 in the downward direction, including the pixel 4 in this row, are connected to perform FD linking.

[0069] During the previous horizontal line period, the select transistor SEL in the pixel 4 in the second row from the top was on, whereas during the current horizontal line period, the select transistor SEL in the pixel 4 in the second row from the top is off. When the select transistor SEL is turned off, the diffusion layer between the source of the amplifier transistor AMP and the drain of the select transistor SEL becomes floating, and electrons move from this diffusion layer toward the power supply voltage VDD node, increasing the potential of the diffusion layer. A parasitic capacitance is formed between this diffusion layer and the floating diffusion region FD connected to the gate of the amplifier transistor AMP. When the potential of the diffusion layer increases, the potential of the floating diffusion region FD also increases due to the influence of the parasitic capacitance. Therefore, when FD link is performed in the pixel circuit 20a according to the comparative example shown in FIG. 5 , the voltage level of the pixel signal supplied to the vertical signal line VSL increases as the potential of the floating diffusion region FD increases, which may result in visible black stripes in the captured image.

[0070] 7 shows the potential of the diffusion layer between the source of the amplifier transistor AMP and the drain of the select transistor SEL, and the potential of the amplifier transistor AMP and the select transistor SEL in the pixel 4 in the second row from the top of FIG. 6 . As shown, the pixel 4 in the second row from the top was the driving target during the previous horizontal line period, but is not the driving target during the current horizontal line period. Therefore, during the previous horizontal line period, the potential of the diffusion layer described above becomes a voltage level corresponding to the charge in the floating diffusion region FD connected to the gate of the amplifier transistor AMP. Meanwhile, during the current horizontal line period, the diffusion layer between the source of the amplifier transistor AMP and the drain of the select transistor SEL in this pixel 4 becomes floating, and electrons are discharged from this diffusion layer through the channel of the amplifier transistor AMP to the power supply voltage VDD node, raising the potential of this diffusion layer. Furthermore, because there is parasitic capacitance between this diffusion layer and the gate (floating diffusion region FD) of the amplifier transistor AMP, the potential of the floating diffusion region FD also rises.

[0071] As described above, in the pixel circuit 20a according to the comparative example shown in FIG. 5, two vertical signal lines VSL are connected to the second pixel group IG2 that is the target of the FD link, and one of the vertical signal lines VSL is set to floating, which may result in degradation of image quality, such as black streaks being visible in the captured image.

[0072] 5, it is conceivable to turn on both of the two selection transistors SEL connected to the two vertical signal lines VSL connected to the second pixel group IG2. In this case, the same pixel signal is output from the two vertical signal lines VSL, which causes a problem of a decrease in frame rate.

[0073] Fig. 8 is a diagram illustrating a decrease in frame rate. In the example of Fig. 6, a plurality of first pixel groups IG1, each including four pixels 4, are arranged along the first direction X and the second direction Y, and four vertical signal lines VSL are arranged between two first pixel groups IG1 adjacent to each other in the first direction X. The second pixel group IG2, including eight pixels 4 indicated by a bold frame in Fig. 6, is the target of the FD link. If pixel signals output from the second pixel group IG2 are simultaneously supplied to different vertical signal lines VSL, the other second pixel groups IG2 will be unable to supply pixel signals to these vertical signal lines VSL and will be forced to supply pixel signals at staggered times, resulting in a decrease in frame rate by half.

[0074] 9 is a diagram showing the pixel layout of the photodetector 1 according to this embodiment. As shown in Fig. 9 , a first pixel column 21 in which a plurality of first pixel groups IG1, each including four pixels 4, are arranged in a first direction X, a first transistor group 22 in which conversion efficiency switching transistors FDG and reset transistors RST are arranged alternately in the first direction X, a second pixel column 23 in which a plurality of first pixel groups IG1 are arranged in the first direction X, and a second transistor group 24 in which amplification transistors AMP and selection transistors SEL are arranged alternately in the first direction X are arranged in sequence in a second direction Y.

[0075] FIG. 9 illustrates a honeycomb-shaped dashed line. As shown by the dashed line, the first pixel group IG1 is connected to the conversion efficiency switching transistor FDG and reset transistor RST arranged diagonally, and the amplifier transistor AMP and select transistor SEL arranged diagonally. For example, the first pixel group IG1 in the thick frame BF1 in FIG. 9 is connected to the conversion efficiency switching transistor FDG and reset transistor RST in the thick frame BF2, and the amplifier transistor AMP and select transistor SEL in the thick frame BF3. Furthermore, the first pixel group IG1 in the thick frame BF4, which is an FD link target with the first pixel group IG1 in the thick frame BF1, is connected to the conversion efficiency switching transistor FDG and reset transistor RST in the thick frame BF5, and the amplifier transistor AMP and select transistor SEL in the thick frame BF6. The thick frames BF2 and BF5 and the thick frames BF3 and BF6 are arranged on either side of the thick frames BF1 and BF4, sandwiching them therebetween.

[0076] This allows pixel signals to be supplied to vertical signal lines VSL (not shown) extending in the second direction Y from between the thick frames BF3 and BF6.

[0077] The pixel layout in Fig. 9 matches the configuration of the pixel circuit 20 in Fig. 4. As can be seen from Fig. 9 and Fig. 4, the two first pixel groups IG1 included in the second pixel group IG2, the conversion efficiency switching transistor FDG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are arranged symmetrically on both sides of the vertical signal line VSL extending in the second direction Y.

[0078] Furthermore, by arranging the first transistor group 22, in which the conversion efficiency switching transistors FDG and the reset transistors RST are arranged alternately, and the second transistor group 24, in which the amplification transistors AMP and the selection transistors SEL are arranged alternately, at a distance from each other in the second direction Y, and by arranging the first pixel column 21, in which a plurality of first pixel groups IG1 are arranged in the first direction X, between the first transistor group 22 and the second transistor group 24, it is possible to make the wiring within the pixel circuit 20 as short as possible.

[0079] In the above-described embodiment, an example has been described in which a floating diffusion region is shared by a second pixel group including two or more first pixel groups, but the first pixel group may also be a 1×1 pixel group. In this case, the distinction between the first pixel group IG1 and the second pixel group IG2 is eliminated, and one signal line is provided for each pixel group including two or more pixels that share a floating diffusion region among the multiple pixels, and each signal line transmits pixel signals from all or some of the pixels included in the corresponding pixel group. In this case, if the floating diffusion regions of all pixels included in the pixel group are shared, each signal line transmits pixel signals of a voltage level corresponding to the combined charge obtained by photoelectrically converting all of the pixels. If the floating diffusion regions of all pixels included in the pixel group are not shared, the signal line transmits pixel signals from two or more pixels included in the pixel group with a time lag.

[0080] In the photodetection device 1 according to this embodiment, the number of pixels constituting the first pixel group IG1 is arbitrary, and may be 1 x 2 pixels or some other number besides the above-mentioned 4 x 4 pixels. That is, the first pixel group IG1 may be square pixels with the same number of pixels in the first direction X and the second direction Y, or rectangular pixels with different numbers of pixels in the first direction X and the second direction Y. Furthermore, the number and arrangement of the first pixel groups IG1 included in the second pixel group IG2 are also arbitrary.

[0081] 10A is a diagram showing a second pixel group IG2 including two first pixel groups IG1 aligned in a first direction X. In the first pixel group IG1 in Fig. 10A, one floating diffusion region FD is shared by a total of two pixels: two pixels in the first direction X and one pixel in the second direction Y. Furthermore, the second pixel group IG2 includes two first pixel groups IG1.

[0082] Each pixel 4 may be composed of two phase difference detection pixels 4. Fig. 10B is a diagram showing an example in which each of four pixels 4 included in a first pixel group IG1 is composed of two phase difference detection pixels 4L, 4R. Figs. 10A and 10B show an example in which two first pixel groups IG1 form a second pixel group IG2 and each second pixel group IG2 shares a floating diffusion region FD, but the number of first pixel groups IG1 included in the second pixel group IG2 is arbitrary.

[0083] 9 shows an example in which the vertical signal line VSL is arranged in the second direction Y, and the first pixel column 21, the first transistor group 22, the second pixel column 23, and the second transistor group 24 are arranged in the first direction X that intersects with the second direction Y. However, as shown in FIG. 10C , the vertical signal line VSL may be arranged in the first direction X, and the first pixel column 21, the first transistor group 22, the second pixel column 23, and the second transistor group 24 may be arranged in the second direction Y.

[0084] In this manner, in this embodiment, one signal line is provided for each pixel group including two or more pixels that share a floating diffusion region, and pixel signals from all or some of the pixels included in the corresponding pixel group are transmitted via this signal line. This prevents the diffusion layer between the amplification transistor and the selection transistor from floating during FD link, which causes the voltage level of the vertical signal line to rise, and also eliminates the risk of a decrease in frame rate during FD link.

[0085] Furthermore, in this embodiment, one vertical signal line VSL is provided for each second pixel group IG2 that includes two or more first pixel groups IG1, each including two or more pixels 4. This allows, when performing FD linking that shares all of the floating diffusion regions FD included in the second pixel group IG2, pixel signals of voltage levels corresponding to combined charges obtained by photoelectrically converting all of the pixels 4 included in the second pixel group IG2 to be supplied to the corresponding vertical signal line VSL. Furthermore, when FD linking is not performed, pixel signals for each of the two or more first pixel groups IG1 included in the second pixel group IG2 can be supplied to the vertical signal line VSL with a time lag.

[0086] According to this embodiment, one vertical signal line VSL is provided for each second pixel group IG2, so pixel signals can be supplied to each vertical signal line VSL without reducing the frame rate or degrading the image quality.

[0087] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0088] FIG. 11 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0089] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 11, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0090] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0091] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0092] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0093] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0094] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0095] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0096] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0097] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0098] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 11, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0099] FIG. 12 is a diagram showing an example of the installation position of the imaging unit 12031.

[0100] In FIG. 12, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0101] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0102] 12 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0103] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0104] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0105] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0106] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0107] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the components described above. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0108] The present technology can be configured as follows: (1) A photodetector device comprising: a plurality of pixels each having a photoelectric conversion element; and a signal line provided for each pixel group including two or more of the plurality of pixels that share a floating diffusion region, the signal line transmitting pixel signals of all or some of the pixels included in the corresponding pixel group. (2) The photodetector device described in (1), wherein the signal line transmits pixel signals of a voltage level corresponding to a combined charge of charges photoelectrically converted by all of the pixels included in the pixel group when the floating diffusion region is shared by all of the pixels included in the pixel group, and transmits pixel signals of the two or more pixels included in the pixel group with a time lag when the floating diffusion region is not shared by all of the pixels included in the pixel group. (3) The photodetector according to (1) or (2), wherein the pixel groups include: a plurality of first pixel groups each generated by dividing the plurality of pixels and including two or more of the pixels sharing a floating diffusion region; and a second pixel group including two or more of the first pixel groups, wherein the signal line is provided for each second pixel group to transmit pixel signals of all or some of the pixels included in the corresponding second pixel group. (4) The photodetector according to (3), wherein the signal line transmits a pixel signal obtained by combining charges photoelectrically converted by all of the pixels when the floating diffusion region of all the pixels included in the second pixel group is shared, and transmits pixel signals for each of the two or more first pixel groups included in the second pixel group with a time lag when the floating diffusion region of all the pixels included in the second pixel group is not shared. (5) The photodetector according to (3) or (4), wherein the signal lines corresponding to the plurality of second pixel groups are arranged in one direction. (6) The photodetector device according to any one of (3) to (5), further comprising: a transfer transistor provided for each of the plurality of pixels; and a reset transistor, a conversion efficiency switching transistor, an amplification transistor, and a selection transistor provided for each of the first pixel groups, wherein all of the selection transistors included in the corresponding second pixel groups are connected to the signal line.(7) The photodetector according to (6), wherein, when the floating diffusion regions of all the pixels included in the second pixel group corresponding to the signal line are shared, all the selection transistors connected to the signal line are turned on. (8) The photodetector according to (6), wherein, when the floating diffusion regions of all the pixels included in the second pixel group corresponding to the signal line are not shared, the selection transistors connected to the signal line are turned on sequentially. (9) The photodetector according to (7), wherein, for each second pixel group, all the floating diffusion regions included in the second pixel group are shared by turning on all the conversion efficiency switching transistors included in the second pixel group. (10) The photodetector according to any one of (6) to (9), wherein the conversion efficiency switching transistors, the reset transistors, the amplification transistors, and the selection transistors included in the second pixel group corresponding to the signal line are arranged symmetrically on both sides of the direction in which the signal line extends. (11) The photodetector according to any one of (6) to (10), comprising: a first transistor group arranged along a first direction and including all of the reset transistors and the conversion efficiency switching transistors included in the second pixel group; and a second transistor group arranged along the first direction and spaced apart from the first transistor group in a second direction intersecting the first direction, including all of the amplification transistors and the selection transistors included in the second pixel group. (12) The photodetector according to (11), comprising a plurality of the first transistor groups and a plurality of the second transistor groups alternately arranged and spaced apart in the second direction, and a plurality of the photoelectric conversion elements and a plurality of the floating diffusion regions included in the plurality of pixels are arranged between the first transistor group and the second transistor group adjacent to each other in the second direction.(13) The photodetector according to (11) or (12), wherein the plurality of amplification transistors and the selection transistors included in the second pixel group corresponding to the signal line, and the plurality of reset transistors and the plurality of conversion efficiency switching transistors included in the corresponding second pixel group, are arranged in a direction inclined from the first direction and the second direction with respect to the plurality of photoelectric conversion elements included in the corresponding second pixel group. (14) The photodetector according to (13), wherein the plurality of amplification transistors and the selection transistors included in the second pixel group corresponding to the signal line, and the plurality of reset transistors and the plurality of conversion efficiency switching transistors included in the corresponding second pixel group, are arranged on both sides of the plurality of photoelectric conversion elements included in the corresponding second pixel group, with the plurality of photoelectric conversion elements included in the corresponding second pixel group sandwiched therebetween. (15) The photodetector according to any one of (11) to (14), wherein the second pixel groups include: a plurality of first pixel columns arranged along the first direction and spaced apart in a second direction intersecting the first direction, each having a plurality of the pixels; a plurality of second pixel columns arranged along the first direction between the plurality of first pixel columns arranged in the second direction, each having a plurality of the pixels; and the first transistor group or the second transistor group is arranged between the first pixel column and the second pixel column adjacent to each other in the second direction. (16) The photodetector according to any one of (3) to (15), wherein the first pixel group includes the same or different numbers of the pixels in the first direction and the second direction intersecting each other. (17) The photodetector according to any one of (3) to (15), wherein the second pixel group includes the same or different numbers of the pixels in the first direction and the second direction intersecting each other. (18) The photodetector according to any one of (1) to (17), wherein at least some of the pixels included in the plurality of pixels have two sub-pixels that detect a phase difference. (19) An electronic device comprising: the photodetector according to any one of (1) to (17), and a processing unit that performs predetermined image processing on image data generated based on pixel signals detected by the photodetector.

[0109] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0110] REFERENCE SIGNS LIST 1 Photodetector, 2 Pixel array section, 3 Peripheral circuit section, 4 Pixel, 4L Phase difference detection pixel, 4R Phase difference detection pixel, 5 Row selection section, 6 Constant current source section, 7 Analog-to-digital conversion section, 8 Horizontal transfer scanning section, 9 Signal processing section, 10 Timing control section, 11 Reference signal generation section, 20, 20a Pixel circuit, 21 First pixel row, 22 First transistor group, 23 Second pixel row, 24 Second transistor group, 30 Electronic device, 31 Imaging lens, 32 Image processing section, 33 Recording section, 34 Control section

Claims

1. A photodetection device comprising: a plurality of pixels, each having a photoelectric conversion element; and a signal line provided for each pixel group including two or more of the plurality of pixels that share a floating diffusion region, the signal line transmitting pixel signals from all or some of the pixels in the corresponding pixel group.

2. The photodetection device according to claim 1, wherein the signal line transmits pixel signals at a voltage level corresponding to a combined charge obtained by photoelectric conversion of all of the pixels when the floating diffusion region is shared by all of the pixels included in the pixel group, and transmits pixel signals of the two or more pixels included in the pixel group with a time lag when the floating diffusion region is not shared by all of the pixels included in the pixel group.

3. The photodetection device according to claim 1, wherein the pixel groups comprise: a plurality of first pixel groups each including two or more of the pixels that are generated by dividing the plurality of pixels and share a floating diffusion region; and a second pixel group including two or more of the first pixel groups; and wherein the signal line is provided for each second pixel group to transmit pixel signals from all or some of the pixels included in the corresponding second pixel group.

4. The photodetection device according to claim 3, wherein the signal line transmits a pixel signal that combines charges photoelectrically converted by all of the pixels included in the second pixel group when the floating diffusion region of all of the pixels included in the second pixel group is shared, and transmits pixel signals for each of the two or more first pixel groups included in the second pixel group at different times when the floating diffusion region of all of the pixels included in the second pixel group is not shared.

5. The photodetector according to claim 3, wherein a plurality of the signal lines corresponding to a plurality of the second pixel groups are arranged in one direction.

6. The photodetector according to claim 3, comprising: a transfer transistor provided for each of the plurality of pixels; and a reset transistor, a conversion efficiency switching transistor, an amplification transistor, and a selection transistor provided for each of the first pixel groups, wherein all of the selection transistors included in the corresponding second pixel groups are connected to the signal line.

7. The photodetector device according to claim 6, wherein when the floating diffusion region is shared by all of the pixels included in the second pixel group corresponding to the signal line, all of the selection transistors connected to the signal line are turned on.

8. The photodetector device according to claim 6, wherein when the floating diffusion region of all of the pixels included in the second pixel group corresponding to the signal line is not shared, the multiple selection transistors connected to the signal line are sequentially turned on.

9. The photodetector according to claim 7, wherein, for each of the second pixel groups, all of the conversion efficiency switching transistors included in the second pixel group are turned on, thereby sharing all of the floating diffusion regions included in the second pixel group.

10. The photodetector device according to claim 6, wherein the plurality of conversion efficiency switching transistors, the plurality of reset transistors, the plurality of amplification transistors, and the plurality of selection transistors included in the second pixel group corresponding to the signal line are arranged symmetrically on both sides of the direction in which the signal line extends.

11. The photodetector according to claim 6, comprising: a first transistor group arranged along a first direction and including all of the reset transistors and the conversion efficiency switching transistors included in the second pixel group; and a second transistor group arranged along the first direction and spaced apart from the first transistor group in a second direction intersecting the first direction, including all of the amplification transistors and the selection transistors included in the second pixel group.

12. The photodetector according to claim 11, comprising a plurality of first transistor groups and a plurality of second transistor groups each arranged alternately and spaced apart in the second direction, and wherein the plurality of photoelectric conversion elements and the plurality of floating diffusion regions of the plurality of pixels are arranged between the first transistor groups and the second transistor groups adjacent to each other in the second direction.

13. The photodetector device according to claim 11, wherein the plurality of amplification transistors and the selection transistors included in the second pixel group corresponding to the signal line, and the plurality of reset transistors and the plurality of conversion efficiency switching transistors included in the corresponding second pixel group, are arranged in a direction inclined from the first direction and the second direction with respect to the plurality of photoelectric conversion elements included in the corresponding second pixel group.

14. The photodetector device according to claim 13, wherein the plurality of amplification transistors and the selection transistors included in the second pixel group corresponding to the signal line, and the plurality of reset transistors and the plurality of conversion efficiency switching transistors included in the corresponding second pixel group, are arranged on both sides of the plurality of photoelectric conversion elements included in the corresponding second pixel group, sandwiching them therebetween.

15. The photodetector device of claim 11, wherein the second pixel groups comprise: a plurality of first pixel columns arranged along the first direction and spaced apart in a second direction intersecting the first direction, each having a plurality of the pixels; a plurality of second pixel columns arranged along the first direction between the plurality of first pixel columns arranged in the second direction, each having a plurality of the pixels; and the first transistor group or the second transistor group is arranged between the first pixel column and the second pixel column adjacent to each other in the second direction.

16. The photodetection device according to claim 3, wherein the first pixel group includes the same or different numbers of pixels in a first direction and a second direction that intersect with each other.

17. The photodetection device according to claim 3, wherein the second pixel group includes the same or different numbers of pixels in a first direction and a second direction that intersect with each other.

18. The photodetector according to claim 1, wherein at least some of the pixels included in the plurality of pixels have two sub-pixels that detect a phase difference.

19. An electronic device comprising: the photodetector according to claim 1; and a processing unit that performs predetermined image processing on image data generated based on pixel signals detected by the photodetector.

Images