Member for semiconductor manufacturing device and method for regenerating same

Abstract

This member 10 for a semiconductor manufacturing device comprises: a first ceramic plate 21 having a wafer-mounting surface 26 on the upper surface thereof; a second ceramic plate 22 disposed on the lower surface of the first ceramic plate 21; and a first amorphous layer 24 present between the first ceramic plate 21 and the second ceramic plate 22. The corrosion resistance of the first ceramic plate 21 is higher than the corrosion resistance of alumina and the second ceramic plate 22.

Description

Semiconductor manufacturing equipment components and their regeneration method

[0001] The present invention relates to a semiconductor manufacturing equipment member and a method for recycling the same.

[0002] Conventionally, semiconductor manufacturing equipment components are known that utilize plasma to perform CVD or etching on wafers. As disclosed in Patent Document 1, one such semiconductor manufacturing equipment component has a ceramic insulating layer formed on the upper surface of a ceramic dielectric layer in which an electrostatic electrode is embedded. The ceramic insulating layer is formed, for example, of a CVD film, a PVD film, an AD film, or a thermal spray film. The ceramic insulating layer has a wafer mounting surface on the upper surface. Furthermore, alumina is exemplified as a material for the ceramic insulating layer.

[0003] Patent No. 7214867

[0004] However, since alumina generally does not have a high corrosion resistance, the thickness of the alumina ceramic insulating layer can be reduced or the grain boundaries can be eroded by corrosive gases, shortening the life of the semiconductor manufacturing equipment components. Also, the bonding strength between the ceramic insulating layer and the ceramic dielectric layer can be insufficient.

[0005] The present invention has been made to solve the above-mentioned problems, and its main object is to extend the life of the product and increase the bonding strength between the ceramic plates.

[0006] [1] A semiconductor manufacturing equipment member of the present invention comprises: a first ceramic plate having a wafer mounting surface on an upper surface thereof; a second ceramic plate disposed on a lower surface of the first ceramic plate; and a first amorphous layer present between the first ceramic plate and the second ceramic plate, wherein the corrosion resistance of the first ceramic plate is higher than the corrosion resistance of alumina and the second ceramic plate.

[0007] In this semiconductor manufacturing equipment component, the corrosion resistance of the first ceramic plate, which has a wafer-receiving surface on its upper surface, is higher than that of the alumina and second ceramic plates. Therefore, the first ceramic plate can be prevented from thinning due to corrosive gases and from eroding grain boundaries. This extends the product's lifespan. Furthermore, the presence of the first amorphous layer between the first and second ceramic plates results in a relatively high bonding strength between the two plates.

[0008] In this specification, "upper" and "lower" do not represent absolute positional relationships, but rather relative positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0009] [2] In the semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member described in [1] above), the first ceramic plate may contain at least one selected from the group consisting of magnesium-aluminum oxynitride, YO, and TaZrO, and the second ceramic plate may contain AlO.

[0010] [3] In the semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member described in [2] above), the first ceramic plate may be formed of a material having magnesium-aluminum oxynitride as a main phase, the distance between the wafer chucking surface and the chucking electrode may be 0.33 mm or less, and the distance between the chucking electrode and the upper surface of the second ceramic plate may be 0.17 mm or more. This makes it possible to make the chucking force of the semiconductor manufacturing equipment member equal to or greater than that of a conventional product (a semiconductor manufacturing equipment member in which the space between the chucking electrode and the wafer chucking surface is made of alumina).

[0011] [4] The semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member according to any one of [1] to [3] above) may comprise a semiconductor manufacturing equipment member including: a first deteriorated layer present on a side of the first ceramic plate that contacts the first amorphous layer; and a second deteriorated layer present on a side of the second ceramic plate that contacts the first amorphous layer.

[0012] [5] The semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member according to any one of [1] to [4] above) may include a third ceramic plate disposed on the lower surface of the second ceramic plate, and a second amorphous layer present between the second ceramic plate and the third ceramic plate. In this case, the third ceramic plate may be formed of a material having a higher thermal conductivity than the second ceramic plate, or may be formed of a material having a lower purity than the second ceramic plate.

[0013] [6] In the semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member described in [5] above), a refrigerant flow path through which a refrigerant flows or a gas flow path for supplying a gas to the wafer mounting surface may be provided at a position of the second ceramic plate facing the second amorphous layer or at a position of the third ceramic plate facing the second amorphous layer.

[0014] [7] The semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member described in [5] or [6] above) may include a third deteriorated layer present on the side of the second ceramic plate that contacts the second amorphous layer, and a fourth deteriorated layer present on the side of the third ceramic plate that contacts the second amorphous layer.

[0015] [8] The method for recycling a semiconductor manufacturing equipment member of the present invention may include: (a) processing the upper surface of the first ceramic plate of the semiconductor manufacturing equipment member described in any one of [1] to [7] above to form a processed surface on the first ceramic plate from which the wafer-mounting surface has been removed; and (b) further processing the processed surface to form a new wafer-mounting surface.

[0016] [9] The method for recycling a semiconductor manufacturing equipment member of the present invention may include: (a) processing the upper surface of the first ceramic plate of the semiconductor manufacturing equipment member described in any one of [1] to [7] above to form a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; and (b) directly bonding a recycling ceramic plate having higher corrosion resistance than alumina and the second ceramic plate to the processed surface.

[0017] In this case, the regenerative fluororesin plate used in step (b) may not have a wafer mounting surface on its upper surface before direct bonding, and a wafer mounting surface may be formed on its upper surface after direct bonding, or a plate with a wafer mounting surface already formed on its upper surface before direct bonding may be directly bonded.

[0018]

[10] The method for recycling a semiconductor manufacturing equipment member of the present invention may include: (a) processing the first ceramic plate of the semiconductor manufacturing equipment member described in any one of [1] to [7] above to remove the first ceramic plate so as to expose the second ceramic plate, and forming a processed surface on the second ceramic plate; and (b) directly bonding a ceramic plate for recycling, which has higher corrosion resistance than alumina and the second ceramic plate, to the processed surface.

[0019] In this case, the ceramic plate for recycling used in step (b) may not have a wafer mounting surface on its upper surface before direct bonding, and a wafer mounting surface may be formed on its upper surface after direct bonding, or a plate with a wafer mounting surface already formed on its upper surface before direct bonding may be directly bonded.

[0020] A plan view of a semiconductor manufacturing equipment member 10. A cross-sectional view taken along line A-A in FIG. 1. A partially enlarged view of FIG. 2. An explanatory diagram of a polishing apparatus 50. A cross-sectional view of a semiconductor manufacturing equipment member 10 having a refrigerant flow path 70. A cross-sectional view of a semiconductor manufacturing equipment member 10 having a refrigerant flow path 70. A cross-sectional view of a semiconductor manufacturing equipment member 10 having a gas flow path 80. A cross-sectional view of a semiconductor manufacturing equipment member 10 having a gas flow path 80. A regeneration process diagram for a semiconductor manufacturing equipment member 10. A regeneration process diagram for a semiconductor manufacturing equipment member 10. A regeneration process diagram for a semiconductor manufacturing equipment member 10.

[0021] A preferred embodiment of the present invention will be described below with reference to the drawings, in which: Fig. 1 is a plan view of a semiconductor manufacturing equipment member 10, Fig. 2 is a cross-sectional view taken along line AA in Fig. 1, and Fig. 3 is an enlarged view of a portion of Fig. 2.

[0022] As shown in FIG. 2, the semiconductor manufacturing equipment member 10 includes a ceramic plate stack 20, a cooling plate 30, and an adhesive sheet 40.

[0023] The ceramic plate stack 20 is a three-layer ceramic disk. The ceramic plate stack 20 includes a first ceramic plate 21 having a wafer mounting surface 26 on its upper surface, a second ceramic plate 22 disposed on the lower surface of the first ceramic plate 21, and a third ceramic plate 23 disposed on the lower surface of the second ceramic plate 22. A first amorphous layer 24 is present between the first ceramic plate 21 and the second ceramic plate 22, and a second amorphous layer 25 is present between the second ceramic plate 22 and the third ceramic plate 23. When measured by XRD, the first amorphous layer 24 exhibits a broader peak than the first ceramic plate 21 and the second ceramic plate 22, and the second amorphous layer 25 exhibits a broader peak than the second ceramic plate 22 and the third ceramic plate 23. In a cross-sectional magnification image of the ceramic plate stack 20 observed at 4,000,000 magnification using a transmission electron microscope (TEM), the first and second amorphous layers 24, 25 are observed as thin bands. The first amorphous layer 24 may be formed as a single layer or as multiple layers (e.g., three layers). This also applies to the second amorphous layer 25. To enhance the bonding strength between the first ceramic plate 21 and the second ceramic plate 22 and between the second ceramic plate 22 and the third ceramic plate 23, the average thicknesses t1, t2 of the first and second amorphous layers 24, 25 are preferably 0.1 nm or greater, more preferably 1 nm or greater. Furthermore, to prevent the inclusion of different materials, the average thicknesses t1, t2 of the first and second amorphous layers 24, 25 are preferably 30 nm or less, more preferably 20 nm or less. Therefore, the average thicknesses t1 and t2 of the first and second amorphous layers 24 and 25 are preferably, for example, 0.1 nm to 30 nm, and more preferably 1 nm to 20 nm. When the first amorphous layer 24 is composed of multiple layers, the thickness of the first amorphous layer 24 refers to the total thickness of the multiple layers. This also applies to the second amorphous layer 25.

[0024] The average thicknesses t1 and t2 of the first and second amorphous layers 24 and 25 obtained by TEM observation are measured as follows: On a TEM photograph (magnification: 4,000,000 times) of one field of view, the thicknesses of the first and second amorphous layers 24 and 25 are measured at five locations at 10-nm intervals along the bonding interface, and the average thicknesses of the first and second amorphous layers 24 and 25 in one field of view are calculated. Similar thickness measurements by TEM observation are performed on five fields of view, including near the center, the periphery, and the center of the radius when the semiconductor manufacturing equipment member 10 is viewed in plan, without bias. The average thickness t1 of the first amorphous layer 24 is calculated by dividing the sum of the average thicknesses of the first amorphous layer 24 in the five fields of view by the number of fields, which is five. The average thickness t2 of the second amorphous layer 25 is calculated by dividing the sum of the average thicknesses of the second amorphous layer 25 in the five fields of view by the number of fields, which is five.

[0025] The fact that the thin strip observed by TEM is an amorphous layer can be confirmed by observing a halo pattern that is wider inside the thin strip than on either side of the thin strip when X-ray diffraction (XRD) patterns are obtained for the inside of the thin strip and both sides (ceramic plates) of the thin strip. Usually, when X-ray diffraction (XRD) patterns are measured for both sides (ceramic plates) of the thin strip, diffraction patterns corresponding to the crystals of the material that makes up each ceramic plate are observed.

[0026] The upper surface of the first ceramic plate 21 serves as a wafer mounting surface 26 on which a wafer W is mounted. An annular seal band 26a is formed along the outer edge of the wafer mounting surface 26, and multiple circular small protrusions 26b are formed on the entire inner surface of the seal band 26a. The seal band 26a and the circular small protrusions 26b have the same height, e.g., several μm to several tens of μm (e.g., 50 μm). The diameter of the circular small protrusions 26b is, e.g., several hundreds of μm (e.g., 800 μm). The portion of the wafer mounting surface 26 not provided with the seal band 26a or the circular small protrusions 26b is referred to as the reference surface 26c. The corrosion resistance of the first ceramic plate 21 is higher than that of alumina and the second ceramic plate 22. The corrosion resistance may be resistance to halogen-based corrosive gases (e.g., at least one of NF3, CF4, ClF3, Cl2, BCl3, and HBr). For example, it is preferable that the first ceramic plate 21 has a smaller etch rate with respect to NF gas (a type of corrosive gas) used in plasma etching than the second ceramic plate 22. Furthermore, it is preferable that the first ceramic plate 21 is more stable than the second ceramic plate 22 in the atmosphere (e.g., acidic or alkaline atmosphere) in which the semiconductor manufacturing equipment member 10 is used. Note that it is sufficient that the corrosion resistance of the first ceramic plate 21 is higher than that of the second ceramic plate 22 as a whole, and the second ceramic plate 22 may partially contain ceramics whose corrosion resistance is equal to or smaller than that of the first ceramic plate 21.

[0027] The second ceramic plate 22 is a ceramic circular plate whose mating surface with the first ceramic plate 21 has the same diameter as the first ceramic plate 21. The second ceramic plate 22 incorporates, from top to bottom, an absorbing electrode 27 and a heater electrode 28. The absorbing electrode 27 is a planar electrode connected to an external DC power supply via a power supply member (not shown). The absorbing electrode 27 may be a mesh electrode or a printed electrode. The power supply member is electrically insulated from the cooling plate 30. When a DC voltage is applied to the absorbing electrode 27, the wafer W is attracted and fixed to the wafer mounting surface 26 (specifically, the upper surfaces of the seal bands 26 a and the small circular protrusions 26 b) by electrostatic attraction. When the DC voltage is removed, the wafer W is released from the wafer mounting surface 26. The absorbing electrode 27 may be embedded in either the first ceramic plate 21 or the second ceramic plate 22, but is preferably embedded in a position where the absorbing electrode 27 will remain when the semiconductor manufacturing equipment component 10 is remanufactured. The heater electrode 28 is a resistance heating element formed so that, in a plan view, wiring extends from one of a pair of terminals across the entire wafer mounting surface 26 to the other of the pair of terminals, and the pair of terminals are connected to an external heater power supply via a power supply member (not shown). The power supply member is electrically insulated from the cooling plate 30. When power is supplied to the heater electrode 28 from the heater power supply, the heater electrode 28 generates heat and heats the wafer W on the wafer mounting surface 26.

[0028] The first ceramic plate 21 is preferably a plate containing at least one selected from the group consisting of magnesium-aluminum oxynitride, Y2O3, and TaZrO2, and the second ceramic plate 22 is preferably an alumina plate (e.g., an alumina plate with a purity of 99.5% by mass or more).

[0029] Examples of magnesium-aluminum oxynitride include the ceramic material described in Japanese Patent No. 5680664, i.e., a ceramic material primarily composed of magnesium, aluminum, oxygen, and nitrogen, which has a magnesium-aluminum oxynitride phase as its main phase and exhibits an XRD peak at least between 2θ = 47 and 50° (preferably between 2θ = 47 and 49°) when using CuKα radiation (the material may also have a subphase, a crystalline phase of MgO-AlN solid solution in which aluminum nitride is solid-solved in magnesium oxide). This material has a lower NF3 etch rate than alumina (see, for example, Table 1 in Japanese Patent No. 5680664). Here, the term "main phase" refers to a component that accounts for 50% or more by volume, and the term "subphase" refers to a phase other than the main phase that has an identified XRD peak. Since the area ratio in cross-sectional observation is considered to reflect the volume ratio, the main phase is defined as the region that accounts for 50% or more of the area in an EPMA elemental mapping image, and the subphase is defined as the region other than the main phase.

[0030] Examples of alumina plates with a purity of 99.5% by mass or more include the alumina plates shown in Example 5 and Comparative Examples 1 and 3 of Japanese Patent No. 5972630 and Experimental Examples 1 to 10 of Japanese Patent No. 6373212. These alumina plates have a high dielectric strength (70 kV / mm or more).

[0031] The third ceramic plate 23 is a ceramic circular plate having a step on its outer periphery, with the diameter of its upper portion being the same as that of the second ceramic plate 22 and the diameter of its lower portion being larger than that of the second ceramic plate 22. The third ceramic plate 23 is made of, for example, a material (e.g., an AlN sintered body) having a higher thermal conductivity than the second ceramic plate 22.

[0032] The first ceramic plate 21 has a first affected layer 21a on the side in contact with the first amorphous layer 24, and the second ceramic plate 22 has a second affected layer 22a on the side in contact with the first amorphous layer 24. For example, when XRD is measured, the first affected layer 21a exhibits a broader peak than the portion of the first ceramic plate 21 other than the first affected layer 21a, but a sharper peak than the first amorphous layer 24. For example, when XRD is measured, the second affected layer 22a exhibits a broader peak than the portion of the second ceramic plate 22 other than the second affected layer 22a, but a sharper peak than the first amorphous layer 24. In an enlarged cross-sectional image of the ceramic plate stack 20 taken by TEM, the first affected layer 21a is observed to have a different morphology from the portion of the first ceramic plate 21 other than the first affected layer 21a, and the second affected layer 22a is observed to have a different morphology from the portion of the second ceramic plate 22 other than the second affected layer 22a. The thickness of the first and second affected layers 21a, 22a is preferably 10 nm or more, and more preferably 100 nm or more and 1 μm or less.

[0033] The second ceramic plate 22 has a third affected layer 22b on the side in contact with the second amorphous layer 25, and the third ceramic plate 23 has a fourth affected layer 23b on the side in contact with the second amorphous layer 25. For example, when XRD is measured, the third affected layer 22b exhibits a broader peak than the portion of the second ceramic plate 22 other than the third affected layer 22b, but a sharper peak than the second amorphous layer 25. For example, when XRD is measured, the fourth affected layer 23b exhibits a broader peak than the portion of the third ceramic plate 23 other than the fourth affected layer 23b, but a sharper peak than the second amorphous layer 25. In an enlarged cross-sectional image of the ceramic plate stack 20 taken by TEM, the third affected layer 22b is observed to have a different morphology from the portion of the second ceramic plate 22 other than the third affected layer 22b, and the fourth affected layer 23b is observed to have a different morphology from the portion of the third ceramic plate 23 other than the fourth affected layer 23b. The thickness of the third and fourth affected layers 22b, 23b is preferably 10 nm or more, and more preferably 100 nm or more and 1 μm or less.

[0034] The cooling plate 30 is a circular plate with good thermal conductivity (a circular plate with a diameter equal to or larger than the diameter of the lower portion of the third ceramic plate 23 of the ceramic plate stack 20). A refrigerant flow path 32 through which a refrigerant circulates is formed within the cooling plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include a fluorine-based inert liquid. The refrigerant flow path 32 is formed in a single stroke across the entire cooling plate 30 in a plan view, from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port, respectively, of an external refrigerant device (not shown). The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, and is temperature-adjusted before being supplied again from the supply port to one end of the refrigerant flow path 32. The cooling plate 30 may also be used as an RF electrode.

[0035] The cooling plate 30 may be made of a material such as a metal or a composite material of metal and ceramic. Metallic materials include Al, Ti, Mo, and alloys thereof. Metal-ceramic composite materials include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also known as SiSiCTi), a porous SiC material impregnated with Al and / or Si, and a composite material of AlO and TiC. It is preferable to select a material for the cooling plate 30 that has a thermal expansion coefficient close to that of the material of the third ceramic plate 23.

[0036] The adhesive sheet 40 is a circular double-sided adhesive tape that bonds the lower surface of the ceramic plate stack 20 to the upper surface of the cooling plate 30. Examples of materials for the adhesive sheet 40 include epoxy resin, acrylic resin, and silicone resin. Note that a metal bonding layer may be used instead of the adhesive sheet 40.

[0037] The thickness d (see FIG. 3 ) of the ceramic portion 29 between the chucking electrode 27 and the wafer mounting surface 26 of the semiconductor manufacturing equipment member 10 may be set based on the capacitance C0 of alumina having a predetermined thickness d0 and a predetermined electrode area S0. Specifically, the thickness d of the ceramic portion 29 may be set so that the capacitance C of the ceramic portion 29 for the predetermined electrode area S0 is equal to or greater than the capacitance C0. For example, when the thickness d0 of the reference alumina (dielectric constant 10.4) is set to 0.35 mm, the first ceramic plate 21 is made of a ceramic material (dielectric constant 9.5) whose main phase is a magnesium-aluminum oxynitride phase and whose XRD peak appears at least at 2θ = 47 to 50° when using CuKα radiation, and the second ceramic plate 22 is made of alumina (dielectric constant 10.4), the distance d of the ceramic portion 29 is preferably 0.33 mm or less, and the distance d' (see FIG. 3 ) between the chucking electrode 27 and the upper surface of the second ceramic plate 22 is preferably 0.17 mm or greater. By doing so, the chucking force of the semiconductor manufacturing equipment member 10 can be made equal to or greater than that of a conventional product (a semiconductor manufacturing equipment member in which the space between the chucking electrode 27 and the wafer chucking surface 26 is made of alumina).

[0038] Next, an example of how the semiconductor manufacturing equipment component 10 configured as described above is described. First, with the semiconductor manufacturing equipment component 10 installed in a chamber (not shown), a wafer W is placed on the wafer mounting surface 26. The chamber is then depressurized using a vacuum pump to a predetermined vacuum level, and a DC voltage is applied to the attraction electrode 27 of the ceramic plate stack 20 to generate an electrostatic attraction force, thereby attracting and fixing the wafer W to the wafer mounting surface 26 (specifically, the upper surface of the seal band 26a or the upper surface of the small circular protrusions 26b). Next, a reactive gas atmosphere at a predetermined pressure (e.g., several tens to several hundreds of Pa) is created in the chamber. In this state, a high-frequency voltage is applied between an upper electrode (not shown) installed in the ceiling of the chamber and the cooling plate 30 of the semiconductor manufacturing equipment component 10 to generate plasma. The surface of the wafer W is treated with the generated plasma. A coolant is circulated through the coolant flow path 32 of the cooling plate 30. Furthermore, power is supplied to the heater electrode 28 to heat the wafer W as needed.

[0039] Next, a manufacturing example of the ceramic plate stack 20 will be described. First, the first ceramic plate 21 and the second ceramic plate 22 are fabricated. For example, the first ceramic plate 21 is fabricated by hot-pressing and firing a compact containing ceramic powder (e.g., a mixed powder of MgO powder, Al2O3 powder, and AlN powder, which are raw materials for a ceramic material having a magnesium-aluminum oxynitride phase as the main phase). This process allows the first ceramic plate 21 to be made into a dense body. The second ceramic plate 22 is fabricated by hot-pressing and firing a compact containing ceramic powder (e.g., alumina powder) in which the attraction electrodes 27 and heater electrodes 28 are embedded. This process allows the second ceramic plate 22 to be made into a dense body. The third ceramic plate 23 is fabricated by hot-pressing and firing a compact containing ceramic powder (e.g., aluminum nitride powder). This process allows the third ceramic plate 23 to be made into a dense body. At this stage, the first to third ceramic plates 21 to 23 do not have affected layers.

[0040] Next, the first ceramic plate 21 is subjected to lapping using a polishing apparatus 50 shown in FIG. 4 . The polishing apparatus 50 includes a large-diameter disc-shaped polishing table 52 equipped with a polishing pad 54, a small-diameter disc-shaped carrier 56, and a pipe 58 for supplying a slurry containing abrasive grains to the polishing pad 54. The polishing table 52 has a shaft at the center of its underside, which is rotated by a drive motor (not shown), causing it to rotate about its axis (spin). The carrier 56 has a shaft at the center of its upper surface, which is rotated by a drive motor (not shown), causing it to rotate about its axis (spin). The carrier 56 is positioned off-center on the polishing table 52. To polish the first ceramic plate 21 using this polishing apparatus 50, the first ceramic plate 21 is attached to the underside of the carrier 56, and the first ceramic plate 21 is sandwiched between the polishing pad 54 of the polishing table 52 and the carrier 56. A slurry containing abrasive grains is then supplied to the polishing pad 54 from the pipe 58. As a result, slurry is supplied between the first ceramic plate 21 and the polishing pad 54 of the polishing table 52. In this state, the first ceramic plate 21 is pressed against the polishing pad 54 by the carrier 56, while the polishing table 52 and the carrier 56 are rotated to perform polishing. The polishing conditions are set so that the surface roughness (arithmetic mean roughness) Ra of the underside of the first ceramic plate 21 is 1 nm or less. The surface roughness (arithmetic mean roughness) Ra of the polished surface is measured using a non-contact surface roughness meter in accordance with ISO 25178. Furthermore, a first affected layer 21a is formed on the polished surface side of the first ceramic plate 21.

[0041] The second ceramic plate 22 is subjected to lapping on both the upper and lower surfaces using a polishing device 50 in the same manner as the first ceramic plate 21. As a result, the surface roughness Ra of both surfaces of the second ceramic plate 22 becomes 1 nm or less. In addition, second and third affected layers 22a, 22b are formed on both surfaces of the second ceramic plate 22.

[0042] The smaller-diameter surface of the third ceramic plate 23 is subjected to lapping using a polishing device 50 in the same manner as the first ceramic plate 21. As a result, the surface roughness Ra of the polished surface of the third ceramic plate 23 becomes 1 nm or less. In addition, a fourth affected layer 23b is formed on the polished surface of the third ceramic plate 23.

[0043] Next, the surface (polished surface) of the first ceramic plate 21 on which the first altered layer 21a is formed and the surface (polished surface) of the second ceramic plate 22 on which the second altered layer 22a is formed are subjected to surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are appropriately adjusted, for example, within the range of a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. This removes oxides and adsorbed molecules from the surface of the first ceramic plate 21 on which the first altered layer 21a is formed and the surface of the second ceramic plate 22 on which the second altered layer 22a is formed, forming amorphous layers and activating the ceramic plates. Then, while maintaining the high vacuum condition, the first ceramic plate 21 and the second ceramic plate 22 are overlapped so that the surface on which the first altered layer 21a is formed and the surface on which the second altered layer 22a is formed face each other, and are bonded under pressure (direct bonding). The load during the application of pressure is set, for example, to 0.1 to 50 kN. This results in a bonded body in which the first ceramic plate 21 and the second ceramic plate 22 are bonded together. To improve the bonding strength of this bonded body, the bonded body may be subjected to a heat treatment. For example, the bonded body may be subjected to a heat treatment at about 100° C. after room-temperature bonding.

[0044] The surfaces (polished surfaces) of the second ceramic plate 22 on which the third altered layer 22b is formed and the third ceramic plate 23 on which the fourth altered layer 23b is formed are subjected to surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment) under high vacuum. This removes oxides and adsorbed molecules from the surfaces of the second ceramic plate 22 on which the third altered layer 22b is formed and the surfaces of the third ceramic plate 23 on which the fourth altered layer 23b is formed, thereby forming amorphous layers and activating the ceramic plates. Then, while maintaining the high vacuum condition, the second ceramic plate 22 and the third ceramic plate 23 are overlapped with each other so that the surfaces of the third altered layer 22b and the fourth altered layer 23b face each other, and are bonded under pressure (direct bonding). The FAB conditions and the pressure load are as described above. This results in a ceramic plate laminate 20. The ceramic plate laminate 20 may be heat-treated to improve the bonding strength of the ceramic plate laminate 20. For example, a heat treatment at about 100° C. may be performed after room temperature bonding.

[0045] The strength of the amorphous layer was compared with that of an AD film and a thermally sprayed film. An AD film was formed on the surface of a separately prepared MMC substrate (test piece). A cylindrical stud pin was fixed to the surface of the AD film with adhesive. An upward load (away from the AD film) was applied to the stud pin. At approximately 60 MPa, the AD film, not the bonding interface between the AD film and the test piece, fractured. A similar experiment was also conducted using a thermally sprayed film instead of the AD film. The thermally sprayed film also fractured at approximately 60 MPa. Meanwhile, a stud pin was fixed to the surface of the first ceramic plate 21 of the ceramic plate stack 20 with adhesive. An upward load was applied to the stud pin. At 70 MPa, the bonding interface between the stud pin and the ceramic plate fractured. This indicates that the amorphous layer has greater strength than an AD film or a thermally sprayed film.

[0046] In the semiconductor manufacturing equipment component 10 described above, the corrosion resistance of the first ceramic plate 21, which has the wafer mounting surface 26 on its upper surface, is higher than that of the alumina and second ceramic plate 22. Therefore, the first ceramic plate 21 can be prevented from being thinned or eroded at grain boundaries by corrosive gases. This extends the product's lifespan. Furthermore, the presence of the first amorphous layer 24 between the first ceramic plate 21 and the second ceramic plate 22 results in a relatively high bond strength between the plates 21 and 22. The presence of the second amorphous layer 25 between the second ceramic plate 22 and the third ceramic plate 23 also results in a relatively high bond strength between the plates 22 and 23.

[0047] Alternatively, the first ceramic plate 21 may contain at least one selected from the group consisting of magnesium-aluminum oxynitride, Y2O3, and TaZrO2, and the second ceramic plate 22 may contain Al2O3. This allows the corrosion resistance of the first ceramic plate 21 to be higher than that of alumina and the second ceramic plate 22.

[0048] Furthermore, since the third ceramic plate 23 is made of a material (such as an AlN sintered body) having a higher thermal conductivity than the second ceramic plate 22, the uniformity of heat distribution and heat dissipation of the wafer W are improved.

[0049] Furthermore, the semiconductor manufacturing equipment component 10 utilizes a laminate of the first and second ceramic plates 21, 22. Therefore, ceramic plates with different properties can be used as the first and second ceramic plates 21, 22. This allows the semiconductor manufacturing equipment component 10 to be easily adapted to the characteristics required.

[0050] It goes without saying that the present invention is not limited to the above-described embodiment, and can be embodied in various forms as long as they fall within the technical scope of the present invention.

[0051] For example, in the semiconductor manufacturing equipment component 10 described above, the ceramic plate stack 20 may have a refrigerant flow path 70 at a position of the second ceramic plate 22 facing the amorphous layer 25, as shown in FIG. 5 . Alternatively, the ceramic plate stack 20 may have a refrigerant flow path 70 at a position of the third ceramic plate 23 facing the amorphous layer 25, as shown in FIG. 6 . In FIGS. 5 and 6 , the same components as those in the above-described embodiment are denoted by the same reference numerals. The refrigerant flow path 70 is formed in a single stroke from one end (inlet) to the other end (outlet) across the entire wafer mounting surface 26 in a plan view. One end and the other end of the refrigerant flow path 70 are connected to a supply port and a recovery port of an external refrigerant device (not shown), respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 70 passes through the refrigerant flow path 70, returns from the other end of the refrigerant flow path 70 to the recovery port of the external refrigerant device, and is temperature-adjusted before being supplied again from the supply port to one end of the refrigerant flow path 70.

[0052] In the semiconductor manufacturing equipment member 10 described above, the ceramic plate stack 20 may have a gas flow path 80 at a position of the second ceramic plate 22 facing the amorphous layer 25, as shown in FIG. 7 . Alternatively, the ceramic plate stack 20 may have a gas flow path 80 at a position of the third ceramic plate 23 facing the amorphous layer 25, as shown in FIG. 8 . In FIGS. 7 and 8 , the same components as those in the above-described embodiment are denoted by the same reference numerals. The gas flow path 80 is an annular flow path concentric with the ceramic plate stack 20. The ceramic plate stack 20 includes a gas supply path 81 extending from the underside of the cooling plate 30 to the gas flow path 80, and gas ejection paths 82 opening from multiple locations of the gas flow path 80 to the reference surface 26 c of the wafer mounting surface 26. Gas (e.g., a thermally conductive gas such as He gas) supplied from gas supply path 81 to gas flow path 80 is filled through gas ejection path 82 into the space below wafer W (the space surrounded by the lower surface of wafer W, seal band 26a, small circular protrusions 26b, and reference surface 26c). The filled gas improves thermal conduction between wafer W and wafer mounting surface 26.

[0053] In the above-described embodiment, if the first ceramic plate 21 loses its original characteristics due to aging or the like, the semiconductor manufacturing equipment component 10 can be recycled and reused by the method for recycling the semiconductor manufacturing equipment component 10 shown in Figures 9 to 11. In Figures 9 to 11, the same components as those in the above-described embodiment are designated by the same reference numerals. Note that, for convenience, the bonding sheet 40 and the cooling plate 30 are omitted in Figures 9 to 11.

[0054] For example, in FIG. 9 , the upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 of the semiconductor manufacturing equipment component 10 ( FIG. 9A ) is machined and removed, while the lower portion of the first ceramic plate 21 remains ( FIG. 9B ). This results in a machined surface of the first ceramic plate 21 from which the wafer mounting surface 26 has been removed. Next, the machined surface of the first ceramic plate 21 is further machined to form a new wafer mounting surface 126 (seal band 126 a, small circular protrusions 126 b, and reference surface 126 c) ( FIG. 9C ). This results in a reusable semiconductor manufacturing equipment component 110. The machining method is not particularly limited, but examples include grinding and polishing. Other machining methods include blasting and laser processing. The wafer mounting surface 26 can also be masked before blasting to selectively remove the seal band 26 a and small circular protrusions 26 b that make up the wafer mounting surface 26. The new wafer mounting surface 126 (seal band 126a, small circular protrusion 126b, and reference surface 126c) can be formed by blasting or laser processing.

[0055] In FIG. 10 , the upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 of the semiconductor manufacturing equipment component 10 ( FIG. 10A ) is machined and removed, while the lower portion of the first ceramic plate 21 remains ( FIG. 10B ). This results in a machined surface of the first ceramic plate 21 from which the wafer mounting surface 26 has been removed. Next, a reclaimed ceramic plate 221, which has higher corrosion resistance than alumina and the second ceramic plate 22, is prepared ( FIG. 10C ). The reclaimed ceramic plate 221 has a wafer mounting surface 226 (seal band 226a, small circular protrusions 226b, and reference surface 226c) preformed on its upper surface. Next, the machined surface of the first ceramic plate 21 and the lower surface of the reclaimed ceramic plate 221 are lapped and polished. After surface activation treatment is performed on each polished surface, the two plates are bonded (direct bonding, FIG. 10D ). After bonding, an amorphous layer 224 is formed between the first ceramic plate 21 and the reclaimed ceramic plate 221. This results in a reusable semiconductor manufacturing equipment component 210. The recycled ceramic plate 221 may not have a wafer mounting surface 226. In this case, the recycled ceramic plate 221 may be bonded to the processed surface of the first ceramic plate 21, and then the wafer mounting surface 226 may be formed on the upper surface of the ceramic plate 221. The processing method is not particularly limited, but examples include grinding or polishing. Other processing methods include blasting and laser processing. While there is no problem if the recycled ceramic plate 221 has higher corrosion resistance than the second ceramic plate 22 and alumina, to reproduce the performance of the semiconductor manufacturing equipment component 10, it is preferable that the recycled ceramic plate 221 have the same composition as the first ceramic plate 21. The wafer mounting surface 226 can be formed by blasting, laser processing, or the like.

[0056] In FIG. 11 , the first ceramic plate 21 of the semiconductor manufacturing equipment component 10 ( FIG. 11A ) is machined and removed to expose the second ceramic plate 22 ( FIG. 11B ). Here, the first amorphous layer 24 is also ground and removed along with the first ceramic plate 21 (and the second altered layer 22a (see FIG. 3 ) may also be removed). This results in a machined surface (exposed surface) on the second ceramic plate 22. Next, a reclaimed ceramic plate 321, which has higher corrosion resistance than alumina and the second ceramic plate 22, is prepared ( FIG. 11C ). The reclaimed ceramic plate 321 has a wafer mounting surface 326 (seal band 326a, small circular protrusions 326b, and reference surface 326c) pre-formed on its upper surface. The exposed machined surface of the second ceramic plate 22 and the underside of the reclaimed ceramic plate 321 are then lapped and polished. After surface activation of the polished surfaces, the two are bonded (direct bonding, FIG. 11D ). After bonding, an amorphous layer 324 is formed between the reclaimed ceramic plate 321 and the second ceramic plate 22. This results in a reusable semiconductor manufacturing equipment component 310. The reclaimed ceramic plate 321 may not have a wafer mounting surface 326. In this case, the reclaimed ceramic plate 321 is bonded to the exposed processed surface of the second ceramic plate 22, and then the wafer mounting surface 326 is formed on the upper surface of the reclaimed ceramic plate 321. The processing method is not particularly limited, but examples include grinding or polishing. Other processing methods include blasting and laser processing. While there is no problem if the reclaimed ceramic plate 321 has higher corrosion resistance than the second ceramic plate 22 and alumina, to reproduce the performance of the semiconductor manufacturing equipment component 10, it is preferable that the reclaimed ceramic plate 321 have the same composition as the first ceramic plate 21. The wafer mounting surface 326 can be formed by blasting, laser processing, or the like.

[0057] In the ceramic plate stack 20 of the semiconductor manufacturing equipment member 10 described above, the third ceramic plate 23 is formed from a material with a higher thermal conductivity than the second ceramic plate 22, but the material is not limited to this. For example, the third ceramic plate 23 may be formed from a material with a lower purity than the second ceramic plate 22 (e.g., an alumina sintered body with a purity of 90 to 95% by mass). This allows the cost of the third ceramic plate 23 to be kept low.

[0058] The ceramic plate stack 20 of the semiconductor manufacturing equipment member 10 described above includes the third ceramic plate 23, but the third ceramic plate 23 may not be included.

[0059] In the semiconductor manufacturing equipment member 10 described above, the chucking electrode 27 and the heater electrode 28 are embedded in the second ceramic plate 22, but only one of the chucking electrode 27 and the heater electrode 28 may be embedded in the second ceramic plate 22. Alternatively, an RF electrode may also be embedded in the second ceramic plate 22. Moreover, instead of embedding the chucking electrode 27 in the second ceramic plate 22, the chucking electrode 27 may be embedded in the first ceramic plate 21.

[0060] In the semiconductor manufacturing equipment member 10 described above, a resistive heating element wired across the entire wafer mounting surface 26 is used as the heater electrode 28. However, for example, the wafer mounting surface 26 may be divided into multiple zones, and a heater electrode may be embedded in each zone so that power can be controlled independently.

[0061] In the semiconductor manufacturing equipment member 10 described above, at least one of the side surface of the ceramic plate stack 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be coated with an insulating film. Examples of the insulating film include a thermally sprayed film of alumina, yttria, or the like.

[0062] This application claims priority from Japanese Patent Application No. 2024-055227, filed on March 29, 2024, the entire contents of which are incorporated herein by reference.

[0063] The present invention can be used in semiconductor manufacturing equipment.

[0064] 10 Semiconductor manufacturing equipment member, 20 Ceramic plate laminate, 21 First ceramic plate, 21a First affected layer, 22 Second ceramic plate, 22a Second affected layer, 22b Third affected layer, 23 Third ceramic plate, 23b Fourth affected layer, 24 First amorphous layer, 25 Second amorphous layer, 26 Wafer mounting surface, 26a Seal band, 26b Small circular protrusion, 26c Reference surface, 27 Adsorption electrode, 28 Heater electrode, 29 Ceramic part, 30 Cooling plate, 32 Coolant flow path, 40 Adhesive sheet, 50 Polishing device, 52 Polishing surface plate, 54 Polishing pad, 56 Carrier, 58 Pipe, 70 Coolant flow path, 80 Gas flow path, 81 Gas supply path, 82 Gas ejection path.

Claims

1. A component for semiconductor manufacturing equipment comprising: a first ceramic plate having a wafer mounting surface on its upper surface; a second ceramic plate disposed on the lower surface of said first ceramic plate; and a first amorphous layer present between said first and second ceramic plates, wherein the corrosion resistance of said first ceramic plate is higher than the corrosion resistance of alumina and said second ceramic plate.

2. The semiconductor manufacturing equipment member according to claim 1, wherein the first ceramic plate contains at least one selected from the group consisting of magnesium-aluminum oxynitride, Y2O3, and TaZrO2, and the second ceramic plate contains Al2O3.

3. A semiconductor manufacturing equipment member according to claim 2, wherein the first ceramic plate is formed from a material having magnesium-aluminum oxynitride as a main phase, the distance between the wafer chucking surface and the chucking electrode is 0.33 mm or less, and the distance between the chucking electrode and the upper surface of the second ceramic plate is 0.17 mm or more.

4. A component for semiconductor manufacturing equipment according to claim 1 or 2, comprising: a first deteriorated layer present on the side of said first ceramic plate that contacts said first amorphous layer; and a second deteriorated layer present on the side of said second ceramic plate that contacts said first amorphous layer.

5. A component for semiconductor manufacturing equipment according to claim 1 or 2, comprising: a third ceramic plate disposed on the lower surface of the second ceramic plate; and a second amorphous layer present between the second ceramic plate and the third ceramic plate.

6. A semiconductor manufacturing equipment component according to claim 5, wherein a refrigerant flow path through which a refrigerant circulates or a gas flow path for supplying gas to the wafer mounting surface is provided at a position of the second ceramic plate facing the second amorphous layer or at a position of the third ceramic plate facing the second amorphous layer.

7. A component for semiconductor manufacturing equipment according to claim 5, comprising: a third deteriorated layer present on the side of said second ceramic plate that contacts said second amorphous layer; and a fourth deteriorated layer present on the side of said third ceramic plate that contacts said second amorphous layer.

8. A method for recycling a semiconductor manufacturing equipment component, comprising: (a) processing the upper surface of the first ceramic plate of the semiconductor manufacturing equipment component described in claim 1 or 2 to form a processed surface on the first ceramic plate from which the wafer-mounting surface has been removed; and (b) further processing the processed surface to form a new wafer-mounting surface.

9. A method for recycling a semiconductor manufacturing equipment component, comprising: (a) processing the upper surface of the first ceramic plate of the semiconductor manufacturing equipment component described in claim 1 or 2 to form a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; and (b) directly bonding a recycling ceramic plate, which has higher corrosion resistance than alumina and the second ceramic plate, to the processed surface.

10. A method for recycling a semiconductor manufacturing equipment component, comprising: (a) processing the first ceramic plate of the semiconductor manufacturing equipment component described in claim 1 or 2 to remove the second ceramic plate so as to expose the second ceramic plate, and forming a processed surface on the second ceramic plate; and (b) directly bonding a ceramic plate for recycling, which has higher corrosion resistance than alumina and the second ceramic plate, to the processed surface.

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