Testing method and testing device

Abstract

A test method according to one embodiment includes: a step of preparing a test circuit having first and second series circuits; a drive step of driving a first driven switch unit in the first series circuit by means of a two-pulse type first drive signal having first and second pulses, and driving a second driven switch unit in the second series circuit by means of a one-pulse type second drive signal having a third pulse; and a monitoring step of monitoring the voltage of the first driven switch unit and the voltage of a switch unit that is among the two switch units in the first series circuit and different from the second driven switch unit. The time difference between the rising timing of the second pulse and the falling timing of the third pulse is defined as an interference time, and conditions for oscillation to occur in the second driven switch unit are acquired while adjusting the interference time.

Description

Test method and test device

[0001] The present disclosure relates to a testing method and a testing apparatus.

[0002] Patent Document 1 discloses a drive circuit for a DC motor including a U-phase coil, a V-phase coil, and a W-phase coil. The drive circuit described in Patent Document 1 includes a three-phase inverter.

[0003] Japanese Patent Application Laid-Open No. 2022-134631

[0004] [Summary] One embodiment of the present disclosure relates to a test device and a test method that can easily test an oscillation state between phases in a power conversion device having multiple phases.

[0005] A testing method according to the present disclosure provides a testing circuit having: a first series circuit formed by connecting a first high-side switch unit and a first low-side switch unit in series between a high potential line and a low potential line electrically connected to a DC power supply unit; a second series circuit formed by connecting a second high-side switch unit and a second low-side switch unit in series between the high potential line and the low potential line and connected in parallel to the first series circuit between the high potential line and the low potential line; a capacitor connected between the high potential line and the low potential line to smooth a DC voltage supplied from the DC power supply unit; and an inductive load connecting a connection line between the first high-side switch unit and the first low-side switch unit and a connection line between the second high-side switch unit and the second low-side switch unit, wherein the first high-side switch unit has a plurality of first high-side transistors connected in parallel, the first low-side switch unit has a plurality of first low-side transistors connected in parallel, and the second high-side switch unit has a plurality of second high-side transistors connected in parallel. the second low-side switch unit has a plurality of second low-side transistors connected in parallel; a driving step of driving a first drive target switch unit, which is one of the first high-side switch unit and the first low-side switch unit, with a first drive signal, and driving a second drive target switch unit, which is one of the second high-side switch unit and the second low-side switch unit and is on a different side from the first drive target switch unit in terms of high side and low side, with a second drive signal, wherein the first drive signal is a two-pulse drive signal having a first pulse and a second pulse subsequent to the first pulse, and the second drive signal is a one-pulse drive signal having a third pulse, and a rising timing of the third pulse is within the first pulse; and a monitoring step of monitoring a voltage of the switch unit, which is one of the first high-side switch unit and the first low-side switch unit and is different from the second drive target switch unit, and monitoring a voltage of the second drive target switch unit,The time difference between the falling timing of the third pulse is set as an interference time, and the driving step and the monitoring step are performed while adjusting the interference time, thereby acquiring a condition for causing oscillation in the second drive target switch unit.

[0006] FIG. 1 is a schematic diagram of a system configuration of a power conversion device including a test object to be tested by a test method according to a first embodiment. FIG. 2 is a diagram illustrating an example of a switch unit included in the power conversion device shown in FIG. 1. FIG. 3 is a schematic diagram illustrating the general configuration of a test device according to the first embodiment. FIG. 4 is a diagram illustrating an example of the configuration of a high-side switch unit and a low-side switch unit included in a series circuit (first series circuit). FIG. 5 is a diagram illustrating an example of the configuration of a high-side switch unit and a low-side switch unit included in a series circuit (second series circuit). FIG. 6 is a timing chart illustrating an example of a waveform of a drive signal and a voltage waveform of a switch unit included in a test circuit according to the first embodiment. FIG. 7 is a flowchart of an example of a test method according to the first embodiment. FIG. 8 is a chart illustrating an example of changes in the first drive signal and the second drive signal resulting from adjustment of the interference time, and changes in voltage monitored by a monitor device. FIG. 9 is a schematic diagram illustrating the mechanism by which oscillation occurs. FIG. 10 is a diagram illustrating the relationship between interference time and the maximum surge voltage of the switch unit used to measure oscillation. Fig. 11 is a block diagram for explaining the schematic configuration of a test apparatus according to a second embodiment. Fig. 12 is a timing chart showing an example of a waveform of a drive signal and a waveform of a voltage of a switch section of a test circuit according to the second embodiment. Fig. 13 is a flowchart of an example of a test method according to the second embodiment. Fig. 14 is a diagram showing a modified example of the power conversion apparatus shown in Fig. 1. Fig. 15 is a block diagram showing a modified example of the test apparatus.

[0007] DETAILED DESCRIPTION Various exemplary embodiments will be described below with reference to the drawings. In the drawings, the same or equivalent parts are designated by the same reference numerals, and redundant description will be omitted.

[0008] First Embodiment Fig. 1 is a schematic diagram of a system configuration of a power conversion device including a test object to be tested by a test method according to a first embodiment. The power conversion device 1 is a device that converts power between direct current and alternating current. The power conversion device 1 is mounted on a vehicle such as a hybrid vehicle or an electric vehicle. The alternating current is multi-phase alternating current. Therefore, the power conversion device 1 is an n-phase power conversion device (n is 2 or more). Unless otherwise specified below, a configuration will be described in which n is 3 and the alternating current is three-phase alternating current having a U phase, a V phase, and a W phase.

[0009] As shown in FIG. 1 , the power conversion device 1 is disposed between an AC device (or AC circuit) driven by AC and a DC power supply unit 3 .

[0010] The DC power supply unit 3 includes a high-voltage DC power supply. An example of the rated voltage of the DC power supply unit 3 is 300 V or more and 900 V or less. The DC power supply unit 3 may be configured to be capable of storing electricity. Examples of the DC power supply unit 3 include a secondary battery and an electric double layer capacitor. Examples of the secondary battery include a nickel-metal hydride secondary battery and a lithium-ion secondary battery. The DC power supply unit 3 may be a battery that combines a secondary battery and an electric double layer capacitor. The DC power supply unit 3 may be an all-solid-state battery. The DC power supply unit 3 may include a DC / DC converter.

[0011] In the embodiment shown in Fig. 1, the AC device is a motor (rotating electric machine) 4 having coils (inductances) 4u, 4v, and 4w. Coil 4u is a U-phase coil corresponding to the U-phase. Coil 4v is a V-phase coil corresponding to the V-phase. Coil 4w is a W-phase coil corresponding to the W-phase. Coils 4u, 4v, and 4w are connected in a Y-connection, for example.

[0012] The power conversion device 1 includes a series circuit 10u, a series circuit 10v, and a series circuit 10w. The series circuits 10u, 10v, and 10w are electrically connected in parallel between a high-potential line 5 electrically connected to the positive electrode of the DC power supply unit 3 and a low-potential line 6 electrically connected to the negative electrode of the DC power supply unit 3.

[0013] Each of the series circuits 10u, 10v, and 10w has two switch units 11 connected in series between the high potential line 5 and the low potential line 6. Thus, the power conversion device 1 has six switch units 11. Each switch unit 11 has a first terminal (first main terminal) Td, a second terminal (second main terminal) Ts, and a third terminal (control terminal) Tg.

[0014] The power conversion device 1 has a driver circuit 12 corresponding to each of the six switch units 11. Thus, the power conversion device 1 has six driver circuits 12. The driver circuits 12 are circuits that generate control signals for controlling the switch units 11 in response to input signals from a control device 2. The control device 2 may be provided external to the power conversion device 1 or may be provided within the power conversion device 1. When the power conversion device 1 is mounted on, for example, a hybrid vehicle or an electric vehicle, an ECU (Electronic Control Unit) mounted on the vehicle may be used as the control device 2. The driver circuits 12 are electrically connected to third terminals Tg of the corresponding switch units 11 and input a drive signal to the third terminals Tg.

[0015] Each switch section 11 is configured to switch between an on state in which there is electrical continuity between the first terminal Td and the second terminal Ts, and an off state in which there is no electrical continuity between the first terminal Td and the second terminal Ts, depending on the drive signal input from the driver circuit 12 to the third terminal Tg.

[0016] When the six switch units 11 and the six driver circuits 12 of the power conversion device 1 are to be described separately, the switch units 11 and the driver circuits 12 will be referred to as follows.

[0017] Of the two switch units 11 included in the series circuit 10u, the switch unit 11 closer to the high potential line 5 is referred to as a high-side switch unit 11Hu, and the switch unit 11 closer to the low potential line 6 is referred to as a low-side switch unit 11Lu. The driver circuit 12 corresponding to the high-side switch unit 11Hu is referred to as a driver circuit 12Hu, and the driver circuit 12 corresponding to the low-side switch unit 11Lu is referred to as a driver circuit 12Lu.

[0018] Of the two switch units 11 included in the series circuit 10v, the switch unit 11 closer to the high potential line 5 is referred to as a high-side switch unit 11Hv, and the switch unit 11 closer to the low potential line 6 is referred to as a low-side switch unit 11Lv. The driver circuit 12 corresponding to the high-side switch unit 11Hv is referred to as a driver circuit 12Hv, and the driver circuit 12 corresponding to the low-side switch unit 11Lv is referred to as a driver circuit 12Lv.

[0019] Of the two switch units 11 included in the series circuit 10w, the switch unit 11 closer to the high potential line 5 is referred to as a high-side switch unit 11Hw, and the switch unit 11 closer to the low potential line 6 is referred to as a low-side switch unit 11Lw. The driver circuit 12 corresponding to the high-side switch unit 11Hw is referred to as a driver circuit 12Hw, and the driver circuit 12 corresponding to the low-side switch unit 11Lw is referred to as a driver circuit 12Lw.

[0020] In the series circuit 10u, the first terminal Td of the high-side switch unit 11Hu is electrically connected to the high-potential line 5, and the second terminal Ts of the high-side switch unit 11Hu is electrically connected to the first terminal Td of the low-side switch unit 11Lu. The second terminal Ts of the low-side switch unit 11Lu is electrically connected to the low-potential line 6. The series circuit 10u is a half-bridge circuit including the high-side switch unit 11Hu and the low-side switch unit 11Lu, and corresponds to the U-phase leg. A node (connection point) N1 between the high-side switch unit 11Hu and the low-side switch unit 11Lu corresponds to the output of the series circuit 10u and is electrically connected to the coil 4u. The third terminal Tg of the high-side switch unit 11Hu is electrically connected to the driver circuit 12Hu. The third terminal Tg of the low-side switch unit 11Lu is electrically connected to the driver circuit 12Lu.

[0021] In the series circuit 10v, the first terminal Td of the high-side switch unit 11Hv is electrically connected to the high-potential line 5, and the second terminal Ts of the high-side switch unit 11Hv is electrically connected to the first terminal Td of the low-side switch unit 11Lv. The second terminal Ts of the low-side switch unit 11Lv is electrically connected to the low-potential line 6. The series circuit 10v is a half-bridge circuit including the high-side switch unit 11Hv and the low-side switch unit 11Lv, and corresponds to the V-phase leg. A node (connection point) N2 between the high-side switch unit 11Hv and the low-side switch unit 11Lv corresponds to the output of the series circuit 10v and is electrically connected to the coil 4v. The third terminal Tg of the high-side switch unit 11Hv is electrically connected to the driver circuit 12Hv. The third terminal Tg of the low-side switch unit 11Lv is electrically connected to the driver circuit 12Lv.

[0022] In the series circuit 10w, the first terminal Td of the high-side switch unit 11Hw is electrically connected to the high-potential line 5, and the second terminal Ts of the high-side switch unit 11Hw is electrically connected to the first terminal Td of the low-side switch unit 11Lw. The second terminal Ts of the low-side switch unit 11Lw is electrically connected to the low-potential line 6. The series circuit 10w is a half-bridge circuit including the high-side switch unit 11Hw and the low-side switch unit 11Lw, and corresponds to the W-phase leg. A node (connection point) N3 between the high-side switch unit 11Hw and the low-side switch unit 11Lw corresponds to the output of the series circuit 10w and is electrically connected to the coil 4w. The third terminal Tg of the high-side switch unit 11Hw is electrically connected to the driver circuit 12Hw. The third terminal Tg of the low-side switch unit 11Lw is electrically connected to the driver circuit 12Lw.

[0023] The power conversion device 1 has three capacitors 13u, 13v, and 13w for smoothing the DC voltages supplied to the series circuits 10u, 10v, and 10w from the DC power supply unit 3. The capacitors 13u, 13v, and 13w are DC link capacitors.

[0024] Capacitor 13u is a capacitor corresponding to series circuit 10u, and is arranged in parallel with series circuit 10u between the high potential line 5 and the low potential line 6. Capacitor 13v is a capacitor corresponding to series circuit 10v, and is arranged in parallel with series circuit 10v between the high potential line 5 and the low potential line 6. Capacitor 13w is a capacitor corresponding to series circuit 10w, and is arranged in parallel with series circuit 10w between the high potential line 5 and the low potential line 6.

[0025] FIG. 2 is a diagram illustrating an example of the switch unit 11 included in the power conversion device 1 shown in FIG. 1 . The switch unit 11 includes a plurality of transistors 111 connected in parallel. The transistors 111 may be bipolar transistors, unipolar transistors, or the like. An example of a bipolar transistor is an insulated gate bipolar transistor (IGBT). An example of a unipolar transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). The transistors 111 may be power semiconductors. Examples of semiconductor materials for the transistors 111 include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). Hereinafter, unless otherwise specified, the transistors 111 are MOSFETs.

[0026] The drains of the plurality of transistors 111 are electrically connected to a first terminal Td. The sources of the plurality of transistors 111 are electrically connected to a second terminal Ts. The gates of the plurality of transistors 111 are electrically connected to a third terminal Tg. Therefore, when the switch unit 11 is regarded as a single MOSFET formed by the plurality of transistors 111 connected in parallel, the first terminal Td, the second terminal Ts, and the third terminal Tg correspond to the drain, the source, and the gate.

[0027] The series circuits 10u, 10v, and 10w may have different configurations, but hereinafter, unless otherwise specified, the series circuits 10u, 10v, and 10w have the same configuration, and the transistor 111 is a MOSFET.

[0028] Next, a test method and a test device according to a first embodiment will be described. The test method and the test device according to the first embodiment are a method and a device for performing a double pulse test. The test method and the test device are a method and a device for testing oscillation characteristics between a first phase and a second phase selected from three phases (U phase, V phase, and W phase) of the power conversion device 1. The second phase is a phase different from the first phase.

[0029] 3 is a block diagram illustrating a schematic configuration of a test apparatus according to an embodiment of the present invention. The test apparatus 100 shown in FIG.

[0030] [Test Circuit] The test circuit 20 includes a DC power supply unit 3a, a series circuit (first series circuit) 10a, a series circuit (second series circuit) 10b, and a coil (inductive load) 4ab. The DC power supply unit 3a may be the same as the DC power supply unit 3 shown in FIG. 1. The DC power supply unit 3a may be a power supply unit different from the DC power supply unit 3, as long as it can supply the same DC voltage as the DC power supply unit 3 to the series circuits 10a and 10b.

[0031] The series circuits 10a and 10b correspond to two series circuits selected from the series circuits 10u, 10v, and 10w. For example, if the series circuit 10a corresponds to the series circuit 10u, the series circuit 10b corresponds to the series circuit 10v or the series circuit 10w. The series circuits 10a and 10b are electrically connected in parallel between a high-potential line 5a electrically connected to the positive electrode of the DC power supply unit 3a and a low-potential line 6a electrically connected to the negative electrode of the DC power supply unit 3a.

[0032] The series circuit 10a includes a high-side switch unit (first high-side switch unit) 11Ha and a low-side switch unit (second low-side switch unit) 11La. The high-side switch unit 11Ha and the low-side switch unit 11La are the same as the switch unit 11 shown in FIG. 1 and include a first terminal Td, a second terminal Ts, and a third terminal Tg.

[0033] The first terminal Td of the high-side switch unit 11Ha is electrically connected to the high-potential line 5a. The second terminal Ts of the high-side switch unit 11Ha is connected to the first terminal Td of the low-side switch unit 11La by a connection line 21a. A part of the connection line 21a is a node Na of the high-side switch unit 11Ha and the low-side switch unit 11La, and corresponds to the output of the series circuit 10a. The second terminal Ts of the low-side switch unit 11La is electrically connected to the low-potential line 6a.

[0034] The second terminal Ts and the third terminal Tg of the high-side switch unit 11Ha are connected by a connection line 22a, that is, the second terminal Ts and the third terminal Tg of the high-side switch unit 11Ha are short-circuited.

[0035] The series circuit 10b includes a high-side switch unit (second high-side switch unit) 11Hb and a low-side switch unit (second low-side switch unit) 11Lb. The high-side switch unit 11Hb and the low-side switch unit 11Lb are the same as the switch unit 11 shown in FIG. 1 and include a first terminal Td, a second terminal Ts, and a third terminal Tg.

[0036] A first terminal Td of the high-side switch unit 11Hb is electrically connected to the high-potential line 5a. A second terminal Ts of the high-side switch unit 11Hb is connected to the first terminal Td of the low-side switch unit 11Lb by a connection line 21b. A part of the connection line 21b is a node Nb of the high-side switch unit 11Hb and the low-side switch unit 11Lb, and corresponds to the output of the series circuit 10b. A second terminal Ts of the low-side switch unit 11Lb is electrically connected to the low-potential line 6a.

[0037] The second terminal Ts and the third terminal Tg of the low-side switch unit 11Lb are connected by a connection line 22b, that is, the second terminal Ts and the third terminal Tg of the low-side switch unit 11Lb are short-circuited.

[0038] One end of the coil 4ab is connected to the node Na, and the other end of the coil 4ab is connected to the node Nb, so that the connection line 21a and the connection line 21b are connected by the coil 4ab.

[0039] The test circuit 20 has two capacitors 13a and 13b for smoothing the DC voltage supplied from the DC power supply unit 3a to the series circuits 10a and 10b. The capacitors 13a and 13b are known as DC link capacitors.

[0040] The capacitor 13a corresponds to the series circuit 10a and is arranged in parallel with the series circuit 10a between the high-potential line 5a and the low-potential line 6a. One end of the capacitor 13a is electrically connected to the first terminal Td of the high-side switch unit 11Ha, and the other end of the capacitor 13a is electrically connected to the second terminal Ts of the low-side switch unit 11La. One end of the capacitor 13a may be directly connected to the first terminal Td of the high-side switch unit 11Ha, and the other end of the capacitor 13a may be directly connected to the second terminal Ts of the low-side switch unit 11La. When the series circuit 10a is a module, one end of the capacitor 13a may be directly connected to an external connection terminal of the module corresponding to the first terminal Td of the high-side switch unit 11Ha, and the other end of the capacitor 13a may be directly connected to an external connection terminal of the module corresponding to the second terminal Ts of the low-side switch unit 11La.

[0041] Capacitor 13a may be the same as any one of capacitors 13u, 13v, and 13w so that the correspondence between capacitor 13a and series circuit 10a coincides with the correspondence between capacitors 13u, 13v, and 13w and series circuit 10u, 10v, and 10w shown in Figure 1. For example, when series circuit 10a corresponds to series circuit 10u, capacitor 13a may be the same as capacitor 13u.

[0042] The capacitor 13b corresponds to the series circuit 10b and is arranged in parallel with the series circuit 10b between the high-potential line 5a and the low-potential line 6a. One end of the capacitor 13b is electrically connected to the first terminal Td of the high-side switch unit 11Hb, and the other end of the capacitor 13b is electrically connected to the second terminal Ts of the low-side switch unit 11Lb. One end of the capacitor 13b may be directly connected to the first terminal Td of the high-side switch unit 11Hb, and the other end of the capacitor 13b may be directly connected to the second terminal Ts of the low-side switch unit 11Lb. When the series circuit 10b is a module, one end of the capacitor 13b may be directly connected to an external connection terminal of the module corresponding to the first terminal Td of the high-side switch unit 11Hb, and the other end of the capacitor 13b may be directly connected to an external connection terminal of the module corresponding to the second terminal Ts of the low-side switch unit 11Lb.

[0043] Capacitor 13b may be the same as any one of capacitors 13u, 13v, and 13w so that the correspondence between capacitor 13b and series circuit 10b coincides with the correspondence between capacitors 13u, 13v, and 13w and series circuit 10u, 10v, and 10w shown in Figure 1. For example, when series circuit 10b corresponds to series circuit 10v, capacitor 13b may be the same as capacitor 13v.

[0044] FIG. 4 is a diagram illustrating an example of the configuration of the high-side switch section 11Ha and the low-side switch section 11La included in the series circuit 10a.

[0045] The high-side switch unit 11Ha has a plurality of high-side transistors (first high-side transistors) 111Ha connected in parallel, as shown in Fig. 4. The low-side switch unit 11La has a plurality of low-side transistors (second low-side transistors) 111La connected in parallel, as shown in Fig. 4.

[0046] The high-side transistor 111Ha and the low-side transistor 111La are the same as the transistor 111 shown in Fig. 2. Therefore, in this embodiment, the high-side transistor 111Ha and the low-side transistor 111La are MOSFETs.

[0047] The drains, sources, and gates of the high-side transistors 111Ha are electrically connected to the first terminal Td, the second terminal Ts, and the third terminal Tg of the high-side switch unit 11Ha, respectively. In this connection, the first terminal Td, the second terminal Ts, and the third terminal Tg of the high-side switch unit 11Ha correspond to the drains, sources, and gates.

[0048] The drains, sources, and gates of the plurality of low-side transistors 111La are electrically connected to the first terminal Td, the second terminal Ts, and the third terminal Tg of the low-side switch unit 11La. In this connection relationship, the first terminal Td, the second terminal Ts, and the third terminal Tg of the low-side switch unit 11La correspond to the drains, sources, and gates.

[0049] FIG. 5 is a diagram illustrating an example of the configuration of the high-side switch section 11Hb and the low-side switch section 11Lb included in the series circuit 10b.

[0050] The high-side switch unit 11Hb has a plurality of high-side transistors (second high-side transistors) 111Hb connected in parallel, as shown in Fig. 5. The low-side switch unit 11Lb has a plurality of low-side transistors (second high-side transistors) 111Lb connected in parallel, as shown in Fig. 5.

[0051] The high-side transistor 111Hb and the low-side transistor 111Lb are the same as the transistor 111 shown in Fig. 2. Therefore, in this embodiment, the high-side transistor 111Hb and the low-side transistor 111Lb are MOSFETs.

[0052] The drains, sources, and gates of the high-side transistors 111Hb are electrically connected to the first terminal Td, the second terminal Ts, and the third terminal Tg of the high-side switch unit 11Hb, respectively. In this connection, the first terminal Td, the second terminal Ts, and the third terminal Tg of the high-side switch unit 11Hb correspond to the drains, sources, and gates.

[0053] The drains, sources, and gates of the low-side transistors 111Lb are electrically connected to the first terminal Td, the second terminal Ts, and the third terminal Tg of the low-side switch unit 11Lb, respectively. In this connection, the first terminal Td, the second terminal Ts, and the third terminal Tg of the low-side switch unit 11Lb correspond to the drains, sources, and gates.

[0054] As described above, the first terminal Td, the second terminal Ts, and the third terminal Tg of the high-side switch unit 11Ha, the low-side switch unit 11La, the high-side switch unit 11Hb, and the low-side switch unit 11Lb correspond to the drain, the source, and the gate. Therefore, in the following description, the first terminal Td, the second terminal Ts, and the third terminal Tg may be considered as the drain, the source, and the gate.

[0055] In the first embodiment, a double pulse test (specifically, a two-phase double pulse test) is performed by using the series circuit 10b of the test circuit 20 as a measurement phase and the series circuit 10a as an interference phase.

[0056] As shown in FIG. 6, a two-pulse first drive signal S1 formed by a first pulse P1 and a second pulse P2 is input to a low-side switch section (first drive target switch section) 11La included in the series circuit (interference phase) 10a to drive the low-side switch section 11Lb, and a one-pulse second drive signal S2 formed by a third pulse P3 is input to a high-side switch section (second drive target switch section) 11Hb included in the series circuit (measurement phase) 10b to drive the high-side switch section 11Hb, thereby testing the oscillation characteristics of the high-side switch section 11Hb of the measurement phase that are caused by the influence of the interference phase.

[0057] FIG. 6 is a timing chart showing an example of the waveform of a drive signal and the waveform of a monitored voltage, which will be described later.

[0058] "VLags" shown in Figure 6 is the voltage (gate-source voltage) of the third terminal (gate) Tg of the low-side switch unit 11La relative to the second terminal (source) Ts, and corresponds to the drive signal to the third terminal Tg of the low-side switch unit 11La. For ease of explanation, VLags will be referred to as the drive signal VLags hereinafter. As shown in Figure 6, in the first embodiment, the drive signal VLags corresponds to the first drive signal S1.

[0059] "VHbgs" shown in Figure 6 is the voltage (gate-source voltage) of the third terminal (gate) Tg with respect to the second terminal (source) Ts of the high-side switch unit 11Hb, and corresponds to the drive signal to the third terminal Tg of the high-side switch unit 11Hb. For ease of explanation, VHbgs will be referred to as the drive signal VHbgs hereinafter. As shown in Figure 6, in the first embodiment, the drive signal VHbgs corresponds to the second drive signal S2.

[0060] In FIG. 6, the letters "H" and "L" written individually mean "high" and "low" signal levels (or voltage levels), respectively.

[0061] As shown in Figure 6, the first pulse P1, the second pulse P2, and the third pulse P3 are rectangular pulses. The second pulse P2 is a pulse that follows the first pulse P1 (follows the first pulse P1). The rising timing of the third pulse P3 is within the first pulse P1, i.e., the third pulse P3 is a pulse that rises while the first pulse P1 is at a high level. The falling timing of the third pulse P3 is at the same time as the rising timing of the second pulse P2 at the latest. In other words, the falling timing of the third pulse P3 is the same as or before the rising timing of the second pulse P2.

[0062] 3 further includes a drive signal generating unit 30 and a monitoring device 40. The drive signal generating unit 30 generates a first drive signal S1 and a second drive signal S2 (see FIG. 6 ) and inputs them to the test circuit 20. The monitoring device 40 monitors the voltage of the high-side switch unit 11Hb serving as the second drive target switch unit and the voltage of the high-side switch unit 11Hb, which is different from the low-side switch unit 11La serving as the first drive target switch unit, out of the high-side switch unit 11Ha and the low-side switch unit 11La included in the series circuit 10a.

[0063] [Drive Signal Generator] The drive signal generator 30 has a function generator (FG) 31, gate drivers (GD) 12a and 12b, and a DC power supply 32. Hereinafter, the function generator 31, the gate driver 12a, and the gate driver 12b will be referred to as FG31, GD12a, and GD12b.

[0064] FG31 is a pulse generator that generates a first gate control signal corresponding to the first drive signal S1 and inputs it to GD12a, and also generates a second gate control signal corresponding to the second drive signal S2 and inputs it to GD12b.

[0065] The GDs 12 a and 12 b are electrically connected to a DC power supply 32 , and are driven by the voltage supplied from the DC power supply 32 .

[0066] The GD 12a is a driver circuit that generates a first drive signal S1 based on the first gate control signal from the FG 31 and inputs the signal to the low-side switch unit 11La.

[0067] The first drive signal S1 is generated by the first gate control signal generated by FG ​​31, and the waveform (pulse waveform) of the first drive signal S1 is the same as the waveform of the first gate control signal. In other words, the waveform of the first drive signal S1 is adjusted by adjusting the waveform of the first gate control signal.

[0068] FG31 and GD12a are connected by signal lines 331 and 332. Signal line 331 is a signal line that provides a low-level potential in the first gate control signal, and signal line 332 is a signal line that provides a high-level potential in the first gate control signal.

[0069] GD 12a is electrically connected to the second terminal (source) Ts of the low-side switch unit 11La by a signal line 341, and is electrically connected to the third terminal (gate) Tg of the low-side switch unit 11La by a signal line 342. As a result, the first drive signal S1 generated by GD 12a is input to the third terminal Tg of the low-side switch unit 11La as a drive signal VLbgs.

[0070] The signal line 341 is a signal line that provides a low-level potential of the first drive signal S1 (drive signal VLags), and the signal line 342 is a signal line that provides a high-level potential of the first drive signal S1. The GD 12a inputs the first drive signal S1 (drive signal VLags) to the third terminal Tg of the low-side switch unit 11La via the signal lines 341 and 342. More specifically, the GD 12a provides a high-level potential of the first drive signal S1 to the signal line 342 at a predetermined timing, thereby inputting the first drive signal S1 to the third terminal Tg of the low-side switch unit 11La as a drive signal VLags that corresponds to the voltage between the second terminal Ts and the third terminal Tg.

[0071] The GD 12b is a driver circuit that generates a second drive signal S2 based on the second gate control signal from the FG 31 and inputs the second drive signal S2 to the high-side switch unit 11Hb.

[0072] The second drive signal S2 is generated by the second gate control signal generated by FG ​​31, and the waveform (pulse waveform) of the second drive signal S2 is the same as the waveform of the second gate control signal. In other words, the waveform of the second drive signal S2 is adjusted by adjusting the waveform of the second gate control signal.

[0073] FG31 and GD12b are connected by signal lines 351 and 352. Signal line 351 is a signal line that provides a low-level potential in the second gate control signal, and signal line 352 is a signal line that provides a high-level potential in the second gate control signal.

[0074] GD 12b is electrically connected to the second terminal (source) Ts of the high-side switch unit 11Hb by a signal line 361, and is electrically connected to the third terminal (gate) Tg of the high-side switch unit 11Hb by a signal line 362. As a result, the second drive signal S2 generated by GD 12b is input to the third terminal Tg of the high-side switch unit 11Hb as a drive signal VHbgs.

[0075] The signal line 361 is a signal line that provides a low-level potential of the second drive signal S2, and the signal line 362 is a signal line that provides a high-level potential of the second drive signal S2. The GD 12b inputs the second drive signal S2 (drive signal VHbgs) to the third terminal Tg of the high-side switch unit 11Hb via the signal line 361 and the signal line 362. More specifically, by providing a high-level potential of the second drive signal S2 to the signal line 362 at a predetermined timing, the second drive signal S2 is input to the third terminal Tg of the high-side switch unit 11Hb as the drive signal VHbgs that corresponds to the voltage between the second terminal Ts and the third terminal Tg.

[0076] [Monitoring Device] The monitoring device 40 includes a differential probe (DP) 41 as a voltage detector, and an oscilloscope 42 that displays the voltage detection result by the differential probe 41 .

[0077] The differential probe 41 includes a probe line 431 , a probe line 432 , a probe line 441 and a probe line 442 .

[0078] The probe line 431 is electrically connected to the first terminal (drain) Td of the high-side switch unit 11Ha to measure the potential of the first terminal Td, and the probe line 432 is electrically connected to the second terminal (source) Ts of the high-side switch unit 11Ha to measure the potential of the second terminal Ts.

[0079] The differential probe 41 calculates the difference between the potential of the first terminal Td and the potential of the second terminal Ts of the high-side switch unit 11Ha measured by the probe line 431 and the probe line 432, and outputs the calculation result to the oscilloscope 42 as the voltage VHads of the high-side switch unit 11Ha (see Figure 6).

[0080] The probe line 441 is electrically connected to the first terminal (drain) Td of the high-side switch unit 11Hb to measure the potential of the first terminal Td. The probe line 442 is electrically connected to the second terminal Ts of the high-side switch unit 11Hb to measure the potential of the second terminal (source) Ts. The differential probe 41 calculates the difference between the potential of the first terminal Td and the potential of the second terminal Ts of the high-side switch unit 11Hb measured by the probe lines 441 and 442, and outputs the calculation result to the oscilloscope 42 as the voltage VHbds of the high-side switch unit 11Hb (see FIG. 6 ).

[0081] In the test device 100, the transition of the voltage state of each switch section of the test circuit 20 when the low-side switch section 11La is driven by the drive signal VLags (first drive signal S1) and the high-side switch section 11Hb is driven by the drive signal VHbgs (second drive signal S2) will be explained using Figure 6.

[0082] The meanings of "VHags", "VLbgs", "VLads", and "VLbds" shown in Fig. 6 are as follows: The meanings of "VLags", "VHbgs", "VHads", and "VHbds" shown in Fig. 6 are as described above, and therefore will not be described again.

[0083] <<VHags>> VHags is the voltage (gate-source voltage) of the third terminal (gate) Tg of the high-side switch unit 11Ha with respect to the second terminal (source) Ts, and corresponds to the drive signal to the third terminal Tg of the high-side switch unit 11Ha. For ease of explanation, VHags will be referred to as the drive signal VHags below.

[0084] In the test circuit 20, the second terminal Ts and the third terminal Tg of the high-side switch unit 11Ha are short-circuited, so the drive signal VHags is maintained at a low level as shown in Fig. 6. This state corresponds to the fact that, in the test performed on the test circuit 20, the drive signal VHags is not input to the third terminal Tg of the high-side switch unit 11Ha.

[0085] <<VLbgs>> VLbgs is the voltage (gate-source voltage) of the third terminal (gate) Tg of the low-side switch unit 11Lb with respect to the second terminal (source) Ts, and corresponds to the drive signal to the third terminal Tg of the low-side switch unit 11Lb. For ease of explanation, VLbgs will be referred to as the drive signal VLbgs below.

[0086] In the test circuit 20, the second terminal Ts and the third terminal Tg of the low-side switch unit 11Lb are short-circuited, and therefore the drive signal VLbgs is maintained at a low level, as shown in Fig. 6. This state corresponds to the fact that, in the test performed on the test circuit 20, the drive signal VLbgs is not input to the third terminal Tg of the low-side switch unit 11Lb.

[0087] <<VLads>> VLads corresponds to the voltage of the low-side switch unit 11La. Specifically, VLads corresponds to the voltage (drain-source voltage) between the first terminal (drain) Td and the second terminal (source) Ts of the low-side switch unit 11La. For ease of explanation, VLads will be referred to as voltage VLads hereinafter.

[0088] <<VLbds>> VLbds corresponds to the voltage of the low-side switch unit 11Lb. Specifically, VLbds corresponds to the voltage (drain-source voltage) between the first terminal (drain) Td and the second terminal (source) Ts of the low-side switch unit 11Lb. For ease of explanation, VLbds will be referred to as voltage VLbds below.

[0089] As shown in FIG. 6 , the drive signal VLags is a first drive signal S1 having a first pulse P1 and a second pulse P2. The first pulse P1 is a pulse that rises at time t1 and falls at time t3. An example of the pulse width of the first pulse P1 (the time between time t1 and time t3) is 10 μs or more and 200 μs or less. The second pulse P2 is a pulse that rises at time t5 and falls at time t6. An example of the pulse width of the second pulse P2 (the time between time t5 and time t6) is the same as that of the first pulse P1. The drive signal VHbgs is a second drive signal S2 having a third pulse P3. The third pulse P3 is a pulse that rises at time t2 between time t1 and time t3 and, in the state shown in FIG. 6 , falls at time t4 between time t3 and time t5. As will be described later, the relationship between time t4 and time t5 is adjusted as appropriate. An example of the pulse width of the third pulse P3 (the time between time t2 and time t4) is the same as that of the first pulse P1.

[0090] When the test circuit 20 is driven by the drive signals VLags (first drive signal S1) and VHbgs (second drive signal S2), the voltages of the switches in the test circuit 20 change as follows.

[0091] The voltage VHads of the high-side switch unit 11Ha is at a low level until time t1, then transitions to a high level at time t1, then transitions to a low level at time t3, then transitions to a high level again at time t5, and then transitions to a low level at time t6.

[0092] The voltage VLads of the low-side switch unit 11La is at a high level until time t1, then transitions to a low level at time t1, then transitions to a high level at time t3, then transitions to a low level again at time t5, and then transitions to a high level at time t6.

[0093] The voltage VHbds of the high-side switch unit 11Hb is at a high level until time t2, transitions to a low level at time t2, and then transitions to a high level at time t4.

[0094] The voltage VLbds of the low-side switch unit 11Lb is at a low level until time t2, transitions to a high level at time t2, and then transitions to a low level at time t4.

[0095] Next, a test method according to an embodiment will be described with reference to Fig. 7. Fig. 7 is a flowchart of an example of the test method according to the first embodiment.

[0096] First, test circuit 20 shown in Fig. 3 is prepared (test circuit preparation step S11). For example, one of two series circuits selected from series circuits 10u, 10v, and 10w corresponding to the U, V, and W phases in power conversion device 1 shown in Fig. 1 is set to series circuit 10a shown in Fig. 3, and the other is set to series circuit 10b shown in Fig. 3, and wiring shown in Fig. 3 is applied to prepare test circuit 20. The wiring of power conversion device 1 shown in Fig. 1 may be adjusted to wiring for two phases as shown in Fig. 3 and used as test circuit 20.

[0097] In this embodiment, in the test circuit preparation step S11, the drive signal generating section 30 and the monitor device 40 are set in the test circuit 20 to prepare the test device 100.

[0098] Next, the drive signal generating unit 30 is started to input the drive signal VLags (first drive signal S1) to the low-side switch unit 11La and the drive signal VHbgs (second drive signal S2) to the high-side switch unit 11Hb, thereby driving the low-side switch unit 11La and the high-side switch unit 11Hb (driving step S12).

[0099] During the driving step S12, the voltage VHads of the high-side switch unit 11Ha and the voltage VHbds of the high-side switch unit 11Hb are monitored by the monitor device 40 (monitoring step S13). For convenience of illustration, the driving step S12 and the monitoring step S13 are shown separately in Fig. 7, but as described above, the monitoring step S13 is performed together with the driving step S12.

[0100] In the test of the test circuit 20, the time difference between time t5, which is the rising timing of the second pulse P2 of the first drive signal S1, and time t4, which is the falling timing of the third pulse P3 of the second drive signal S2, is defined as the interference time td (see FIG. 6 ), and the interference time td is adjusted within a certain adjustment range to obtain oscillation conditions under which oscillation occurs in the high-side switch unit 11Hb. The oscillation of the high-side switch unit 11Hb is an oscillation between the multiple high-side transistors 111Hb included in the high-side switch unit 11Hb.

[0101] 7, once the driving step S12 and the monitoring step S13 are performed, it is determined whether or not all of the planned adjustments for the interference time td have been performed (determination step S14). The determination step S14 may be performed based on, for example, the number of adjustments of the interference time td, or based on whether or not the interference time td has reached a predetermined interference time td.

[0102] If the planned adjustment of the interference time td has not been performed ("No" in the determination step S14), the interference time td is adjusted by adjusting at least one of the first drive signal S1 and the second drive signal S2 (interference time adjustment step S15). The adjustment of the interference time td can be performed, for example, by shifting the interference time td by a certain amount. The adjustment of the interference time td can be performed by advancing the falling time t4 of the third pulse P3 of the second drive signal S2.

[0103] When the interference time adjusting step S15 is performed, the driving step S12 and the monitoring step S13 are performed using the new first driving signal S1 and second driving signal S2 based on the newly set interference time td.

[0104] When all the planned adjustments of the interference time td have been performed ("Yes" in the determination step S14), the conditions (interference times) under which oscillation occurs in the high-side switch unit 11Hb are identified as oscillation conditions based on the monitoring results corresponding to each interference time td (oscillation condition identification step S16). When all the planned adjustments of the interference time td have been performed and oscillation does not occur for any of the interference times td, it may be identified as "no oscillation condition."

[0105] For example, the above test method may be performed as follows: First, as an initial setting, time t5, which is the rising timing of the second pulse P2, and time t4, which is the falling timing of the third pulse P3, are matched, and then the driving step S12 and the monitoring step S13 are performed. Thereafter, the falling timing of the third pulse P3 is advanced by a certain amount to adjust the interference time td, and the driving step S12 and the monitoring step S13 are performed.

[0106] The adjustment of the interference time td may be performed by a tester manually operating the FG 31, or may be performed automatically by the FG 31 by having the FG 31 execute a predetermined program. When the FG 31 automatically adjusts the interference time td, the FG 31 also automatically performs the determination step S14.

[0107] FIG. 8 is a chart showing an example of changes in the drive signal Lags (first drive signal S1) and drive signal VHbgs (second drive signal S2) and changes in the voltages VHads and VHbds that accompany adjustment of the interference time.

[0108] The "Vgs" column in the chart shown in Figure 8 shows changes in the drive signal VLags and the drive signal VHbgs as the interference time is adjusted. The "Vgs" column in the chart shown in Figure 8 shows enlarged waveforms of the drive signal VLags (first drive signal S1) and the drive signal VHbgs (second drive signal S2) near times t4 and t5. The horizontal axis in the "Vgs" column in the chart shown in Figure 8 represents time.

[0109] The "Vds" column in the chart shown in FIG. 8 shows changes in the voltages VHads and VHbds as the interference time is adjusted. In the "Vds" column in the chart shown in FIG. 8, the horizontal axis represents time, and the vertical axis represents voltage Vds. In FIG. 8, the time scale of the horizontal axis in the voltage "Vds" column does not match the time scale in the "Vgs" column, from the viewpoint of schematically showing changes in the voltages VHads and VHbds. The waveforms in the voltage "Vds" column are schematic representations of actual measurement results.

[0110] Pattern 1 shown in Figure 8 is a case where time t4 and time t5 coincide. That is, in pattern 1, the rising timing of the second pulse P2 of the drive signal VLags coincides with the rising timing of the third pulse P3 of the drive signal VHbgs. In this case, voltage VHads rises earlier, and voltage VHbds rises later. In this case, the rising timing of voltage VHads and the rising timing of voltage VHbds are sufficiently different.

[0111] Pattern 2 shown in Figure 8 is a case where time t4 is made earlier than in Pattern 1, and Pattern 3 is a case where time t4 is made earlier than in Pattern 2. By making time t4 earlier as in Patterns 2 and 3, the rising timing of voltage VHads and the rising timing of voltage VHbds become closer. At a predetermined timing (Pattern 2 in the case of Figure 8), oscillation due to the interference occurs, as shown in area A1 of Pattern 2.

[0112] The results of the study of the mechanism by which oscillation occurs will be described with reference to Fig. 9. Fig. 9 is a schematic diagram for explaining the mechanism by which the oscillation occurs. Fig. 9 is a diagram in which some elements are extracted from the test circuit 20.

[0113] 3, in the high-side switch unit 11Ha, the second terminal Ts and the third terminal Tg are short-circuited, and therefore the high-side switch unit 11Ha is considered to be equivalent to the capacitor C1. When the third pulse P3 of the second drive signal Lbgs in the high-side switch unit 11Hb falls, the high-side switch unit 11Hb is considered to be equivalent to the capacitor C2. Specifically, each of the multiple high-side transistors 111Hb included in the high-side switch unit 11Hb is considered to be equivalent to a capacitor.

[0114] As shown in Fig. 6, when the second pulse P2 of the first drive signal S1 rises (time t5), the voltage VHads of the high-side switch unit 11Ha rises. In this case, ringing occurs in the closed circuit including the capacitor C1 and the capacitor 13a, as shown by the dashed line in Fig. 8. As shown in Fig. 6, when the third pulse P3 of the second drive signal S2 falls (time t4), the voltage VHbds rises.

[0115] Ringing occurring in the closed circuit including capacitor C1 and capacitor 13a shown by the dashed line in Fig. 9 propagates along the path shown by the dashed line, which partially overlaps with the closed circuit including capacitor C1 and capacitor 13a shown by the dashed line in Fig. 9, and propagates to the high-side switch unit 11Hb, which is regarded as capacitor C2. It is believed that the ringing occurring due to this high-side switch unit 11Ha overlaps with the fluctuation in voltage VHads occurring at the timing of the rise of voltage VHads, causing oscillation between the multiple high-side transistors 111Hb included in the high-side switch unit 11Hb.

[0116] 10 is a diagram showing the relationship between interference time and the maximum surge voltage of the high-side switch unit 11Hb. The horizontal axis represents interference time [ns], and the vertical axis represents maximum surge voltage [V]. As shown in FIG. 10, the maximum surge voltage changes with changes in interference time, with the maximum surge voltage peaking in region A2. This region A2 corresponds to the location where the oscillation occurs. In other words, the occurrence of oscillation causes an extremely large surge voltage.

[0117] The test apparatus 100 described in the first embodiment and the test method using the same can identify the conditions under which the oscillation occurs (interference time td). If the oscillation conditions can be identified in this way, the generation of surge voltages associated with oscillation can be prevented by driving the switches of the power conversion device 1 shown in FIG. 1 under conditions under which oscillation does not occur. As a result, problems caused by surge voltages, such as damage to the power conversion device 1 or abnormal operation, can be eliminated.

[0118] For example, motor bench testing is known as a test for measuring the rotation speed, durability, and exhaust performance of a motor. This motor bench testing also tests the power conversion device used to drive the motor. However, in motor bench testing, continuously controlled pulses are continuously input to the power conversion device. Therefore, if oscillation occurs as described above, there is a risk of damage to the power conversion device or the switch unit used therein. Furthermore, because it is necessary to create a bench mounting jig that matches the shape of the motor used in the test, the cost and effort required to conduct the test increase.

[0119] In contrast, the test apparatus 100 and test method described above perform a double-pulse test using a two-pulse signal as the first drive signal S1 input to the test circuit 20, and the second drive signal S2 is also a single-pulse signal. Therefore, the number of pulses input when the first drive signal S1 and the second drive signal S2 are input to the test circuit 20 is a maximum of two. This does not involve continuous operation, such as a motor pulse test, in which pulses are continuously input. Therefore, the test circuit 20 (specifically, the low-side switch unit 11La, the high-side switch unit 11Hb, etc.) hardly generates heat, and the test circuit 20 (specifically, the low-side switch unit 11La, the high-side switch unit 11Hb, etc.) is not damaged because it is not a continuous operation mode in which a load is continuously applied. Furthermore, the test apparatus 100 and test method described above allow the test circuit 20 to be easily tested by simply preparing the test apparatus 100 shown in FIG. 3 .

[0120] Therefore, the test device 100 and the test method described above can easily test the oscillation characteristics between phases used in an n-phase power conversion device. Furthermore, the test device 100 and the test method described above can safely test the test circuit 20 (specifically, the low-side switch unit 11La, the high-side switch unit 11Hb, etc.) that is the test target while preventing damage to the test circuit 20.

[0121] When adjusting the interference time td, adjusting the falling timing of the third pulse P3 to be earlier makes it easier to align the ringing that occurs on the interference phase side (series circuit 10a side in this embodiment) with the rising timing of the voltage of the high-side switch unit 11Hb of the measurement phase (series circuit 10b in this embodiment), and as a result, it becomes easier to identify the oscillation conditions.

[0122] 3, the test circuit 20 is tested by acquiring the oscillation conditions of the high-side switch unit 11Hb of the series circuit 10b. However, the test circuit 20 may also be tested by acquiring the oscillation conditions of the low-side switch unit 11Lb of the series circuit 10b. This case will be described as a second embodiment.

[0123] 11 is a block diagram of a test apparatus 100A according to the second embodiment. The test apparatus 100A includes a test circuit 20A, a drive signal generating section 30, and a monitor device 40.

[0124] The test circuit 20A includes a DC power supply unit 3a, a series circuit 10a, a series circuit 10b, and a coil (inductive load) 4ab, similar to the test circuit 20. The DC power supply unit 3a and the coil 4ab are the same as those in the first embodiment, and therefore will not be described.

[0125] As in the first embodiment, the series circuits 10a and 10b correspond to two series circuits selected from the series circuits 10u, 10v, and 10w shown in Fig. 1. The series circuits 10a and 10b are electrically connected in parallel between a high-potential line 5a electrically connected to the positive electrode of the DC power supply unit 3a and a low-potential line 6a electrically connected to the negative electrode of the DC power supply unit 3a.

[0126] The series circuit 10a includes a high-side switch unit 11Ha and a low-side switch unit 11La. The high-side switch unit 11Ha and the low-side switch unit 11La are the same as the switch unit 11 shown in FIG. 1 and include a first terminal Td, a second terminal Ts, and a third terminal Tg.

[0127] A first terminal Td of the high-side switch unit 11Ha is electrically connected to the high-potential line 5a, and a second terminal Ts of the high-side switch unit 11Ha is connected to a first terminal Td of the low-side switch unit 11La by a connection line 21a. A part of the connection line 21a is a node Na between the high-side switch unit 11Ha and the low-side switch unit 11La, and corresponds to the output of the series circuit 10a. A second terminal Ts of the low-side switch unit 11La is electrically connected to the low-potential line 6a.

[0128] The second terminal Ts and the third terminal Tg of the low-side switch unit 11La are connected by a connection line 22a, that is, the second terminal Ts and the third terminal Tg of the low-side switch unit 11La are short-circuited.

[0129] The series circuit 10b includes a high-side switch unit 11Hb and a low-side switch unit 11Lb. The high-side switch unit 11Hb and the low-side switch unit 11Lb are the same as the switch unit 11 shown in FIG. 1 and include a first terminal Td, a second terminal Ts, and a third terminal Tg.

[0130] A first terminal Td of the high-side switch unit 11Hb is electrically connected to the high-potential line 5a, and a second terminal Ts of the high-side switch unit 11Hb is connected to the first terminal Td of the low-side switch unit 11Lb by a connection line 21b. A part of the connection line 21b is a node Nb between the high-side switch unit 11Hb and the low-side switch unit 11Lb, and corresponds to the output of the series circuit 10b. A second terminal Ts of the low-side switch unit 11Lb is electrically connected to the low-potential line 6a.

[0131] The second terminal Ts and the third terminal Tg of the high-side switch unit 11Hb are connected by a connection line 22b, that is, the second terminal Ts and the third terminal Tg of the high-side switch unit 11Hb are short-circuited.

[0132] One end of the coil 4ab is connected to the node Na, and the other end of the coil 4ab is connected to the node Nb, so that the connection line 21a and the connection line 21b are connected by the coil 4ab.

[0133] The test circuit 20A has two capacitors 13a and 13b for smoothing the DC voltage supplied from the DC power supply unit 3a to the series circuits 10a and 10b. The description of the capacitors 13a and 13b is the same as that of the first embodiment, and therefore will not be repeated.

[0134] As in the first embodiment, the high-side switch unit 11Ha has a plurality of high-side transistors 111Ha connected in parallel as shown in FIG. 4, the low-side switch unit 11La has a plurality of low-side transistors 111La connected in parallel as shown in FIG. 5, and the high-side transistors 111Ha and the low-side transistors 111La are MOSFETs.

[0135] The first terminal Td, the second terminal Ts, and the third terminal Tg of the high-side switch unit 11Ha and the low-side switch unit 11La correspond to the drain, the source, and the gate, as in the first embodiment. Therefore, in the second embodiment, the first terminal Td, the second terminal Ts, and the third terminal Tg may also be considered as the drain, the source, and the gate in some cases.

[0136] In the second embodiment, a double pulse test is performed using the series circuit 10b of the test circuit 20A as a measurement phase and the series circuit 10a as an interference phase.

[0137] In the second embodiment, a two-pulse first drive signal S1 (see FIG. 12) formed by a first pulse P1 and a second pulse P2 is input to a high-side switch unit (first drive target switch unit) 11Ha included in a series circuit (interference phase) 10a to drive the high-side switch unit 11Ha, and a one-pulse second drive signal S2 (see FIG. 12) formed by a third pulse P3 is input to a low-side switch unit (second drive target switch unit) 11Lb included in a series circuit (measurement phase) 10b to drive the low-side switch unit 11Lb, thereby testing the oscillation characteristics of the low-side switch unit 11Lb of the measurement phase that are caused by the influence of the interference phase.

[0138] 12, the first pulse P1, the second pulse P2, and the third pulse P3 are rectangular pulses. The second pulse P2 is a pulse following the first pulse P1. The rising timing of the third pulse P3 is within the first pulse P1, i.e., the third pulse P3 is a pulse that rises while the first pulse P1 is at a high level.

[0139] Fig. 12 is a timing chart showing an example of the waveform of a drive signal and the waveform of a monitored voltage, which will be described later. The meanings of "VHags," "VLHgs," etc., and the individual letters "H" and "L" shown in Fig. 12 are the same as those in Fig. 6. As shown in Fig. 12, in the second embodiment, the drive signal VHags corresponds to the first drive signal S1, and the drive signal VLbgs corresponds to the second drive signal S2.

[0140] The drive signal generating section 30 and the monitor device 40 will be described with reference to FIG. 11 again.

[0141] [Drive Signal Generator] The drive signal generator 30 has an FG 31, GDs 12a and 12b, and a DC power supply 32. The FG 31, GDs 12a and 12b, and the DC power supply 32 are the same as those in the first embodiment.

[0142] As in the first embodiment, the GD 12a generates the two-pulse first drive signal S1 based on the first gate control signal from the FG 31. In the second embodiment, the signal line 341 is electrically connected to the second terminal (source) Ts of the high-side switch unit 11Ha, and the signal line 342 is electrically connected to the third terminal (gate) Tg of the high-side switch unit 11Ha. As a result, the first drive signal S1 generated by the GD 12a is input to the third terminal Tg of the high-side switch unit 11Ha as the drive signal VHags.

[0143] As in the first embodiment, GD 12b generates the one-pulse second drive signal S2 based on the second gate control signal from FG 31. In the second embodiment, signal line 361 is electrically connected to the second terminal (source) Ts of the low-side switch unit 11Lb, and signal line 362 is electrically connected to the third terminal (gate) Tg of the low-side switch unit 11Lb. As a result, the second drive signal S2 generated by GD 12b is input to the third terminal Tg of the low-side switch unit 11Lb as drive signal VLbgs.

[0144] [Monitoring Device] The monitoring device 40 has a differential probe 41 as a voltage detector and an oscilloscope 42 that displays the voltage detection result by the differential probe 41 .

[0145] The differential probe 41 has a probe line 431, a probe line 432, a probe line 441 and a probe line 442, similar to the first embodiment.

[0146] The probe line 431 is electrically connected to the first terminal (drain) Td of the low-side switch unit 11La to measure the potential of the first terminal Td. The probe line 432 is electrically connected to the second terminal Ts of the low-side switch unit 11La to measure the potential of the second terminal (source) Ts. The differential probe 41 calculates the difference between the potential of the first terminal Td and the potential of the second terminal Ts of the low-side switch unit 11La measured by the probe lines 431 and 432, and outputs the calculation result to the oscilloscope 42 as the voltage VLads of the low-side switch unit 11La (see FIG. 12 ).

[0147] The probe line 441 is electrically connected to the first terminal (drain) Td of the low-side switch unit 11Lb to measure the potential of the first terminal Td. The probe line 442 is electrically connected to the second terminal Ts of the low-side switch unit 11Lb to measure the potential of the second terminal (source) Ts. The differential probe 41 calculates the difference between the potential of the first terminal Td and the potential of the second terminal Ts of the low-side switch unit 11Lb measured by the probe lines 441 and 442, and outputs the calculation result to the oscilloscope 42 as the voltage VLbds of the low-side switch unit 11Lb (see FIG. 12 ).

[0148] The transition of the voltage state of each switch section of the test circuit 20A when the high-side switch section 11Ha and the low-side switch section 11Lb are driven by the drive signal VHags (first drive signal S1) and the drive signal VLbgs (second drive signal S2) in the test device 100A will be explained using Figure 12.

[0149] As shown in FIG. 12, the drive signal VHags is a first drive signal S1 having a first pulse P1 and a second pulse P2. The first pulse P1 is a pulse that rises at time t1 and falls at time t3. The second pulse P2 is a pulse that rises at time t5 and falls at time t6. The drive signal VLbgs is a one-pulse second drive signal S2 having a third pulse P3. The third pulse P3 is a pulse that rises at time t2 between time t1 and time t3, and in the state shown in FIG. 12, falls at time t4 between time t3 and time t5. In the second embodiment as well, the relationship between time t4 and time t5 is adjusted as appropriate.

[0150] When the test circuit 20A is driven by the drive signals VHags and VLbgs, the voltages of the switches in the test circuit 20A change as follows.

[0151] The voltage VHads of the high-side switch unit 11Ha is at a high level until time t1, then transitions to a low level at time t1, then transitions to a high level at time t3, then transitions to a low level again at time t5, and then transitions to a high level at time t6.

[0152] The voltage VLads of the low-side switch unit 11La is maintained at a low level until time t1, and then transitions to a high level at time t1, and then to a low level at time t3. Thereafter, the voltage VLads transitions to a high level again at time t5, and then to a low level at time t6.

[0153] The voltage VHbds of the high-side switch unit 11Hb is at a low level until time t2, transitions to a high level at time t2, and transitions to a low level at time t4.

[0154] The voltage VLbds of the low-side switch unit 11Lb is at a high level until time t2, transitions to a low level at time t2, and transitions to a high level at time t4.

[0155] Next, a test method according to an embodiment will be described with reference to Fig. 13. Fig. 13 is a flowchart of an example of a test method according to a second embodiment.

[0156] 11 is prepared (test circuit preparation step S21). The method for preparing the test circuit 20A is the same as the test circuit preparation step S11 in the first embodiment, except that the test circuit 20A is prepared instead of the test circuit 20. In the second embodiment, in the test circuit preparation step S21, the drive signal generation unit 30 and the monitoring device 40 are set to the test circuit 20A to prepare the test device 100A.

[0157] Next, the drive signal generating unit 30 is started to input the drive signal VHags to the high-side switch unit 11Ha and the drive signal VLbgs to the low-side switch unit 11Lb, thereby driving the high-side switch unit 11Ha and the low-side switch unit 11Lb (driving step S22).

[0158] During the driving step S22, the voltage VLads of the low-side switch unit 11La and the voltage VLbds of the low-side switch unit 11Lb are monitored by the monitor device 40 (monitoring step S23). For convenience of illustration, the driving step S22 and the monitoring step S23 are shown separately in Fig. 13, but as described above, the monitoring step S23 is performed together with the driving step S22.

[0159] In the test of the test circuit 20A, the time difference between time t5, which is the rising timing of the second pulse P2 of the first drive signal S1, and time t4, which is the falling timing of the third pulse P3 of the second drive signal S2, is defined as the interference time td (see FIG. 12 ), and the interference time td is adjusted within a certain adjustment range to obtain oscillation conditions under which oscillation occurs in the low-side switch unit 11Lb. The oscillation of the low-side switch unit 11Lb is an oscillation between the plurality of low-side transistors 111Lb included in the low-side switch unit 11Lb.

[0160] Specifically, in the testing method of the second embodiment, a determination step S24, an interference time adjustment step S25, and an oscillation condition specification step S26 are performed as shown in Fig. 13. The determination step S24, the interference time adjustment step S25, and the oscillation condition specification step S26 are the same as the determination step S14, the interference time adjustment step S15, and the oscillation condition specification step S16 of the first embodiment.

[0161] The second embodiment is similar to the first embodiment except that the oscillation characteristics of the low-side switch unit 11Lb are tested instead of the high-side switch unit 11Hb. Therefore, the test apparatus 100A according to the second embodiment and the test method using the same have the same effects as the test apparatus 100 according to the first embodiment and the test method using the same.

[0162] (Variation 1) The power conversion device may have a common capacitor 13 for series circuits 10u, 10v, and 10w, instead of capacitors 13u, 13v, and 13w as in power conversion device 1A shown in Fig. 14. Fig. 14 is a diagram showing a variation of the power conversion device shown in Fig. 1.

[0163] The configuration of the power conversion device 1A is the same as that of the power conversion device 1, except that it has a capacitor 13 instead of the capacitors 13u, 13v, and 13w. The capacitance of the capacitor 13 may be the sum of the capacitances of the capacitors 13u, 13v, and 13w. In this case, the power conversion device 1A and the power conversion device 1 are equivalent in terms of electric circuits.

[0164] The test device and test method described in the first and second embodiments can also be applied to the power conversion device 1A shown in FIG.

[0165] 15 is a block diagram showing a modification of the test apparatus 100. The test apparatus 100B is different from the test apparatus 100 in that it includes a test circuit 20B instead of the test circuit 20. The rest of the configuration is the same as that of the test apparatus 100.

[0166] Test circuit 20B differs from test circuit 20 in that it has a capacitor 13ab common to series circuits 10a and 10b instead of capacitors 13a and 13b, but the rest of the configuration is the same as that of test circuit 20. In test circuit 20B of modification 2, the capacitance of capacitor 13ab may be the sum of the capacitances of capacitors 13a and 13b. In this case, test circuit 20B and test circuit 20 are equivalent in terms of electrical circuitry.

[0167] Test device 100B is the same as test device 100 except that it has test circuit 20B instead of test circuit 20, and test circuit 20B is the same as test circuit 20 except that it has capacitor 13ab common to series circuit 10a and series circuit 10b instead of capacitor 13a and capacitor 13b.Therefore, test device 100B and the test method using it have the same effects as in the first embodiment.

[0168] As described in the first modification, the test device 100B is effective for testing the interphase oscillation characteristics of the power conversion device 1A having a common capacitor 13 for the series circuits 10u, 10v, and 10w.

[0169] As can be seen from the above description, the test method and test device according to the present disclosure make it possible to easily test the inter-phase oscillation characteristics of a power conversion device including multiple phases.

[0170] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Elements in different embodiments can be combined to form other embodiments. From the above description, it will be understood that the various embodiments of the present disclosure are illustrative in all respects, and that various changes can be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

[0171] In the above embodiment, the transistor is a MOSFET, but the transistor may be another type of transistor such as an IGBT. When the transistor is a transistor other than a MOSFET, the terms "drain," "source," and "gate" in the above embodiment may be replaced with the corresponding names of the other transistor.

[0172] Although the coils 4a, 4b, and 4ab are given as examples of inductive loads, the inductive loads used in the test circuit are not limited to coils.

[0173] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0174] [A1] (First embodiment, second embodiment, FIGS. 3, 4, 5-7, 11-13, and 15) a test circuit (20, 20A) including: a first series circuit (10a) formed by connecting a first high-side switch unit (11Ha) and a first low-side switch unit (11La) in series between a high-potential line (5a) and a low-potential line (6a) electrically connected to a DC power supply unit (3a); a second series circuit (10b) formed by connecting a second high-side switch unit (11Hb) and a second low-side switch unit (11Lb) in series between the high-potential line and the low-potential line, and connected in parallel to the first series circuit between the high-potential line and the low-potential line; capacitors (13a, 13b, 13ab) connected between the high-potential line and the low-potential line for smoothing a DC voltage supplied from the DC power supply unit; and an inductive load (4ab) connecting a connection line (21a) between the first high-side switch unit and the first low-side switch unit and a connection line (21b) between the second high-side switch unit and the second low-side switch unit, a preparation step (S11, S21) of preparing the test circuit, wherein the first high-side switch section has a plurality of first high-side transistors (111Ha) connected in parallel, the first low-side switch section has a plurality of first low-side transistors (111La) connected in parallel, the second high-side switch section has a plurality of second high-side transistors (111Hb) connected in parallel, and the second low-side switch section has a plurality of second low-side transistors (111Lb) connected in parallel; a driving step (S12) of driving a first drive target switch unit (11La (FIG. 3), 11Ha (FIG. 11)) which is one of the first high-side switch unit and the first low-side switch unit with a first drive signal (S1), and driving a second drive target switch unit (11Hb (FIG. 3), 11Lb (FIG. 11)) which is one of the second high-side switch unit and the second low-side switch unit and is on a side different from the first drive target switch unit in terms of high side and low side with a second drive signal (S2);the first drive signal is a two-pulse drive signal having a first pulse (P1) and a second pulse (P2) subsequent to the first pulse, the second drive signal is a one-pulse drive signal having a third pulse (P3), and a rising timing (t2) of the third pulse is within the first pulse; and a monitoring process (S13, S23) of monitoring a voltage of a switch unit (11Ha (FIG. 3), 11La (FIG. 11)) different from the first drive target switch unit out of the first high-side switch unit and the first low-side switch unit, and monitoring a voltage of the second drive target switch unit (11Hb (FIG. 3), 11Lb (FIG. 11)), The time difference between the rising timing (t5) of the second pulse and the falling timing (t4) of the third pulse is set as an interference time (td), and the driving step and the monitoring step are performed while adjusting the interference time, thereby acquiring a condition under which oscillation occurs in the second drive target switch unit.

[0175] [A2] (FIGS. 3 and 11) The test method according to [A1], wherein the test circuit (20, 20A) has two of the capacitors (13a, 13b) corresponding to the first series circuit and the second series circuit.

[0176] [A3] (FIG. 15) The test method according to [A1], wherein the capacitor is a capacitor (13ab) common to the first series circuit and the second series circuit.

[0177] [A4] (FIGS. 3 and 11) The test method according to any one of [A1] to [A3], wherein the pair of the first drive target switch unit and the second drive target switch unit is a pair of the second high-side switch unit (11Hb) and the first low-side switch unit (11La), or a pair of the second low-side switch unit (11Lb) and the first high-side switch unit (11Ha).

[0178] [A5] The testing method according to any one of [A1] to [A4], wherein the interference time is adjusted by advancing the falling timing of the third pulse.

[0179] [A6] The test method according to any one of [A1] to [A5], wherein the interference time is adjusted by automatically adjusting at least one of a rising timing of the second pulse and a falling timing of the third pulse.

[0180] [A7] (FIGS. 3 and 11) The first high-side switch unit, the first low-side switch unit, the second high-side switch unit, and the second low-side switch unit each have a first terminal (Td), a second terminal (Ts), and a third terminal (Tg), and are switch units in which a conduction state between the first terminal and the second terminal is controlled in response to a drive signal input to the third terminal, the first terminal of each of the first high-side switch unit and the second high-side switch unit is electrically connected to the high potential line, the second terminal of each of the first low-side switch unit and the second low-side switch unit is electrically connected to the low potential line, the second terminal of the first high-side switch unit and the first terminal of the second high-side switch unit are electrically connected, and the second terminal and the third terminal of each of the first high-side switch unit and the first low-side switch unit other than the first drive target switch unit are short-circuited, The test method according to any one of [A1] to [A6], wherein the second terminal and the third terminal of the switch unit other than the second test switch unit among the second high-side switch unit and the second low-side switch unit are short-circuited.

[0181] [A8] (Fig. 1, Fig. 14) The test method according to any one of [A1] to [A7], wherein the first series circuit is a leg of a first phase in an n-phase power conversion device (1, 1A), the second series circuit is a leg of a second phase different from the first phase in the n-phase power conversion device, and n is an integer of 2 or more.

[0182] [B1] (First embodiment, second embodiment, FIGS. 3 to 6, 11, 12, 15) A first series circuit (10a) formed by connecting in series between a high potential line (5a) and a low potential line (6a) a first high side switch section (11Ha) having a plurality of first high side transistors (111Ha) connected in parallel and a first low side switch section (11La) having a plurality of first low side transistors (111La) connected in parallel, and a second series circuit (10b) formed by connecting in series between the high potential line (5a) and the low potential line a second high side switch section (11Hb) having a plurality of second high side transistors (111Hb) connected in parallel and a second low side switch section (111Lb) having a plurality of second low side transistors (111Lb) connected in parallel, and a DC power supply section (3a) that supplies a DC voltage between the high potential line and the low potential line, A capacitor (13, 13a, 13b) is connected between the high potential line and the low potential line to smooth the DC voltage.an inductive load (4ab) connecting a connection line (21a) between the first high-side switch unit and the first low-side switch unit and a connection line (21b) between the second high-side switch unit and the second low-side switch unit; a drive signal generation unit (30) that generates a two-pulse first drive signal (S1) formed by a first pulse (P1) and a second pulse (P2) subsequent to the first pulse, and a one-pulse second drive signal (S2) formed by a third pulse (P3) so that a rising timing (t4) of the third pulse is within the first pulse, the drive signal generation unit inputting the first drive signal to a first drive target switch unit that is one of the second high-side switch unit and the second low-side switch unit, and inputting the second drive signal to a second drive target switch unit that is a switch unit on a different side from the first drive target switch unit in terms of high side and low side, between the first high-side switch unit and the first side switch unit; A test device comprising: a monitor device (40) that monitors the voltage of a switch unit different from the first drive target switch unit among the first high-side switch unit and the first low-side switch unit, and monitors the voltage of the second drive target switch unit.

[0183] [B2] (FIGS. 3 and 11) The first high-side switch unit, the first low-side switch unit, the second high-side switch unit, and the second low-side switch unit each have a first terminal (Td), a second terminal (Ts), and a third terminal (Tg), and are switch units in which a conduction state between the first terminal and the second terminal is controlled in response to a drive signal input to the third terminal, the first terminal of each of the first high-side switch unit and the second high-side switch unit is electrically connected to the high potential line, the second terminal of each of the first low-side switch unit and the second low-side switch unit is electrically connected to the low potential line, the second terminal of the first high-side switch unit and the first terminal of the second high-side switch unit are electrically connected, and the second terminal and the third terminal of each of the first high-side switch unit and the first low-side switch unit other than the first drive target switch unit are short-circuited, The test device according to [B1], wherein the second terminal and the third terminal of the switch unit other than the second drive target switch unit among the second high-side switch unit and the second low-side switch unit are short-circuited.

[0184] [B3] (FIGS. 3 and 11) The test device according to [B1] or [B2], wherein the test circuit has two of the capacitors (13a, 13b) corresponding to the first series circuit and the second series circuit.

[0185] [B4] (FIG. 15) The test apparatus according to [B1] or [B2], wherein the capacitor is a capacitor (13ab) common to the first series circuit and the second series circuit.

[0186] [B5] (FIG. 3, FIG. 11) The test apparatus according to any one of [B1] to [B4], wherein the drive signal generating unit

[30] is configured to be able to automatically adjust at least one of the rising timing of the second pulse and the falling timing of the third pulse.

[0187] [A9] The test method according to any one of [A1] to [A8], further comprising: a determination step of determining whether or not all adjustments of the interference time have been completed; an interference time adjustment step of adjusting the interference time when it is determined in the determination step that all adjustments of the interference time have not been completed; and an oscillation condition specification step of specifying oscillation conditions based on monitoring results when it is determined in the determination step that all adjustments of the interference time have been completed.

[0188] DESCRIPTION OF SYMBOLS 1, 1A... Power conversion device 2... Control device 3, 3a... DC power supply unit 4... Motor (rotating electric machine) 4ab... Coil (inductive load) 4u, 4v, 4w... Coil 5, 5a... High potential line 6, 6a... Low potential line 10a... Series circuit (first series circuit) 10b... Series circuit (second series circuit) 10u, 10v, 10w... Series circuit 11... Switch unit, 11Ha... High side switch unit (first high side switch unit, first switch unit to be driven) 11Hb... High side switch unit (second high side switch unit, second switch unit to be driven) 11Hu, 11Hv, 11H2... High side switch unit 11La... Low side switch unit (second low side switch unit, first switch unit to be driven) 11Lb... Low side switch unit (second low side switch unit, second switch unit to be driven) DESCRIPTION OF SYMBOLS 11Lu, 11v, 11w...Low-side switch section 12...Driver circuit 12a, 12b...Gate driver (GD) 12Hu, 12Hv, 12Hw, 12Lu, 12Lv, 12Lw...Driver circuit 13, 13a, 13ab...Capacitor 13u, 13v, 13w...Capacitor 20, 20A, 20B...Test circuit 21a, 21b, 22a, 22b...Connection line 30...Drive signal generating section 31...Function generator (FG) 32...DC power supply 40...Monitoring device 41...Differential probe 42...Oscilloscope 100, 100A, 100B...Testing device 111...Transistor 111Ha...High-side transistor, high-side transistor (first high-side transistor) 111Hb...High-side transistor, high-side transistor (second high-side transistor) 111La...Low-side transistor, low-side transistor (second low-side transistor) 111Lb...Low-side transistor, low-side transistor (second high-side transistor) 331, 332...Signal line 341, 342...Signal line 351, 352...Signal line 361, 362...Signal line 431, 432...Probe line 441, 442...Probe line C1, C2...Capacitor N1, N2, N3...Node (connection point) Na, Nb...Node P1...First pulse P2...Second pulse P3...Third pulse S1...First drive signal S2...Second drive signal S11, S21...Test circuit preparation step S12,S22: Driving step; S13, S23: Monitoring step; S15, S25: Interference time adjusting step; S16, S26: Oscillation condition specifying step; Td: First terminal; Tg: Third terminal; Ts: Second terminal; td: Interference time,

Claims

1. A test circuit having: a first series circuit formed by connecting a first high-side switch unit and a first low-side switch unit in series between a high potential line and a low potential line electrically connected to a DC power supply unit; a second series circuit formed by connecting a second high-side switch unit and a second low-side switch unit in series between the high potential line and the low potential line and connected in parallel to the first series circuit between the high potential line and the low potential line; a capacitor connected between the high potential line and the low potential line to smooth the DC voltage supplied from the DC power supply unit; and an inductive load connecting a connection line between the first high-side switch unit and the first low-side switch unit and a connection line between the second high-side switch unit and the second low-side switch unit, wherein the first high-side switch unit has a plurality of first high-side transistors connected in parallel; the first low-side switch unit has a plurality of first low-side transistors connected in parallel; the second high-side switch unit has a plurality of second high-side transistors connected in parallel; and the second low-side switch unit has a plurality of second low-side transistors connected in parallel. the test circuit includes a preparation step of preparing the test circuit; a drive step of driving a first drive target switch unit, which is one of the first high-side switch unit and the first low-side switch unit, with a first drive signal, and driving a second drive target switch unit, which is one of the second high-side switch unit and the second low-side switch unit and is on a different side from the first drive target switch unit in terms of high side and low side, with a second drive signal, the first drive signal being a two-pulse drive signal having a first pulse and a second pulse subsequent to the first pulse, and the second drive signal being a one-pulse drive signal having a third pulse, the rising timing of the third pulse being within the first pulse; and a monitoring step of monitoring a voltage of the switch unit, which is different from the first drive target switch unit, of the first high-side switch unit and the first low-side switch unit, and monitoring the voltage of the second drive target switch unit,and performing the driving step and the monitoring step while adjusting an interference time that is a time difference between the rising timing of the second pulse and the falling timing of the third pulse, thereby acquiring a condition under which oscillation occurs in the second drive target switch unit.

2. The test method according to claim 1, wherein the test circuit has two of the capacitors corresponding to the first series circuit and the second series circuit.

3. The test method according to claim 1, wherein the capacitor is a capacitor common to the first series circuit and the second series circuit.

4. A testing method according to any one of claims 1 to 3, wherein the pair of the first switch unit to be driven and the second switch unit to be driven is the pair of the second high-side switch unit and the first low-side switch unit, or the pair of the second low-side switch unit and the first high-side switch unit.

5. A test method according to any one of claims 1 to 4, wherein the interference time is adjusted by advancing the falling timing of the third pulse.

6. A testing method according to any one of claims 1 to 5, wherein the interference time is adjusted by automatically adjusting at least one of the rising timing of the second pulse and the falling timing of the third pulse.

7. The testing method according to any one of claims 1 to 6, wherein the first high-side switch unit, the first low-side switch unit, the second high-side switch unit, and the second low-side switch unit each have a first terminal, a second terminal, and a third terminal, and the conduction state between the first terminal and the second terminal is controlled in response to a drive signal input to the third terminal, the first terminal of each of the first high-side switch unit and the second high-side switch unit is electrically connected to the high potential line, the second terminal of each of the first low-side switch unit and the second low-side switch unit is electrically connected to the low potential line, the second terminal of the first high-side switch unit and the first terminal of the second high-side switch unit are electrically connected, the second terminal and the third terminal of the switch unit of the first high-side switch unit and the first low-side switch unit other than the first switch unit to be driven are short-circuited, and the second terminal and the third terminal of the switch unit of the second high-side switch unit and the second low-side switch unit other than the second switch unit to be driven are short-circuited.

8. A testing method according to any one of claims 1 to 7, wherein the first series circuit is a leg of a first phase in an n-phase power conversion device, the second series circuit is a leg of a second phase different from the first phase in the n-phase power conversion device, and n is an integer of 2 or greater.

9. A first series circuit formed by connecting in series between a high potential line and a low potential line a first high side switch unit having a plurality of first high side transistors connected in parallel and a first low side switch unit having a plurality of first low side transistors connected in parallel; a second series circuit formed by connecting in series between the high potential line and the low potential line a second high side switch unit having a plurality of second high side transistors connected in parallel and a second low side switch unit having a plurality of second low side transistors connected in parallel; a DC power supply unit supplying a DC voltage between the high potential line and the low potential line; a capacitor connected between the high potential line and the low potential line and smoothing the DC voltage; an inductive load connecting a connection line between the first high side switch unit and the first low side switch unit and a connection line between the second high side switch unit and the second low side switch unit; a drive signal generation unit that generates a two-pulse first drive signal formed of a first pulse and a second pulse subsequent to the first pulse, and a one-pulse second drive signal formed of a third pulse such that the rising timing of the third pulse is within the first pulse, the drive signal generation unit inputting the first drive signal to a first drive target switch unit that is one of the second high-side switch unit and the second low-side switch unit, and inputting the second drive signal to a second drive target switch unit that is a switch unit of the first high-side switch unit and the first low-side switch unit that is on a different side from the first drive target switch unit in terms of high side and low side; and a monitor device that monitors the voltage of the switch unit of the first high-side switch unit and the first low-side switch unit that is different from the first drive target switch unit, and also monitors the voltage of the second drive target switch unit.

10. The test device according to claim 9, wherein the first high-side switch section, the first low-side switch section, the second high-side switch section, and the second low-side switch section each have a first terminal, a second terminal, and a third terminal, and the conduction state between the first terminal and the second terminal is controlled in accordance with a drive signal input to the third terminal, the first terminal of each of the first high-side switch section and the second high-side switch section is electrically connected to the high potential line, the second terminal of each of the first low-side switch section and the second low-side switch section is electrically connected to the low potential line, the second terminal of the first high-side switch section and the first terminal of the second high-side switch section are electrically connected, the second terminal and the third terminal of the switch section of the first high-side switch section and the first low-side switch section other than the first switch section to be driven are short-circuited, and the second terminal and the third terminal of the switch section of the second high-side switch section and the second low-side switch section other than the second switch section to be driven are short-circuited.

11. The test apparatus according to claim 9 or 10, comprising two of the capacitors corresponding to the first series circuit and the second series circuit.

12. The test apparatus according to claim 9 or 10, wherein the capacitor is a common capacitor for the first series circuit and the second series circuit.

13. The test device according to any one of claims 9 to 12, wherein the drive signal generating section is configured to be able to automatically adjust at least one of the rising timing of the second pulse and the falling timing of the third pulse.

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