Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a glass core layer; a core electrode unit disposed on the glass core layer; a build-up insulating unit disposed on the glass core layer; and a build-up wiring unit disposed on the build-up insulating unit, wherein the outermost surface of the glass core layer is slanted with respect to the outermost surface of the build-up insulating unit.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. To prevent this, a glass core structure, in which a glass plate is formed in the core portion of the circuit board, has been proposed.

[0007] However, if the core part is a glass plate, there is a problem of reduced adhesion and reliability between the glass plate and other electrode parts.

[0008] In particular, the glass itself is inherently unreliable, and when manufacturing individual circuit boards from panels into units, the glass plate can become brittle, further weakening the reliability of the circuit boards. Furthermore, manufacturing individual glass units presents challenges, such as additional damage to components due to chamfering and separation between the insulating layer and the glass plate.

[0009] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which have improved reliability by improving the strength of a glass core layer through an inclined structure between a glass core layer and a build-up insulation layer and suppressing separation or damage between the build-up insulation layer and the glass core layer.

[0010] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which suppress damage due to chamfering and reduce residual stress by setting different inclination angles on the outer surfaces of each of the glass core layer and the build-up insulation, thereby preventing breakage problems.

[0011] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which chipping is eliminated according to the surface finish, warping is suppressed through structural symmetry, and mechanical strength degradation is prevented.

[0012] In addition, since the build-up insulation layer and the glass core layer have the same surface through the same process, consistent stress is distributed between them, thereby enabling the implementation of a circuit board with improved mechanical reliability and a semiconductor package including the same.

[0013] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0014] A circuit board according to an embodiment of the present invention includes a glass core layer; a core electrode portion disposed on the glass core layer; a build-up insulation portion disposed on the glass core layer; and a build-up wiring portion disposed on the build-up insulation portion; wherein an outermost surface of the glass core layer is inclined with respect to an outermost surface of the build-up insulation portion.

[0015] The first inclination angle of the outermost surface of the above-mentioned build-up insulation with respect to the upper surface of the glass core layer may be different from the second inclination angle of the outermost surface of the above-mentioned glass core layer with respect to the upper surface of the above-mentioned glass core layer.

[0016] The first slope angle may be smaller than the second slope angle.

[0017] The outer surface of the glass core layer may have a first surface that is the outermost surface and a second surface that is in contact with the first surface and is inclined with respect to the first surface.

[0018] The second surface may be in contact with the upper or lower surface of the glass core layer.

[0019] The length in the vertical direction of the first surface may be greater than the length in the vertical direction of the second surface.

[0020] The second surface may be positioned between the upper surface and the lower surface of the glass core layer.

[0021] The second side may be positioned parallel to and in contact with the outermost surface of the build-up insulation.

[0022] The third inclination angle with respect to the upper surface of the glass core layer of the second surface may be the same as the first inclination angle with respect to the upper surface of the glass core layer of the outermost surface of the build-up insulation.

[0023] The third inclination angle with respect to the upper surface of the glass core layer of the second surface may be different from the second inclination angle with respect to the upper surface of the glass core layer of the outermost surface of the build-up insulation.

[0024] The outermost surface of the above glass core layer may be spaced apart from the outermost surface of the above build-up insulation by a predetermined distance.

[0025] The upper or lower surface of the glass core layer may include a partially exposed surface.

[0026] It may further include a cover layer disposed on the outer surface of the glass core layer and the outer surface of the build-up insulation.

[0027] The above cover layer may be arranged to extend further inward than the outermost surface of the build-up insulation.

[0028] It may further include a protective film spaced apart from the outermost surface of the glass core layer and arranged on the outer surface of the build-up insulation.

[0029] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, which improve reliability by improving the strength of a glass core layer through an inclined structure between a glass core layer and a build-up insulation layer and suppressing separation or damage between the build-up insulation layer and the glass core layer.

[0030] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which suppress damage due to chamfering and reduce residual stress by setting different inclination angles on the outer surfaces of each of the glass core layer and the build-up insulation, thereby preventing breakage problems.

[0031] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which chipping is eliminated according to the surface finish, warping is suppressed through structural symmetry, and mechanical strength degradation is prevented.

[0032] In addition, since the build-up insulation layer and the glass core layer have the same surface through the same process, consistent stress is distributed between them, thereby providing a circuit board with improved mechanical reliability and a semiconductor package including the same.

[0033] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0034] Figure 1 is a plan view of a circuit board according to a first embodiment of the present invention.

[0035] Figure 2 is a drawing taken along line AA' in Figure 1,

[0036] Figure 3 is an enlarged view of part K1 in Figure 2,

[0037] Figure 4 is another example of Figure 3,

[0038] Figure 5 is another example of Figure 3,

[0039] Fig. 6 is another example of Fig. 3,

[0040] Fig. 7 is another example of Fig. 3,

[0041] Figures 8 to 15 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0042] Fig. 16 is a cross-sectional view of a circuit board according to the second embodiment,

[0043] Figure 17 is an enlarged view of the K2 portion in Figure 16,

[0044] Fig. 18 is a cross-sectional view of a circuit board according to the third embodiment.

[0045] Figure 19 is an enlarged view of part K3 in Figure 18,

[0046] Fig. 20 is another example of Fig. 19,

[0047] Fig. 21 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0048] Fig. 22 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0049] Fig. 23 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0050] Fig. 24 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0051] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0052] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0053] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0054] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0055] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0056] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0057] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0058] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0059] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0060] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0061] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0062] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0063] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0064] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0065] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0066] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0067] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0068] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0069] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0070] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0071] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0072] FIG. 1 is a plan view of a circuit board according to a first embodiment of the present invention, FIG. 2 is a view taken along line AA' in FIG. 1, FIG. 3 is an enlarged view of a portion K1 in FIG. 2, FIG. 4 is another example of FIG. 3, FIG. 5 is another example of FIG. 3, FIG. 6 is another example of FIG. 3, and FIG. 7 is another example of FIG. 3.

[0073] Referring to FIGS. 1 and 2, a circuit board (100) according to the first embodiment may include an insulating portion (110) and an electrode portion (120). In the embodiment, the insulating portion (110) may be provided in a structure in which a plurality of insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the plurality of insulating portions (110), thereby performing a function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0074] In addition, the circuit board (100) may include a protective layer (SR) and a build-up structure. The build-up structure may include a build-up insulating portion and a build-up wiring portion. In addition, the build-up structure may include a core portion including a glass core layer (111) and a core electrode portion (121). In addition, the build-up insulating portion may be formed of a plurality of build-up layers. For example, when the circuit board includes a core layer, the build-up insulating portions (112, 113) may include an upper build-up insulating portion (112) and a lower build-up insulating portion (113), as in the embodiment. Specifically, in the embodiment, the circuit board may include an upper build-up insulating portion (112) disposed on an upper surface of the core layer and a lower build-up insulating portion (113) disposed on a lower surface of the core layer. Specifically, as illustrated, the circuit board (100) may include a glass core layer (111), a build-up insulating portion (112, 113), a core electrode portion (121), and a build-up wiring portion (122, 123). Furthermore, the circuit board (100) may further include a protective layer (SR) disposed on an upper surface of the upper build-up insulating portion and / or a lower surface of the lower build-up insulating portion. In addition, in the following embodiments of the present invention, the upper and / or lower build-up insulating portions (112, 113) may include a plurality of insulating layers laminated along a vertical direction (Y-axis direction). In the embodiment, the horizontal direction may be a first direction or X-axis direction, and the vertical direction (or lamination direction) may be a second direction or Y-axis direction. The horizontal direction and the vertical direction may be perpendicular to each other. The build-up wiring section (122, 123) is disposed and embedded in each layer (e.g., insulating layer) of the build-up insulation section (112, 113), thereby performing the function of transmitting signals and / or power from the main board (not shown) to the semiconductor element. The build-up wiring section (122, 123) may include a circuit layer and a via electrode.The circuit layer may be arranged on one surface of each of a plurality of insulating layers included in the upper and / or lower build-up insulating portions to transmit signals and / or power, and the via electrode may penetrate at least a portion of each of the plurality of insulating layers to electrically connect each circuit layer. In addition, the circuit layer may include a bonding portion (not shown) arranged on the build-up insulating portion to electrically connect the semiconductor element and / or the electronic element with the circuit board.

[0075] The insulating portion (110) of the circuit board or each insulating layer forming the insulating portion (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating portion (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating portion (110) of the circuit board may include sapphire. For example, the insulating portion (110) of the circuit board may include an optically isotropic film. For example, the insulating portion (110) of the circuit board may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA). For example, the insulating portion (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating portion (110) of the circuit board may have a structure in which a filler such as silica or alumina is arranged in a thermosetting resin or a thermoplastic resin. The insulating portion (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0076] In one embodiment, the insulation (110) may include a glass core layer (111) including a reinforcing member.

[0077] The glass core layer (111) may be made of a glass material. For example, the glass core layer (111) may include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials such as fluorine glass, phosphate glass, chalcogen glass, etc. may also be used. In addition, the glass core layer (111) may further include other additives to form a glass having specific physical properties. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these and other elements. In addition, the glass core layer (111) may include an insulating material.

[0078] The glass core layer (111) can suppress warpage that occurs due to thinning of the circuit board. In other words, by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board, warpage can be reduced. For example, the glass core layer (111) may have high rigidity and a low coefficient of thermal expansion compared to other insulating layers or protective layers.

[0079] And the upper build-up insulation part (112) or the lower build-up insulation part (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin can be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and can include an inorganic filler such as silica. When the insulating resin is used as a core, it can include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating portion (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating portion (110) can be provided by laminating ABF without a core layer.

[0080] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0081] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and may be arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0082] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0083] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layers in the build-up insulating portions (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the glass core layer (111), the upper build-up insulating portion (112), and the lower build-up insulating portion (113).

[0084] Specifically, in the embodiment, the electrode portion (120) may include a core electrode portion (121) and a build-up wiring portion (122, 123). The build-up wiring portion (122, 123) may include an upper electrode portion (122) and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up wiring portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up insulation portion (112) and may be an 'upper build-up wiring portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up insulation portion (113) and may be a 'lower build-up layer electrode portion'. Alternatively, the electrode portion may include a build-up wiring portion and a build-up via electrode (via portion).

[0085] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the glass core layer (111) and a core via electrode (121b) penetrating the glass core layer (111).

[0086] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up insulating portion (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up insulating portion (112).

[0087] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up insulation portion (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up insulation portion (113).

[0088] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion (second wiring portion) having a fine pitch and a wiring portion (first wiring portion) having a pitch larger than the second wiring portion.

[0089] The protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material that has insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0090] The protective layer (SR) may be disposed on the build-up insulation portions (112, 113). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on the upper build-up insulation portion (112) and a second protective layer (SR2) disposed under the lower build-up insulation portion (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along the lamination direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0091] Furthermore, the circuit board (100) may further include ` located on the outer surface.

[0092] As illustrated, the cover layer (CV) may be positioned at the outermost side of the circuit board (100). The cover layer (CV) may cover the outer surface of the glass core layer (111) and the outer surfaces of the build-up insulating portions (112, 113). In addition, the cover layer (CV) may also cover the outer surface of the protective layer (SR). With this configuration, the strength of the glass core layer is improved after chamfering of the glass core layer (111), and the outer surface can be easily protected. In addition, separation between the build-up insulating portion and the glass core layer, lifting of the pattern, damage, etc. can be suppressed by the coating layer. Therefore, the reliability of the circuit board can be improved.

[0093] The bonding portion (not shown) may be disposed on the protective layer (SR). For example, the bonding portion (not shown) may be disposed on the upper surface of the protective layer (SR). The bonding portion (not shown) may be located outside the build-up wiring portions (122, 123). For example, in the upper build-up insulating portion (112), the bonding portion (not shown) may be located on the upper surface of the build-up wiring portions (122, 123). In addition, the bonding portion (not shown) may include a protrusion disposed on the upper surface of the protective layer (SR) and a via region penetrating the protective layer (SR). In an embodiment, the via region and the protrusion may each include a plurality of protrusions or convex portions protruding toward an adjacent protective layer (SR). For example, on the first protective layer (SR1), the via region and the protrusion may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0094] Furthermore, the bonding portion (not shown) may include a plurality of metal layers, or additional metal layers may be disposed on the bonding portion. The durability and reliability of the bonding portion (not shown) can be further improved. For example, the bonding portion or the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. As a result, the bonding strength between the metal layer and the bonding portion (not shown) is improved, and the corrosion resistance and durability of the bonding portion (not shown) are improved, and the loss of electrical signals can also be minimized. The metal layer may be formed on the bonding portion (not shown) by deposition, electroplating, or the like of various metals.

[0095] In addition, a semiconductor element may be placed on the upper build-up insulating portion (112). The semiconductor element may be electrically connected to the second wiring portion, which is the aforementioned micro-pattern. The circuit board may be placed so as to have a high wiring density for connecting the semiconductor element and signals. In addition, the second wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided so as to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0096] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0097] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0098] Referring further to FIG. 3, in the circuit board (100) according to the embodiment, the outermost surface (IS1) of the glass core layer (111) may be positioned at an angle with respect to the outermost surface (IS2) of the build-up insulation. As described above, the upper build-up insulation (112) may be positioned on the upper surface (US) of the glass core layer (111), and the lower build-up insulation (113) may be positioned on the lower surface (BS) of the glass core layer (111). Hereinafter, the build-up insulation will be described based on the upper build-up insulation.

[0099] In addition, in the embodiment, the inclination of the outermost side surface (IS1) of the glass core layer (111) may be different from the inclination of the outermost side surface (IS2) of the build-up insulation portion (112). That is, the first inclination angle (θ1) may be different from the second inclination angle (θ2). The first inclination angle (θ1) may be the inclination angle of the outermost side surface (IS2) of the build-up insulation portion (112) with respect to the upper surface (US) of the glass core layer (111). And the second inclination angle (θ2) may be the inclination angle of the outermost side surface (IS1) of the glass core layer (111) with respect to the upper surface (US) of the glass core layer (111). The second inclination angle (θ2) may be the inclination angle formed in a part of the outermost side surface (IS1) of the glass core layer (111) with respect to the upper surface (US1) of the glass core layer (111). For example, the second inclination angle (θ2) may be an inclination angle formed at the center of the outermost surface (IS1) of the glass core layer (111) in the lamination direction (Y-axis direction) with the upper surface (US) of the glass core layer (111). In the drawing, the inclination angle is illustrated through virtual planes (VUS1, VUS2) that are parallel to the upper surface (US) of the glass core layer (111). In addition, the inclination angle may be an angle formed based on the inner side, not the outer side, of the circuit board.

[0100] In addition, due to the chamfering of the glass core layer (111), the inclination angles (e.g., the first inclination angle (θ1), the second inclination angle (θ2)) of the outermost surface (IS1) of the glass core layer (111) and the outermost surface (IS2) of the build-up insulation portion (112) may be different from each other. As a result, the breakage phenomenon (chipping) of the glass core layer (111) can be easily eliminated, so that the strength of the glass core layer (111) can be further improved. The residual stress can be reduced, so that breakage of the glass core layer can be prevented. Furthermore, damage due to the chamfering of the upper build-up insulation portion (112) can be further suppressed. Accordingly, the reliability of the circuit board can be further improved.

[0101] In addition, in the embodiment, the first inclination angle (θ1) may be smaller than the second inclination angle (θ2). By this configuration, the build-up insulation (112) in contact with the upper surface (US) of the glass core layer (111) can be positioned further apart from the chamfering device or chamfering machine during chamfering. Accordingly, damage to the build-up insulation (112) can be further prevented. In addition, the area where chipping is removed in the glass core layer (111) due to chamfering increases, and the shape of the glass core layer (111) can have structural symmetry even after chamfering. In other words, by suppressing the shape of a groove or the like on the outermost surface (IS1) of the glass core layer (111), the decrease in mechanical strength can be reduced, the distortion phenomenon can be suppressed, and the thermal imbalance can also be resolved.

[0102] In addition, the outer surface (IS1) of the glass core layer (111) may include a first surface (IS1a) and a second surface (IS1b). The first surface (IS1a) may be the outermost surface of the outer surface (IS1) of the glass core layer. And the second surface (IS1b) may be an outer surface located between the first surface (IS1a) and the upper surface (US) (or lower surface). Accordingly, the second surface (IS1b) may be in contact with the upper surface (US) or the lower surface (BS) of the glass core layer (111). For example, the second surface (IS1b) may be parallel to the upper surface (US) or the lower surface (BS) of the glass core layer (111) and form the same surface.

[0103] Additionally, the first side (IS1a) may be in contact with the second side (IS1b). The first side (IS1a) may be misaligned with the second side (IS1b) in the horizontal direction (X-axis direction). That is, the first side (IS1a) may not overlap with the second side (IS1b) in the horizontal direction (X-axis direction).

[0104] And the first surface (IS1a) and the second surface (IS1b) are components of the outer surface (IS1`) of the glass core layer (111) and can be positioned between the upper surface (US) and the lower surface (BS) of the glass core layer (111).

[0105] In an embodiment, the first side (IS1a) may not be parallel to the second side (IS1b). That is, the first side (IS1a) may not be flush with the second side (IS1b) but may be inclined at a predetermined angle.

[0106] That is, the angle formed by the first surface (IS1a) with the virtual surface (VUS2) may correspond to the second inclination angle (θ2). The angle formed by the second surface (IS1b) with the virtual surface (VUS1) may be different from the second inclination angle (θ2). In addition, the angle formed by the second surface (IS1b) with the virtual surface (VUS1) may be a third inclination angle (θ3). In other words, the third inclination angle (θ3) may be the inclination angle of the second surface (IS1b) with respect to the upper surface (US) of the glass core layer (111).

[0107] In addition, the third inclination angle (θ3) according to the embodiment may be the same as the first inclination angle (θ1). In other words, in the circuit board according to the embodiment, at least a part (e.g., the second surface) of the outer surface (IS) of the glass core layer (111) may form the same surface as the outer surface (IS2) of the build-up insulating portion (112). In addition, the second surface (IS1b) may be in contact with and positioned parallel to the outer surface (IS2) of the build-up insulating portion (112).

[0108] By this configuration, the same dicing or chamfering process is performed simultaneously on the build-up insulation (112) and the glass core layer (111), so that a consistent stress can be distributed between the build-up insulation (112) and the glass core layer (111) at the interface between the build-up insulation (112) and the glass core layer (111), or separation between them can be suppressed. Accordingly, the reliability of the circuit board can be further improved.

[0109] Additionally, the third inclination angle (θ3) according to the embodiment may be different from the second inclination angle (θ2). In other words, in the circuit board according to the embodiment, the outer surface (IS) of the glass core layer (111) may not form a parallel surface between one region and another region.

[0110] By this configuration, the build-up insulation (112) can be positioned on the upper surface (US) or lower surface (BS) of the glass core layer (111) and can be spaced apart from the first surface (IS1a) of the glass core layer (111) in the horizontal direction (X-axis direction) as much as possible.

[0111] Additionally, at least a portion of the outer surface of the build-up insulation (112) may be spaced apart from the second surface (IS1b) in the horizontal direction (X-axis direction).

[0112] This configuration can further reduce damage to the upper build-up insulation due to chamfering. This can further improve the reliability of the circuit board.

[0113] In addition, the thickness (T1) of the first side (IS1a) may be different from or the same as the thickness (T2) of the second side (IS1b). The thickness (T1) of the first side (IS1a) is the length in the vertical direction (Y-axis direction) of the first side (IS1a). And the thickness (T2) of the second side (IS1b) is the length in the vertical direction (Y-axis direction) of the second side (IS1b). In this example, the thickness (T1) of the first side (IS1a) may be different from the thickness (T2) of the second side (IS1b). And the thickness (T1) of the first side (IS1a) may be greater than the thickness (T2) of the second side (IS1b).

[0114] This configuration allows for a relative increase in the area (or volume) at the center of the glass core layer. This facilitates the maintenance of the circuit board's mechanical strength. Furthermore, it can alleviate stress concentration at the center of the glass core layer.

[0115] In addition, a cover layer (CV) may be disposed on the outer surface (IS1) of the glass core layer (111). In addition, the cover layer (CV) may also be disposed on the outer surface (IS2) of the build-up insulation. Accordingly, the outer surface of the circuit board can be easily protected. In particular, by preventing the formation of cracks or the like on the outer surface of the inner glass core layer (111), the reliability of the circuit board can be improved.

[0116] Additionally, the cover layer (CV) may extend further inward than the outer surface (IS1) of the build-up insulation (112). For example, the cover layer (CV) may be positioned on the exposed upper surface (or lower surface) of the build-up insulation.

[0117] Additionally, the cover layer (CV) may be positioned on the outer surface of the protective layer (SR). The cover layer (CV) may be positioned on the exposed upper surface (or lower surface) of the protective layer.

[0118] Furthermore, as described above, the upper build-up insulation (112) may be formed of a plurality of layers. For example, the upper build-up insulation (112) may include a first upper build-up insulation (112a) and a second upper build-up insulation (112b). The first upper build-up insulation (112a) and the second upper build-up insulation (112b) may be sequentially laminated in the lamination direction. In addition, the first-first inclination angle (θ1a) with respect to the outermost surface of the first upper build-up insulation (112a) and the first-second inclination angle (θ1b) of the second upper build-up insulation (112b) may be the same as or different from each other. For example, as illustrated, the first-first inclination angle (θ1a) with respect to the outermost surface of the first upper build-up insulation (112a) and the first-second inclination angle (θ1b) of the second upper build-up insulation (112b) may be different. Additionally, the first-first inclination angle (θ1a) with respect to the outermost surface of the first upper build-up insulation portion (112a) may be greater than the first-second inclination angle (θ1b) with respect to the second upper build-up insulation portion (112b). Conversely, the first-first inclination angle (θ1a) with respect to the outermost surface of the first upper build-up insulation portion (112a) may be smaller than the first-second inclination angle (θ1b) with respect to the second upper build-up insulation portion (112b).

[0119] And as a variation, the slope of the outer surface of at least some layers of the upper build-up insulation (112) may correspond to the second slope angle.

[0120] Referring further to FIG. 4, the first inclination angle (θ1) is the inclination angle of the outer surface (IS2) of the build-up insulation with respect to the upper surface (US2) of the glass core layer (111). And the second inclination angle (θ2) may be the inclination angle of the outermost surface (IS1) of the glass core layer (111) with respect to the upper surface (US) of the glass core layer (111). In addition, the third inclination angle (θ3) may be the angle formed by the second surface (IS1b) with the imaginary plane or the inclination angle of the second surface (IS1b) with respect to the upper surface (US) of the glass core layer (111).

[0121] In another example, the third inclination angle (θ3) may be different from the first inclination angle (θ1). In other words, in the circuit board according to the embodiment, the outer surface (IS) of the glass core layer (111) in contact with the build-up insulation may not have a surface that is parallel to the outer surface (IS2) of the build-up insulation (112). That is, the outer surface (IS) of the glass core layer (111) may form the same surface as the outer surface (IS2) of the build-up insulation (112). For example, the third inclination angle (θ3) may be greater than the first inclination angle (θ1). By this configuration, the distance between the outermost surface of the glass core layer (111) and the build-up insulation can be secured to the maximum extent possible. By this configuration, the strength of the glass core layer through chamfering can be improved while damage due to chamfering can be further suppressed. Accordingly, the reliability of the circuit board can be further improved.

[0122] Referring further to FIG. 5, the thickness of the glass core layer (111) may also vary from region to region. For example, the thickness (T1) of the first surface (IS1a) may be different from the thickness (T2) of the second surface (IS1b). In another example, the thickness (T1) of the first surface (IS1a) may be greater than the thickness (T2) of the second surface (IS1b).

[0123] In addition, the thickness of the second surface (IS1b) may also vary depending on the position of the second surface. For example, the thickness (T2a) of the second surface in contact with the upper surface (US) of the glass core layer (111) may be different from the thickness (T2b) of the second surface in contact with the lower surface (BS). The thickness (T2a) of the second surface in contact with the upper surface (US) of the glass core layer (111) may be smaller or larger than the thickness (T2b) of the second surface in contact with the lower surface (BS).

[0124] By this configuration, the area (or volume) at the center of the glass core layer can be relatively increased. For example, the thickness of each region of the second surface can be adjusted based on the circuit pattern on the upper or lower side, the thickness of the build-up insulation, etc. based on the glass core layer (111). As a result, stress concentration, etc. can be alleviated, and the mechanical strength of the circuit board can be easily maintained while thermal expansion can be easily controlled, thereby improving the reliability of the board.

[0125] In addition, in response to this thickness difference, the second surface may have different inclination angles depending on the location. Referring further to FIG. 6, according to another example, the inclination angles may be different for each region on the outer surface (IS1) of the glass core layer (111). In a circuit board, the outer surface (IS) of the glass core layer (111) may not form parallel surfaces between one region and another region. Accordingly, the third inclination angle (θ3) may be different from the second inclination angle (θ2).

[0126] Furthermore, the third inclination angle (θ3) on the second surface in contact with the upper surface (US) and the third inclination angle (θ3') on the second surface in contact with the lower surface (BS) may also be different from each other. For example, the third inclination angle (θ3) on the second surface in contact with the upper surface (US) may be less than or equal to the third inclination angle (θ3') on the second surface in contact with the lower surface (BS).

[0127] Furthermore, the first inclination angle (θ1) may be the same as the third inclination angle (θ3). However, the first inclination angle (θ1) on the outer surface of the upper build-up insulation portion (112) may be different from the first inclination angle (θ1') on the outer surface of the lower build-up insulation portion (113).

[0128] Additionally, the second inclination angles (θ2, θ2') at the outermost surfaces (IS2, IS2') of the build-up insulation (112) in contact with the upper surface (US) or the lower surface (BS) may also be different from each other.

[0129] On the outer surface of the first protective layer (SR1), the fourth inclination angle (θ4) may be the same as the first inclination angle (θ1). And, the inclination angles may be different depending on the position of the protective layer.

[0130] For example, the fourth inclination angle (θ4) on the outer surface of the first protective layer (SR1) may be different from the fourth inclination angle (θ4') on the outer surface of the second protective layer (SR2).

[0131] By this configuration, the distance between the outermost surface of the glass core layer of the upper build-up insulation portion and the lower build-up insulation portion based on the glass core layer (111) may be different. In addition, this may be equally applied to the protective layer on the build-up insulation portion. In addition, the angle of each region of the second surface may be adjusted depending on the circuit pattern in the upper build-up insulation portion or the lower build-up insulation portion and the thickness of the build-up insulation portion. This makes it easy to control stress or thermal expansion, thereby improving the reliability of the substrate.

[0132] Referring further to Fig. 7, the thickness (T1) of the first side (IS1a) may be different from the thickness (T2) of the second side (IS1b). In this example, the thickness (T1) of the first side (IS1a) may be smaller than the thickness (T2) of the second side (IS1b). In response to the thickness of the second side (IS1b), the distance between the build-up insulation and the first side (IS1a), which is the outermost surface of the glass core layer (111), may increase. Accordingly, the distance between the beveling device or the beveling machine and the build-up insulation can be easily secured during beveling. Accordingly, damage to the build-up insulation can be prevented more effectively.

[0133] Figures 8 to 15 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0134] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0135] In addition, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of a plurality of unit circuit boards. The mother circuit board may be separated into a plurality of unit circuit boards along a sawing line. To form such a mother circuit board, a glass layer may be first placed. The glass layer (or glass core layer) may be manufactured by various methods. The following description will be based on the manufacturing of a unit circuit board.

[0136] A method for manufacturing a circuit board according to an embodiment may include a step of providing a glass core layer, a step of forming a first through hole in the glass core layer, a step of forming a core electrode portion on an upper surface and a lower surface of the glass core layer and an inner surface of the first through hole, a step of forming an upper build-up insulating portion and a lower build-up insulating portion, a step of forming a build-up wiring portion, a step of forming a protective layer, etc., a step of performing dicing, a step of performing chamfering on an outer surface of a diced circuit board, and a step of forming a protective film or forming a cover layer.

[0137] Referring to FIG. 8, a method for manufacturing a glass core layer (or core substrate) in a circuit board according to an embodiment may first prepare a glass core layer (111) made of glass. The glass core layer (111) may correspond to the glass core layer or core layer described above.

[0138] Referring to FIG. 9, a first through hole (111h) can be formed in the glass core layer (111). The first through hole (111h) can correspond to the via hole described above. The first through hole (111h) can be formed by performing etching on both sides of the glass core layer (111). For example, a via electrode can be formed in the via hole or through hole of the glass layer. For example, the first through hole (111h) can be formed by a photolithography process using a photomask or various etching methods such as a laser method.

[0139] Referring to FIG. 10, a seed layer (121') of a core electrode portion can be formed on one surface (upper surface or lower surface) of a glass core layer (111). For example, a seed layer (121') of a core electrode portion can be formed on the upper surface and the lower surface of the glass core layer (111) and the inner wall of the first through hole (111h). For example, a dry method (e.g., sputtering), wet method, etc. can be applied to the formation of the seed layer (121') of the core electrode portion. In particular, spin coating, diffusion coating, spray coating, dip coating, etc., or CVD, ALD, etc. can be applied here.

[0140] Referring to Fig. 11, plating can be performed on the seed layer (121') of the core electrode portion. Plating on the seed layer (121') of the core electrode portion can be performed by various methods. Thus, the core electrode portion (121) can be formed.

[0141] For example, the seed layer and the plating layer can be formed by sputtering. Sputtering is a technology that bombards a target (metal plate) with an inert element such as argon to expel metal molecules and then attach a film to the surface. When an inert gas is flowed as a sputtering gas in a vacuum chamber and a direct current is applied to the target, plasma can be generated between the substrate to be deposited and the target. In this plasma, the inert gas can be ionized into positive ions by a high-power direct current system. At this time, the positive ions of the inert gas can be accelerated to the cathode by the direct current system and collide with the surface of the target. The target material that collides with the surface of the target in this way can be ejected from the surface by exchanging momentum through a perfectly elastic collision between the atoms. When ions collide with a kinetic energy greater than the interatomic binding energy of a material, the ion impact pushes atoms between the material's lattice to different locations, resulting in surface escape. This phenomenon is called sputtering. Various plating methods, as described above, can also be used. This allows the formation of a core electrode.

[0142] In addition, as described above, the core electrode portion can be formed of a first layer and a second layer. The core electrode portion can be recrystallized through a heat treatment method such as Condition 2 or Condition 3 described above. As a result, the core electrode portion can have the density of the azimuth plane and the average grain size described above.

[0143] Referring to Fig. 12, after the core electrode portion (121) is formed on the glass core layer (111), an upper build-up insulating portion (112) and a lower build-up insulating portion (113) may be further formed. Similarly, a through hole may be formed in each insulating layer, and a build-up wiring portion may be formed in each insulating layer. The build-up wiring portion may be formed by a method such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards.

[0144] Furthermore, a protective layer may also be formed on the build-up insulation portion (112, 113). For example, the protective layer may be formed on the upper or lower portion of the upper build-up insulation portion (112) and the lower build-up insulation portion (113). Additionally, an opening area for a conductive member may be formed in the protective layer.

[0145] Additionally, the build-up insulation (112, 113) and the protective layer may not be formed in some areas on the glass core layer (111). And dicing may be performed on the exposed glass core layer (111).

[0146] First, circuit boards can be manufactured into individual units through dicing from a large panel form. Prior to dicing, the panels can be inspected for defects (scratches, open circuits, etc.).

[0147] And by performing dicing, circuit boards of individual units can be manufactured. At this time, dicing can be performed in various ways. For example, dicing can include various cutting methods, such as mechanical dicing, laser dicing, and etching dicing.

[0148] Dicing can be performed at various angles, as illustrated. For example, dicing can be performed in various directions, such as perpendicular to or non-perpendicular to the upper surface of the glass core layer. Accordingly, the outer surface of each circuit board separated into individual units by dicing can have the shape of the outer surface described in the circuit board according to various embodiments.

[0149] Referring to Fig. 13, chamfering may be performed after dicing. The chamfering may be performed on the outer surface of the circuit board. Such chamfering may include mechanical chamfering, chemical chamfering, thermal chamfering, waterjet chamfering, ultrasonic chamfering, etc. However, in addition to 'chamfering', chamfering may also be called 'edge treatment', etc.

[0150] In this example, thermal chamfering is performed using a chamfering device (HE), so that the chamfering process can be performed quickly without mechanical cracking on the outer surface of the glass core layer (111). Furthermore, through precise processing, cracks such as microcracks formed on the outer surface of the glass core layer (111) can be easily removed.

[0151] Referring to FIGS. 14 and 15, a protective film (see FIG. 19, etc.) can be formed on the outer surface of the build-up insulation (protective layer). The protective film can be spaced horizontally from the outermost surface of the glass core layer (111).

[0152] And a cover layer (CV) can be formed. The cover layer (CV) can be arranged on the outer surface of the glass core layer (111) and the outer surface of the build-up insulation (112, 113).

[0153] Afterwards, chips, etc. may be mounted on the circuit board, or additional processes such as molding may be performed.

[0154] Furthermore, the structures of the various embodiments and modifications described above can be equally applied to the circuit board according to the present embodiment.

[0155] Fig. 16 is a cross-sectional view of a circuit board according to the second embodiment, and Fig. 17 is an enlarged view of part K2 in Fig. 16.

[0156] Referring to FIGS. 16 and 17, a circuit board (100A) according to the second embodiment may include an insulating portion (110) and an electrode portion (120). In the embodiment, the insulating portion (110) may be provided with a structure in which a plurality of insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the plurality of insulating portions (110), thereby performing a function of transmitting a signal and / or power from a main board (not shown) to a semiconductor element. Furthermore, the circuit board (100) may further include a protective layer, a bonding layer, a cover layer, etc. disposed on the electrode portion (120).

[0157] Furthermore, the configurations described in the embodiments of the present invention can be applied equally, except for the details described below. Furthermore, the structures of the various modified examples described above can also be applied equally, except for the details described below.

[0158] In this embodiment, the outermost side (IS1) of the glass core layer (111) can be spaced apart from the outermost side (IS2) of the build-up insulation (112) by a predetermined distance (gap1, gap2).

[0159] Accordingly, the upper surface (US) and the lower surface (BS) of the glass core layer (111) may be at least partially exposed. That is, the upper surface (US) of the glass core layer (111) may include an exposed surface (OA1). Similarly, the lower surface (BS) of the glass core layer (111) may include an exposed surface (OA2). In addition, at least a portion of the upper surface (US) and the lower surface (BS) of the glass core layer (111) may not be in contact with the build-up insulation (112, 113). In other words, at least a portion of the upper surface (US) and the lower surface (BS) of the glass core layer (111) may not overlap the build-up insulation (112, 113) in the vertical direction (Y-axis direction).

[0160] This can be applied equally to the protective layer. Furthermore, due to the chamfering, the outermost surface (IS1) of the glass core layer (111) can have a round or curved structure. In addition, the second inclination angle (θ2) of the outermost surface (IS1) of the glass core layer (111) can be different from the first inclination angle (θ1) of the outer surface (IS2) of the build-up insulation portion (112, 113).

[0161] Additionally, the first separation distance (gap1) between the upper build-up insulation (112) and the outermost surface (IS1) of the glass core layer (111) may be the same as or different from the second separation distance (gap2) between the lower build-up insulation (113) and the outermost surface (IS1) of the glass core layer (111).

[0162] For example, the first separation distance (gap1) between the upper build-up insulation (112) and the outermost surface (IS1) of the glass core layer (111) may be different from the second separation distance (gap2) between the lower build-up insulation (113) and the outermost surface (IS1) of the glass core layer (111).

[0163] The position and area of ​​the upper build-up insulation (112) and the lower build-up insulation (113) can be controlled based on the glass core layer (111). Accordingly, stress control and thermal expansion control can be easily performed, thereby improving the reliability of the substrate.

[0164] Fig. 18 is a cross-sectional view of a circuit board according to the third embodiment, Fig. 19 is an enlarged view of part K3 in Fig. 18, and Fig. 20 is another example of Fig. 19.

[0165] Referring to FIGS. 18 to 20, a circuit board (100B) according to a third embodiment may include an insulating portion (110) and an electrode portion (120). In an embodiment, the insulating portion (110) may be provided in a structure in which a plurality of insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the plurality of insulating portions (110), thereby performing a function of transmitting signals and / or power from a main board (not shown) to a semiconductor element. Furthermore, the circuit board (100) may further include a protective layer, a bonding layer, a cover layer, etc. disposed on the electrode portion (120).

[0166] Furthermore, the configurations described in the embodiments of the present invention can be applied equally, except for the details described below. Furthermore, the structures of the various modified examples described above can also be applied equally, except for the details described below.

[0167] In this example, the circuit board may further include a protective film (CT1, CT2) spaced apart from the outermost surface of the glass core layer (111) and arranged on the outer surface of the build-up insulation (112, 113).

[0168] The protective film (CT1, CT2) may also be positioned on the outer surface of the protective layer. That is, the protective film (CT1, CT2) may be positioned on the outer surface of the first protective layer and the outer surface of the second protective layer.

[0169] The outermost surface of the glass core layer (111) may be spaced apart from the outermost surface of the build-up insulation (112). Accordingly, the upper surface (US) and the lower surface (BS) of the glass core layer (111) may be at least partially exposed. The structures of the glass core layer and the build-up insulation in the second embodiment described above may be applied in the same manner. Accordingly, the upper surface (US) of the glass core layer (111) may include an exposed surface. In addition, corresponding to the upper surface, the lower surface (BS) of the glass core layer (111) may include an exposed surface that is exposed.

[0170] In addition, at least a portion of the upper surface (US) and the lower surface (BS) of the glass core layer (111) may not be in contact with the build-up insulation (112, 113). In other words, at least a portion of the upper surface (US) and the lower surface (BS) of the glass core layer (111) may not overlap with the build-up insulation (112, 113) in the vertical direction (Y-axis direction). In addition, this structure may be equally applied to the protective layer.

[0171] And the protective films (CT1, CT2) can overlap at least partially in the horizontal direction with the build-up insulation (112, 113) or the protective layers (SR1, Sr2). And the protective films (CT1, CT2) can overlap in the vertical direction with the glass core layer (111). In addition, the protective films (CT1, CT2) can be arranged to be spaced apart from the outermost surface of the glass core layer (111) in the horizontal direction.

[0172] By using these protective films (CT1, CT2), the phenomenon of the build-up insulation and the protective layer being damaged by chamfering equipment, etc. can be suppressed.

[0173] Furthermore, the thickness of the cover layer (CV) may vary depending on the location. For example, the cover layer (CV) may have a different thickness (Taa) on the upper surface of the first protective layer (SR1) and a different thickness (Tab) on the exposed surface (OA1) exposed on the upper surface (US). Considering reliability, etc., the thickness (Tab) on the exposed surface (OA1) of the cover layer (CV) exposed on the upper surface (US) may be greater than the thickness (Taa) on the upper surface of the first protective layer (SR1).

[0174] In addition, as another example, the cover layer (CV) may be positioned at the outermost side of the circuit board (100) and may have a constant thickness (Taa, Tab). For example, the cover layer (CV) may be arranged along the outer surface and the exposed upper surface of the glass core layer (111) and the outer surface of the build-up insulation (protective layer), and may have a folded structure corresponding to the shape of the outer surface of these components. That is, the cover layer (CV) may have a shape corresponding to the topology of the components to which it is attached. For example, the cover layer (CV) may have the same thickness (Taa) at the upper surface of the first protective layer (SR1) and the same thickness (Tab) at the exposed surface (OA1) exposed from the upper surface (US).

[0175] Fig. 21 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 22 is a cross-sectional view showing a semiconductor package according to the second embodiment, Fig. 23 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 24 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0176] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0177] Referring to FIG. 21, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0178] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0179] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0180] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0181] A second substrate (1200) may be placed on the first substrate (1100).

[0182] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0183] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0184] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0185] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0186] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0187] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0188] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0189] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0190] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0191] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0192] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0193] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a solder layer formed between the plurality of components by recrystallization.

[0194] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0195] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0196] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0197] Additionally, looking further into FIG. 21, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0198] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0199] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0200] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0201] Referring to FIG. 22, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0202] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0203] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0204] Referring to FIG. 23, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0205] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0206] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0207] Referring to FIG. 24, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0208] In this way, the semiconductor package of the fourth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0209] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0210] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0211] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0212] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0213] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0214] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0215] The semiconductor package of the fourth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0216] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0217] Meanwhile, the third semiconductor element (1330) in the fourth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0218] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0219] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0220] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0221] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0222] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0223] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Glass core layer; A core electrode portion disposed on the above glass core layer; A build-up insulation layer disposed on the glass core layer; and Includes a build-up wiring section arranged in the above build-up insulation section; A circuit board in which the slope of the outermost surface of the glass core layer is different from the slope of the outermost surface of the build-up insulation.

2. In paragraph 1, A circuit board in which the first inclination angle of the upper surface of the glass core layer on the outermost surface of the above-mentioned build-up insulation is different from the second inclination angle of the upper surface of the glass core layer on the outermost surface of the above-mentioned glass core layer.

3. In paragraph 2, A circuit board wherein the first inclination angle is smaller than the second inclination angle.

4. In paragraph 1, A circuit board having a first surface, which is the outermost surface of the glass core layer, and a second surface that is in contact with the first surface and is inclined with respect to the first surface.

5. In paragraph 4, The above second surface is a circuit board in contact with the upper or lower surface of the glass core layer.

6. In paragraph 4, A circuit board having a length in the vertical direction of the first surface greater than a length in the vertical direction of the second surface.

7. In paragraph 4, The above second surface is a circuit board located between the upper and lower surfaces of the glass core layer.

8. In paragraph 4, A circuit board in which the second surface is positioned parallel to and in contact with the outermost surface of the build-up insulation.

9. In paragraph 4, A circuit board in which the third inclination angle with respect to the upper surface of the glass core layer of the second surface is the same as the first inclination angle with respect to the upper surface of the glass core layer of the outermost surface of the build-up insulation.

10. In paragraph 4, A circuit board in which the third inclination angle with respect to the upper surface of the glass core layer of the second surface is different from the second inclination angle with respect to the upper surface of the glass core layer of the outermost surface of the build-up insulation.

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